A back contact cell, a method of manufacturing the same and a photovoltaic module

Abstract

This invention belongs to the field of photovoltaic module manufacturing technology, specifically relating to a back contact cell, its fabrication method, and a photovoltaic module. The fabrication method of the back contact cell includes: forming a P-type doped polycrystalline silicon layer on the inner layer of the back side of a silicon wafer; performing a first patterning process on the P-type doped polycrystalline silicon layer using a laser, followed by alkaline etching to fabricate an N-type doped polycrystalline silicon layer on the inner layer of the back side of the silicon wafer; performing a second patterning process on the N-type doped polycrystalline silicon layer on the P-type doped polycrystalline silicon layer using a laser; performing a third patterning process on the PN isolation region using a laser; texturing the front side to remove the N-type doped polycrystalline silicon layer from the back P-type doped polycrystalline silicon layer, generating a passivation antireflection layer and metallizing it to obtain the back contact cell. In the fabrication method provided by this invention, the conventional isolation region structure is improved to a flat isolation region structure, increasing the reflection of incident light within the silicon substrate, thereby improving the light absorption efficiency and conversion efficiency of the back contact cell.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic module manufacturing technology, specifically relating to a back contact cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Back-contact (BC) solar cells are a type of high-efficiency solar cell where all electrodes are located on the back of the cell, avoiding shading from the front electrodes and significantly improving photoelectric conversion efficiency. The core advantages of BC cells include: 1. High conversion efficiency: Maximizing light absorption by reducing front shading. 2. Aesthetics: No front electrodes, suitable for building-integrated photovoltaics (BIPV). 3. Low resistance loss: The back electrode design optimizes carrier transport paths.

[0003] However, existing BC batteries still suffer from the following problems: 1. The surface morphology of the traditional PN isolation region is mainly pyramidal, resulting in poor light reflection and affecting the short-circuit current (Isc). 2. The traditional PN isolation region has a large height difference between the isolation region and the boron / phosphorus diffusion layer, which is not conducive to the lateral transport of charge carriers inside the silicon substrate, affecting the fill factor (FF). 3. Poor light reflection and poor lateral transport of charge carriers lead to a decrease in the overall efficiency of the battery. Furthermore, existing fabrication methods make it difficult to precisely control the surface morphology of the PN isolation region to optimize light reflection characteristics, and cannot effectively reduce the height difference between the isolation region and the boron / phosphorus diffusion layer to improve lateral transport of charge carriers. At the same time, the lack of coordinated design of the interface structure between the isolation region and the diffusion layer makes it difficult to balance light absorption efficiency and charge carrier transport performance during the process.

[0004] Therefore, there is an urgent need for a method to prepare back-contact batteries that can precisely control the surface morphology of the PN isolation region. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a back contact battery and its preparation method, which solves the problems of low light absorption efficiency and conversion efficiency of back contact batteries in the prior art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution.

[0007] A method for preparing a back contact battery includes: Step 1, after texturing, cleaning and polishing a silicon wafer, a first tunneling oxide layer and a first intrinsic polycrystalline silicon layer are sequentially deposited on the back side, and then the first intrinsic polycrystalline silicon layer is boron doped to form a P-type doped polycrystalline silicon layer and a BSG film layer in the inner layer and the surface layer of the silicon wafer, respectively.

[0008] Step 2: The P-type doped polysilicon layer is patterned for the first time using a laser, followed by alkaline etching.

[0009] Step 3: Sequentially deposit a second tunneling silicon oxide layer and a second intrinsic polysilicon layer on the back side of the silicon wafer. Perform phosphorus doping on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. Use a laser to perform a second patterning process on the N-type doped polysilicon layer on the P-type doped polysilicon layer.

[0010] Step four: Use laser to perform a third patterning process on the PN isolation region;

[0011] Step 5: Texturing is performed on the front side of the silicon wafer, and the N-type doped polycrystalline silicon layer on the P-type doped polycrystalline silicon layer is removed from the back side; passivation antireflection layers are generated on the front and back sides of the silicon wafer, silver paste is printed on the passivation antireflection layers, and metal electrodes are formed after sintering to obtain the back contact battery.

[0012] In some embodiments of the present invention, in step two, the laser parameters in the first patterning process are as follows: a pulsed laser is used, with a pulse width of 5 ps to 30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150 μm to 300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 ~9×10 3 j / m 2 The overlap rate is 10% to 80%. If the laser spot or energy density, or the overlap rate, is too small, it may result in the inability to effectively pattern the P-type doped polysilicon layer. Alternatively, if the laser parameters are too large, it may result in excessive etching depth or even damage to the silicon substrate.

[0013] In some embodiments of the present invention, in step three, the laser parameters in the second patterning process are as follows: a pulsed laser is used, with a pulse width of 5 ps to 30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150 μm to 300 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 ~6.5×10 3 j / m 2 The overlap rate is 10-80%. If the laser spot or energy density, or the overlap rate, is too small, it may result in the inability to effectively pattern the P-type doped polysilicon layer. Alternatively, if the laser parameters are too large, it may result in excessive etching depth, damaging the already formed N-type doped polysilicon layer, or even damaging the silicon substrate.

[0014] In some embodiments of the present invention, in step four, the laser parameters in the third patterning process are as follows: the laser is a pulsed laser with a wavelength of 1ps to 30ps, a spot size of 30μm to 300μm, a wavelength of 355nm or 532nm, and an energy density of 0.5×10⁻⁶. 3 j / m 2 ~5.5×103 j / m 2 The overlap rate is 10%~80%. If the laser spot or energy density, or the overlap rate, is too small, it may result in the inability to effectively pattern the P-type doped polysilicon layer. Alternatively, if the laser parameters are too large, it may result in excessive etching depth, affecting the morphology of the isolation region.

[0015] In some embodiments of the present invention, in step three, after the first patterning process, the BSG film layer is removed from the front side of the silicon wafer.

[0016] Specifically, in some embodiments of the present invention, an HF solution with a mass concentration of 30% is used to remove the BSG film layer shown.

[0017] In some embodiments of the present invention, in step four, after the third patterning process, the BSG film layer is removed from the front side of the silicon wafer.

[0018] Specifically, in some embodiments of the present invention, an HF solution with a mass concentration of 30% is used to remove the BSG film layer shown.

[0019] In some embodiments of the present invention, the thickness of the first intrinsic polysilicon layer is 200nm~400nm; the thickness of the BSG layer is 40nm~60nm.

[0020] In some embodiments of the present invention, the thickness of the second intrinsic polysilicon layer is 100nm~300nm; the thickness of the PSG layer is 30nm~70nm.

[0021] The present invention also provides a back contact battery, which is prepared by the aforementioned preparation method.

[0022] In some embodiments of the present invention, the reflectivity of the isolation region of the back contact battery is 30% to 50%. Preferably, the reflectivity of the PN isolation region is 40% to 45%.

[0023] In some embodiments of the present invention, the following are included: a silicon wafer substrate, wherein N-regions and P-regions are intersected on the silicon wafer substrate, and a PN isolation region is further included between the N-regions and the P-regions; the height difference between the P-regions and the isolation region is D1, where D1 is 0.5 μm to 5.0 μm; and the height difference between the N-regions and the isolation region is D2, where D2 is 0 μm to 2.0 μm.

[0024] The PN isolation zone further includes a first side region and a central region adjacent to the P region, and a second side region adjacent to the N region; the first side region, the central region, and the second side region are all flat tower base polished structures or flat tower base polished with sparse groove pyramid structures.

[0025] The width difference between region P and the first side region of the isolation is W1, where W1 is 0.1μm to 5.0μm;

[0026] The overall width W2 of the PN isolation region is 20.0 μm to 200.0 μm;

[0027] The height difference between the N region and the second side region is W3, where W3 is 0.1 μm to 5.0 μm.

[0028] In some embodiments of this invention, a small D1 may lead to a risk of conduction between the N and P regions. A small D2 may also lead to a risk of conduction between the N and P regions. A large W1 may affect the subsequent deposition of the passivation and antireflection layer, reducing cell efficiency. A large W2 may increase the lateral transport of charge carriers in the N and P regions, affecting the fill factor and reducing cell efficiency. A large W3 may affect the subsequent deposition of the passivation and antireflection layer, reducing cell efficiency.

[0029] In some embodiments of the present invention, the angle between the first side region and the horizontal direction of the back of the battery is ∠1, and ∠1 is 30°~150°. If the angle is <30°, the laser requires higher precision and it is not conducive to the deposition of the passivation and antireflection layer in the isolation structure region.

[0030] In some embodiments of the present invention, the included angle of the second side region along the horizontal direction of the back of the battery is ∠2, and ∠2 is 30°~160°.

[0031] In some embodiments of the present invention, the silicon substrate has a first side and a second side. The first side includes alternating N-regions and P-regions with opposite conductivity types, and a PN isolation region located between them, mainly serving to isolate the two different conductivity regions on the back side of the battery to prevent carriers from being unable to be collected. The second side includes a textured structure, with the first tunneling passivation layer and the P-type doped polysilicon layer sequentially stacked in the P-region along the thickness direction of the semiconductor substrate. The second tunneling passivation layer and the N-type doped polysilicon layer are sequentially stacked in the N-region along the thickness direction of the semiconductor substrate. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer.

[0032] This invention also discloses a photovoltaic module, including the aforementioned back contact battery.

[0033] Based on the technical solution of the present invention, the present invention has the following beneficial effects compared with the prior art: In the preparation method provided by the present invention, different regions are treated by three lasers, and the reflectivity of the isolation region is 40%~45%. The conventional isolation region structure with pyramid textured surface is improved into a flat isolation region structure, which can increase the reflection of incident light in the silicon substrate, thereby improving the light absorption efficiency and conversion efficiency of the back contact battery.

[0034] The preparation method provided by this invention does not require the use of a mask, thus avoiding the problem of low product yield caused by inaccurate positioning when using lasers in existing technologies.

[0035] The back contact battery provided in this invention has a lower laser energy in the isolation region. Combined with the strong protective properties of the texturing additive, the tunneling oxide layer and the underlying silicon substrate are less susceptible to subsequent wet corrosion damage. This results in a smaller height between the isolation region and the boron / phosphorus diffusion layer, which is beneficial for the lateral transport of charge carriers inside the silicon substrate and improves the flyback effect (FF).

[0036] This invention provides two different preparation processes, which widen the process window for some processes and can effectively improve the production efficiency and yield of products. Attached Figure Description

[0037] Figure 1 This is a flowchart of the preparation method provided in Embodiment 1 of the present invention.

[0038] Figure 2 This is a schematic diagram of a back-contact solar cell provided by the present invention.

[0039] Figure 3 This is a topographic image of the PN isolation region of a back-contact solar cell provided in an embodiment of the present invention; wherein, Figure 3 In the image, A represents the morphology of the PN and GAP regions in a 3D laser scanning microscope. Figure 3 In the diagram, B represents the line height map after laser scanning of the PN and GAP regions of the 3D laser scanning microscope, reflecting the line height difference between each region.

[0040] Figure 4 This is a flowchart of the preparation method provided in Embodiment 4 of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments thereof. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0042] The following description is based on specific embodiments.

[0043] Example 1

[0044] A method for preparing a back contact battery includes the following steps (e.g.) Figure 1 (as shown)

[0045] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 200s.

[0046] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2 h, working pressure 100 mTorr, and the thickness of the intrinsic polycrystalline silicon layer is 200 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is...

[0047] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent boron diffusion.

[0048] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0049] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 800℃, diffusion time 5 min, BCl3 flow rate 50 sccm, O2 flow rate 500 sccm; oxidation propagation temperature 900℃, O2 flow rate 5000 sccm, propagation time 30 min, resulting in a 40 nm thick BSG layer.

[0050] S4, Laser 1: A laser is used to perform the first patterning process on the P-type doped polysilicon layer on the back side of the silicon substrate. The parameters for Laser 1 are: pulsed laser, pulse width of 5 ps, wavelength of 532 nm, spot size of 150 μm, and energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0051] S5. Single-sided film removal: The BSG film layer on the front side of the silicon wafer is removed using a high-concentration HF solution (30% HF solution by mass) for 600 seconds.

[0052] S6. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 50 seconds.

[0053] S7. Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer with a thickness of 2 nm and a second intrinsic polycrystalline silicon layer with a thickness of 100 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2 h, working pressure 100 mTorr, and intrinsic polycrystalline silicon layer thickness 100 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent phosphorus doping, and the purpose of setting the mask layer is...

[0054] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent phosphorus doping.

[0055] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0056] S8. Phosphorus Doping: Phosphorus doping is performed on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions are: temperature 750℃, diffusion time 5 min, POCl3 carried by nitrogen gas at a flow rate of 500 sccm, and O2 flow rate of 500 sccm; oxidation propagation temperature 850℃, O2 flow rate 1000 sccm, propagation time 20 min, resulting in a 30 nm thick PSG layer.

[0057] S9, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 532 nm, a spot size of 150 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0058] S10, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process parameters are: 1ps pulsed laser, 30μm spot size, 355nm wavelength, and energy density of 0.5×10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0059] S11, Single-sided film removal 2: Use a high-concentration HF solution (30% HF solution by mass) to remove the BSG film layer on the front side of the silicon wafer for 600 seconds.

[0060] S12. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 400s.

[0061] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0062] S13, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. Passivation and antireflection layers are deposited on the surface of the initially prepared silicon wafer.

[0063] S14, Metallization: Screen printing, sintering, and photoinjection to obtain the back contact battery. The battery result is as follows. Figure 2 As shown, the morphology of the PN isolation region is as follows: Figure 3 As shown.

[0064] Example 2

[0065] A method for preparing a back contact battery includes the following steps:

[0066] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 450s.

[0067] S2, Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 300 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 1000 sccm, reaction temperature 600℃, time 3h, working pressure 300 mTorr, and intrinsic polycrystalline silicon layer thickness 300 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is...

[0068] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent boron diffusion.

[0069] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0070] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 900℃, diffusion time 35 min, BCl3 flow rate 250 sccm, O2 flow rate 1000 sccm; oxidation propagation temperature 1000℃, O2 flow rate 20000 sccm, propagation time 60 min, resulting in a 50 nm thick BSG layer.

[0071] S4, Laser 1: A laser is used to perform the first patterning process on the P-type doped polysilicon layer on the back side of the silicon substrate. The parameters for Laser 1 are: pulsed laser, pulse width of 20 ps, ​​wavelength of 532 nm, spot size of 200 μm, and energy density of 6 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%.

[0072] S5. Single-sided film removal: The BSG film layer on the front side of the silicon wafer is removed using a high-concentration HF solution (30% HF solution by mass) for 600 seconds.

[0073] S6. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 200 seconds.

[0074] S7. Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer with a thickness of 2 nm and a second intrinsic polycrystalline silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 1000 sccm, reaction temperature 600℃, time 3h, working pressure 300 mTorr, and intrinsic polycrystalline silicon layer thickness 200 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a basis for subsequent phosphorus doping, and the purpose of setting the mask layer is...

[0075] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent phosphorus doping.

[0076] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0077] S8. Phosphorus Doping: Phosphorus doping was performed on the second intrinsic polysilicon layer, forming an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions were: temperature 800℃, diffusion time 20 min, POCl3 carried by nitrogen gas at a flow rate of 900 sccm, and O2 flow rate of 800 sccm; oxidation propagation temperature 900℃, O2 flow rate 6000 sccm, propagation time 40 min, resulting in a 50 nm thick PSG layer.

[0078] S9, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 20 ps, ​​a wavelength of 355 nm, a spot size of 200 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%.

[0079] S10, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process parameters are: 15ps pulsed laser, 150μm spot size, 532nm wavelength, and energy density of 3×10⁻⁶. 3 j / m 2 The overlap rate is 50%.

[0080] S11, Single-sided film removal 2: Use a high-concentration HF solution (30% HF solution by mass) to remove the BSG film layer on the front side of the silicon wafer for 600 seconds.

[0081] S12. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 500s.

[0082] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0083] S13, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. Passivation and antireflection layers are deposited on the surface of the initially prepared silicon wafer.

[0084] S14, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0085] Example 3

[0086] A method for preparing a back contact battery includes the following steps:

[0087] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 500s.

[0088] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 400 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 2000 sccm, reaction temperature 700℃, time 4h, working pressure 500 mTorr, and the thickness of the intrinsic polycrystalline silicon layer is 400 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is...

[0089] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent boron diffusion.

[0090] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0091] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 950℃, diffusion time 50 min, BCl3 flow rate 500 sccm, O2 flow rate 2000 sccm; oxidation propagation temperature 1050℃, O2 flow rate 30000 sccm, propagation time 80 min, resulting in a 60 nm thick BSG layer.

[0092] S4, Laser 1: A laser is used to perform the first patterning process on the P-type doped polysilicon layer on the back side of the silicon substrate. The parameters for Laser 1 are: pulsed laser, pulse width 30 ps, ​​wavelength 532 nm, spot size 300 μm, and energy density of 9 × 10⁻⁶. 3 j / m 2 The overlap rate is 80%.

[0093] S5. Single-sided film removal: The BSG film layer on the front side of the silicon wafer is removed using a high-concentration HF solution (30% HF solution by mass) for 600 seconds.

[0094] S6. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 300 seconds.

[0095] S7. Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer with a thickness of 2 nm and a second intrinsic polycrystalline silicon layer with a thickness of 300 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 2000 sccm, reaction temperature 700℃, time 4 h, working pressure 500 mTorr, and intrinsic polycrystalline silicon layer thickness 300 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent phosphorus doping, and the purpose of setting the mask layer is...

[0096] The first intrinsic polysilicon layer is the intrinsic polysilicon layer that prevents dopant atoms from entering its bottom during subsequent phosphorus doping.

[0097] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0098] S8. Phosphorus Doping: Phosphorus doping was performed on the second intrinsic polysilicon layer, forming an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions were: temperature 850℃, diffusion time 30 min, POCl3 carried by nitrogen gas at a flow rate of 1200 sccm, and O2 flow rate of 1000 sccm; oxidation propagation temperature 950℃, O2 flow rate of 10000 sccm, propagation time 60 min, resulting in a 70 nm thick PSG layer.

[0099] S9, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 30 ps, ​​a wavelength of 355 nm, a spot size of 300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%.

[0100] S10, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process parameters are: 30ps pulsed laser, 300μm spot size, 532nm wavelength, and energy density of 5.5×10⁻⁶. 3 j / m 2 The overlap rate is 80%.

[0101] S11, Single-sided film removal 2: Use a high-concentration HF solution (30% HF solution by mass) to remove the BSG film layer on the front side of the silicon wafer for 600 seconds.

[0102] S12. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 600s.

[0103] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0104] S13, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. Passivation and antireflection layers are deposited on the surface of the initially prepared silicon wafer.

[0105] S14, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0106] Example 4

[0107] A method for preparing a back contact battery includes the following steps (e.g.) Figure 4 (as shown)

[0108] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 200s.

[0109] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2 h, working pressure 100 mTorr, and intrinsic polycrystalline silicon layer thickness 200 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is to prevent dopant atoms from entering the underlying intrinsic polycrystalline silicon layer during subsequent boron diffusion.

[0110] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0111] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 800℃, diffusion time 5 min, BCl3 flow rate 50 sccm, O2 flow rate 500 sccm; oxidation propagation temperature 900℃, O2 flow rate 5000 sccm, propagation time 30 min, resulting in a 40 nm thick BSG layer.

[0112] S4, Laser 1: A laser is used to pattern the P-type doped polysilicon layer on the back silicon.

[0113] The parameters of laser 1 are as follows: pulsed laser, pulse width of 5 ps, wavelength of 355 nm, spot size of 150 μm, and energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0114] S5. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 200 seconds.

[0115] S6, Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer and a second intrinsic polycrystalline silicon layer with a thickness of 2 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions of the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2h, working pressure 100mTorr, and intrinsic polycrystalline silicon layer thickness 100nm.

[0116] S7. Phosphorus Doping: Phosphorus doping is performed on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions are: temperature 750℃, diffusion time 5 min, POCl3 carried by nitrogen gas at a flow rate of 500 sccm, and O2 flow rate of 500 sccm; oxidation propagation temperature 850℃, O2 flow rate 1000 sccm, propagation time 20 min, resulting in a 30 nm thick PSG layer.

[0117] S8, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 532 nm, a spot size of 150 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0118] S9, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process conditions are: 1ps pulsed laser, 30μm spot size, 532nm wavelength, and energy density of 0.5×10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0119] S10, Acid Etching: The front side of the silicon wafer is acid-etched using a high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution. The preparation parameters of the high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution are as follows: hydrofluoric acid is selected from raw materials with a mass ratio of 48%~50%, and its volume concentration in the formula is 15%; nitric acid is selected from raw materials with a mass ratio of 68%~70%, and its volume concentration in the formula is 18%; sulfuric acid is selected from raw materials with a mass ratio of 96%~98%, and its volume concentration in the formula is 12%; the etching time is controlled at 180 seconds.

[0120] S11. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 600s.

[0121] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0122] S12, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. A passivation and antireflection layer is deposited on the surface of the initially prepared silicon wafer.

[0123] S13, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0124] Example 5

[0125] A method for preparing a back contact battery includes the following steps:

[0126] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 400s.

[0127] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 300 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 1000 sccm, reaction temperature 600℃, time 3h, working pressure 300 mTorr, and intrinsic polycrystalline silicon layer thickness 300 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is to prevent dopant atoms from entering the underlying intrinsic polycrystalline silicon layer during subsequent boron diffusion.

[0128] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0129] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 900℃, diffusion time 25 min, BCl3 flow rate 250 sccm, O2 flow rate 1000 sccm; oxidation propagation temperature 1000℃, O2 flow rate 15000 sccm, propagation time 50 min, resulting in a 50 nm thick BSG layer.

[0130] S4, Laser 1: A laser is used to pattern the P-type doped polysilicon layer on the back silicon.

[0131] The parameters of laser 1 are as follows: pulsed laser, pulse width of 15 ps, wavelength of 532 nm, spot size of 200 μm, and energy density of 6 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%.

[0132] S5. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 200 seconds.

[0133] S6, Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer and a second intrinsic polycrystalline silicon layer with a thickness of 2 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions of the intrinsic polycrystalline silicon layer are: SiH4 flow rate 1500 sccm, reaction temperature 600℃, time 3h, working pressure 300 mTorr, and intrinsic polycrystalline silicon layer thickness 200 nm.

[0134] S7. Phosphorus Doping: Phosphorus doping is performed on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions are: temperature 800℃, diffusion time 20 min, POCl3 carried by nitrogen gas at a flow rate of 700 sccm, and O2 flow rate of 8000 sccm; oxidation propagation temperature 900℃, O2 flow rate of 5000 sccm, propagation time 40 min, resulting in a 50 nm thick PSG layer.

[0135] S8, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 20 ps, ​​a wavelength of 355 nm, a spot size of 200 μm, and an energy density of 3 × 10⁻⁶. 3 j / m 2 The overlap rate is 30%.

[0136] S9, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process conditions are: 20ps pulsed laser, 200μm spot size, 355nm wavelength, and energy density of 4×10⁻⁶. 3 j / m 2 The overlap rate is 60%.

[0137] S10, Acid Etching: The front side of the silicon wafer is acid-etched using a high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution. The preparation parameters of the high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution are as follows: hydrofluoric acid is selected from raw materials with a mass ratio of 48%~50%, and its volume concentration in the formula is 15%; nitric acid is selected from raw materials with a mass ratio of 68%~70%, and its volume concentration in the formula is 18%; sulfuric acid is selected from raw materials with a mass ratio of 96%~98%, and its volume concentration in the formula is 12%; the etching time is controlled at 400 seconds.

[0138] S11. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 600s.

[0139] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0140] S12, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. A passivation and antireflection layer is deposited on the surface of the initially prepared silicon wafer.

[0141] S13, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0142] Example 6

[0143] A method for preparing a back contact battery includes the following steps:

[0144] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 500s.

[0145] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 400 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 2000 sccm, reaction temperature 700℃, time 4 h, working pressure 500 mTorr, and intrinsic polycrystalline silicon layer thickness 400 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is to prevent dopant atoms from entering the underlying intrinsic polycrystalline silicon layer during subsequent boron diffusion.

[0146] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0147] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 950℃, diffusion time 50 min, BCl3 flow rate 500 sccm, O2 flow rate 2000 sccm; oxidation propagation temperature 1050℃, O2 flow rate 30000 sccm, propagation time 80 min, resulting in a 60 nm thick BSG layer.

[0148] S4, Laser 1: A laser is used to pattern the P-type doped polysilicon layer on the back silicon.

[0149] The parameters of laser 1 are as follows: pulsed laser, pulse width of 30 ps, ​​wavelength of 355 nm, spot size of 300 μm, and energy density of 9 × 10⁻⁶. 3 j / m 2 The overlap rate is 80%.

[0150] S5. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 200 seconds.

[0151] S6, Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer and a second intrinsic polycrystalline silicon layer with a thickness of 2 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 2000 sccm, reaction temperature 700℃, time 4h, working pressure 500 mTorr, and intrinsic polycrystalline silicon layer thickness 300 nm.

[0152] S7. Phosphorus Doping: Phosphorus doping was performed on the second intrinsic polysilicon layer, forming an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions were: temperature 850℃, diffusion time 30 min, POCl3 carried by nitrogen gas at a flow rate of 1200 sccm, and O2 flow rate of 1000 sccm; oxidation propagation temperature 950℃, O2 flow rate of 10000 sccm, propagation time 60 min, resulting in a 70 nm thick PSG layer.

[0153] S8, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 30 ps, ​​a wavelength of 355 nm, a spot size of 300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 50%.

[0154] S9, Laser 3: The PN isolation region is patterned three times using a laser. Laser 3 process conditions are: 30ps pulsed laser, 300µm spot size, 355nm wavelength, and energy density of 5.5×10⁻⁶. 3 j / m 2 The overlap rate is 80%.

[0155] S10, Acid Etching: The front side of the silicon wafer is acid-etched using a high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution. The preparation parameters of the high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution are as follows: hydrofluoric acid is selected from raw materials with a mass ratio of 48%~50%, and its volume concentration in the formula is 15%; nitric acid is selected from raw materials with a mass ratio of 68%~70%, and its volume concentration in the formula is 18%; sulfuric acid is selected from raw materials with a mass ratio of 96%~98%, and its volume concentration in the formula is 12%; the etching time is controlled at 600 seconds.

[0156] S11. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 600s.

[0157] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0158] S12, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. A passivation and antireflection layer is deposited on the surface of the initially prepared silicon wafer.

[0159] S13, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0160] Comparative Example 1

[0161] The back contact battery provided in this comparative example has a textured insulating region. The difference between this and the preparation method in Example 5 is that it undergoes two laser treatments. The specific preparation method is as follows:

[0162] S1. Alkali polishing: The N-type semiconductor substrate is subjected to alkali polishing treatment, and a second texture structure is formed on the surface of the semiconductor substrate. The second texture structure may include a flat tower-like microstructure. The alkali polishing is carried out using a 6% NaOH solution and the polishing time is 200s.

[0163] S2. Intrinsic Silicon Growth 1: A first tunneling silicon oxide layer with a thickness of 2 nm and a first intrinsic polycrystalline silicon layer with a thickness of 200 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions for the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2 h, working pressure 100 mTorr, and intrinsic polycrystalline silicon layer thickness 200 nm. The purpose of setting the intrinsic polycrystalline silicon layer is to provide a foundation for subsequent boron diffusion, and the purpose of setting the mask layer is to prevent dopant atoms from entering the underlying intrinsic polycrystalline silicon layer during subsequent boron diffusion.

[0164] The tunneling oxide layer utilizes the quantum tunneling effect to enable efficient electron transport while preventing hole recombination, thereby passivating the back of the solar cell.

[0165] S3. Boron Doping: Boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG layer on the inner and outer layers of the silicon wafer, respectively. Boron doping conditions: temperature 800℃, diffusion time 5 min, BCl3 flow rate 50 sccm, O2 flow rate 500 sccm; oxidation propagation temperature 900℃, O2 flow rate 5000 sccm, propagation time 30 min, resulting in a 40 nm thick BSG layer.

[0166] S4, Laser 1: A laser is used to pattern the P-type doped polysilicon layer on the back silicon.

[0167] The parameters of laser 1 are as follows: the laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0168] S5. Alkaline Etching: A secondary alkaline etching process is performed using an alkaline polishing technique. The alkaline etching is carried out using a 6% (w / w) NaOH solution, and the polishing time is 50 seconds.

[0169] S6, Intrinsic Silicon Growth 2: A second tunneling silicon oxide layer and a second intrinsic polycrystalline silicon layer with a thickness of 2 nm are sequentially deposited on the back side of the silicon wafer. The deposition conditions of the intrinsic polycrystalline silicon layer are: SiH4 flow rate 300 sccm, reaction temperature 500℃, time 2h, working pressure 100mTorr, and intrinsic polycrystalline silicon layer thickness 100nm.

[0170] S7. Phosphorus Doping: Phosphorus doping is performed on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. The phosphorus diffusion conditions are: temperature 750℃, diffusion time 5 min, POCl3 carried by nitrogen gas at a flow rate of 500 sccm, and O2 flow rate of 500 sccm; oxidation propagation temperature 850℃, O2 flow rate 1000 sccm, propagation time 20 min, resulting in a 30 nm thick PSG layer.

[0171] S8, Laser 2: A laser is used to perform secondary patterning on the N-type doped polysilicon layer on the back silicon substrate. The parameters of Laser 2 are: the laser beam is a pulsed laser with a pulse width of 5 ps, a wavelength of 355 nm, a spot size of 150 μm, and an energy density of 2 × 10⁻⁶. 3 j / m 2 The overlap rate is 10%.

[0172] S9. Acid Etching: The front side of the silicon wafer is acid-etched using a high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution. The preparation parameters of the high-concentration hydrofluoric acid, nitric acid, and sulfuric acid mixed solution are as follows: hydrofluoric acid is selected from raw materials with a mass ratio of 48%~50%, and its volume concentration in the formula is 15%; nitric acid is selected from raw materials with a mass ratio of 68%~70%, and its volume concentration in the formula is 18%; sulfuric acid is selected from raw materials with a mass ratio of 96%~98%, and its volume concentration in the formula is 12%; the etching time is controlled at 180 seconds.

[0173] S10. Texturing: A textured surface is formed on the front side, and the N-type doped polysilicon layer in the P-region is removed from the back side, forming an isolation region in the PN region. The texturing conditions are: a 6% NaOH solution is used, and the texturing time is 600s.

[0174] During the texturing process, due to the strong protective effect of the selected texturing additives, and the fact that the tunneling oxide layer under PSG in the PN isolation zone remains intact due to different laser processing conditions, it provides a certain degree of barrier function. Under appropriate texturing process conditions, after the process is completed, the isolation zone has a flat, polished tower base structure or a flat, polished tower base with a sparsely grooved pyramid structure, and the gap between the formed isolation zone and the PN zone is relatively shallow.

[0175] S11, Double-sided coating: Passivation and antireflection layers are formed on the front and back sides. Passivation and antireflection layers are deposited on the surface of the pre-fabricated silicon wafer.

[0176] S12, Metallization: Screen printing, sintering, and photoinjection are used to obtain the back contact battery.

[0177] Comparative Example 2

[0178] The difference between Comparative Example 2 and Comparative Example 1 is that, after S8, alkaline etching and silicon oxide mask deposition are performed, followed by steps S9 to S12 in Comparative Example 1. Specifically, the alkaline etching and silicon oxide mask deposition steps are as follows:

[0179] Alkaline etching: A secondary alkaline etching process is performed using alkaline polishing. Alkaline polishing is carried out using a 6% (w / w) NaOH solution for 200 seconds.

[0180] Mask: A silicon oxide mask is prepared on the surface of a silicon wafer. The thickness of the silicon oxide mask is 80 nm.

[0181] Comparative Example 3

[0182] The difference between Comparative Example 3 and Comparative Example 2 is that a silicon nitride mask is deposited after alkaline etching; the remaining steps are the same as in Comparative Example 2. Specifically, the steps for depositing the silicon nitride mask are as follows:

[0183] Mask: A silicon nitride mask is prepared on the surface of a silicon wafer. The thickness of the silicon nitride is 80 nm.

[0184] Performance testing:

[0185] The performance of the prepared back contact battery was tested, and the test results are shown in Table 1.

[0186] Table 1 Test Results

[0187] Group short circuit current Fill factor Conversion efficiency reflectivity Example 1 16.53 85.58 26.84 40% Example 2 16.50 85.62 26.83 41.8% Example 3 16.52 85.70 26.86 44.6% Example 4 16.45 85.69 26.86 42.5% Example 5 16.52 85.63 26.81 43.4% Example 6 16.51 85.68 26.82 42.1% Comparative Example 1 16.38 85.50 26.68 10.9% Comparative Example 2 16.50 85.55 26.79 40.3% Comparative Example 3 16.51 85.57 26.80 40.6%

[0188] As shown in Table 1, isolation regions with smooth morphology can be obtained in Examples 1 to 6. Compared with Comparative Example 1, isolation regions with smooth morphology can increase the reflection of incident light in the silicon substrate, thereby improving the light absorption efficiency and conversion efficiency of the back contact cell.

[0189] Examples 1 to 6 can all produce isolation regions with flat morphology. Compared with Comparative Examples 2 and 3, although the isolation regions obtained are all flat structures, their preparation methods are complicated, and the height difference between the back contact battery n region and the isolation region is too large, which affects the transmission of lateral current, thereby reducing the short-circuit current, fill factor and conversion efficiency of the back contact battery.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for preparing a back contact battery, characterized in that, include: Step 1: After texturing, cleaning and polishing, a first tunneling oxide layer and a first intrinsic polysilicon layer are deposited sequentially on the back side of the silicon wafer. Then, boron doping is performed on the first intrinsic polysilicon layer to form a P-type doped polysilicon layer and a BSG film layer in the inner and outer layers of the silicon wafer, respectively. Step 2: The P-type doped polysilicon layer is patterned for the first time using a laser, followed by alkaline etching. Step 3: Sequentially deposit a second tunneling silicon oxide layer and a second intrinsic polysilicon layer on the back side of the silicon wafer. Perform phosphorus doping on the second intrinsic polysilicon layer to form an N-type doped polysilicon layer and a PSG layer on the inner and outer layers of the silicon wafer, respectively. Use a laser to perform a second patterning process on the N-type doped polysilicon layer on the P-type doped polysilicon layer. Step four: Use laser to perform a third patterning process on the PN isolation region; Step 5: Texturing is performed on the front side of the silicon wafer, and the N-type doped polycrystalline silicon layer on the P-type doped polycrystalline silicon layer is removed from the back side; passivation antireflection layers are generated on the front and back sides of the silicon wafer, silver paste is printed on the passivation antireflection layers, and metal electrodes are formed after sintering to obtain the back contact battery.

2. The method for preparing a back contact battery as described in claim 1, characterized in that, In step two, the laser parameters for the first patterning process are as follows: pulsed laser with a pulse width of 5 ps to 30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150 μm to 300 μm, and an energy density of 4 × 10⁻⁶. 3 j / m 2 ~9×10 3 j / m 2 The overlap rate is 10% to 80%.

3. The method for preparing a back contact battery as described in claim 1, characterized in that, In step three, the laser parameters for the second patterning process are as follows: pulsed laser with a pulse width of 5 ps to 30 ps, ​​a wavelength of 355 nm or 532 nm, a spot size of 150 μm to 300 μm, and an energy density of 3.55 × 10⁻⁶. 3 j / m 2 ~6.5×10 3 j / m 2 The overlap rate is 10% to 80%.

4. The method for preparing a back contact battery as described in claim 1, characterized in that, In step four, the laser parameters for the third patterning process are as follows: pulsed laser with a pulsed laser frequency of 1 ps to 30 ps, ​​a spot size of 30 μm to 300 μm, a wavelength of 355 nm or 532 nm, and an energy density of 0.5 × 10⁻⁶. 3 j / m 2 ~5.5×10 3 j / m 2 The overlap rate is 10%~80%.

5. The method for preparing a back contact battery as described in claim 1, characterized in that, In step three, after the first patterning process, the BSG film layer is removed from the front side of the silicon wafer. In step four, after the third patterning process, the BSG film layer is removed from the front side of the silicon wafer.

6. The method for preparing a back contact battery as described in claim 1, characterized in that, In step one, the thickness of the first intrinsic polysilicon layer is 200nm~400nm; the thickness of the BSG layer is 40nm~60nm. In step three, the thickness of the second intrinsic polysilicon layer is 100nm~300nm; the thickness of the PSG layer is 30nm~70nm.

7. The method for preparing a back contact battery as described in claim 1, characterized in that, In step five, the texturing is carried out using an alkaline solution with a mass concentration of 5% to 6%, and the texturing time is 400s to 600s.

8. A back-contact battery, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 7.

9. The back contact battery as described in claim 8, characterized in that, The reflectivity of the PN isolation region of the back contact battery is 30%~50%.

10. A photovoltaic module, characterized in that, Including the back contact battery as described in claim 8 or 9.

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