A battery piece preparation method for reducing cutting loss, a photovoltaic battery piece, a laminated battery, and a photovoltaic module
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHUZHOU JIETAI NEW ENERGY TECH CO LTD
- Filing Date
- 2026-01-14
- Publication Date
- 2026-06-16
Smart Images
Figure CN122227702A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of battery manufacturing technology, and more specifically, to a method for preparing battery cells with reduced cutting losses, photovoltaic cells, tandem cells, and photovoltaic modules. Background Technology
[0002] In the solar cell manufacturing industry, to improve the power generation of solar modules, solar cells need to be cut into several equal-area wafers to make modules. However, during the cutting process, a cut surface is formed at the cutting point, which generates many defects. These defects are called cut damage, which affects the electrical performance of the solar cell, leading to a decrease in open-circuit voltage (Uoc) and contact power efficiency (Pff). This is especially true for TOPCon solar modules, where the electrical performance loss caused by cutting is significant, impacting module power output and becoming an obstacle to the development of TOPCon solar module power. Improving the electrical performance loss caused by cutting is therefore urgently needed.
[0003] To reduce the damage caused by cutting solar cells, the mainstream technology currently on the market is half-cell passivation technology. This involves applying a passivation coating to the cut solar cells and applying voltage to the cover and substrate during the coating process to create an electric field inside the cell. This electric field accelerates the movement of hydrogen ions, making it easier for them to reach the surface of the cell (i.e., the hydrogen ions in the cell are activated), achieving hydrogen passivation. A passivation layer is formed on the cut surface, repairing defects and reducing damage caused by cutting. However, this technology requires relatively complex equipment, adding many additional machines, including slicing machines, half-cell passivation machines, and half-cell testing machines, resulting in high equipment investment costs. Summary of the Invention
[0004] 1. The technical problem that the invention aims to solve This application addresses the core problem of reduced open-circuit voltage and fill factor due to cutting damage during the cutting process of solar cells. It provides a method for preparing solar cells, photovoltaic solar cells, tandem solar cells, and photovoltaic modules that reduces cutting damage. This application removes the PN junction from the source by laser film opening and wet etching, effectively reducing cutting damage, simplifying the process, and improving module power.
[0005] 2. Technical Solution The summary section of this application is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.
[0006] To achieve the above objectives, the technical solution provided in this application is as follows: As a first aspect of this application, a method for preparing a solar cell with reduced cutting loss includes the following steps: Laser film-opening treatment is performed on the front cutting position of the silicon wafer after boron diffusion is completed, so that the thickness of the borosilicate glass layer in this area is reduced and the structure is loosened. After laser-etched silicon wafers are processed, alkaline polishing and RCA wet etching are performed to completely remove the PN junction in the front laser area.
[0007] Furthermore, the laser film-opening process uses an infrared laser.
[0008] Furthermore, in the infrared laser film-opening process, the laser power is 40-70%, the laser speed is 20000mm / s-30000mm / s, and within this speed range, the CT time can meet the production capacity requirements, and the laser area width is 100-800um.
[0009] Furthermore, the infrared laser film-opening process uses an infrared laser with a frequency of 100kHz-140kHz and a power of 80W or higher. The frequency of the infrared laser film-opening process is adjusted accordingly within the above-mentioned range based on the laser speed. The power of the infrared laser is preferably 80W-120W. If the laser power is below 80W, the laser energy will be insufficient and the film-opening effect will not be achieved. After alkaline washing, PN junction residue will appear in the laser area. The laser-treated area appears to be in a molten state under a microscope, with a junction depth of more than 3µm. More specifically, the junction depth is generally 3µm-5µm.
[0010] Furthermore, the reaction temperature of the alkaline polishing process is 50-80℃, the concentration of the alkaline solution is 0.5-2wt%, the etching depth of the front laser area is 1-4µm, and a tower base structure of 12-20µm is simultaneously formed on the back of the silicon wafer.
[0011] Furthermore, the RCA wet etching process achieves an etching depth of over 4µm in the laser region, preferably 4µm-7µm, and presents a tower-based morphology, ensuring that the PN junction is completely removed.
[0012] Furthermore, the cell fabrication includes the following steps performed sequentially: Step 1, Texturing: Texturing is performed on both sides of the silicon wafer to form a pyramid structure to reduce light reflectivity; Step 2, Boron diffusion: A boron source is introduced into the front side of the texturized silicon wafer. The boron source decomposes at high temperature and reacts with silicon to generate boron atoms, which diffuse into the silicon wafer to form a PN junction. Step 3, Laser Deposition: Laser deposition is performed on the cutting position on the front side of the silicon wafer to reduce the thickness of the borosilicate glass layer and loosen its structure; Step 4, BSG removal and alkaline polishing: Remove the borosilicate glass layer from the edge of the silicon wafer and the back side, and remove the BSG layer and PN junction in the front laser area through an alkaline polishing process, while forming a large tower base structure on the back side. Step 5, Backside passivation layer preparation: A tunneling oxide layer and an amorphous silicon thin film are sequentially grown on the backside of the silicon wafer; Step 6, Phosphorus diffusion: Crystallize amorphous silicon into polycrystalline silicon and dope it with phosphorus to form a polycrystalline silicon thin film; Step 7, PSG and RCA removal cleaning: Remove the phosphosilicate glass layer and polysilicon film around the edges and front of the silicon wafer, and perform deep etching on the laser area to ensure that the PN junction is completely removed; Step 8, Preparation of front passivation layer: Deposit an aluminum oxide thin film on the front side of the silicon wafer; Step 9, Front-side film preparation: Deposit a silicon nitride antireflective film on the front side of the silicon wafer; Step 10, Backside Film Preparation: Deposit a silicon nitride antireflection film on the backside of the silicon wafer; Step 11, Metallization preparation: Metal electrodes are formed by screen printing and sintering; Step 12, Testing and Sorting: Test and sort the finished battery cells.
[0013] Furthermore, the sheet resistance of the boron-doped silicon wafer on the front side is controlled at 400-440 Ω / sq; the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the amorphous silicon thin film is 150-190 nm; the sheet resistance of the phosphorus-doped polycrystalline silicon thin film on the back side of the silicon wafer is controlled at 40-60 Ω / sq.
[0014] Furthermore, the thickness of the aluminum oxide film on the front side of the silicon wafer is 3-6 nm; the thickness of the silicon nitride antireflective film on the front side is 67-81 nm, with a refractive index of 2.02-2.16; and the thickness of the silicon nitride antireflective film on the back side is 69-85 nm, with a refractive index of 2.03-2.17.
[0015] As a second aspect of this application, a photovoltaic cell of this application is prepared by the above-described preparation method, wherein the PN junction at the cut position on the front side of the cell is completely removed.
[0016] As a third aspect of this application, a stacked battery includes: Top cell, which can be a perovskite cell, cadmium telluride solar cell, copper indium gallium selenide solar cell, or gallium arsenide solar cell; Intermediate connection layer; The bottom cell is the aforementioned photovoltaic cell; The top battery, the intermediate connecting layer, and the bottom battery are stacked and connected.
[0017] As a third aspect of this application, a photovoltaic module includes the aforementioned photovoltaic cells or the aforementioned tandem cells.
[0018] 3. Beneficial effects Compared with existing known technologies, the technical solution provided in this application has the following significant advantages: This application discloses a method for manufacturing solar cells with reduced cutting damage. During the cell manufacturing process, the synergistic effect of infrared laser film opening and subsequent alkaline polishing and RCA wet etching completely removes the PN junction in the cutting area from the source, significantly reducing cutting damage to the solar cells. This method not only effectively improves the open-circuit voltage and fill factor of the solar module, achieving power enhancement, but also makes full use of existing laser equipment, avoiding complex half-cell passivation processes and significantly reducing production costs. Furthermore, the laser processing is precisely located outside the grid line area, ensuring that electron transport efficiency is not affected, providing a simple and efficient solution for the large-scale application of multi-cell solar cells. Attached Figure Description
[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application.
[0020] In the attached diagram: Figure 1 This is a schematic diagram of the molten morphology formed on the front oxide layer of the solar cell after infrared laser treatment; it can be seen that the morphology after infrared laser treatment on the front oxide layer of the solar cell is different from the morphology formed by other lasers such as green and purple skin. Figure 2 This is a schematic diagram of the dimensions of the back-side tower base of the solar cell; the size of the back-side tower base exceeds 15um, indicating that in order to achieve the expected etching depth in the front laser area after alkaline polishing, the alkaline concentration and reaction temperature are increased. This optimization not only ensures the effective removal of the PN junction, but also increases the size of the back-side tower base structure, which is beneficial for light absorption. Figure 3 This is a schematic diagram of the structure of a TOPCon solar cell currently in mass production; Figure 4 This is a schematic diagram of the TOPCon solar cell structure after laser processing. By removing the PN junction at the cut position on the front side, and... Figure 3 Compared to the standard structure, it significantly reduces cutting damage; Figure 5 This is a schematic diagram of the cutting location on the surface of the solar cell, i.e., the area affected by the laser.
[0021] Explanation of the labels in the diagram: 1. Silicon substrate; 21. P+ emitter; 22. Tunneling oxide layer; 31. Alumina layer; 32. Phosphorus-doped polycrystalline silicon layer; 41. Front silicon nitride layer; 42. Back silicon nitride layer; 51. Front electrode; 52. Back electrode; 6. Laser-acting area. Detailed Implementation
[0022] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0023] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0024] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0025] Example 1 This embodiment provides a method for preparing solar cells with reduced cutting damage, comprising the following steps: Step 1, Texturing Process: First, contaminants on the silicon wafer surface are removed in an alkaline hydrogen peroxide solution in a pre-cleaning tank. Then, the wafer is transferred to a texturing tank. In an alkaline solution containing texturing additives, the alkaline solution reacts with the silicon wafer surface, forming a pyramid structure. This texturing process is performed on both sides of the silicon wafer, significantly reducing surface light reflectivity and enhancing its absorption of incident light. The alkaline solution is a potassium hydroxide solution at 75°C with an alkaline concentration of 4 wt%. Step 2, Boron diffusion process: The texturized silicon wafer is placed in a high-temperature diffusion furnace tube, and boron trichloride (BCl3) is introduced as a boron source. Under a precisely controlled temperature environment, the boron source decomposes at high temperature and reacts with silicon to generate boron atoms, which penetrate into the silicon wafer through diffusion to form a P-type doped layer on the front side of the silicon wafer, thereby forming a PN junction. The sheet resistance on the front side of the boron-doped silicon wafer is controlled at 440Ω / sq. Step 3, Laser Delamination Process: An infrared laser is used to perform laser delamination at the tangent position on the front side of the silicon wafer. The laser action area is... Figure 5At the red line location, by thinning and modifying the borosilicate glass (BSG) layer, the BSG layer thickness is significantly reduced and the microstructure becomes looser, thereby increasing the corrosion rate in alkaline solution. The laser power is set to 70%, and the laser scanning speed is 30,000 mm / s. Maintaining this speed ensures that the CT time meets production capacity requirements, and the width of the laser-affected area is controlled within 800 μm. The infrared laser frequency is 100 kHz, and the laser output power is maintained at 80 W-110 W. At this power, the laser film-opening effect is good, and no PN junction residue remains in the laser area after alkaline washing.
[0026] See Figure 1 The morphology of the laser-treated area after laser film opening is in a molten state under a microscope, and the junction depth of the laser area is 5 μm. The boron doping surface concentration in the laser-treated area of the silicon wafer is reduced from the conventional range of 1E+18 to 1E+19 to the range of 1E+17 to 1E+18. The boron doping surface concentration in the laser area is reduced by 1-2 orders of magnitude. This technology can be flexibly adapted to multi-cell cell architectures such as two-cell and three-cell cells.
[0027] Step 4: BSG Removal and Alkaline Polishing: First, the borosilicate glass (BSG) layer on the edges and back of the silicon wafer is selectively removed using a chain-type machine with hydrofluoric acid (HF) solution. Then, the wafer is transferred to a tank-type machine, passing through a pre-cleaning tank containing alkali and hydrogen peroxide to remove contaminants from the wafer surface. Next, it enters an alkaline polishing tank containing alkaline polishing additives for etching. To achieve an etching depth of 5µm in the laser area, remove the BSG layer in the laser area on the front of the silicon wafer, and further react with the silicon substrate to completely remove the PN junction, the alkaline polishing tank temperature needs to be raised to 80℃ and the alkali concentration adjusted to 2wt%. Under these conditions, a 20µm tower-like structure is simultaneously formed on the back of the silicon wafer, increasing its reflectivity.
[0028] It is worth noting that the current alkaline polishing formula cannot achieve the expected etching depth in the front laser area to remove the PN junction. Therefore, it is necessary to increase the concentration of alkali and the reaction temperature to meet the requirements. Increasing the alkali concentration will lead to an increase in the consumption of alkali chemicals. However, increasing the alkali concentration and reaction temperature will also increase the reaction on the back of the silicon wafer, thereby forming a large tower-like structure on the back of the silicon wafer, which can increase light absorption. In addition to significantly reducing the thickness of the BSG layer and making the microstructure looser, the laser also has a doping effect. The etching depth of the alkaline polishing process in the laser area is insufficient to completely remove the PN junction in the front laser area. In this embodiment, the subsequent RCA process is used to etch the laser area with chemical solutions. Since the BSG layer in the laser area has been removed in the alkaline polishing process, the alkali can continue to further increase the etching depth in the laser area, making the laser area exhibit a tower-like morphology. The etching depth in the laser area is above 4 μm. The two processes work together to ensure that the etching depth in the laser area meets the requirements, thereby achieving the goal of completely removing the PN junction and reducing cutting losses from the source.
[0029] Step 5, Backside Passivation Layer Fabrication: Using low-pressure chemical vapor deposition (LPCVD), an ultrathin tunneling oxide layer and an amorphous silicon film are sequentially grown on the backside of the silicon wafer under precisely controlled low-pressure and high-temperature conditions. The tunneling oxide layer provides good interface passivation and provides tunneling barriers for different charge carriers. The amorphous silicon film deposited on the tunneling oxide layer effectively promotes electron migration rate while suppressing hole migration rate. The thickness of the tunneling oxide layer is 2 nm, and the thickness of the amorphous silicon film is 190 nm.
[0030] Step 6, Phosphorus diffusion process: The silicon wafer after depositing the amorphous silicon thin film is placed in a high-temperature diffusion furnace tube. Phosphorus oxychloride (POCl3) is used as the phosphorus source. Under a precisely controlled high-temperature atmosphere, the amorphous silicon in the amorphous silicon thin film is crystallized into a polycrystalline silicon structure. At the same time, the phosphorus source is effectively doped into the polycrystalline silicon through high-temperature doping to form a phosphorus-doped polycrystalline silicon thin film. The sheet resistance of the phosphorus-doped polycrystalline silicon thin film on the back of the silicon wafer is controlled within the range of 60Ω / sq.
[0031] Step 7, PSG and RCA Removal Cleaning Process: First, the phosphosilicate glass (PSG) layer on the edge and front of the silicon wafer is selectively removed using a chain machine with hydrofluoric acid (HF) solution. Then, it is transferred to a tank machine in an alkaline solution containing RCA additives. The alkaline solution reacts with the silicon wafer surface to remove the polysilicon film coated on the edge and front of the silicon wafer. Potential leakage problems are solved by edge etching, and the laser area on the front is further etched to ensure that the PN junction is completely removed.
[0032] Step 8, Front Passivation Layer Preparation: An aluminum oxide (Al2O3) thin film is precisely deposited on the front side of the silicon wafer using atomic layer deposition (ALD). This aluminum oxide film provides both surface and bulk passivation, thereby improving the open-circuit voltage and short-circuit current of the solar cell, ultimately optimizing and improving the conversion efficiency. The thickness of the aluminum oxide film is 6 nm.
[0033] Step 9, Front-side film preparation process: Using tubular plasma-enhanced chemical vapor deposition (PECVD) technology, hydrogen passivation is performed on the surface of the battery cell after front-side passivation, and a silicon nitride anti-reflection film is deposited. This process achieves hydrogen passivation and optical anti-reflection functions simultaneously by precisely controlling the film thickness within the range of 81nm and the refractive index within the range of 2.02-2.16, effectively improving the surface passivation quality and optimizing the light absorption efficiency.
[0034] Step 10, Backside Film Preparation Process: Using tubular plasma-enhanced chemical vapor deposition (PECVD) technology, hydrogen passivation is performed on the backside of the solar cell, and a silicon nitride antireflection film is deposited. By precisely controlling the film thickness within the range of 85nm and the refractive index within the range of 2.03-2.17, efficient hydrogen passivation is achieved while optimizing the optical properties of the backside.
[0035] Step 11, Metallization Preparation Process: Using screen printing technology, the basic principle is that ink can pass through the mesh openings in the image areas of the screen while ink cannot pass through the mesh openings in the non-image areas. After the screen is squeezed and deformed by a scraper, the metal paste is printed onto the battery cell. Under high temperature conditions, the screen-printed metal paste is sintered to form a metal electrode to collect current. The sintering temperature is 900℃.
[0036] Step 12, Testing and Sorting Process: By conducting comprehensive electrical performance parameter tests on the finished battery cells, and accurately detecting and comparing key indicators such as color characteristics and conversion efficiency according to preset grading standards, the battery cells are finally automatically classified and graded to ensure the consistency of product performance and the controllability of quality.
[0037] In the cell manufacturing process, this invention uses an infrared laser to perform laser film opening treatment on the tangent position of the front side of the silicon wafer after the boron expansion process. The cut area will form a molten morphology. Subsequently, the PN junction in the laser area is removed by alkaline polishing and RCA wet etching processes, thereby solving the cutting damage problem from the source and realizing the improvement of module power.
[0038] Infrared lasers exhibit significant technological advantages in solar cell manufacturing processes. Regarding cost control, this invention fully utilizes existing infrared laser equipment in production lines, eliminating the need for additional investment in newer laser equipment such as green or violet lasers. Given current market conditions, the investment in a single dedicated laser device can reach several million yuan; this solution effectively avoids this expense. In terms of process synergy, the area treated by infrared lasers will form a unique molten morphology (such as...). Figure 1 As shown in the diagram, this microstructural change necessitates a higher alkali concentration in the subsequent etching process. While increasing the alkali concentration increases chemical consumption, it simultaneously promotes the formation of a large-size tower-based structure on the back of the silicon wafer. This morphological feature is beneficial for the deposition quality of the back passivation layer and can also improve the back reflectivity by enhancing light scattering, thereby significantly improving the optical performance of the back of the solar cell. It is worth noting that this technical approach was discovered accidentally by the inventors during experiments. Prior to this invention, those skilled in the art generally believed that the electrical performance loss caused by solar cell cutting was mainly due to the numerous defects generated at the cutting surface. Therefore, the mainstream approach was to use solar cell half-cell passivation technology to passivate the cut solar cells and repair the defects on the cutting surface to reduce the damage caused by cutting. However, the inventors discovered in experiments that the core of the electrical performance loss caused by solar cell cutting originates from the PN junction; the presence of a PN junction at the cutting location is the fundamental reason affecting the open-circuit voltage and fill factor.
[0039] Furthermore, through extensive experimentation, the inventors concluded that when the surface of a boron-expanded silicon wafer is treated with infrared lasers of specific power and scanning speed, a unique molten morphology forms in the cut area. This microstructural change allows subsequent etching processes to completely remove the PN junction. This led the inventors to design a new cell fabrication process that completely removes the PN junction in the cut area from its source through the synergistic effect of infrared laser film opening and subsequent alkaline polishing and RCA wet etching. Compared to traditional techniques that only repair defects on the cut surface, this invention significantly reduces cell cutting damage by completely removing the PN junction in the cut area from its source. This method not only effectively improves the open-circuit voltage and fill factor of the cell module, achieving power enhancement, but also fully utilizes existing laser equipment, avoiding complex half-cell passivation processes and significantly reducing production costs. In addition, the laser treatment is precisely located outside the grid line region, ensuring that electron transport efficiency is not affected, providing a simple and efficient solution for the large-scale application of multi-cell cells.
[0040] Example 2 The method for preparing a solar cell with reduced cutting damage according to this embodiment includes the following steps: Step 1: Pile Making Process First, contaminants on the silicon wafer surface are removed in an alkaline hydrogen peroxide solution in a pre-cleaning tank. Then, the wafer is transferred to a texturing tank, where it reacts in an alkaline solution containing texturing additives to form a pyramid structure on both sides of the wafer, reducing light reflectivity. In this embodiment, the alkaline solution is a sodium hydroxide solution, the temperature is set at 45°C, and the alkaline concentration is set at 1 wt%. These conditions ensure uniform texturing while optimizing surface roughness.
[0041] Step 2, Boron expansion process The texturized silicon wafer is placed in a high-temperature diffusion furnace tube, and boron trichloride is introduced as a boron source to form a PN junction at high temperature. The sheet resistance of the front side of the boron-doped silicon wafer is controlled at 400 Ω / sq to precisely control the doping depth.
[0042] Step 3: Laser film opening process Infrared lasers were used to perform laser-induced thinning of the borosilicate glass layer at the diced area on the front side of the silicon wafer, resulting in a thinner layer and a looser structure. The laser power was set to 40%, the laser speed to a fixed 25000 mm / s, and the laser area width to 100 μm. The infrared laser frequency was 120 kHz, and the power was set to 90 W. The laser-treated area appeared molten under a microscope, with a junction depth of 3 μm.
[0043] Step 4: BSG removal and alkaline polishing process The silicon wafer edges and back borosilicate glass layer were removed using hydrofluoric acid solution, followed by alkaline polishing. The alkaline polishing reaction temperature was set at 50°C, and the alkaline concentration was set at 0.5 wt%. The etching depth of the front laser area was 1 μm, while a 12 μm tower-like structure was simultaneously formed on the back of the silicon wafer. This optimization ensured the initial removal of the PN junction while enhancing back-side light absorption.
[0044] Step 5: Backside passivation layer preparation process A tunneling oxide layer and an amorphous silicon thin film were grown on the back side of a silicon wafer using LPCVD. The tunneling oxide layer was 1 nm thick, and the amorphous silicon thin film was 150 nm thick, to provide excellent interface passivation and carrier transport efficiency.
[0045] Step 6, Phosphorus diffusion process Amorphous silicon is crystallized into a polycrystalline silicon thin film by doping with a phosphorus source. The sheet resistance of the phosphorus-doped polycrystalline silicon thin film on the back side of the silicon wafer is controlled at 40 Ω / sq to ensure doping uniformity.
[0046] Step 7: PSG and RCA cleaning process The phosphosilicate glass layer and the surrounding polycrystalline silicon thin film are removed, and the laser-treated area is then deeply etched. In this embodiment, RCA etching achieves a depth of 4 μm in the laser-treated area, revealing a tower-like morphology and completely removing the PN junction. This step, combined with alkaline polishing, eliminates cutting damage at its source.
[0047] Step 8: Preparation of the front passivation layer An aluminum oxide film was deposited on the front side of a silicon wafer using the ALD method. The aluminum oxide film thickness was 3 nm to optimize the surface passivation effect.
[0048] Step 9: Frontal film preparation process A silicon nitride antireflective film was deposited using PECVD technology. In this embodiment, the silicon nitride film thickness on the front side is 67 nm, achieving both hydrogen passivation and antireflection functions.
[0049] Step 10: Backside film preparation process The back-side silicon nitride antireflective coating is also deposited using PECVD technology. The back-side silicon nitride film is 69 nm thick to ensure the optical performance on the back side.
[0050] Step 11, Metallization Preparation Process Metal electrodes are formed by screen printing and sintering, with the sintering temperature set at 800℃ to ensure electrode adhesion.
[0051] Step 12: Testing and sorting process The finished battery cells undergo electrical performance testing and sorting to ensure consistent quality.
[0052] Example 3 This embodiment provides a method for preparing solar cells with reduced cutting damage, comprising the following steps: Step 1: Pile Making Process In a pre-cleaning tank, an alkaline hydrogen peroxide solution is used to remove contaminants from the silicon wafer surface. The wafer is then transferred to a texturing tank, where it reacts in an alkaline solution containing texturing additives to form a uniform pyramid structure on both sides. In this embodiment, the alkaline solution temperature is set at 60°C and the alkaline concentration at 2.5 wt%, thereby optimizing the surface texture and enhancing light absorption.
[0053] Step 2, Boron expansion process The texturized silicon wafer is placed in a high-temperature diffusion furnace tube, and boron trichloride is introduced as a boron source to form a PN junction under high temperature. In this embodiment, the sheet resistance of the front side of the boron-doped silicon wafer is controlled to be 420 Ω / sq to achieve precise doping depth and junction characteristics.
[0054] Step 3: Laser film opening process An infrared laser was used to perform laser-induced film removal on the diced area of a silicon wafer to modify the borosilicate glass layer structure. The laser power was set to 55%, the laser scanning speed was fixed at 20000 mm / s, and the width of the laser-treated area was 450 μm. The infrared laser frequency was 140 kHz, and the output power was maintained at 120 W. After laser treatment, the junction depth in the treated area was 5 μm, exhibiting a molten state, which effectively improved the efficiency of subsequent etching.
[0055] Step 4: BSG removal and alkaline polishing process First, the edges and back borosilicate glass layer of the silicon wafer were removed using hydrofluoric acid solution, followed by alkaline polishing. The alkaline polishing reaction temperature was set at 65℃, the alkaline solution concentration was 1.25wt%, the etching depth of the front laser area was 2.5µm, and a 16µm tower base structure was simultaneously formed on the back of the silicon wafer to ensure the initial removal of the PN junction and optimize back-side light management.
[0056] Step 5: Backside passivation layer preparation process A tunneling oxide layer and an amorphous silicon film were grown on the back side of a silicon wafer using low-pressure chemical vapor deposition. The tunneling oxide layer was 1.5 nm thick, and the amorphous silicon film was 170 nm thick, providing excellent tunneling passivation and carrier selectivity.
[0057] Step 6, Phosphorus diffusion process Amorphous silicon is crystallized into a polycrystalline silicon thin film by high-temperature doping with a phosphorus source. In this embodiment, the sheet resistance of the phosphorus-doped polycrystalline silicon thin film on the back side of the silicon wafer is controlled to be 50 Ω / sq, ensuring doping uniformity and conductivity.
[0058] Step 7: PSG and RCA cleaning process The phosphorus silicate glass layer and the polycrystalline silicon thin film were removed, and the laser area was deeply etched. RCA etching achieved a etching depth of 6 μm in the laser area and formed a tower-based morphology, completely eliminating the PN junction and removing cutting damage at the source.
[0059] Step 8: Preparation of the front passivation layer An aluminum oxide film with a thickness of 4.5 nm was deposited on the front side of a silicon wafer using atomic layer deposition to enhance the surface passivation effect.
[0060] Step 9: Frontal film preparation process A silicon nitride antireflective coating was deposited using tubular plasma-enhanced chemical vapor deposition (PECVD). The front-side silicon nitride film thickness was 74 nm, achieving synergistic optimization of hydrogen passivation and antireflection.
[0061] Step 10: Backside film preparation process The back-side silicon nitride antireflective coating was also deposited using tubular plasma-enhanced chemical vapor deposition (PECVD). The back-side silicon nitride film thickness was 77 nm, improving the optical performance of the back side.
[0062] Step 11, Metallization Preparation Process Metal electrodes are formed by screen printing and sintering, with the sintering temperature set at 850℃ to ensure electrode adhesion and conductivity.
[0063] Step 12: Testing and sorting process Electrical performance testing and sorting of finished battery cells are conducted to ensure product consistency and quality reliability.
[0064] Example 4 Combination Figure 3 and Figure 4 A photovoltaic cell of this embodiment is prepared by the cell preparation method for reducing cutting loss. The cell includes a silicon substrate 1. The front side of the silicon substrate 1 consists of a P+ emitter 21, an aluminum oxide layer 31, a front silicon nitride layer 41, and a front electrode 51. The front side of the silicon substrate 1 also includes a tunneling oxide layer 22, a phosphorus-doped polycrystalline silicon layer 32, a back silicon nitride layer 42, and a back electrode 52. The cutting position in the middle of the front side of the cell is the laser action area 6. By performing laser film opening treatment in this area, the PN junction is completely removed.
[0065] Example 5 A stacked battery according to this embodiment includes: Top cell, which can be a perovskite cell, cadmium telluride solar cell, copper indium gallium selenide solar cell, or gallium arsenide solar cell; Intermediate connection layer; The bottom cell is the photovoltaic cell described in Example 4; The top battery, the intermediate connecting layer, and the bottom battery are stacked and connected.
[0066] Example 6 A photovoltaic module according to this embodiment includes the photovoltaic cell described in embodiment 4 or the tandem cell described in embodiment 5.
[0067] The above description is merely a selection of preferred embodiments of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this application.
Claims
1. A method for preparing solar cells with reduced cutting losses, characterized in that, Includes the following steps: Laser film-opening treatment is performed on the front cutting position of the silicon wafer after boron diffusion is completed, so that the thickness of the borosilicate glass layer in this area is reduced and the structure is loosened. After laser-etched silicon wafers are processed, alkaline polishing and RCA wet etching are performed to completely remove the PN junction in the front laser area.
2. The method for preparing a solar cell with reduced cutting loss according to claim 1, characterized in that, The laser film-opening process uses an infrared laser.
3. The method for preparing a solar cell with reduced cutting loss according to claim 2, characterized in that, In the infrared laser film-opening process, the laser power is 40-70%, the laser speed is 20000mm / s-30000mm / s, and the laser area width is 100-800um.
4. A method for preparing a battery cell with reduced cutting loss according to claim 2 or 3, characterized in that, The infrared laser film-opening process uses an infrared laser with a frequency of 100kHz-140kHz and a power of 80W or more. The laser-treated area appears to be in a molten state under a microscope, with a junction depth of more than 3µm.
5. The method for preparing a solar cell with reduced cutting loss according to claim 4, characterized in that, The reaction temperature of the alkaline polishing process is 50-80℃, the concentration of the alkaline solution is 0.5-2wt%, the etching depth of the front laser area is 1-4µm, and a tower base structure of 12-20µm is simultaneously formed on the back of the silicon wafer.
6. The method for preparing a solar cell with reduced cutting loss according to claim 5, characterized in that, The RCA wet etching process achieves an etching depth of over 4 μm in the laser region and presents a tower-like morphology, ensuring that the PN junction is completely removed.
7. The method for preparing a solar cell with reduced cutting loss according to claim 6, characterized in that, This includes the following steps performed sequentially: Step 1, Texturing: Texturing is performed on both sides of the silicon wafer to form a pyramid structure to reduce light reflectivity; Step 2, Boron diffusion: A boron source is introduced into the front side of the texturized silicon wafer. The boron source decomposes at high temperature and reacts with silicon to generate boron atoms, which diffuse into the silicon wafer to form a PN junction. Step 3, Laser Deposition: Laser deposition is performed on the cutting position on the front side of the silicon wafer to reduce the thickness of the borosilicate glass layer and loosen its structure; Step 4, BSG removal and alkaline polishing: Remove the borosilicate glass layer from the edge of the silicon wafer and the back side, and remove the BSG layer and PN junction in the front laser area through an alkaline polishing process, while forming a large tower base structure on the back side. Step 5, Backside passivation layer preparation: A tunneling oxide layer and an amorphous silicon thin film are sequentially grown on the backside of the silicon wafer; Step 6, Phosphorus diffusion: Crystallize amorphous silicon into polycrystalline silicon and dope it with phosphorus to form a polycrystalline silicon thin film; Step 7, PSG and RCA removal cleaning: Remove the phosphosilicate glass layer and polysilicon film around the edges and front of the silicon wafer, and perform deep etching on the laser area to ensure that the PN junction is completely removed; Step 8, Preparation of front passivation layer: Deposit an aluminum oxide thin film on the front side of the silicon wafer; Step 9, Front-side film preparation: Deposit a silicon nitride antireflective film on the front side of the silicon wafer; Step 10, Backside Film Preparation: Deposit a silicon nitride antireflection film on the backside of the silicon wafer; Step 11, Metallization preparation: Metal electrodes are formed by screen printing and sintering; Step 12, Testing and Sorting: Test and sort the finished battery cells.
8. The method for preparing a solar cell with reduced cutting loss according to claim 7, characterized in that, The sheet resistance of the boron-doped silicon wafer on the front side is controlled at 400-440 Ω / sq; the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the amorphous silicon thin film is 150-190 nm; the sheet resistance of the phosphorus-doped polycrystalline silicon thin film on the back side of the silicon wafer is controlled at 40-60 Ω / sq.
9. A method for preparing a solar cell with reduced cutting loss according to claim 7, characterized in that, The thickness of the alumina film on the front side of the silicon wafer is 3-6 nm; the thickness of the silicon nitride antireflective coating on the front side is 67-81 nm, with a refractive index of 2.02-2.16; and the thickness of the silicon nitride antireflective coating on the back side is 69-85 nm, with a refractive index of 2.03-2.
17.
10. A photovoltaic cell, characterized in that, The battery cell is prepared by any one of the preparation methods described in claims 1-9, wherein the PN junction at the cut position on the front side of the cell is completely removed.
11. A stacked battery, characterized in that, include: Top cell, which can be a perovskite cell, cadmium telluride solar cell, copper indium gallium selenide solar cell, or gallium arsenide solar cell; Intermediate connection layer; The bottom cell is the photovoltaic cell as described in claim 10; The top battery, the intermediate connecting layer, and the bottom battery are stacked and connected.
12. A photovoltaic module, characterized in that, It includes the photovoltaic cell of claim 10 or the tandem cell of claim 11.