A method for texturing a polysilicon wafer based on metal catalyzed chemical etching

Abstract

The application discloses a kind of based on metal catalytic chemical etching polycrystalline silicon wafer texturing method, it is related to photovoltaic polycrystalline silicon wafer processing technical field;The present application is pretreated to polycrystalline silicon wafer by layering purification treatment process, effectively removes surface impurities and oxide layer, provides clean and uniform substrate for subsequent metal catalytic chemical etching texturing, at the same time, segmented catalytic etching process is used, ensure that the uniform distribution and depth extension of the textured surface light trapping structure, solve the problem that the textured surface structure is not uniform, the depth is inconsistent caused by traditional one-time etching, these improvements significantly improve the texturing quality and consistency, provide a good foundation for subsequent SEM image analysis and reflectivity determination.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic polycrystalline silicon wafer processing technology, specifically a method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching. Background Technology

[0002] With the rapid development of the photovoltaic industry, improving the photoelectric conversion efficiency of solar cells has become the focus of industry attention. As one of the main materials for solar cells, the optimization of the surface structure of polycrystalline silicon wafers is crucial for improving light absorption capacity.

[0003] Traditional polycrystalline silicon wafer texturing technology, especially the one-step etching method, has several shortcomings. First, traditional pretreatment processes often result in incomplete removal or uneven oxide layer removal when removing impurities and oxide layers from the silicon wafer surface, leading to inconsistent texture formation during subsequent texturing processes and affecting overall texturing quality. Second, the one-step etching process makes it difficult to precisely control the etching reaction process, easily causing uneven texture and inconsistent depth, which in turn affects the accuracy of SEM image analysis and the reliability of subsequent reflectivity determination. In addition, traditional technologies lack effective texturing quality feedback and optimization mechanisms, making it difficult to make precise adjustments based on SEM image analysis results, thus limiting production efficiency and product quality.

[0004] To address the problems of incomplete pretreatment, uneven etching, and lack of effective optimization mechanisms based on SEM image analysis in traditional polycrystalline silicon wafer texturing technology, this invention proposes a polycrystalline silicon wafer texturing method based on metal-catalyzed chemical etching, which is of particular importance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching. This method effectively solves the problems of pretreatment and uneven etching in traditional technologies by using a layered purification process and a segmented catalytic etching process, combined with high-precision SEM image acquisition and analysis technology. This significantly improves the texturing quality and consistency. At the same time, the added closed-loop optimization process for texturing achieves precise process optimization based on SEM image morphology features, improving production efficiency and product quality, and providing strong support for the large-scale texturing of photovoltaic polycrystalline silicon wafers.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching, the specific steps of which are as follows: S1. Polycrystalline silicon wafer pretreatment: The polycrystalline silicon wafer is cleaned and dried in sequence to remove surface impurities and oxide layer; S2. Metal-catalyzed chemical etching texturing: The pretreated polycrystalline silicon wafer is immersed in a metal-catalyzed etching solution for constant-temperature catalytic etching to form a textured light-trapping structure. After that, it is taken out, cleaned, and dried. S3. SEM Image Acquisition: Selected areas on the surface of the texturized polycrystalline silicon wafer are captured by scanning electron microscopy to obtain at least 3 sets of SEM images with different fields of view; S4. SEM Image Alignment Processing: The SEM image is preprocessed and aligned using a weighted feature point similarity alignment algorithm to obtain a standardized morphology image without offset. S5. Quantitative calculation of geometric features: Extract the target region from the aligned and standardized morphology image, and calculate the geometric features of the velvet light trapping structure within the selected region. The geometric features include length, angle, perimeter, area, major axis, minor axis, roundness, best ellipse fitting parameters, minimum bounding rectangle fitting parameters, and centroid coordinates. The roundness is calculated using the formula for calculating the roundness of the velvet light trapping structure. S6. Semi-quantitative analysis of reflectivity: Based on geometric features, a textured surface morphology-reflectivity correlation model is constructed to semi-quantitatively determine the quality of silicon wafer reflectivity under the current texturing conditions, and to complete the texturing of polycrystalline silicon wafers.

[0007] Furthermore, the pretreatment of the S1 polycrystalline silicon wafer adopts a layered purification process. The specific steps are as follows: First, the polycrystalline silicon wafer undergoes surface dust pre-cleaning, using airflow to remove loosely attached impurities. Then, a deep cleaning process is performed, first immersing it in a cleaning solution for ultrasonic cleaning, maintaining uniform force during the oscillation to avoid scratches on the silicon wafer surface. After cleaning, it is removed and subjected to acidic oxide layer removal treatment. The silicon wafer is completely immersed in an acidic solution, using a combination of static soaking and slow agitation to ensure that both sides and edges of the wafer are fully in contact with the solution, removing the original oxide layer and passivation layer. Afterward, a neutral rinsing process is performed, repeatedly rinsing the silicon wafer surface using a step-by-step rinsing method to avoid acid residue interfering with subsequent catalytic corrosion. After rinsing... The drying process employs a gradual heating method, first using low-temperature pre-drying to remove surface free moisture, then constant-temperature drying to ensure complete evaporation of internal moisture, and finally cooling to room temperature. The entire pretreatment process ensures the silicon wafer surface is free from external scratches, impurities, and oxide layer regeneration, providing a clean and uniform substrate for subsequent metal-catalyzed chemical etching texturing. This layered purification process solves the problems of incomplete impurity removal and uneven oxide layer removal in traditional pretreatment, effectively improving the consistency of the subsequent textured light-trapping structure and laying the foundation for overall texturing quality. Furthermore, this pretreatment process is highly compatible with subsequent catalytic etching processes, will not damage the silicon wafer substrate, and requires no additional auxiliary reagents, simplifying the operation process while improving pretreatment stability.

[0008] Furthermore, the S2 metal catalytic chemical etching texturing process employs a segmented catalytic etching process. The specific steps are as follows: First, the pre-treated polycrystalline silicon wafer undergoes a catalytic solution pre-wetting treatment. The silicon wafer is slowly immersed in the metal catalytic etching solution to ensure complete wetting of the wafer surface and the absence of air bubbles, avoiding defects in the texturing process caused by areas without catalytic solution contact. After pre-wetting, the first stage of catalytic etching begins. This stage focuses on inducing the nucleation of light-trapping structures, maintaining the stability of the etching system, and allowing metal ions to be uniformly adsorbed on the silicon wafer surface and form catalytically active sites, ensuring a uniform distribution of the subsequent light-trapping structures. After the first stage of etching, the second stage of catalytic etching begins. This stage focuses on expanding the depth and optimizing the morphology of the light-trapping structures, controlling the etching reaction process to allow nucleation sites to form. The process gradually expands into a complete light-trapping structure, avoiding irregular morphology caused by rapid structure formation. After the second stage of etching, a passivation termination stage is initiated, using a termination solution to quickly stop the catalytic etching reaction and prevent excessive etching that could lead to the collapse of the textured surface structure. Immediately afterwards, a cleaning process is performed. First, a rapid rinsing method is used to remove residual etching solution from the surface, followed by deep cleaning to remove adsorbed metal ions and etching products. Finally, a drying process is carried out, avoiding high-temperature damage to the textured surface structure. This segmented catalytic etching process solves the problem of uneven textured surface structure and inconsistent depth caused by traditional one-time etching, effectively improving the regularity of the light-trapping structure and providing a good foundation for subsequent SEM image analysis and reflectivity determination. At the same time, it can effectively control the etching reaction process and reduce the defect rate of the textured surface.

[0009] Furthermore, the S3SEM image acquisition employs a layered multi-field-of-view precise acquisition process. The specific steps are as follows: First, determine the silicon wafer acquisition area, selecting the central and edge regions of the silicon wafer as the core acquisition area to ensure representativeness and reflect the overall textured surface morphology. Next, prepare for acquisition by fixing the textured and dried silicon wafer onto the SEM sample stage, ensuring the wafer is flat and without tilt to avoid distortion during imaging. Then, perform tiered field-of-view settings: first, set a low-magnification field of view for global scanning to determine the effective acquisition area free of defects and impurities. Then, select at least three different sub-fields of view within the effective acquisition area, ensuring each sub-field of view contains sufficient textured light-trapping structures to avoid analysis errors due to insufficient structure quantity in the field of view. During the imaging process, adjust the SEM equipment parameters to ensure image clarity. To meet the analysis requirements, multiple single-field-of-view images are captured, with multiple sets of images taken for each sub-field-of-view. High-quality images without noise or blur are selected, followed by image screening and archiving. Invalid images with shooting distortion, excessive noise, or unclear structure are removed, while high-quality images are retained as the basis for subsequent processing. This layered multi-field-of-view precise acquisition process solves the problems of insufficient image representativeness and limited effective information caused by traditional random acquisition. It ensures that the acquired SEM images can comprehensively reflect the overall morphology of the silicon wafer texture, avoiding errors in subsequent geometric feature calculation and reflectivity determination due to local field-of-view deviations. At the same time, multiple shooting and screening improve image quality, providing a reliable guarantee for subsequent image alignment and feature calculation. Furthermore, this acquisition process is highly adaptable to subsequent image processing workflows, effectively improving overall analysis efficiency.

[0010] Furthermore, the weighted feature point similarity alignment algorithm in S4 is formulated as follows: ,middle To align and adapt the weighting coefficients, For the final alignment similarity, The gray-level feature function of the feature points in the reference image. Let the grayscale feature function be the feature point grayscale feature function at the corresponding position in the image to be aligned. The feature function is the contour feature function of the feature points in the reference image. Let the contour feature function be the feature point contour of the corresponding location in the image to be aligned. For grayscale feature weights, The weights represent the contour features; the parameters and weights in this formula are clearly defined and definite. and The weights are determined based on the light-trapping structure characteristics of the textured surface of polycrystalline silicon wafers. Through feature sensitivity analysis of a large number of textured SEM images, the weight of grayscale features on alignment stability is determined to be... The weight of the contour features on the alignment accuracy is . , and The value of was determined through multiple comparative experiments to ensure that the feature points matched the light-trapping structure of the velvety surface were compatible. To adapt the weighting coefficients, the algorithm dynamically adjusts the density of the velvet structure, calibrating the adaptation coefficients for dense and sparse regions of the light-trapping structure to ensure consistent alignment across different fields of view. The algorithm first extracts the corner points and centroids of the velvet light-trapping structure in the SEM image as core feature points. Then, it calculates the weighted similarity of feature points between the reference image and the image to be aligned using this formula. The position corresponding to the maximum weighted similarity is selected for precise alignment, effectively controlling the alignment error to an extremely low range. This solves the problems of poor adaptability to velvet morphology and large alignment errors in existing algorithms, providing a standardized image basis for subsequent accurate calculation of geometric features. This formula significantly improves the stability and accuracy of SEM image alignment.

[0011] Furthermore, the target region extraction in S5 employs a layered precise extraction process. The specific steps are as follows: First, the aligned, standardized morphology image is preprocessed and optimized to ensure clear distinction between the light-trapping structure and the background. Then, the extraction region is delineated. Based on the distribution characteristics of the textured surface morphology of silicon wafers, multiple independent selected analysis regions are delineated, ensuring clear boundaries for each region to avoid cross-regional interference. Next, preliminary extraction is performed, using contour recognition to extract all suspected light-trapping structures in the image, removing background impurities and invalid noise. Then, the structure validity is determined, screening the pre-extracted structures for validity. The criteria are that the structure has a complete contour, no obvious defects, and no excessive adhesion. Defective structures, adhered structures, and pseudo-structures are removed to ensure that the analysis object is a valid textured light-trapping structure. Structural labeling is performed, marking each effective light-trapping structure after screening to avoid duplicate and missed analyses. Next, region aggregation is conducted, summarizing the effective structures within each selected region to ensure the number of structures analyzed in a single session meets requirements. Finally, feature extraction is prepared by digitizing the labeled effective structures to provide a standardized data carrier for subsequent geometric feature calculations. This hierarchical and precise extraction process solves the problems of structural omission, pseudo-structure interference, and duplicate analysis inherent in traditional target region extraction. It ensures that all extracted light-trapping structures are valid analysis objects, improving the accuracy and reliability of geometric feature calculations. Simultaneously, it effectively controls analysis errors, providing a precise data foundation for subsequent semi-quantitative reflectance determination. Furthermore, this extraction process is adaptable to various subsequent geometric feature calculations, exhibiting strong compatibility.

[0012] Furthermore, the optimal ellipse fitting and minimum bounding rectangle fitting in S5 adopt a step-by-step fitting optimization process. The specific implementation steps are as follows: First, the marked effective velvet light-trapping structures are processed into contour data, and the complete contour coordinate points of each structure are extracted to form a standardized contour dataset. Then, the optimal ellipse fitting is performed. First, the fitting benchmark is determined, with the centroid of the light-trapping structure as the fitting center to avoid fitting deviation. Then, the contour coordinate points are screened, and abnormal coordinate points on the contour edge are removed to avoid fitting distortion caused by abnormal points. After that, the ellipse parameters are iteratively calculated. Through multiple iterations, the fitting parameters are optimized to ensure that the ellipse can fit the contour of the light-trapping structure to the greatest extent. After the fitting is completed, the fitting effect is verified to determine the degree of fit between the fitted ellipse and the structure contour. If the degree of fit does not meet the standard, the iterative calculation is repeated. If the degree of fit meets the standard, the ellipse fitting parameters are recorded. Next, a minimum bounding rectangle fitting is performed. Using the major and minor axes of the fitted ellipse as reference benchmarks, the extreme coordinate points of the structural contour are first determined, and then the range of the bounding rectangle is initially determined based on the extreme points. Then, the rectangle angle is optimized by rotating and adjusting the rectangle angle to ensure that the rectangle is in a minimum bounding state and can fit the actual shape of the light trapping structure. After the fitting is completed, the parameters are verified and the consistency between the ellipse fitting parameters and the rectangle fitting parameters is compared to ensure the accuracy of the fitting results. This step-by-step fitting optimization process solves the problems of large fitting deviation and low fit caused by traditional direct fitting, improves the accuracy of ellipse fitting and rectangle fitting, and ensures that the fitting parameters can truly reflect the geometric characteristics of the light trapping structure, providing a reliable basis for subsequent geometric feature analysis and reflectivity determination. At the same time, this step-by-step fitting process can effectively adapt to light trapping structures with different shapes and has strong adaptability.

[0013] Furthermore, the formula for calculating the roundness of the velvet-textured light-trapping structure in S5 is as follows: ,in The roundness value after correction of the velvet surface light-trapping structure. The two-dimensional projected area of ​​the light-trapping structure. The two-dimensional projected perimeter of the light-trapping structure. The depth correction factor for the light-trapping structure is derived from the three-dimensional characteristics of the textured light-trapping structure on a polycrystalline silicon wafer. Traditional roundness formulas only apply to two-dimensional planar structures, while textured light-trapping structures are three-dimensional. The depth affects the correlation between the actual light-trapping effect and reflectivity; therefore, the depth correction factor is introduced. correction, The determination of the roundness of the light-trapping structure at different depths was achieved through SEM 3D scanning and 2D projection comparison experiments. Correlation analysis was performed to determine the roundness of the light-trapping structure at different depths, and correction factors were calibrated to ensure that the roundness value accurately reflects the regularity of the 3D light-trapping structure. For the two-dimensional projected area, The two-dimensional projection perimeter is extracted from aligned standardized SEM images. The roundness value calculated by this formula can accurately reflect the actual morphological regularity of the velvety light-trapping structure, avoiding the calculation deviation caused by neglecting three-dimensional depth in traditional formulas. This provides accurate data support for subsequent morphology-reflectivity correlation models, and the formula significantly improves the accuracy and relevance of geometric feature calculation.

[0014] Furthermore, the textured surface morphology-reflectivity correlation model in S6 employs a hierarchical and graded judgment process. The specific implementation steps are as follows: First, establish a morphology feature grading standard. Based on the core geometric features of the textured surface light-trapping structure, divide different feature levels and clarify the morphology feature performance corresponding to each level. Then, establish a reflectivity interval correspondence standard, classifying reflectivity into three levels: excellent, good, and poor, clarifying the reflectivity interval corresponding to each level. Next, establish a correlation mapping between morphology features and reflectivity levels. Through numerous comparative experiments, determine the correspondence between different morphology feature levels and reflectivity levels, forming a basic correlation model. Then, optimize the model by introducing a geometric feature collaborative judgment factor to avoid errors caused by single feature judgment, combining multiple core geometric features. Collaborative judgment improves the accuracy of model judgment. A semi-quantitative judgment is then implemented, substituting the geometric feature parameters calculated by S5 into the correlation model. First, a single-feature hierarchical judgment is performed, followed by a multi-feature collaborative judgment. This comprehensive assessment determines the quality level of silicon wafer reflectivity under the current texturing conditions. After the judgment is completed, the results are output, and the core morphological features affecting reflectivity are marked, providing direction for subsequent texturing optimization. This hierarchical judgment process solves the problems of traditional reflectivity judgment relying on direct measurement and being highly subjective. It enables semi-quantitative judgment of reflectivity quality without actual measurement, while also addressing the problem of large errors in single-feature judgment, improving accuracy, effectively predicting texturing quality in advance, avoiding subsequent processing losses of unqualified products, and reducing production costs.

[0015] Furthermore, after the semi-quantitative determination of reflectance in S6 is completed, a closed-loop optimization process for the texturing process is added. The specific implementation steps are as follows: First, the reflectance determination results are classified. For results judged as excellent, the current texturing process parameters and corresponding morphological feature parameters are recorded to form a high-quality process database, providing a reference for subsequent large-scale production. For results judged as good, the core morphological defects affecting reflectance improvement are analyzed to determine targeted optimization directions. No major adjustments to the process are required; only minor adjustments to local parameters are needed. For results judged as poor, the core problems existing in the morphological features are comprehensively analyzed to determine the core links for process optimization. Then, optimization adjustments are made for each link. First, the preceding process steps are traced back to determine the specific process links that lead to morphological defects. Then, the process is optimized for that link. After texturing is completed, the texturing process is repeated. Then, the process of SEM image acquisition, image processing, geometric feature calculation, and reflectivity determination is repeated until the determination result reaches the excellent or good level. During the optimization process, the correspondence between each process adjustment and morphological features and reflectivity is recorded, and the process optimization database is continuously improved. This closed-loop optimization process solves the problems of traditional texturing parameter adjustment relying on experience and being highly blind. It realizes precise process optimization based on morphological features, effectively improving the stability of texturing quality. At the same time, by establishing a process database, it can realize process reuse in large-scale production, improve production efficiency, reduce the fluctuation of texturing surface quality, and adapt to the needs of large-scale texturing of photovoltaic polycrystalline silicon wafers. Moreover, this closed-loop optimization process is highly compatible with the overall texturing method, does not require additional complex equipment, and is easy to promote and apply.

[0016] Compared with existing technologies, this method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching has the following advantages: I. This invention pre-treats polycrystalline silicon wafers through a layered purification process, effectively removing surface impurities and oxide layers, providing a clean and uniform substrate for subsequent metal-catalyzed chemical etching texturing. At the same time, the segmented catalytic etching process ensures the uniform distribution and depth extension of the light-trapping structure on the textured surface, solving the problems of uneven textured surface structure and inconsistent depth caused by traditional one-time etching. These improvements significantly enhance the texturing quality and consistency, providing a good foundation for subsequent SEM image analysis and reflectivity determination.

[0017] Second, this invention adds a closed-loop optimization process for the texturing process. By classifying and processing the reflectivity determination results, corresponding optimization measures are taken for different levels of results, realizing precise process optimization based on morphological characteristics. For results judged as excellent, the current texturing process parameters are recorded to form a high-quality process database; for results judged as good or poor, local parameter fine-tuning or step-by-step optimization is performed until the excellent or good level is achieved. This closed-loop optimization mechanism effectively improves the stability of texturing quality. At the same time, by establishing a process database, process reuse in large-scale production is realized, improving production efficiency, reducing production costs, and adapting to the needs of large-scale texturing of photovoltaic polycrystalline silicon wafers.

[0018] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0020] Figure 1 This is a flow chart of a polycrystalline silicon wafer texturing method based on metal-catalyzed chemical etching. Figure 2 A detailed flow chart of a layered purification pretreatment process for a polycrystalline silicon wafer texturing method based on metal-catalyzed chemical corrosion; Figure 3 This is a detailed flow chart of a segmented catalytic etching texturing process for polycrystalline silicon wafers based on metal-catalyzed chemical etching. Detailed Implementation

[0021] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below. Example

[0022] This embodiment strictly follows the operating procedure of a polycrystalline silicon wafer texturing method based on metal-catalyzed chemical etching, such as... Figure 1 As shown, the specific implementation process is as follows: A layered purification process is used to process a small batch of experimental polycrystalline silicon wafers, such as... Figure 2As shown, this process ensures thorough removal of impurities and oxide layers from the silicon wafer surface through step-by-step purification, laying the foundation for a uniform textured surface in subsequent texturing. First, loosely attached dust and other impurities are removed from the silicon wafer surface via airflow purging. This operation quickly removes easily detachable surface impurities, preventing their re-adhesion in subsequent cleaning stages. Next, the silicon wafer is immersed in a specialized cleaning solution for ultrasonic cleaning. Ultrasonic vibration allows the cleaning solution to penetrate deep into the tiny crevices of the silicon wafer surface, efficiently removing stubborn impurities. Simultaneously, the vibration intensity is strictly controlled to ensure uniform stress on the silicon wafer, preventing surface scratches that could affect the integrity of the subsequent texturing structure. After cleaning, the silicon wafer is completely immersed in an acidic solution using a combination of static immersion and slow agitation, ensuring sufficient contact between the acidic solution and the wafer. On the silicon wafer surface, the native oxide layer and passivation layer are uniformly removed, while avoiding excessive local reactions that could damage the surface. Then, the silicon wafer surface is repeatedly rinsed using a step-by-step rinsing method. By gradually diluting residual chemicals, the cleaning solution and acidic solution adhering to the surface are thoroughly removed, preventing secondary corrosion caused by residual substances. Finally, a drying process is performed. First, a low-temperature pre-drying removes free surface moisture to avoid rapid evaporation and watermarks caused by direct high-temperature drying. Then, a constant-temperature drying process ensures that all internal moisture evaporates, guaranteeing a dry and clean silicon wafer surface. After drying, the wafer is naturally cooled to room temperature to prevent sudden temperature changes from affecting the silicon wafer structure.

[0023] Texturing is performed using a segmented catalytic corrosion process, such as... Figure 3As shown, this process, through precise staged control of the etching process, enables the orderly formation of light-trapping structures from nucleation to optimization, ensuring uniform textured surface morphology and excellent light-trapping effect. First, the pre-treated polycrystalline silicon wafer is slowly immersed in a metal catalytic etching solution to complete the pre-wetting treatment. This step ensures full contact between the silicon wafer surface and the etching solution, guaranteeing uniform initiation of the subsequent etching reaction and avoiding uneven nucleation due to insufficient wetting in localized areas. After pre-wetting, the first stage of catalytic etching begins. This stage focuses on inducing the nucleation of light-trapping structures, maintaining stable parameters such as temperature and concentration in the etching system. This allows metal ions to be uniformly adsorbed on the silicon wafer surface and form catalytically active sites. A stable system environment ensures uniform distribution of active sites, guaranteeing the orderly growth of the subsequent light-trapping structures. After the first stage of etching, the second stage of catalytic etching begins, focusing on the depth expansion and morphology optimization of the light-trapping structures. This is achieved by controlling the etching reaction... The process of time, rate, and other factors allows the nucleation sites to gradually expand into a complete light-trapping structure. Precise control of the reaction process can avoid over- or under-growth of the structure, ensuring that the depth and morphology of the light-trapping structure meet the design requirements. After the second stage of etching, the passivation termination stage begins. A termination solution is used to quickly terminate the catalytic etching reaction, which can precisely control the degree of etching and prevent the reaction from continuing and damaging the already formed light-trapping structure. Then, a cleaning process is immediately carried out. First, the residual etching solution on the surface is removed by rapid rinsing to prevent the residual solution from continuing to corrode the silicon wafer. Then, a deep cleaning is performed to remove the metal ions and etching products adsorbed on the surface, preventing these impurities from affecting the purity of the textured surface and subsequent photoelectric performance. Finally, the silicon wafer is dried to ensure that the textured surface structure is stable and shaped.

[0024] A layered, multi-field-of-view precision acquisition process is employed to acquire images. This process comprehensively and accurately captures the textured surface morphology information of silicon wafers, providing high-quality data support for subsequent image analysis and feature calculation. First, the acquisition area of ​​the silicon wafer is determined. The central and edge areas of each silicon wafer are selected as the core acquisition areas. Covering the key areas of the silicon wafer avoids result deviations caused by local sampling, ensuring that the acquired data reflects the overall texturing quality of the silicon wafer. The texturized and dried silicon wafers are fixed on the SEM sample stage to ensure sample stability during imaging and avoid image blurring due to shaking. Then, the field of view is set in layers. First, a low-magnification field of view is set for a global scan of the silicon wafer to quickly screen out effective acquisition areas free of defects and impurities, improving the targeting and efficiency of subsequent high-magnification imaging. Then, four different sub-fields of view are selected within each effective acquisition area to ensure… Each sub-field of view contains a sufficient amount of velvety light-trapping structures. Sufficient effective structures ensure the statistical reliability of subsequent feature calculations. Before shooting, the voltage, current, and other parameters of the SEM equipment are adjusted to provide hardware support for obtaining clear images. Multiple shots are taken for each sub-field of view, acquiring 5 sets of images for each sub-field of view. High-quality images without noise or blur are selected through multiple shots to reduce the random errors that may exist in a single shot. Finally, images are screened and archived, and invalid images with shooting distortion, excessive noise, or unclear structure are removed. High-quality images are retained as the basis for subsequent processing to ensure that the data used in subsequent analysis is accurate and reliable.

[0025] A weighted feature point similarity alignment algorithm is used to preprocess and align the acquired high-quality SEM images. The formula is as follows: ,middle To align and adapt the weighting coefficients, For the final alignment similarity, The gray-level feature function of the feature points in the reference image. Let the grayscale feature function be the feature point grayscale feature function at the corresponding position in the image to be aligned. The feature function is the contour feature function of the feature points in the reference image. Let the contour feature function be the feature point contour of the corresponding location in the image to be aligned. For grayscale feature weights, Using contour feature weights, this algorithm can eliminate offset errors between images from different fields of view through precise feature point matching, solving image misalignment problems caused by sample placement, slight equipment shaking, etc. during image capture. By weighting grayscale features and contour features in the image, precise positioning and matching of feature points are achieved, thereby completing image calibration and ultimately obtaining a standardized topographic image without offset. This provides accurate and consistent image data support for subsequent target region extraction and geometric feature calculation, avoiding distortion of feature calculation results due to image offset.

[0026] First, a layered precision extraction process is employed to extract the target region. This process accurately separates effective light-trapping structures from background impurities, ensuring the authenticity and validity of the objects for subsequent feature calculations. The aligned, standardized morphology image is preprocessed and optimized to improve image contrast and clarity, facilitating subsequent structure identification. Then, based on the morphological distribution characteristics of the silicon wafer texture, multiple independent selected analysis regions are delineated, each with clear boundaries to avoid confusion between structures in different regions and improve the focus of the analysis. Contour recognition is used to extract all suspected light-trapping structures from the image, while simultaneously removing background impurities and invalid noise to reduce interference from irrelevant information. The effectiveness of the initially extracted structures is assessed, retaining only those with complete contours, no obvious defects, and no excessive adhesion, while discarding incomplete, adhered, and pseudo-structures to ensure that the structures used for calculation meet the analytical requirements. Each of the selected effective light-trapping structures is marked, and the effective structures within each selected region are summarized and statistically analyzed to ensure that the number of structures analyzed in a single instance meets the statistical requirements of the calculation. Finally, the marked effective structures are digitized to provide quantifiable basic data for feature calculations.

[0027] Based on the digitized effective structure, the geometric features of the velvet light-trapping structure within the selected region are calculated, including length, angle, perimeter, area, major axis, minor axis, roundness, optimal ellipse fitting parameters, minimum bounding rectangle fitting parameters, and centroid coordinates. These geometric features can comprehensively quantify the morphology and size of the velvet light-trapping structure. The roundness calculation uses the formula for velvet light-trapping structure roundness calculation, which is: ,in The roundness value after correction of the velvet surface light-trapping structure. The two-dimensional projected area of ​​the light-trapping structure. The two-dimensional projected perimeter of the light-trapping structure. To ensure the accuracy of roundness assessment, a depth correction factor is used for the light-trapping structure. The optimal ellipse fitting and minimum bounding rectangle fitting employ a step-by-step fitting optimization process. This process comprehensively describes the spatial morphology of the light-trapping structure through precise fitting. First, the marked effective textured light-trapping structures are processed for contour data, extracting the complete contour coordinates of each structure to form a standardized contour dataset. When performing optimal ellipse fitting, the centroid of the light-trapping structure is used as the fitting center to ensure the fitting reference closely matches the actual position of the structure. Abnormal coordinate points at the contour edges are eliminated to avoid deviation. Ellipse parameters are then iteratively calculated, and the fitting accuracy is improved through multiple optimizations. After fitting, the fit between the fitted ellipse and the structural contour is verified. If the fit meets the standard, the ellipse fitting parameters are recorded to ensure parameter reliability. Next, minimum bounding rectangle fitting is performed. Using the major and minor axes of the fitted ellipse as references, the extreme coordinates of the structural contour are quickly locked. After initially determining the range of the bounding rectangle, the rectangle angle is adjusted by rotation to fit the actual shape of the light-trapping structure, avoiding excessive deviation between the rectangle fitting and the actual structure. After fitting, the consistency between the ellipse fitting parameters and the rectangle fitting parameters is compared for parameter verification, further ensuring the accuracy of the fitting results.

[0028] A hierarchical and graded judgment process was adopted based on the correlation model between the morphology and reflectivity of the flocking surface. This process can indirectly and accurately determine the quality of reflectivity through morphological characteristics, providing a scientific basis for evaluating the flocking effect. First, a morphological feature grading standard is established, dividing different feature levels based on the core geometric features of the textured light-trapping structure, clarifying the morphological features corresponding to each level, and providing a quantitative basis for subsequent judgment. Next, a reflectivity interval correspondence standard is established, dividing reflectivity into three levels: excellent, good, and poor, clarifying the reflectivity interval corresponding to each level, making the judgment results intuitive and easy to understand. Through numerous comparative experiments, the correspondence between different morphological feature levels and reflectivity levels is determined, forming a basic correlation model. This model can link abstract morphological features with specific reflectivity performance. A geometric feature collaborative judgment factor is introduced to optimize the model, achieving collaborative judgment combining multiple core geometric features, avoiding the limitations of single-feature judgment, and improving the accuracy of the judgment results. The geometric feature parameters calculated by S5 are substituted into the optimized correlation model. First, a single-feature grading judgment is performed to initially screen the reflectivity level range, and then a multi-feature collaborative judgment is performed, comprehensively analyzing the influence weight of each feature to obtain the final result. This comprehensively analyzes the intrinsic relationship between morphology and reflectivity, ultimately determining the quality level of silicon wafer reflectivity under the current texturing conditions. While outputting the judgment results, the core morphological feature factors affecting reflectivity are marked, providing a clear direction for subsequent process optimization.

[0029] The reflectivity assessment results are categorized and processed. Closed-loop optimization is used to continuously improve the process and ensure stable improvement in texturing quality. If the assessment result is excellent, the current texturing process parameters and corresponding morphological feature parameters are recorded and stored in a high-quality process database, providing a mature and reliable process reference for subsequent texturing of silicon wafers of the same specifications. If the assessment result is good, the core morphological defects affecting reflectivity improvement are analyzed, targeted optimization directions are determined, and only local parameter adjustments are made to the texturing process to efficiently improve reflectivity while controlling optimization costs. If the assessment result is poor, the core problems existing in the morphological features are comprehensively analyzed, previous process steps are traced, and the specific process steps leading to morphological defects are accurately located to avoid blind optimization. After optimizing the process of that step, the texturing process is repeated. Then, the SEM image acquisition, image processing, geometric feature calculation, and reflectivity assessment process is repeated until the assessment result reaches the excellent or good level, ensuring that the texturing quality meets the standards. During the optimization process, the correspondence between each process adjustment and morphological features and reflectivity is recorded, continuously improving the process optimization database, accumulating optimization experience, and achieving continuous iterative upgrades of the texturing process.

[0030] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching, characterized in that, The specific steps of this method are as follows: S1. Polycrystalline silicon wafer pretreatment: The polycrystalline silicon wafer is cleaned and dried in sequence to remove surface impurities and oxide layer; S2. Metal-catalyzed chemical etching texturing: The pretreated polycrystalline silicon wafer is immersed in a metal-catalyzed etching solution for constant-temperature catalytic etching to form a textured light-trapping structure. After that, it is taken out, cleaned, and dried. S3. SEM Image Acquisition: Selected areas on the surface of the texturized polycrystalline silicon wafer are captured by scanning electron microscopy to obtain at least 3 sets of SEM images with different fields of view; S4. SEM Image Alignment Processing: The SEM image is preprocessed and aligned using a weighted feature point similarity alignment algorithm to obtain a standardized morphology image without offset. S5. Quantitative calculation of geometric features: Extract the target region from the aligned and standardized morphology image, and calculate the geometric features of the velvet light trapping structure within the selected region. The geometric features include length, angle, perimeter, area, major axis, minor axis, roundness, best ellipse fitting parameters, minimum bounding rectangle fitting parameters, and centroid coordinates. The roundness is calculated using the formula for calculating the roundness of the velvet light trapping structure. S6. Semi-quantitative analysis of reflectivity: Based on geometric features, a textured surface morphology-reflectivity correlation model is constructed to semi-quantitatively determine the quality of silicon wafer reflectivity under the current texturing conditions, and to complete the texturing of polycrystalline silicon wafers.

2. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The pretreatment of the S1 polycrystalline silicon wafer adopts a layered purification process. The specific implementation steps are as follows: First, the surface dust of the polycrystalline silicon wafer is pre-cleaned by airflow sweeping to remove loose adhering impurities. Then, a deep cleaning process is performed by immersing the wafer in a cleaning solution for ultrasonic oscillation cleaning. During the oscillation process, uniform force is maintained to avoid scratches on the surface of the silicon wafer. After cleaning, the wafer is removed and subjected to acidic oxide layer removal treatment. The silicon wafer is completely immersed in an acidic solution and the original oxide layer and passivation layer on the surface are removed by static soaking combined with slow turning. Then, a neutral rinsing process is performed, in which the surface of the silicon wafer is repeatedly rinsed by step-by-step rinsing. After rinsing, the wafer is dried. The drying process adopts a gradual heating method. First, a low-temperature pre-drying is performed to remove free surface moisture. Then, a constant-temperature drying is performed to ensure that the internal moisture is completely evaporated. Finally, the wafer is cooled to room temperature.

3. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The S2 metal catalytic chemical etching texturing process employs a segmented catalytic etching process. The specific steps are as follows: First, the pre-treated polycrystalline silicon wafer undergoes pre-wetting with a catalytic solution. The wafer is slowly immersed in the metal catalytic etching solution. After pre-wetting, the first catalytic etching stage begins. This stage focuses on inducing the nucleation of light-trapping structures, maintaining the stability of the etching system, and allowing metal ions to be uniformly adsorbed on the silicon wafer surface and form catalytically active sites. After the first etching stage, the second catalytic etching stage begins. This stage focuses on expanding the depth and optimizing the morphology of the light-trapping structures. By controlling the etching reaction process, the nucleation sites are gradually expanded into complete light-trapping structures. After the second etching stage, the passivation termination stage begins. A termination solution is used to quickly terminate the catalytic etching reaction. Immediately afterwards, a cleaning process is performed. First, a rapid rinsing method is used to remove residual etching solution from the surface. Then, a deep cleaning process is performed to remove adsorbed metal ions and etching products from the surface. Finally, the wafer is dried.

4. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The S3SEM image acquisition employs a layered multi-field-of-view precision acquisition process. The specific implementation steps are as follows: First, determine the silicon wafer acquisition area, selecting the central and edge areas of the silicon wafer as the core acquisition area. Then, prepare for acquisition by fixing the texturized and dried silicon wafer on the SEM sample stage. Next, perform field-of-view grading settings. First, set a low-magnification field of view for global scanning to determine the effective acquisition area free of defects and impurities. Then, select at least three different sub-fields of view within the effective acquisition area. Each sub-field of view must contain sufficient texturized light-trapping structures. During the shooting process, adjust the SEM equipment parameters first, and then perform multiple shots in a single field of view. Take multiple sets of images in each sub-field of view, and select high-quality images without noise or blur. Then, perform image screening and archiving, removing invalid images with shooting distortion, excessive noise, or unclear structure, and retaining high-quality images as the basis for subsequent processing.

5. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The weighted feature point similarity alignment algorithm in S4 is formulated as follows: ,middle To align and adapt the weighting coefficients, For the final alignment similarity, The gray-level feature function of the feature points in the reference image. Let the grayscale feature function be the feature point grayscale feature function at the corresponding position in the image to be aligned. The feature function is the contour feature function of the feature points in the reference image. Let the contour feature function be the feature point contour of the corresponding location in the image to be aligned. For grayscale feature weights, Weights are assigned to the contour features.

6. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The target region extraction in S5 adopts a layered precise extraction process. The specific implementation steps are as follows: First, the aligned and standardized morphology image is preprocessed and optimized. Then, the extraction region is delineated. Based on the morphology distribution characteristics of silicon wafer texture, multiple independent selected analysis regions are delineated. Each region ensures clear boundaries. Then, preliminary extraction is performed. Contour recognition is used to extract all suspected light-trapping structures in the image, and background impurities and invalid noise are removed. Then, the effectiveness of the structure is judged. The effectiveness of the preliminarily extracted structures is screened. The judgment criteria are that the structure has a complete contour, no obvious defects, and no excessive adhesion. Defective structures, adhered structures, and pseudo-structures are removed. Then, the structure is marked. The effective light-trapping structures after screening are marked one by one. Then, the region is summarized. The effective structures in each selected region are summarized and counted to ensure that the number of structures in a single analysis meets the requirements. Finally, feature extraction preparation is performed. The marked effective structures are digitized.

7. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The optimal ellipse fitting and minimum bounding rectangle fitting in S5 adopt a step-by-step fitting optimization process. The specific implementation steps are as follows: First, the marked effective velvet light trapping structures are processed into contour data, and the complete contour coordinate points of each structure are extracted to form a standardized contour dataset. Then, the optimal ellipse fitting is performed. First, the fitting benchmark is determined, with the centroid of the light trapping structure as the fitting center. Then, the contour coordinate points are screened, and abnormal coordinate points at the contour edge are removed. Then, the ellipse parameters are iteratively calculated. The fitting parameters are optimized through multiple iterations. After the fitting is completed, the fitting effect is verified, and the fit between the fitted ellipse and the structural contour is determined. If the fit is not up to standard, the iterative calculation is repeated. If the fit is up to standard, the ellipse fitting parameters are recorded. Then, the minimum bounding rectangle fitting is performed. The major axis and minor axis of the fitted ellipse are used as reference benchmarks. First, the extreme coordinate points of the structural contour are determined. Then, the range of the bounding rectangle is initially determined based on the extreme points. Then, the rectangle angle is optimized by rotating and adjusting the rectangle angle to fit the actual shape of the light trapping structure. After the fitting is completed, the parameters are verified, and the consistency between the ellipse fitting parameters and the rectangle fitting parameters is compared.

8. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The formula for calculating the roundness of the velvet-like light-trapping structure in S5 is as follows: ,in The roundness value after correction of the velvet surface light-trapping structure. The two-dimensional projected area of ​​the light-trapping structure. The two-dimensional projected perimeter of the light-trapping structure. This is the depth correction factor for the light-trapping structure.

9. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, The textured surface morphology-reflectivity correlation model in S6 adopts a hierarchical and graded judgment process. The specific implementation steps are as follows: First, establish a morphology feature grading standard. Based on the core geometric features of the textured light-trapping structure, divide different feature levels and clarify the morphology feature performance corresponding to each level. Then, establish a reflectivity interval correspondence standard, divide the reflectivity into three levels: excellent, good, and poor, and clarify the reflectivity interval corresponding to each level. After that, establish a correlation mapping between morphology features and reflectivity levels. Through a large number of comparative experiments, determine the correspondence between different morphology feature levels and reflectivity levels, form a basic correlation model, and then optimize the model by introducing a geometric feature collaborative judgment factor. Combine multiple core geometric features for collaborative judgment. Then, implement semi-quantitative judgment by substituting the geometric feature parameters calculated in S5 into the correlation model. First, perform single feature grading judgment, and then perform multi-feature collaborative judgment to comprehensively obtain the quality level of silicon wafer reflectivity under the current texturing conditions. After the judgment is completed, output the judgment result and mark the core morphology feature factors that affect reflectivity.

10. The method for texturing polycrystalline silicon wafers based on metal-catalyzed chemical etching according to claim 1, characterized in that, After the semi-quantitative determination of reflectance in S6 is completed, a closed-loop optimization process for the texturing process is added. The specific implementation steps are as follows: First, the reflectance determination results are classified. For results judged as excellent, the current texturing process parameters and corresponding morphological feature parameters are recorded to form a high-quality process database. For results judged as good, the core morphological defects affecting reflectance improvement are analyzed to determine the targeted optimization direction. No major process adjustments are required; only minor adjustments to local parameters are made. For results judged as poor, the core problems existing in the morphological features are comprehensively analyzed to determine the core links of process optimization. Then, the optimization and adjustment are carried out step by step. First, the previous process steps are traced to determine the specific process links that cause morphological defects. Then, the process is optimized for these links. After optimization, the texturing process is repeated. Then, the SEM image acquisition, image processing, geometric feature calculation and reflectance determination process is repeated until the determination result reaches the excellent or good level. During the optimization process, the correspondence between each process adjustment and morphological features and reflectance is recorded to continuously improve the process optimization database.

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