A BC battery silicon wafer texturing method and BC battery

Abstract

The present application relates to the technical field of solar cells, in particular to a BC cell silicon wafer texturing method and BC cell, the texturing method comprising the following steps: S1, providing a silicon wafer substrate, and performing single-side alkali texturing treatment on the silicon wafer substrate to obtain a pyramid-shaped texturing structure on the surface of the silicon wafer substrate; S2, then placing the silicon wafer substrate in an oxidizing atmosphere and performing thermal oxidation treatment at 600-700 DEG C to grow a 1-5 nm thick sacrificial oxide layer on the surface of the texturing structure; S3, completely removing the sacrificial oxide layer by acid etching to obtain an improved texturing substrate, which can be used for subsequent cell preparation; the method of the present application adds a pretreatment step of growing and removing a sacrificial oxide layer by thermal oxidation before the formal preparation of a cell passivation step, which can effectively repair the lattice damage of the pyramid texturing surface, provides an ideal interface for the deposition of a high-quality passivation layer in subsequent cell preparation, significantly reduces surface recombination, and improves the iVoc and conversion efficiency of the cell.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a method for texturing silicon wafers for BC cells and BC cells. Background Technology

[0002] Back-contact (BC) cells have become a hot research topic in the industry due to their high conversion efficiency and aesthetic appeal. All metal electrodes are located on the back of the cell, maximizing light absorption and utilization. For BC cells, especially in the area on the back where a high-quality PN junction and passivation layer need to be formed, the surface microstructure is crucial.

[0003] Conventional alkaline texturing processes form a pyramidal textured surface on the silicon wafer to reduce reflectivity. However, this textured surface has the following inherent drawbacks: (1) Dense surface defects: The peaks and edges of the pyramids contain high-density dangling bonds, microcracks, and lattice damage, which are serious carrier recombination centers; (2) Sharp and uneven morphology: The overly sharp pyramid apex is prone to electric field concentration, uneven passivation layer thickness, or even poor coverage during subsequent doping (such as phosphorus diffusion) and passivation layer (such as AlOx, SiNx) deposition, which seriously degrades the passivation effect; (3) Cleanliness issues: After texturing, the silicon wafer surface may have residual metal impurities or organic contamination, and traditional cleaning processes are difficult to completely remove contaminants embedded in the microstructure.

[0004] In existing technologies, acid polishing is typically used to passivate the textured surface after texturing (e.g., CN 120568896 A). However, acid polishing is isotropic and reduces the pyramid size. Therefore, the technical problem to be solved by this invention is how to effectively improve the sharp morphology of the alkaline texturing surface structure, repair surface defects and damage, and achieve deep cleaning without sacrificing light absorption, without significantly sacrificing the light absorption capacity of the BC battery. This lays a solid foundation for subsequent passivation processes and ultimately improves the passivation quality and conversion efficiency of the battery. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a method for texturing silicon wafers for BC (Bright Silicon Cell) batteries and a BC battery itself. This invention involves alkaline texturing of the silicon wafer followed by thermal oxidation, and then etching to remove the thermally oxidized layer. This process yields a smoother and more uniform textured surface structure, improving passivation quality while repairing the textured surface, thus providing a high-performance silicon wafer substrate for subsequent BC battery fabrication.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] This invention provides a method for texturing silicon wafers for BC batteries, comprising the following steps:

[0008] S1. Provide a silicon wafer substrate and perform a single-sided alkaline texturing process on it to obtain a pyramid-shaped texturing structure on the surface of the silicon wafer substrate;

[0009] S2. Then, the surface of the textured structure is subjected to thermal oxidation treatment at 600℃-700℃ in an oxidizing atmosphere to grow a 1nm-5nm thick sacrificial oxide layer.

[0010] S3. The sacrificial oxide layer is completely removed by acid etching to obtain the improved textured substrate, which can then be used for subsequent battery fabrication.

[0011] Furthermore, the alkaline texturing process involves etching the silicon wafer substrate with a texturing solution until the texturing reflectivity is within the range of 8%-14%, and controlling the etching amount during the process to be within 0.55g±0.15g.

[0012] Furthermore, the texturing solution is a mixture of potassium hydroxide, polyol, sodium silicate and pure water, wherein the potassium hydroxide accounts for 1wt%-3wt%, the polyol accounts for 0.4%-0.8%, and the sodium silicate accounts for 0.05wt%-0.2wt%.

[0013] Furthermore, the thermal oxidation treatment is carried out in an annealing machine. Oxygen is first introduced for 3-5 minutes, followed by tube-sealing thermal oxidation. The preferred temperature for the thermal oxidation treatment is 650℃-680℃, and the oxidation time is 15-30 minutes. The purpose of choosing an annealing machine for thermal oxidation is to form a denser oxide layer through a "tube-sealing" process under oxygen-free conditions, whereas other machines, such as LPCVD, almost always complete the oxide layer preparation under oxygen-filled conditions. Regarding the process parameters during annealing, since this oxide layer is only a sacrificial layer, it is called a sacrificial oxide layer and does not require a high passivation quality. At the same time, in order to control the growth rate and time of this layer so that it can better meet the "peak shaving and valley filling" effect while saving energy, a relatively low process temperature of 600℃-700℃ is selected.

[0014] Furthermore, the sacrificial oxide layer is removed by corrosion with hydrofluoric acid solution, with a processing time of 100-500 seconds and a processing temperature of 70-90℃, wherein the hydrofluoric acid solution contains 8wt%-10wt% hydrofluoric acid.

[0015] Furthermore, the silicon substrate is N-type or P-type monocrystalline silicon with a resistivity of 10 Ω·cm - 14 Ω·cm and a thickness in the range of 100 micrometers - 200 micrometers. N-type monocrystalline silicon wafers are preferred.

[0016] Another aspect of the present invention provides a BC battery comprising a modified textured substrate prepared by the texturing method described above.

[0017] Furthermore, the improved textured substrate is textured on one side only, with the textured side being the front side. The layers of the battery from the front surface to the back surface are as follows: a silicon nitride layer with a thickness of 70nm-75nm, an aluminum oxide layer with a thickness of 4nm-5nm, a silicon wafer substrate, and an interdigitated NP region. The interdigitated NP region is divided into an N-region structure and a P-region structure. The N-region structure consists of a silicon wafer substrate, a tunnel oxide layer with a thickness of 1nm-2nm, a polycrystalline silicon layer with a thickness of 100nm-150nm, an aluminum oxide layer with a thickness of 4nm-5nm, and a silicon nitride layer with a thickness of 70nm-80nm. The P-region structure consists of a silicon wafer substrate, a tunnel oxide layer with a thickness of 1nm-2nm, a polycrystalline silicon layer with a thickness of 100nm-150nm, an aluminum oxide layer with a thickness of 4nm-5nm, and a silicon nitride layer with a thickness of 70nm-80nm.

[0018] Beneficial technical effects:

[0019] After the alkaline texturing step and before the formal preparation of the battery passivation layer, a pretreatment step of thermal oxidation growth followed by removal of the sacrificial oxide layer is added. The thermal oxidation treatment has the following effects:

[0020] Morphology optimization effect: Through the "tip effect" of thermal oxidation, the sharp textured surface structure becomes smooth and uniform without significantly changing the pyramid size and light absorption capacity, fundamentally avoiding the problems of electric field concentration and poor passivation layer coverage in subsequent processes.

[0021] Surface repair and cleaning effect: The thermal oxidation process can effectively repair the lattice damage of the pyramid textured surface and fix surface contaminants in the sacrificial oxide layer through the "getter" effect. Then, removing the sacrificial oxide layer can achieve deep cleaning and obtain a "cleaner" silicon surface.

[0022] Ultimately, the performance improvement is achieved by providing an ideal interface for the deposition of a high-quality passivation layer in the subsequent battery fabrication, significantly reducing surface recombination, and ultimately resulting in improved battery iVoc and conversion efficiency. Attached Figure Description

[0023] Figure 1 The image shows the SEM image of the textured surface structure of the BC battery silicon wafer textured by the texturing method in Example 1. Detailed Implementation

[0024] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Unless otherwise specifically stated, the numerical values ​​set forth in these embodiments do not limit the scope of the invention. Techniques and methods known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques and methods should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that values ​​expressed, for example, as "within the range of ab" or "between the range of ab," do not include the endpoint values ​​a and b; values ​​expressed as "for ab," "is ab," or "ab" include the endpoint values ​​a and b.

[0026] Experimental methods not specified in the following examples are generally performed according to national standards; if there is no corresponding national standard, they are performed according to general standard requirements or general methods.

[0027] Example 1

[0028] A method for texturing silicon wafers for BC batteries includes the following steps:

[0029] S1. Provide a silicon wafer substrate (N-type monocrystalline silicon, resistivity 10-14 Ω·cm, thickness 135 micrometers), perform single-sided alkaline texturing on its front side (the back side is protected by an oxide layer formed when boron and phosphorus are doped before the alkaline texturing process), use a texturing solution to etch the silicon wafer substrate until the texturing reflectivity is in the range of 11%-14%, and control the etching amount during the process to be controlled at 0.55g±0.05g, wherein the texturing solution is a mixture of potassium hydroxide, isopropanol, sodium silicate and pure water, wherein the proportion of potassium hydroxide is 2wt%, the proportion of isopropanol is 0.7%, the proportion of sodium silicate is 0.1wt%, and the balance to 100wt% is pure water;

[0030] After texturing is completed, a pyramid-shaped texturing structure with a size of 0.8 micrometers to 1.5 micrometers is obtained on the surface of the silicon wafer substrate;

[0031] S2. Then, place it in an annealing machine, first introduce oxygen for 4 minutes, and then perform hot oxidation growth in a closed tube at 670°C for 20 minutes to grow a sacrificial oxide layer of about 3 nm thick on the surface of the velvet structure.

[0032] S3. The sacrificial oxide layer is removed by etching with hydrofluoric acid solution for 250 seconds at a temperature of 80°C. The hydrofluoric acid solution contains 9 wt% hydrofluoric acid and is pure water as the solvent.

[0033] After cleaning and drying, the improved textured substrate is obtained, which can be used for subsequent battery fabrication.

[0034] Example 2

[0035] A method for texturing silicon wafers for BC batteries includes the following steps:

[0036] S1. Provide a silicon wafer substrate (same as in Example 1), and perform alkaline texturing on it. Use a texturing solution to etch the silicon wafer substrate until the texturing reflectivity is within the range of 11%-14%, and control the etching amount during the process to be 0.55g ± 0.05g. The texturing solution is a mixture of potassium hydroxide, isopropanol, sodium silicate, and pure water, wherein the potassium hydroxide accounts for 2wt%, the isopropanol accounts for 0.75%, the sodium silicate accounts for 0.05wt%, and the remainder to 100wt% is pure water.

[0037] After texturing is completed, a pyramid-shaped texturing structure with a size of 0.8 micrometers to 1.5 micrometers is obtained on the surface of the silicon wafer substrate;

[0038] S2. Then, place it in an annealing machine, first introduce oxygen for 3 minutes, and then perform hot oxidation growth in a closed tube at 650°C for 15 minutes to grow a sacrificial oxide layer of about 2 nm thick on the surface of the velvet structure.

[0039] S3. The sacrificial oxide layer is removed by etching with hydrofluoric acid solution for 200 seconds at a temperature of 80°C. The hydrofluoric acid solution contains 10 wt% hydrofluoric acid and is pure water as the solvent.

[0040] After cleaning and drying, the improved textured substrate is obtained, which can be used for subsequent battery fabrication.

[0041] Example 3

[0042] A method for texturing silicon wafers for BC batteries includes the following steps:

[0043] S1. Provide a silicon wafer substrate (same as in Example 1), and perform alkaline texturing on it. Use a texturing solution to etch the silicon wafer substrate until the texturing reflectivity is within the range of 11%-14%, and control the etching amount during the process to be 0.55g ± 0.05g. The texturing solution is a mixture of potassium hydroxide, isopropanol, sodium silicate, and pure water, wherein the proportion of potassium hydroxide is 2wt%, the proportion of isopropanol is 0.65%, the proportion of sodium silicate is 0.15wt%, and the remainder to 100wt% is pure water.

[0044] After texturing is completed, a pyramid-shaped texturing structure with a size of 0.8 micrometers to 1.5 micrometers is obtained on the surface of the silicon wafer substrate;

[0045] S2. Then, place it in an annealing machine, first introduce oxygen for 5 minutes, and then perform hot oxidation growth at 680°C for 30 minutes to grow a sacrificial oxide layer of about 5 nm thick on the surface of the velvet structure.

[0046] S3. The sacrificial oxide layer is removed by etching with hydrofluoric acid solution for 300 seconds at a temperature of 80°C. The hydrofluoric acid solution contains 8 wt% hydrofluoric acid and is pure water as the solvent.

[0047] After cleaning and drying, the improved textured substrate is obtained, which can be used for subsequent battery fabrication.

[0048] Comparative Example 1

[0049] This case only involves the flocking process, and the specific steps are: pre-cleaning, water washing, flocking (the flocking process uses the same parameters as S1 in Example 1), water washing, acid washing (the acid washing uses the same parameters as S3), water washing, slow lifting, and drying.

[0050] Comparative Example 2

[0051] This case follows the method of Example 1 in CN 114784141 A: first alkaline polishing, then thermal oxidation, followed by acid washing, water washing, pre-dehydration, drying, and then flocking (the flocking process uses the same parameters as S1 in Example 1).

[0052] Test case

[0053] BC cells were fabricated using the textured substrates prepared in the examples and comparative examples, respectively. The improved textured substrate in the above examples was textured on one side, with the textured side being the front side. The layers of the BC cell from the front surface to the back surface are as follows: a silicon nitride layer with a thickness of 70nm-75nm, an aluminum oxide layer with a thickness of 4nm-5nm, a silicon wafer substrate, and an interdigitated NP region. The interdigitated NP region is divided into an N-region structure and a P-region structure. The N-region structure consists of a silicon wafer substrate, a tunnel oxide layer with a thickness of 1nm-2nm, a polycrystalline silicon layer with a thickness of 100nm-150nm, an aluminum oxide layer with a thickness of 4nm-5nm, and a silicon nitride layer with a thickness of 70nm-80nm. The P-region structure consists of a silicon wafer substrate, a tunnel oxide layer with a thickness of 1nm-2nm, a polycrystalline silicon layer with a thickness of 100nm-150nm, an aluminum oxide layer with a thickness of 4nm-5nm, and a silicon nitride layer with a thickness of 70nm-80nm.

[0054] The performance of the BC batteries produced in each case is shown in Table 1.

[0055] Table 1 Performance of BC batteries manufactured in each case

[0056]

[0057] As shown in Table 1, the reverse saturation current density J0 of the present invention is smaller than that of the prior art, while the minority carrier lifetime, open-circuit voltage, fill factor, and conversion efficiency are larger than those of the prior art. The textured structure of the textured substrate finally fabricated in Embodiment 1 of the present invention is as follows: Figure 1 As shown, the textured surface structure prepared in Example 1 is more rounded and uniform than that prepared in the original S1 step. Therefore, the method of the present invention adds a pretreatment step of thermal oxidation growth and removal of the sacrificial oxide layer before the formal preparation of the battery passivation step, which can effectively repair the lattice damage of the pyramid textured surface, provide an ideal interface for the subsequent deposition of a high-quality passivation layer, significantly reduce surface recombination, and improve the battery iVoc and conversion efficiency.

[0058] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for texturing silicon wafers for BC batteries, characterized in that, Includes the following steps: S1. Provide a silicon wafer substrate and perform a single-sided alkaline texturing process on it to obtain a pyramid-shaped texturing structure on the surface of the silicon wafer substrate; S2. Then, the surface of the textured structure is subjected to thermal oxidation treatment at 600℃-700℃ in an oxidizing atmosphere to grow a 1nm-5nm thick sacrificial oxide layer. S3. The sacrificial oxide layer is completely removed by acid etching to obtain the improved textured substrate, which can then be used for subsequent battery fabrication.

2. The texturing method for BC battery silicon wafers according to claim 1, characterized in that, The alkaline texturing process involves etching the silicon wafer substrate with a texturing solution until the texturing reflectivity is within the range of 8%-14%, and controlling the etching amount during the process to be within 0.55g±0.15g.

3. The texturing method for BC battery silicon wafers according to claim 1, characterized in that, The texturing solution is a mixture of potassium hydroxide, polyol, sodium silicate and pure water, wherein the potassium hydroxide accounts for 1wt%-3wt%, the polyol accounts for 0.4%-0.8%, and the sodium silicate accounts for 0.05wt%-0.2wt%.

4. The texturing method for BC battery silicon wafers according to claim 1, characterized in that, The thermal oxidation treatment is carried out in an annealing machine. Oxygen is first introduced for 3-5 minutes, followed by hot oxidation in a sealed tube. The temperature of the thermal oxidation treatment is 650℃-680℃, and the oxidation time is 15-30 minutes.

5. The texturing method for silicon wafers used in BC batteries according to claim 1, characterized in that, The sacrificial oxide layer is removed by corrosion with hydrofluoric acid solution, with a processing time of 100-500 seconds and a processing temperature of 70-90℃. The hydrofluoric acid solution contains 8wt%-10wt% hydrofluoric acid.

6. The texturing method for BC battery silicon wafers according to claim 1, characterized in that, The silicon substrate is N-type or P-type monocrystalline silicon with a resistivity of 10 Ω·cm - 14 Ω·cm and a thickness in the range of 100 micrometers to 200 micrometers.

7. A BC battery, characterized in that, Includes a modified napped substrate prepared by the napping method according to any one of claims 1-6.

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