A back contact solar cell, a method of manufacturing the same, and a solar cell module

Abstract

The present application belongs to the technical field of back contact solar cell, and particularly relates to a back contact solar cell, a preparation method thereof and a battery assembly, comprising: at least in the corresponding electrode opening area outside the P-type polysilicon layer, a thin nickel layer, a metal electrode are sequentially arranged, and a conductive film layer is arranged or not arranged between the thin nickel layer and the metal electrode; wherein the thin nickel layer is continuously or discontinuously distributed, and the thin nickel layer is at least one of metal nickel, nickel oxide and nickel-silicon alloy, the maximum thickness of the thin nickel layer is 0.1-5nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polysilicon layer is 1:(100-4000). The present application can significantly improve the carrier transport performance, in the case of using low silver electrode, the open circuit voltage, the minority carrier lifetime and the fill factor are improved, and then the battery efficiency is improved, and the high double side rate can be maintained due to the thin nickel layer; the silver consumption is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of back-contact solar cell technology, specifically relating to a back-contact solar cell, its preparation method, and a battery module. Background Technology

[0002] In the prior art, unlike HBC batteries, TBC batteries adopt a passivated contact structure, that is, they adopt a dual passivated tunneling polycrystalline structure of tunneling oxide layer and N-type polycrystalline silicon, and tunneling oxide layer and P-type polycrystalline silicon. Alumina and / or silicon nitride films are deposited on the back surface of N-type polycrystalline silicon and P-type polycrystalline silicon, and then an electrode opening region is opened outside the alumina and / or silicon nitride film, and a metallic silver electrode is placed in the electrode opening region.

[0003] However, TBC batteries use a structure with metal electrodes in the electrode opening area, which has high contact resistance and low carrier transport efficiency. Since the silver electrode needs to be sintered at high temperature to penetrate the passivation layer to form an ohmic contact, a high silver content must be used to ensure contact and reliability, resulting in a high amount of silver required (the silver content in the metal electrode is more than 90%).

[0004] Moreover, conductive film layers (such as ITO) have advantages such as good light transmittance, excellent conductivity, and reduced silver consumption. However, TBC batteries cannot use the conductive film layer (such as ITO) and metal electrode structure found in HBC batteries because the contact resistance between the P-type polycrystalline silicon and ITO in TBC batteries is too high, which leads to obstructed carrier transport, increased battery series resistance, and a significant decrease in battery efficiency.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0006] The purpose of this invention is to overcome the defect of high silver consumption caused by high contact resistance of the film structure in existing TBC cells. This invention provides a back contact solar cell, its preparation method and cell assembly. This invention can significantly improve carrier transport performance, improve open circuit voltage, minority carrier lifetime and fill factor while using low silver electrodes, thereby improving cell efficiency. At the same time, the thinner nickel layer can maintain a high bifaciality, and the silver consumption is greatly reduced.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a back-contact solar cell, comprising a silicon wafer, N-type semiconductor regions and P-type semiconductor regions alternately disposed on the back side of the silicon wafer, the region between the N-type semiconductor regions and the P-type semiconductor regions being an isolation opening region, and passivation layers disposed outside the N-type semiconductor regions and within the isolation opening region, with electrode opening regions respectively formed on the corresponding passivation layers located outside the N-type semiconductor regions and the P-type semiconductor regions, wherein the N-type semiconductor region includes a first tunneling oxide layer and an N-type polycrystalline silicon layer disposed sequentially from the back side outwards, and the P-type semiconductor region... The P-type semiconductor region includes a second tunneling oxide layer and a P-type polycrystalline silicon layer disposed sequentially from the back side outwards, and further includes: a thin nickel layer, a metal electrode disposed sequentially in at least a corresponding electrode opening region located outside the P-type polycrystalline silicon layer, and a conductive film layer disposed or not disposed between the thin nickel layer and the metal electrode; wherein the thin nickel layer is continuously or discontinuously distributed, and the thin nickel layer is at least one of metallic nickel, nickel oxide, and nickel-silicon alloy, the maximum thickness of the thin nickel layer is 0.1-5 nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000).

[0008] In some preferred embodiments of the present invention, the absolute value of the work function difference between the thin nickel layer and the P-type polycrystalline silicon layer is 0-0.7 eV, and / or the work function of the thin nickel layer is 5.2-5.5 eV.

[0009] In some preferred embodiments of the present invention, the thin nickel layer is a continuously distributed nickel-silicon alloy with a resistivity of 10-20 μΩ·cm.

[0010] In some preferred embodiments of the present invention, the back contact solar cell further includes: a thin nickel layer and a metal electrode sequentially disposed in the corresponding electrode opening region located outside the N-type polycrystalline silicon layer, and a conductive film layer disposed or not disposed between the thin nickel layer and the metal electrode in the corresponding electrode opening region.

[0011] In some preferred embodiments of the present invention, the ratio of the maximum thickness of the corresponding thin nickel layer to the thickness of the N-type polysilicon layer in the corresponding electrode opening region located outside the N-type polysilicon layer is 1:(6-3000).

[0012] In some preferred embodiments of the present invention, a conductive film layer is provided between a thin nickel layer and a metal electrode, wherein the ratio of the maximum thickness of the thin nickel layer to the thickness of the conductive film layer is 1:(4-1600).

[0013] Preferably, the absolute value of the work function difference between the thin nickel layer and the conductive film layer is between 0 and 0.7 eV.

[0014] In some preferred embodiments of the present invention, the thickness of the conductive film layer is 20-160 nm, and / or the conductive film layer is at least one of a transparent conductive film, a metal conductive film, and a metal alloy conductive film.

[0015] In some preferred embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1-2 nm, the thickness of the N-type polycrystalline silicon layer is 30-200 nm, and the thickness of the P-type polycrystalline silicon layer is 100-300 nm.

[0016] In some preferred embodiments of the present invention, the effective doping concentration of the N-type polysilicon layer is greater than 5e18cm. -3 The effective doping concentration of the P-type polycrystalline silicon layer is 2e18cm. -3 -3e20cm -3 .

[0017] In some preferred embodiments of the present invention, the thin nickel layer further contains doping elements, including boron or phosphorus.

[0018] In some preferred embodiments of the present invention, the thin nickel layer contains nickel silicide and / or nickel oxide, wherein the nickel silicide contains at least one selected from Ni2Si, NiSi, and NiSi2.

[0019] In some preferred embodiments of the present invention, the metal electrode may or may not contain silver, and the silver content in the metal electrode is ≤50% by mass; and / or, the passivation layer includes at least one of aluminum oxide, silicon oxide, and silicon nitride.

[0020] In some preferred embodiments of the present invention, the back-contact solar cell further includes at least one of the following structures:

[0021] Structure 1: The width of the isolation opening region is 20-100µm, the width of the N-type semiconductor region is 200-700µm, and the width of the P-type semiconductor region is 300-700µm;

[0022] Structure 2: The back contact solar cell also includes a front passivation and antireflection layer disposed on the front side of the silicon wafer, which includes at least one of amorphous silicon, aluminum oxide, silicon oxide, and silicon nitride.

[0023] Structure 3: The isolation opening area is a texturized surface, while the corresponding areas of the N-type semiconductor region and the P-type semiconductor region are polished surfaces;

[0024] Structure 4: The front side of the silicon wafer is textured.

[0025] Structure 5: A mask layer may or may not be provided between the N-type semiconductor region and the passivation layer, or between the P-type semiconductor region and the passivation layer.

[0026] In a second aspect, the present invention provides a method for preparing a back-contact solar cell, which is used to prepare the back-contact solar cell described in the first aspect. The preparation method includes the following steps:

[0027] S10. Provide a semi-finished battery, which includes a silicon wafer, an N-type semiconductor region and a P-type semiconductor region alternately arranged on the back side of the silicon wafer, an isolation opening region between the N-type semiconductor region and the P-type semiconductor region, and a passivation layer arranged outside the N-type semiconductor region and the P-type semiconductor region and inside the isolation opening region. Electrode opening regions are respectively formed on the corresponding passivation layers located outside the N-type semiconductor region and the P-type semiconductor region. The N-type semiconductor region includes a first tunneling oxide layer and an N-type polycrystalline silicon layer arranged sequentially from the back side outwards, and the P-type semiconductor region includes a second tunneling oxide layer and a P-type polycrystalline silicon layer arranged sequentially from the back side outwards.

[0028] S20. Using a thermal evaporation process or a magnetron sputtering process, a thin nickel layer is formed at least in the corresponding electrode opening region outside the P-type polycrystalline silicon layer on the back side obtained in S10.

[0029] S30. A conductive film layer may or may not be formed on the outside of the thin nickel layer by magnetron sputtering.

[0030] S40. Metal electrodes are formed on the outer surfaces of the corresponding electrode opening regions of the N-type semiconductor region and the P-type semiconductor region, respectively.

[0031] The final thickness of the thin nickel layer is 0.1-5 nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000).

[0032] In some preferred embodiments of the present invention, a conductive film layer is formed in S30, wherein the substrate temperature is controlled to be maintained at 100-200°C during the formation of the conductive film layer; and / or the working pressure for forming the conductive film layer is 0.3-0.8 Pa.

[0033] In some preferred embodiments of the present invention, a thin nickel layer is also provided in the corresponding electrode opening region outside the N-type polysilicon layer in S20.

[0034] In some preferred embodiments of the present invention, S20 includes at least one of the following processes:

[0035] In process 1, the deposition rate using thermal evaporation is 0.02-0.05 nm / s;

[0036] Process 2: Background vacuum <5×10⁻⁶ when using thermal evaporation process -4 Pa;

[0037] Process 3, the conditions for using magnetron sputtering include: the deposition rate is controlled at 0.03-0.08 nm / s, and the substrate temperature is maintained at 150-200℃;

[0038] Process 4: The conditions for using magnetron sputtering include: using a target metal target, introducing argon gas, a process pressure of 0.2-1.0 Pa, and a DC power supply of 20-500 W.

[0039] In some preferred embodiments of the present invention, S20 further includes: first performing a surface pretreatment on the back side obtained in S10 to remove oxides and contaminants from the back side, and then performing the step of forming a thin nickel layer.

[0040] In some preferred embodiments of the present invention, the surface pretreatment is carried out by HF solution immersion or vacuum plasma cleaning. The conditions for HF solution immersion include: HF volume concentration in the HF solution is 0.5%-1%, and immersion time is 10-30 s. The conditions for vacuum plasma cleaning include: in a vacuum environment, in the presence of inert gas, inert gas flow rate is 20-50 sccm, power is 30-80 W, pressure is 0.5-2 Pa, and plasma bombardment cleaning time is 30-60 s.

[0041] In some preferred embodiments of the present invention, S10, the process of providing a semi-finished battery includes:

[0042] S101, Silicon wafers that provide double-sided polishing and cleaning;

[0043] S102. A first semiconductor layer and a first mask layer are formed on the back side of the silicon wafer;

[0044] S103. An etching opening is made on the first semiconductor layer and its corresponding first mask layer on the back side of the silicon wafer to form alternating first semiconductor regions and their outer surfaces corresponding to the first mask layer, and a second semiconductor opening region is formed between adjacent first semiconductor regions.

[0045] S104. Clean and remove the residual first mask layer and first semiconductor layer in the second semiconductor opening area;

[0046] S105. A second semiconductor layer and a second mask layer are formed on the back side of the cleaned silicon wafer; wherein, one of the first semiconductor layer and the second semiconductor layer is N-type and the other is P-type;

[0047] S106. A secondary etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second semiconductor region that is alternately arranged with the first semiconductor region and a second mask layer corresponding to its outer surface, and an isolation opening region is formed between the first semiconductor region and the second semiconductor region.

[0048] S107. By texturing and cleaning, the residual second mask layer and second semiconductor layer in the isolation opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the isolation opening area.

[0049] S108. Perform or not perform the step of removing the first mask layer and the second mask layer;

[0050] S109. Passivation layers are deposited on both the front and back sides of the texturized silicon wafer.

[0051] Thirdly, the present invention provides a battery assembly comprising the back-contact solar cell described in the first aspect.

[0052] Beneficial effects:

[0053] This invention, through the aforementioned technical solution, particularly the structure of a continuous or discontinuous thin nickel layer, a conductive film layer (with or without), and a metal electrode in a TBC battery at least located outside the corresponding electrode opening region outside the P-type polycrystalline silicon layer, replaces the traditional TBC battery structure of a passivation layer (e.g., a silicon nitride / alumina / silicon oxide film) outside the P-type polycrystalline silicon layer and the structure of a silver electrode penetrating the passivation layer through high-temperature sintering to contact the P-type polycrystalline silicon layer. The thin nickel layer can form a low-resistivity nickel silicide with the P-type polycrystalline silicon layer and form an ohmic contact, resulting in high carrier transport efficiency. It allows for the use of a low-silver metal electrode and, with the appropriate maximum thickness of the thin nickel layer and its interaction with the P-type polycrystalline silicon layer, further enhances this advantage. The thin nickel layer, with its high matching compatibility, forms a continuous stepped energy band with the P-type polycrystalline silicon layer, achieving a significant reduction in contact resistance and improved carrier transport performance. This eliminates the need for high-silver electrodes and significantly reduces silver paste consumption. Furthermore, electrode openings are created on the corresponding passivation layers outside the N-type and P-type semiconductor regions. Within these openings, the metal electrode forms ohmic contacts with the N-type and P-type semiconductor regions through the thin nickel layer, eliminating the need for high-temperature sintering after electrode application. This allows for improved open-circuit voltage, minority carrier lifetime, and fill factor, enhancing battery efficiency even with low-silver electrodes. The thin nickel layer also maintains a high bifaciality. Moreover, the metal electrode of this invention can be applied to low-silver electrodes (including non-silver electrodes). The metal electrode can be formed by PVD sputtering, electroplating, or printing (such as silver paste, silver-copper paste, or copper paste), without the need for subsequent high-temperature sintering.

[0054] Further research revealed that the structure of P-type polycrystalline silicon layer in TBC cells cannot use conductive film layer (such as ITO) and silver electrode because the direct contact resistance between P-type polycrystalline silicon layer and conductive film layer (such as ITO) is too high. This is caused by a combination of band mismatch, interfacial interdiffusion and oxidation, and the limitation of intrinsic conductivity of the thin film. Specifically, firstly, from the perspective of band structure, the valence band top of the p-type polycrystalline silicon layer is approximately 5.1-5.2 eV, while the work function of conductive films such as n-type ITO is only 4.6-4.8 eV. This creates a hole Schottky barrier of approximately 0.3-0.5 eV at the interface, hindering hole injection from the p-type polycrystalline silicon layer into the conductive film, directly increasing the contact resistance ρc. Secondly, TBC cells typically undergo high-temperature sintering (400-500℃) after the formation of the silver electrode to penetrate the passivation layer and form an ohmic contact. During this high-temperature sintering process, In and Sn from the conductive film such as ITO diffuse into the p-type polycrystalline silicon layer, causing boron doping compensation and reducing p-type conductivity. Simultaneously, Si from the p-type polycrystalline silicon layer diffuses into the ITO and is oxidized to form SiO. x The high-resistivity interface layer directly leads to unstable and easily increased contact resistance between the P-type polysilicon layer and the conductive film layer (such as ITO). Furthermore, the boron-doped sheet resistance of the P-type polysilicon layer itself is only 30-60Ω / sq, while its resistivity is as high as 500-1000 μΩ・cm. If the film thickness is reduced to thin the light absorption, the sheet resistance and contact resistance will be further increased.

[0055] In this regard, the preferred structure of the thin nickel layer, conductive film layer, and metal electrode in this invention can significantly reduce contact resistance, eliminate the need for high-temperature sintering, further reduce electrode silver consumption, and even allow for the use of silver-free electrodes. Taking a nickel-silicon alloy as an example, the principle is as follows:

[0056] 1. Formation of low-resistivity nickel silicide and ohmic contact: During thin nickel layer deposition, at least part of the Ni near the P-type polysilicon layer reacts with Si in the P-type polysilicon layer to form NiSi. x (e.g., NiSi / NiSi2), NiSi x With a resistivity of only 10-20 μΩ·cm (far lower than the resistivity of 500-1000 μΩ·cm for P-type polycrystalline silicon layers), NiSi / NiSi2 can form an ohmic contact with P-type polycrystalline silicon layers with almost no hole barrier, significantly reducing the contact resistance ρc at the interface (for example, in one specific embodiment, ρc can be reduced from 10 μΩ·cm). - ²Ω・cm² ​​decreased to 10 -4 Ω・cm²-10 -5 Ω・cm²).

[0057] 2. Barrier modulation and bandgap matching: During the deposition of a thin nickel layer, a portion of Ni near the conductive film layer is oxidized to NiO. x (e.g., forming P-type TCO), NiO xThe work function at 5.2-5.5 eV highly matches that of the p-type polycrystalline silicon layer (approximately 5.1-5.2 eV), and it is compatible with conductive films such as ITO, thus forming a p-type polycrystalline silicon layer - NiSi. x -NiO x -ITO continuous stepped energy bands eliminate hole transport barriers and improve carrier transport efficiency.

[0058] 3. Formation of a diffusion barrier layer: A dense Ni / NiSi layer is formed in the nickel-silicon alloy. x Simultaneously, it acts as a diffusion barrier layer, blocking the interdiffusion of In / Sn in conductive films such as ITO with Si in P-type polycrystalline silicon layers, and inhibiting the formation of SiO2 at the interface between the P-type polycrystalline silicon layer and the conductive film layer (such as ITO). x A high-resistivity layer ensures high-temperature stability and guarantees long-term consistency of contact resistance.

[0059] 4. Enhanced conductivity and adhesion: Compared to the adhesion of conductive films such as ITO to P-type polycrystalline silicon layers, thin nickel layers have a stronger adhesion to P-type polycrystalline silicon layers, improving interfacial adhesion. Thin nickel layers can also compensate for insufficient conductivity when thinning P-type polycrystalline silicon layers and reduce series resistance.

[0060] In the preparation method of the present invention, a thin nickel layer is first formed in at least the corresponding electrode opening region outside the P-type polycrystalline silicon layer. The thin nickel layer can form a low-resistivity nickel silicide with the P-type polycrystalline silicon layer. The nickel silicide can form an ohmic contact with the P-type polycrystalline silicon layer, which significantly reduces the contact resistance and further reduces the silver consumption of the electrode, so that a low-silver electrode can be used.

[0061] In the preferred preparation method of the present invention, a structure consisting of a thin nickel layer, a conductive film layer, and a metal electrode is formed sequentially. This structure can utilize the sputtering heat budget of the conductive film layer to promote at least a portion of the thin nickel layer to become more compact, resulting in a thinner layer (when the thin nickel layer is a nickel-silicon alloy, the compaction is manifested in promoting the unreacted metal in the thin nickel layer to further react in situ to generate a metal silicide (such as NiSix) interface layer, thereby forming a more compact thin nickel layer). This is beneficial for significantly reducing contact resistance while maintaining optical transmittance, further reducing the silver consumption of the electrode, and even using a silver-free electrode. The reason for the significant reduction in contact resistance is speculated to be that, taking the thin nickel layer as a nickel-silicon alloy as an example, the S20 thin nickel layer is not a continuous metal silicide (such as NiSix) film formed on the surface of the P-type polycrystalline silicon layer, but a large number of nanoscale metal silicide (such as NiSix) contact islands. After the conductive film layer is sputtered and covered, these islands form a denser thin nickel layer with multiple parallel low-resistance conductive channels. The overall effect is equivalent to a large area of ​​low-resistance contact. This nano-island structure helps to maintain the optical transmittance of the film layer. This nano-island distribution ensures both electrical improvement and minimizes optical loss. Moreover, the work function of the thin nickel layer formed by this method is closer to that of the P-type polycrystalline silicon layer than that of the conductive film layer, which can effectively reduce the hole barrier, significantly reduce the interface contact resistance, thereby improving the open circuit voltage and improving the overall battery efficiency. At the same time, the suitable thin nickel layer ensures sufficient light transmittance on the back side, which also improves the bifaciality of the battery. Moreover, during the sputtering process of the conductive film layer, the unreacted metal in the thin nickel layer further reacts in situ to generate metal silicides to form a dense thin nickel layer. This process consumes only a small portion of the silicon in the P-type polycrystalline silicon layer, effectively avoiding sputtering damage to the P-type polycrystalline silicon layer by the conductive film layer. It does not affect the passivation effect of the semiconductor region, thus ensuring both high overall battery efficiency and bifaciality.

[0062] Preferably, the present invention further controls the substrate temperature during the formation of the conductive film layer to be maintained at 100-200°C. This thermal budget is sufficient to form a denser thin nickel layer, but insufficient to drive the continued deep diffusion of the metal to avoid damage to the passivation layer tunneling through the oxide layer, while ensuring the crystallinity and electrical properties of the conductive film layer. Attached Figure Description

[0063] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 This is a schematic diagram of a specific embodiment of the present invention.

[0065] Explanation of reference numerals in the attached figures

[0066] Silicon wafer 1, first tunneling oxide layer 2, N-type polycrystalline silicon layer 3, second tunneling oxide layer 4, P-type polycrystalline silicon layer 5, back aluminum oxide layer 6, back silicon oxide layer 7, front aluminum oxide layer 8, front silicon oxide layer 9, thin nickel layer 10, conductive film layer 11, silver electrode 12. Detailed Implementation

[0067] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0068] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0069] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0070] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside. During application, light enters from the front of the back-contact solar cell.

[0071] In a first aspect, the present invention provides a back-contact solar cell, comprising a silicon wafer, an N-type semiconductor region and a P-type semiconductor region alternately disposed on the back side of the silicon wafer, the region between the N-type semiconductor region and the P-type semiconductor region being an isolation opening region, and a passivation layer disposed outside the N-type semiconductor region and the P-type semiconductor region but within the isolation opening region, and electrode opening regions respectively formed on the corresponding passivation layers located outside the N-type semiconductor region and the P-type semiconductor region, wherein the N-type semiconductor region includes a first tunneling oxide layer and an N-type polycrystalline silicon layer disposed sequentially from the back side outward, and the P-type semiconductor region includes a second tunneling oxide layer and a P-type polycrystalline silicon layer disposed sequentially from the back side outward, and further comprising: a thin nickel layer and a metal electrode disposed sequentially at least in the corresponding electrode opening region located outside the P-type polycrystalline silicon layer, and a conductive film layer disposed or not disposed between the thin nickel layer and the metal electrode; wherein the thin nickel layer is continuously or discontinuously distributed.

[0072] In this invention, the thin nickel layer can be described as either continuous or discontinuous. This means that the thin nickel layer can be a continuous film, a discontinuous film, or even a discontinuous atomic layer. When the thin nickel layer is discontinuous, its maximum thickness refers to the maximum thickness of the different portions of the nickel layer contained within the discontinuous thin nickel layer. When the thin nickel layer is continuous, its maximum thickness refers to the deposition thickness of the continuous thin nickel layer.

[0073] The thin nickel layer is at least one of metallic nickel, nickel oxide, and nickel-silicon alloy.

[0074] Preferably, the maximum thickness of the thin nickel layer in this invention is 0.1-5 nm, specifically, it can be 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.5 nm, 1.7 nm, 2.0 nm, 2.2 nm, 2.5 nm, 2.8 nm, 3.0 nm, 3.3 nm, 3.5 nm, 3.8 nm, 4.0 nm, 4.2 nm, 4.5 nm, 4.7 nm, 4.9 nm, or 5 nm, or any range between two values. This invention uses a nickel layer of suitable thickness in TBC batteries, which helps reduce optical loss, ensure bifaciality, and achieve low-resistance contact.

[0075] Preferably, the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000), specifically, it can be 1:100, 1:120, 1:150, 1:170, 1:200, 1:220, 1:250, 1:270, 1:300, 1:350, 1:400, 1:450, 1:500, 1:550, 1:600, 1:650, 1:700, 1:750, 1:800, 1:900, 1:1000, 1:1500, 1:2000, 1:2500, 1:3000, 1:3500, or 1:4000, as well as any range between two point values. This invention employs a thin nickel layer and a P-type polycrystalline silicon layer with an appropriate thickness ratio in the TBC battery, which is beneficial for balancing interfacial contact performance and passivation effect.

[0076] In some preferred embodiments of the present invention, the absolute value of the work function difference between the thin nickel layer and the P-type polycrystalline silicon layer is between 0 and 0.7 eV, specifically 0, 0.01 eV, 0.05 eV, 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, 0.3 eV, 0.35 eV, 0.4 eV, 0.45 eV, 0.5 eV, 0.6 eV, 0.65 eV, or 0.7 eV, or any range between any two values. The present invention employs a thin nickel layer and a P-type polycrystalline silicon layer with a small work function difference in the TBC battery, which is beneficial for eliminating the hole transport barrier and improving carrier transport efficiency.

[0077] Preferably, the work function of the thin nickel layer is between 5.2 and 5.5 eV.

[0078] In some preferred embodiments of the present invention, the thin nickel layer is a continuously distributed nickel-silicon alloy. Compared with metallic nickel and nickel oxide, the preferred embodiment of nickel-silicon alloy in the TBC battery of the present invention is more conducive to the formation of ohmic contacts, reducing interface resistance, and improving interface stability.

[0079] More preferably, the resistivity of the continuously distributed nickel-silicon alloy is 10-20 μΩ·cm. The continuously distributed nickel-silicon alloy of this invention has low resistivity, enabling it to form good ohmic contact with the P-type polycrystalline silicon layer in TBC cells, significantly reducing contact resistance.

[0080] In some preferred embodiments of the present invention, the thin nickel layer contains nickel silicide and / or nickel oxide. Nickel silicide facilitates the formation of ohmic contacts with the p-type polysilicon layer. Nickel oxide significantly reduces the potential barrier between the thin nickel layer, the p-type polysilicon layer, and the optional conductive film layer, promoting hole transport and also acting as a diffusion barrier layer to enhance stability.

[0081] More preferably, the nickel silicide contains at least one selected from Ni2Si, NiSi, and NiSi2. Compared to other non-nickel alloys, the present invention uses a preferred Ni2Si-containing nickel silicide, which is more conducive to forming a low-barrier contact interface between the P-type polycrystalline silicon layer and the optional conductive film layer, and between the conductive film layer and the metal electrode.

[0082] In some preferred embodiments of the present invention, the back-contact solar cell further includes: a thin nickel layer and a metal electrode sequentially disposed within the corresponding electrode opening region outside the N-type polycrystalline silicon layer; and a conductive film layer disposed or not disposed between the thin nickel layer and the metal electrode within the corresponding electrode opening region. The present invention also lays a thin nickel layer within the corresponding electrode opening region outside the N-type polycrystalline silicon layer in the TBC cell, which is more conducive to achieving consistent interface contact performance between the N-type semiconductor region and the P-type semiconductor region. The thicknesses of the thin nickel layer outside the N-type polycrystalline silicon layer and the thin nickel layer outside the P-type polycrystalline silicon layer can be the same or different, preferably the same, to simplify the process.

[0083] In some preferred embodiments of the present invention, within the corresponding electrode opening region located outside the N-type polysilicon layer, the ratio of the maximum thickness of the corresponding thin nickel layer to the thickness of the N-type polysilicon layer is 1:(6-3000), more preferably 1:(100-2000). The present invention employs this preferred thickness ratio for the thin nickel layer and the N-type polysilicon layer, which is more conducive to balancing the interface contact performance and passivation effect of the N-type semiconductor region.

[0084] In some preferred embodiments of the present invention, a conductive film layer is provided between the thin nickel layer and the metal electrode.

[0085] More preferably, the ratio of the maximum thickness of the thin nickel layer to the thickness of the conductive film layer is 1:(4-1600), more preferably 1:(100-1600). This invention employs this preferred thickness ratio for the thin nickel layer and the conductive film layer, which is more conducive to balancing conductivity and light transmittance.

[0086] In some preferred embodiments of the present invention, the absolute value of the work function difference between the thin nickel layer and the conductive film layer is between 0 and 0.7 eV, specifically 0, 0.01 eV, 0.05 eV, 0.1 eV, 0.15 eV, 0.2 eV, 0.25 eV, 0.3 eV, 0.35 eV, 0.4 eV, 0.45 eV, 0.5 eV, 0.6 eV, 0.65 eV, or 0.7 eV, or any range between any two points. This preferred scheme is more conducive to realizing a continuous stepped energy band and eliminating the hole transport barrier.

[0087] In some preferred embodiments of the present invention, the thickness of the conductive film layer is 20-160nm, specifically 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 155nm or 160nm, and any range between two point values.

[0088] Preferably, the conductive film layer of this invention is at least one of a transparent conductive film, a metallic conductive film, and a metallic alloy conductive film. More preferably, the transparent conductive film layer is an indium oxide-based thin film doped with at least one of tin, tungsten, titanium, zinc, and gallium, or a zinc oxide-based thin film doped with at least one of aluminum, gallium, and boron. More preferably, the metallic conductive film includes at least one of a nickel layer, an aluminum layer, a copper layer, a silver layer, and a zinc layer. More preferably, the metallic alloy conductive film is at least one of a nickel-copper alloy, a nickel-chromium alloy, and a copper-aluminum alloy.

[0089] In some preferred embodiments of the present invention, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each independently 1-2 nm. The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer may be the same or different in the present invention.

[0090] Preferably, the thickness of the N-type polycrystalline silicon layer in this invention is 30-200 nm.

[0091] Preferably, the thickness of the P-type polycrystalline silicon layer in this invention is 100-300 nm. The TBC battery of this invention, by employing a structure of a P-type polycrystalline silicon layer with low contact resistance, a thin nickel layer, and an optional conductive film layer, allows the P-type polycrystalline silicon layer to be thinned to 100-200 nm to achieve low-resistance contact and high carrier transport efficiency, thereby reducing costs.

[0092] In some preferred embodiments of the present invention, the effective doping concentration of the N-type polysilicon layer is greater than 5e18cm. -3 The effective doping concentration of the P-type polycrystalline silicon layer is 2e18cm. -3 -3e20cm -3 .

[0093] In some preferred embodiments of the present invention, the thin nickel layer further contains doping elements, including boron or phosphorus. This preferred embodiment allows for better control of carrier concentration, improved electron mobility, and reduced resistance, thus contributing to improved stability of the fabrication process and overall battery performance.

[0094] In some preferred embodiments of the present invention, the metal electrode may or may not contain silver. More preferably, the metal electrode is a low-silver electrode, wherein the silver content in the metal electrode is ≤50% by mass. The TBC battery of the present invention, due to the structure of a P-type polycrystalline silicon layer, a thin nickel layer, and an optional conductive film layer, achieves low contact resistance and high carrier transport efficiency, and a low-silver electrode can be used.

[0095] As can be understood in this invention, the metal electrodes are located outside the conductive film layers corresponding to the N-type semiconductor region and the P-type semiconductor region, respectively.

[0096] Preferably, the passivation layer of the present invention comprises at least one of aluminum oxide, silicon oxide, and silicon nitride.

[0097] Preferably, the thickness of the passivation layer is 50-200 nm.

[0098] In some preferred embodiments of the present invention, the width of the isolation opening area is 20-100µm.

[0099] Preferably, the width of the N-type semiconductor region is 200-700µm and the width of the P-type semiconductor region is 300-700µm.

[0100] In some preferred embodiments of the present invention, the back-contact solar cell further includes a front passivation antireflection layer disposed on the front side of the silicon wafer facing outward.

[0101] More preferably, the front passivation antireflection layer includes at least one of amorphous silicon, aluminum oxide, silicon oxide, and silicon nitride. The front passivation antireflection layer and the back passivation layer preferably have the same structure, which simplifies the process and allows for simultaneous deposition.

[0102] Preferably, the thickness of the front passivation antireflection layer in this invention is 50-200 nm.

[0103] In some preferred embodiments of the present invention, the isolation opening area is a textured surface, and the corresponding areas of the N-type semiconductor region and the P-type semiconductor region are polished surfaces.

[0104] In some preferred embodiments of the present invention, the front side of the silicon wafer is a textured surface.

[0105] Preferably, in this invention, a mask layer may or may not be provided between the N-type semiconductor region and the passivation layer, or between the P-type semiconductor region and the passivation layer. The type and thickness of the mask layer can refer to the range in the prior art and can all be used in this invention.

[0106] Secondly, the present invention provides a method for preparing a back-contact solar cell, the method comprising the following steps:

[0107] S10. Provide a semi-finished battery, which includes a silicon wafer, an N-type semiconductor region and a P-type semiconductor region alternately arranged on the back side of the silicon wafer, an isolation opening region between the N-type semiconductor region and the P-type semiconductor region, and a passivation layer arranged outside the N-type semiconductor region and the P-type semiconductor region and inside the isolation opening region. Electrode opening regions are respectively formed on the corresponding passivation layers located outside the N-type semiconductor region and the P-type semiconductor region. The N-type semiconductor region includes a first tunneling oxide layer and an N-type polycrystalline silicon layer arranged sequentially from the back side outwards, and the P-type semiconductor region includes a second tunneling oxide layer and a P-type polycrystalline silicon layer arranged sequentially from the back side outwards.

[0108] S20. Using a thermal evaporation process or a magnetron sputtering process, a thin nickel layer is formed at least in the corresponding electrode opening region outside the P-type polycrystalline silicon layer on the back side obtained in S10.

[0109] S30. A conductive film layer may or may not be formed on the outside of the thin nickel layer by magnetron sputtering.

[0110] S40. Metal electrodes are formed on the outer surfaces of the corresponding electrode opening regions of the N-type semiconductor region and the P-type semiconductor region, respectively.

[0111] The final thickness of the thin nickel layer is 0.1-5 nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000).

[0112] In some preferred embodiments of the present invention, a conductive film layer is formed in S30.

[0113] Preferably, the substrate temperature is maintained at 100-200°C during the formation of the conductive film layer.

[0114] More preferably, the working pressure for forming the conductive film layer is 0.3-0.8 Pa.

[0115] In some preferred embodiments of the present invention, a thin nickel layer is also provided in the corresponding electrode opening region outside the N-type polysilicon layer in S20.

[0116] In some preferred embodiments of the present invention, the preparation method further includes the step of depositing a front passivation antireflection layer on the front side of the silicon wafer. More preferably, the front passivation antireflection layer includes at least one of amorphous silicon, alumina, silicon oxide, and silicon nitride.

[0117] In some preferred embodiments of the present invention, in S20, the deposition rate of the thermal evaporation process is controlled to be 0.02-0.05 nm / s.

[0118] Preferably, the conditions for the thermal evaporation process in this invention include: using a target metal target material and a base vacuum of <5×10⁻⁶. -4 Pa.

[0119] Compared to the thermal evaporation process, the present invention preferably uses magnetron sputtering in S20, which is more conducive to forming a dense and uniform thin nickel layer.

[0120] In some preferred embodiments of the present invention, the conditions for the magnetron sputtering process in S20 include: a deposition rate controlled at 0.03-0.08 nm / s, and / or, a substrate temperature maintained at 150-200°C. The magnetron sputtering process using these preferred process conditions in the present invention is more conducive to forming a dense and uniform thin nickel layer.

[0121] In some preferred embodiments of the present invention, the conditions of the magnetron sputtering process in S20 include: using a target metal target, introducing argon gas, a process pressure of 0.2-1.0 Pa, and a DC power supply of 20-500 W.

[0122] In some preferred embodiments of the present invention, step S20 further includes: first performing a surface pretreatment on the back side obtained in S10 to remove oxides and contaminants from the back side, and then performing the step of forming a thin nickel layer. Surface pretreatment can ensure direct contact between the semiconductor region surface and the thin nickel layer, which is more conducive to the subsequent formation of a high-quality thin nickel layer.

[0123] In some preferred embodiments of the present invention, the surface pretreatment is performed by immersion in HF solution or vacuum plasma cleaning.

[0124] More preferably, the conditions for soaking in the HF solution include: the volume concentration of HF in the HF solution is 0.5%-1%, and the soaking time is 10-30 s.

[0125] More preferably, the conditions for vacuum plasma cleaning include: in a vacuum environment, in the presence of an inert gas, the inert gas flow rate is 20-50 sccm, the power is 30-80 W, the pressure is 0.5-2 Pa, and the plasma bombardment cleaning time is 30-60 s.

[0126] In some preferred embodiments of the present invention, S10, the process of providing a semi-finished battery includes:

[0127] S101, Silicon wafers that provide double-sided polishing and cleaning;

[0128] S102. A first semiconductor layer and a first mask layer are formed on the back side of the silicon wafer;

[0129] S103. An etching opening is made on the first semiconductor layer and its corresponding first mask layer on the back side of the silicon wafer to form alternating first semiconductor regions and their outer surfaces corresponding to the first mask layer, and a second semiconductor opening region is formed between adjacent first semiconductor regions.

[0130] S104. Clean and remove the residual first mask layer and first semiconductor layer in the second semiconductor opening area;

[0131] S105. A second semiconductor layer and a second mask layer are formed on the back side of the cleaned silicon wafer; wherein, one of the first semiconductor layer and the second semiconductor layer is N-type and the other is P-type;

[0132] S106. A secondary etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second semiconductor region that is alternately arranged with the first semiconductor region and a second mask layer corresponding to its outer surface, and an isolation opening region is formed between the first semiconductor region and the second semiconductor region.

[0133] S107. By texturing and cleaning, the residual second mask layer and second semiconductor layer in the isolation opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the isolation opening area.

[0134] S108. Perform or not perform the step of removing the first mask layer and the second mask layer;

[0135] S109. Passivation layers are deposited on both the front and back sides of the texturized silicon wafer. This process uses post-texturing and deposits passivation layers on both sides simultaneously, simplifying the process, reducing manufacturing costs, and ensuring high cell efficiency.

[0136] Thirdly, the present invention provides a battery assembly comprising the back-contact solar cell described in the first aspect.

[0137] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0138] Example 1

[0139] A back-contact solar cell, structure as follows Figure 1 As shown, it is prepared by the following method:

[0140] S10. A semi-finished battery is provided, comprising a silicon wafer 1, with N-type semiconductor regions and P-type semiconductor regions alternately arranged on the back side of the silicon wafer 1, the area between the N-type semiconductor regions and P-type semiconductor regions being an isolation opening region, and passivation layers arranged outside the N-type semiconductor regions and P-type semiconductor regions, inside the isolation opening region, and on the front side (where the back passivation layer is a back aluminum oxide layer 6 and a back silicon oxide layer 7 arranged sequentially, and the front passivation layer is a front aluminum oxide layer 8 and a front silicon oxide layer 9 arranged sequentially, wherein the thickness of the aluminum oxide layer in each passivation layer is 8nm, and the thickness of the silicon oxide layer in each passivation layer is 80nm), and electrode opening regions are respectively formed on the corresponding passivation layers located outside the N-type semiconductor regions and P-type semiconductor regions. The width of the isolation opening region is 100µm, the width of the N-type semiconductor region is 200µm, and the width of the P-type semiconductor region is 500µm. The N-type semiconductor region includes a first tunneling oxide layer 2 (1.2 nm thick) and an N-type polysilicon layer 3 (100 nm thick, with an effective doping concentration of 4e19 cm⁻¹) sequentially disposed from the back side outwards. -3 The P-type semiconductor region includes a second tunneling oxide layer 4 (1.2 nm thick) and a P-type polysilicon layer 5 (100 nm thick, with an effective doping concentration of 3e19 cm⁻¹) disposed sequentially from the back side outwards. -3 );

[0141] The semi-finished battery manufacturing process includes:

[0142] S101, Silicon wafers that provide double-sided polishing and cleaning;

[0143] S102. A P-type first semiconductor layer and a first mask layer (specifically silicon nitride) are formed on the back side of the silicon wafer.

[0144] S103. An etching opening is made on the first semiconductor layer and its corresponding first mask layer on the back side of the silicon wafer to form alternating P-type semiconductor regions and their outer surfaces corresponding to the first mask layer, and a second semiconductor opening region is formed between adjacent P-type semiconductor regions.

[0145] S104. Clean and remove the residual first mask layer and first semiconductor layer in the second semiconductor opening area;

[0146] S105. An N-type second semiconductor layer and a second mask layer (specifically silicon nitride) are formed on the back side of the cleaned silicon wafer.

[0147] S106. A secondary etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form an N-type semiconductor region that is alternately arranged with the P-type semiconductor region and a second mask layer corresponding to its outer surface, and an isolation opening region is formed between the N-type semiconductor region and the P-type semiconductor region.

[0148] S107. By texturing and cleaning, the residual second mask layer and second semiconductor layer in the isolation opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the isolation opening area.

[0149] S108. Remove the first mask layer and the second mask layer;

[0150] S109. Passivation layers are deposited on both the front and back sides of the texturized silicon wafer.

[0151] S20. First, perform surface pretreatment on the back side obtained in S10 to remove oxides and contaminants. The surface pretreatment method is to soak in HF solution with a volume concentration of 0.8% for 15 seconds.

[0152] Then, a discontinuous thin nickel layer 10 (specifically a nickel-silicon alloy layer) is formed on the back side obtained by S10 using a magnetron sputtering process. The conditions for the magnetron sputtering process include: using a target metal target (specifically a nickel target with a mass purity ≥ 99.99%), introducing argon gas at 500 sccm, a process pressure of 0.8 Pa, a DC power supply of 30 W, a substrate temperature of 150℃, and a deposition rate of 0.03 nm / s.

[0153] S30. A conductive film layer 11 (specifically a transparent conductive film ITO with a thickness of 60 nm) is formed on the thin nickel layer 10 by magnetron sputtering (using a transport-while-deposit method); wherein, the magnetron sputtering conditions during the formation of the conductive film layer 11 are controlled as follows: the target material is In by mass percentage. 2 O 3 :SnO 2 ITO with a ratio of 90:10 was deposited to the target thickness at a substrate temperature of 180°C and a working pressure of 0.5 Pa.

[0154] The final thin nickel layer 10, i.e., the nickel-silicon alloy layer, has a maximum thickness of 0.2 nm and a work function of 5.2 eV. The absolute values ​​of the work function difference between the thin nickel layer 10 and the P-type polycrystalline silicon layer 5, and the absolute values ​​of the work function difference between the thin nickel layer 10 and the conductive film layer 11, are 0.1 eV and 0.4 eV, respectively. The ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the P-type polycrystalline silicon layer 5 and the conductive film layer 11 is 1:500:300, and the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the N-type polycrystalline silicon layer 3 is 1:500.

[0155] S40. Silver electrodes 12 (low silver electrodes, silver mass content <50%) are formed on the outer surfaces of the corresponding conductive film layers 11 in the N-type semiconductor region and the P-type semiconductor region, respectively.

[0156] Example 2

[0157] The process was carried out in accordance with Example 1, except that the magnetron sputtering deposition time was extended to adjust the thin nickel layer 10 to be a continuously distributed nickel-silicon alloy with a maximum thickness of 0.5 nm and a resistivity of 15 μΩ·cm. After conversion, the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the P-type polycrystalline silicon layer 5 and the conductive film layer 11 is 1:200:120, and the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the N-type polycrystalline silicon layer 3 is 1:200. The absolute values ​​of the work function difference between the thin nickel layer 10 and the P-type polycrystalline silicon layer 5, and between the thin nickel layer 10 and the conductive film layer 11, are 0.15 eV and 0.45 eV, respectively.

[0158] Example 3

[0159] The experiment was conducted in accordance with Example 1, except that the work function of the thin nickel layer 10 was adjusted to 5.3 eV by changing the deposition rate of the thin nickel layer, while the thickness remained unchanged. After conversion, the absolute values ​​of the work function difference between the thin nickel layer 10 and the P-type polycrystalline silicon layer 5, and the absolute values ​​of the work function difference between the thin nickel layer 10 and the conductive film layer 11, were 0.2 eV and 0.5 eV, respectively.

[0160] Example 4

[0161] The experiment was conducted in accordance with Example 1, except that the thickness of the N-type polysilicon layer 3 was adjusted to 80 nm, while the doping concentration remained unchanged. Calculations showed that the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the N-type polysilicon layer 3 was 1:400.

[0162] Example 5

[0163] The same procedure was followed as in Example 1, except that the thickness of the conductive film 11 was adjusted to 100 nm by extending the magnetron sputtering deposition time. Calculations show that the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the conductive film 11 is 1:500.

[0164] Example 6

[0165] The process was carried out in accordance with Example 1, except that oxygen was introduced during magnetron sputtering to adjust the thin nickel layer 10 to be nickel oxide of the same thickness. In this example, the work function of the final thin nickel layer 10 was 5.4 eV. After conversion, the absolute values ​​of the work function difference between the thin nickel layer 10 and the P-type polycrystalline silicon layer 5, and the absolute values ​​of the work function difference between the thin nickel layer 10 and the conductive film layer 11, were 0.3 eV and 0.6 eV, respectively.

[0166] Example 7

[0167] The process was carried out in accordance with Example 1, except that the conductive film layer 11 was replaced with a composite film layer consisting of a 50 nm thick transparent conductive film layer 11 (specifically ITO) and a 100 nm thick metal conductive film (specifically copper). To meet this condition, the corresponding fabrication process and parameters needed to be adjusted were as follows: in S30, after depositing a 50 nm thick ITO film layer, a 100 nm thick copper metal film was deposited by magnetron sputtering. The absolute value of the work function difference between the thin nickel layer 10 and the conductive film layer 11 was 0.5 eV.

[0168] Example 8

[0169] The procedure was carried out in accordance with Example 1, except that the thickness of the P-type polysilicon layer 5 was adjusted to 150 nm, while the doping concentration remained unchanged. Calculations showed that the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the P-type polysilicon layer 5 was 1:750.

[0170] Example 9

[0171] The same procedure was carried out as in Example 1, except that a conductive film layer 11 was not provided, and instead a low-silver electrode was formed directly on the thin nickel layer 10.

[0172] Comparative Example 1

[0173] The conventional TBC battery structure differs from that of Example 1 in that a thin nickel layer 10 and a conductive film layer 11 are not provided in the electrode opening area, but a silver electrode 12 is directly formed in the electrode opening area.

[0174] Comparative Example 2

[0175] The experiment was conducted with reference to Comparative Example 1, except that silver electrode 12 was a non-low-silver electrode and the silver content in silver electrode 12 was 95%.

[0176] Comparative Example 3

[0177] The same procedure is followed as in Example 1, except that instead of a thin nickel layer 10, a conductive film layer 11 and a low-silver electrode are directly disposed on the outer surfaces of the N-type semiconductor region and the P-type semiconductor region.

[0178] Comparative Example 4

[0179] The same procedure was performed as in Example 1, except that the thickness of the thin nickel layer 10 was adjusted to a normal thickness of 20 nm by significantly extending the magnetron sputtering deposition time.

[0180] Comparative Example 5

[0181] The procedure was carried out in accordance with Example 1, except that the thickness of the P-type polycrystalline silicon layer 5 was set to 10 nm. After calculation, the ratio of the maximum thickness of the thin nickel layer 10 to the thickness of the P-type polycrystalline silicon layer 5 was 1:50.

[0182] Test case

[0183] The back-contact solar cells obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The reduction in silver consumption refers to the degree of relative reduction in silver consumption compared to the conventional structure of Comparative Example 2; for example, the reduction in silver consumption in Example 1 = (silver consumption of Comparative Example 2 - silver consumption of Example 1) / silver consumption of Comparative Example 2 × 100%.

[0184] Table 1

[0185] Performance indicators Open circuit voltage (mV) Minority birth lifetime (µs) Contact resistivity ρc (Ω·cm²) FF (%) Battery efficiency (%) Double-sidedness (%) Reduce silver consumption Example 1 0.7425 1700 0.005 87.5 27.22 78 Reduce by 50% Example 2 0.7423 1652 0.008 87.2 27.18 77 49% reduction Example 3 0.7424 1640 0.007 87.3 27.19 78 Reduce by 50% Example 4 0.7422 1670 0.008 87.1 27.17 78 48% reduction Example 5 0.7421 1652 0.006 87.4 27.10 77 49% reduction Example 6 0.7423 1683 0.007 87.3 27.18 77 49% reduction Example 7 0.7420 1652 0.005 87.2 27.17 76 48% reduction Example 8 0.7424 1686 0.005 87.4 27.20 76 49% reduction Example 9 0.7423 1655 0.007 87.1 27.17 78 Reduce by 50% Comparative Example 1 0.7438 1555 0.074 84.75 26.13 62 Reduced by 45% Comparative Example 2 0.7420 1616 0.025 86.35 27.03 61 No reduction Comparative Example 3 0.7439 1588 0.035 86.04 26.85 63 46% reduction Comparative Example 4 0.712 512 0.156 78.56 21.35 52 Reduced by 45% Comparative Example 5 0.702 882 0.105 80.55 22.91 58 Reduced by 45%

[0186] The results above show that, compared to the comparative example, the embodiment of the present invention significantly improves carrier transport performance, enhancing open-circuit voltage, minority carrier lifetime, and fill factor even with low-silver electrodes, thereby improving battery efficiency. Simultaneously, the thinner nickel layer maintains a high bifaciality. Furthermore, the present invention is applicable to low-silver electrodes, significantly reducing silver consumption.

[0187] Furthermore, as can be seen from Examples 1 and 2-9, the preferred scheme of the present invention is more conducive to improving battery efficiency and bifaciality when using low silver electrodes.

[0188] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A back-contact solar cell, comprising a silicon wafer, N-type semiconductor regions and P-type semiconductor regions alternately disposed on the back side of the silicon wafer, the region between the N-type semiconductor regions and the P-type semiconductor regions being an isolation opening region, and passivation layers disposed outside the N-type semiconductor regions and within the isolation opening region, and electrode opening regions respectively formed on the corresponding passivation layers located outside the N-type semiconductor regions and the P-type semiconductor regions, wherein the N-type semiconductor regions include a first tunneling oxide layer and an N-type polycrystalline silicon layer disposed sequentially from the back side outwards, and the P-type semiconductor regions include a second tunneling oxide layer and a P-type polycrystalline silicon layer disposed sequentially from the back side outwards, characterized in that, Also includes: A thin nickel layer, a metal electrode, and a conductive film layer (with or without a conductive film layer) are sequentially disposed within the corresponding electrode opening region outside the P-type polycrystalline silicon layer. The thin nickel layer may be continuously or discontinuously distributed, and is at least one of metallic nickel, nickel oxide, or a nickel-silicon alloy. The maximum thickness of the thin nickel layer is 0.1-5 nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000). The absolute value of the work function difference between the thin nickel layer and the P-type polycrystalline silicon layer is 0-0.7 eV, and / or the work function of the thin nickel layer is 5.2-5.5 eV.

2. The back-contact solar cell according to claim 1, characterized in that, The thin nickel layer is a continuously distributed nickel-silicon alloy with a resistivity of 10-20 μΩ·cm.

3. The back-contact solar cell according to claim 1, characterized in that, The back-contact solar cell also includes: a thin nickel layer and a metal electrode sequentially disposed in the corresponding electrode opening region outside the N-type polycrystalline silicon layer, and a conductive film layer disposed or not disposed between the thin nickel layer and the metal electrode in the corresponding electrode opening region.

4. The back-contact solar cell according to claim 3, characterized in that, In the corresponding electrode opening region located outside the N-type polysilicon layer, the ratio of the maximum thickness of the corresponding thin nickel layer to the thickness of the N-type polysilicon layer is 1:(6-3000).

5. The back-contact solar cell according to claim 1 or 3, characterized in that, A conductive film layer is disposed between a thin nickel layer and a metal electrode, wherein the ratio of the maximum thickness of the thin nickel layer to the thickness of the conductive film layer is 1:(4-1600).

6. The back-contact solar cell according to claim 5, characterized in that, The absolute value of the work function difference between the thin nickel layer and the conductive film layer is 0-0.7 eV.

7. The back-contact solar cell according to claim 5, characterized in that, The thickness of the conductive film is 20-160 nm, and the conductive film is at least one of transparent conductive film, metal conductive film, and metal alloy conductive film.

8. The back-contact solar cell according to claim 1, characterized in that, The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are each 1-2 nm, the thickness of the N-type polysilicon layer is 30-200 nm, and the thickness of the P-type polysilicon layer is 100-300 nm. And / or, the effective doping concentration of the N-type polysilicon layer is greater than 5e18cm. -3 The effective doping concentration of the P-type polycrystalline silicon layer is 2e18cm. -3 -3e20cm -3 .

9. The back-contact solar cell according to claim 1, characterized in that, The thin nickel layer also contains doping elements, including boron or phosphorus.

10. The back-contact solar cell according to claim 1, characterized in that, The thin nickel layer contains nickel silicide and / or nickel oxide, wherein the nickel silicide contains at least one selected from Ni2Si, NiSi, and NiSi2.

11. The back-contact solar cell according to claim 1, characterized in that, The metal electrode may or may not contain silver, and the silver content in the metal electrode is ≤50% by mass; and / or, the passivation layer includes at least one of aluminum oxide, silicon oxide, and silicon nitride.

12. The back-contact solar cell according to claim 1, characterized in that, Back-contact solar cells also include at least one of the following structures: Structure 1: The width of the isolation opening region is 20-100µm, the width of the N-type semiconductor region is 200-700µm, and the width of the P-type semiconductor region is 300-700µm; Structure 2: The back contact solar cell also includes a front passivation and antireflection layer disposed on the front side of the silicon wafer, which includes at least one of amorphous silicon, aluminum oxide, silicon oxide, and silicon nitride. Structure 3: The isolation opening area is a texturized surface, while the corresponding areas of the N-type semiconductor region and the P-type semiconductor region are polished surfaces; Structure 4: The front side of the silicon wafer is textured. Structure 5: A mask layer may or may not be provided between the N-type semiconductor region and the passivation layer, or between the P-type semiconductor region and the passivation layer.

13. A method for preparing a back-contact solar cell, characterized in that, It is used to prepare a back-contact solar cell as described in any one of claims 1-12, and the preparation method includes the following steps: S10. Provide a semi-finished battery, which includes a silicon wafer, an N-type semiconductor region and a P-type semiconductor region alternately arranged on the back side of the silicon wafer, an isolation opening region between the N-type semiconductor region and the P-type semiconductor region, and a passivation layer arranged outside the N-type semiconductor region and the P-type semiconductor region and inside the isolation opening region. Electrode opening regions are respectively formed on the corresponding passivation layers located outside the N-type semiconductor region and the P-type semiconductor region. The N-type semiconductor region includes a first tunneling oxide layer and an N-type polycrystalline silicon layer arranged sequentially from the back side outwards, and the P-type semiconductor region includes a second tunneling oxide layer and a P-type polycrystalline silicon layer arranged sequentially from the back side outwards. S20. Using a thermal evaporation process or a magnetron sputtering process, a thin nickel layer is formed at least in the corresponding electrode opening region outside the P-type polycrystalline silicon layer on the back side obtained in S10. S30. A conductive film layer may or may not be formed on the outside of the thin nickel layer by magnetron sputtering. S40. Metal electrodes are formed on the outer surfaces of the corresponding electrode opening regions of the N-type semiconductor region and the P-type semiconductor region, respectively. The final thickness of the thin nickel layer is 0.1-5 nm, and the ratio of the maximum thickness of the thin nickel layer to the thickness of the P-type polycrystalline silicon layer is 1:(100-4000).

14. The method for preparing a back-contact solar cell according to claim 13, characterized in that, A conductive film layer is formed in S30, wherein... The substrate temperature is controlled to be maintained at 100-200℃ during the formation of the conductive film layer; and / or the working pressure for forming the conductive film layer is 0.3-0.8 Pa.

15. The method for preparing a back-contact solar cell according to claim 13, characterized in that, In S20, a thin nickel layer is also provided in the corresponding electrode opening region located outside the N-type polycrystalline silicon layer.

16. The method for preparing a back-contact solar cell according to claim 13, characterized in that, S20 includes at least one of the following processes: In process 1, the deposition rate using thermal evaporation is 0.002-0.05 nm / s; Process 2: Background vacuum <5×10⁻⁶ when using thermal evaporation process -4 Pa; Process 3, the conditions for using magnetron sputtering include: deposition rate controlled at 0.003-0.08 nm / s, and substrate temperature maintained at 150-200℃; Process 4: The conditions for using magnetron sputtering include: using a target metal target, introducing argon gas, a process pressure of 0.2-1.0 Pa, and a DC power supply of 20-500 W.

17. The method for preparing a back-contact solar cell according to claim 13, characterized in that, S20 also includes: first performing surface pretreatment on the back side obtained in S10 to remove oxides and contaminants on the back side, and then performing the step of forming a thin nickel layer.

18. The method for preparing a back-contact solar cell according to claim 17, characterized in that, Surface pretreatment methods include immersion in HF solution or vacuum plasma cleaning, wherein... The conditions for soaking in HF solution include: the volume concentration of HF in the HF solution is 0.5%-1%, and the soaking time is 10-30 s; The conditions for vacuum plasma cleaning include: in a vacuum environment, in the presence of an inert gas, with an inert gas flow rate of 20-50 sccm, a power of 30-80 W, a pressure of 0.5-2 Pa, and a plasma bombardment cleaning time of 30-60 s.

19. The method for preparing a back-contact solar cell according to claim 13, characterized in that, S10, The process of providing semi-finished batteries includes: S101, Silicon wafers that provide double-sided polishing and cleaning; S102. A first semiconductor layer and a first mask layer are formed on the back side of the silicon wafer; S103. An etching opening is made on the first semiconductor layer and its corresponding first mask layer on the back side of the silicon wafer to form alternating first semiconductor regions and their outer surfaces corresponding to the first mask layer, and a second semiconductor opening region is formed between adjacent first semiconductor regions. S104. Clean and remove the residual first mask layer and first semiconductor layer in the second semiconductor opening area; S105. A second semiconductor layer and a second mask layer are formed on the back side of the cleaned silicon wafer; wherein, one of the first semiconductor layer and the second semiconductor layer is N-type and the other is P-type; S106. A secondary etching opening is made on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second semiconductor region that is alternately arranged with the first semiconductor region and a second mask layer corresponding to its outer surface, and an isolation opening region is formed between the first semiconductor region and the second semiconductor region. S107. By texturing and cleaning, the residual second mask layer and second semiconductor layer in the isolation opening area are removed, and a textured surface is formed on the front side of the silicon wafer and the isolation opening area. S108. Perform or not perform the step of removing the first mask layer and the second mask layer; S109. Passivation layers are deposited on both the front and back sides of the texturized silicon wafer.

20. A battery assembly, characterized in that, It includes a back-contact solar cell as described in any one of claims 1-12.

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