Photovoltaic cell and method of manufacturing the same, photovoltaic module

Abstract

The present disclosure relates to the field of photovoltaics, and provides a photovoltaic cell, a manufacturing method thereof, and a photovoltaic module. The photovoltaic cell comprises a substrate having a front surface and a back surface opposite to each other along a first direction, the first direction being a thickness direction of the substrate; a first intrinsic layer located on the front surface, the first intrinsic layer comprising a first layer and a second layer located on a side of the first layer away from the substrate, a material of the first layer comprising intrinsic amorphous silicon, and a material of the second layer comprising oxygen-doped intrinsic amorphous silicon; and a first doped layer located on a side of the second layer away from the first layer, the first doped layer and the substrate being doped with a same type of doping element. The present disclosure is at least beneficial to improving photoelectric conversion efficiency of the front surface of the photovoltaic cell.

Description

Technical Field

[0001] This disclosure relates to the photovoltaic field, and in particular to a photovoltaic cell and its manufacturing method, and a photovoltaic module. Background Technology

[0002] With the rapid development of photovoltaic technology, photovoltaic power generation has been widely used as a sustainable and clean energy source. Among them, crystalline silicon (monocrystalline or polycrystalline) cells have a high market share.

[0003] There are many types of crystalline silicon solar cells. Compared to other types, heterojunction with intrinsic thin-film (HIT or HJT) cells exhibit higher photoelectric performance among crystalline silicon cells. They have attracted widespread attention due to their excellent photoelectric conversion efficiency, fewer fabrication steps, low temperature coefficient, and high bifaciality. The photoelectric conversion efficiency of heterojunction cells is mainly affected by electrical and optical factors. Electrically, it is primarily influenced by the recombination of charge carriers at the interfaces between crystalline and amorphous silicon, between amorphous and microcrystalline silicon, and between microcrystalline silicon and the transparent conductive layer. It is also affected by the transport resistance encountered by charge carriers in each film layer.

[0004] Therefore, in order to improve the photoelectric conversion efficiency of heterojunction solar cells, it is necessary to study the composition of each film layer structure. Summary of the Invention

[0005] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the front side of the photovoltaic cell.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a photovoltaic cell, comprising: a substrate having a front side and a back side opposite to each other along a first direction, the first direction being the thickness direction of the substrate; a first intrinsic layer located on the front side, the first intrinsic layer comprising a first layer and a second layer located on the side of the first layer away from the substrate, the material of the first layer comprising intrinsic amorphous silicon, and the material of the second layer comprising oxygen-doped intrinsic amorphous silicon; and a first doped layer located on the side of the second layer away from the first layer, the first doped layer and the substrate being doped with the same type of doping element.

[0007] In some embodiments, the photovoltaic cell further includes: a second intrinsic layer located on the back side; a second doped layer located on the side of the second intrinsic layer away from the substrate, wherein the second doped layer and the substrate are doped with different types of doping elements; a first transparent conductive layer located on the side of the first doped layer away from the second layer; a first electrode located on the side of the first transparent conductive layer away from the first doped layer; a second transparent conductive layer located on the side of the second doped layer away from the second intrinsic layer; and a second electrode located on the side of the second transparent conductive layer away from the second doped layer.

[0008] In some embodiments, the second intrinsic layer includes a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer stacked along the first direction, wherein the density of the second intrinsic amorphous silicon layer is higher than that of the first intrinsic amorphous silicon layer.

[0009] In some embodiments, the thickness of the second layer along the first direction is less than the thickness of the first layer; and / or, the thickness of the second layer along the first direction is less than 1 nm.

[0010] In some embodiments, the surface of the second layer away from the first layer has protrusions.

[0011] In some embodiments, the substrate further has a side surface connecting the front and the back surfaces; at least one of the first intrinsic layer and the first doped layer is also located on the side surface.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a photovoltaic cell, comprising: providing a substrate having a front side and a back side opposite to each other along a first direction, the first direction being the thickness direction of the substrate; forming an initial intrinsic layer on the front side; oxidizing the side of the initial intrinsic layer away from the substrate, such that a portion of the initial intrinsic layer is transformed into a second layer comprising oxygen-doped intrinsic amorphous silicon, and the remaining unoxidized initial intrinsic layer is a first layer comprising intrinsic amorphous silicon, the first layer and the second layer together constituting a first intrinsic layer; forming a first doped layer on the side of the second layer away from the first layer, the first doped layer and the substrate being doped with the same type of doping element.

[0013] In some embodiments, the initial intrinsic layer is formed in a first cavity using a third deposition process; the oxidation treatment step includes: placing the substrate with the initial intrinsic layer formed thereon in a transition cavity, introducing oxygen-containing gas into the transition cavity, and setting the temperature in the transition cavity to 150°C~200°C, so that a portion of the initial intrinsic layer is transformed into a second layer including oxygen-doped intrinsic amorphous silicon; placing the substrate with the second layer formed thereon in a second cavity, and forming the first doped layer in the second cavity using a fourth deposition process.

[0014] In some embodiments, after the oxidation treatment and before forming the first doped layer, the method further includes: performing a surface treatment on the surface of the second layer away from the first layer using a very high frequency power supply, so that the surface of the second layer away from the first layer has protrusions; wherein the power of the very high frequency power supply is 1500W / m2~2500W / m2; and / or, the duration of the surface treatment is 1s~10s; and / or, in the step of performing the surface treatment, silane and hydrogen are also introduced, and the ratio of the flow rate of the introduced silane to the flow rate of the introduced hydrogen is 150~300; and / or, the temperature of the surface treatment is 150℃~200℃.

[0015] In some embodiments, before forming the initial intrinsic layer, the method further includes: forming a first intrinsic amorphous silicon layer on the back side using a first deposition process; forming a second intrinsic amorphous silicon layer on the side of the first intrinsic amorphous silicon layer away from the substrate using a second deposition process, wherein the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer together constitute the second intrinsic layer; wherein the power used in the first deposition process is greater than the power used in the second deposition process; and / or, silane and carbon dioxide are introduced in the first deposition process, and silane, carbon dioxide and hydrogen are introduced in the second deposition process.

[0016] In some embodiments, silane and carbon dioxide are introduced in the first deposition process, and silane, carbon dioxide and hydrogen are introduced in the second deposition process. The gas flow rate of silane introduced in the first deposition process is a first flow rate, and the gas flow rate of silane introduced in the second deposition process is a second flow rate. The first flow rate is greater than the second flow rate.

[0017] In some embodiments, the substrate on which the second layer is formed is placed in a second cavity, and the first doped layer is formed in the second cavity using a fourth deposition process, wherein phosphine, silane, carbon dioxide and hydrogen are introduced in the fourth deposition process.

[0018] In some embodiments, after forming the first doped layer, the method further includes: using a fifth deposition process to form a second doped layer on the side of the second intrinsic layer away from the substrate; wherein the power of the fifth deposition process is higher than that of the fourth deposition process, and the temperature of the fifth deposition process is lower than that of the fourth deposition process.

[0019] In some embodiments, after forming the second doped layer, the method further includes: forming a first transparent conductive layer and a second transparent conductive layer, wherein the first transparent conductive layer is located on the side of the first doped layer away from the second layer, and the second transparent conductive layer is located on the side of the second doped layer away from the second intrinsic layer; and forming a first electrode and a second electrode, wherein the first electrode is located on the side of the first transparent conductive layer away from the first doped layer, and the second electrode is located on the side of the second transparent conductive layer away from the second doped layer.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, including: a battery string, which is formed by connecting a plurality of photovoltaic cells as described in any one of the above claims, or by connecting photovoltaic cells formed by a method for manufacturing a plurality of photovoltaic cells as described in any one of the above claims; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0021] The technical solutions provided in this disclosure have at least the following advantages: The design of the first intrinsic layer on the front side includes a first layer and a second layer stacked along a first direction. The material of the first layer includes intrinsic amorphous silicon, and the material of the second layer includes oxygen-doped intrinsic amorphous silicon. This design facilitates the passivation of surface defects in the first layer, such as silicon dangling bonds, by the second layer, thereby reducing carrier recombination. In addition, the second layer also helps to form a first doped layer with a higher degree of crystallinity, thereby enabling good contact performance between the first intrinsic layer and the first doped layer, thus improving the photoelectric conversion efficiency of the front side of the photovoltaic cell. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a first partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 2 This is a second partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 3 This is a third partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 4 This is a fourth partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure; Figure 5 A process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of this disclosure; Figure 6 A partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in another embodiment of this disclosure after the formation of the initial intrinsic layer; Figure 7 A partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method provided in another embodiment of this disclosure after the formation of the second intrinsic layer; Figure 8 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure; Figure 9 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0024] Explanation of reference numerals in the attached figures: 100. Substrate; 110. Front side; 120. Back side; 130. Side side; 101. First intrinsic layer; 111. First layer; 121. Second layer; 131. Initial intrinsic layer; 102. First doped layer; 103. Second intrinsic layer; 113. First intrinsic amorphous silicon layer; 123. Second intrinsic amorphous silicon layer; 104. Second doped layer; 105. First transparent conductive layer; 106. First electrode; 107. Second transparent conductive layer; 108. Second electrode; 40. Photovoltaic cell; 41. Encapsulating film; 42. Cover plate; 43. Solder ribbon. Detailed Implementation

[0025] As can be seen from the background technology, the photoelectric conversion efficiency of photovoltaic cells needs to be improved.

[0026] This disclosure provides a photovoltaic cell and its manufacturing method, as well as a photovoltaic module. In the photovoltaic cell, the first intrinsic layer on the front side includes a first layer and a second layer stacked along a first direction. The material of the first layer includes intrinsic amorphous silicon, and the material of the second layer includes oxygen-doped intrinsic amorphous silicon. This is beneficial for passivating surface defects of the first layer, such as silicon dangling bonds, by using the second layer, thereby reducing carrier recombination. In addition, the second layer also helps to form a first doped layer with a higher degree of crystallinity, thereby enabling good contact performance between the first intrinsic layer and the first doped layer, thus improving the photoelectric conversion efficiency of the front side of the photovoltaic cell.

[0027] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly defined.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0030] In the description of embodiments of this disclosure, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0031] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0032] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0033] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0034] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0035] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] This disclosure provides a photovoltaic cell according to one embodiment. The photovoltaic cell provided by this disclosure will be described in detail below with reference to the accompanying drawings.

[0038] refer to Figure 1 , Figure 1 This is a partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure. The photovoltaic cell includes: a substrate 100 having a front side 110 and a back side 120 opposite to each other along a first direction X, where the first direction X is the thickness direction of the substrate 100; a first intrinsic layer 101 located on the front side 110, the first intrinsic layer 101 including a first layer 111 and a second layer 121 located on the side of the first layer 111 away from the substrate 100, the material of the first layer 111 including intrinsic amorphous silicon, and the material of the second layer 121 including oxygen-doped intrinsic amorphous silicon; and a first doped layer 102 located on the side of the second layer 121 away from the first layer 111, the first doped layer 102 and the substrate 100 being doped with the same type of doping element.

[0039] Thus, compared to the structure of directly placing a doped layer on the intrinsic layer in conventional heterojunction solar cells, the dangling bonds on the surface of the intrinsic layer are not well passivated, which increases the risk of carrier recombination at the interface between the intrinsic layer and the doped layer. In a photovoltaic cell provided by an embodiment of this disclosure, the first intrinsic layer 101 located on the front side 110 is designed to include a first layer 111 and a second layer 121 stacked along the first direction X. The material of the first layer 111 includes intrinsic amorphous silicon, and the material of the second layer 121 includes oxygen-doped intrinsic amorphous silicon. The surface defects of the first layer 111, such as silicon dangling bonds, can be passivated by the second layer 121, for example, to form more stable silicon-oxygen bonds, thereby reducing carrier recombination. In addition, the second layer 121 also helps to form a first doped layer 102 with a higher degree of crystallinity, thereby enabling good contact performance between the first intrinsic layer 101 and the first doped layer 102, thereby improving the photoelectric conversion efficiency of the front side 110 of the photovoltaic cell.

[0040] It is worth noting that the main material of both the first layer 111 and the second layer 121 is intrinsic amorphous silicon, and therefore both can be considered sub-parts of the first intrinsic layer 101. The difference lies in that the first layer 111 is not doped with oxygen, while the second layer 121 is doped with oxygen. In other words, the first layer 111 can be considered an intrinsic amorphous silicon film, and the second layer 121 can be considered an amorphous silicon oxide film. Due to the oxygen doping in the second layer 121, stable silicon-oxygen bonds can be formed with silicon dangling bonds, thereby reducing interface state defects on the surface of the first layer 111. Moreover, the oxygen doping gives the second layer 121 a certain fixed negative charge, which can provide a certain field passivation effect on the first layer 111, thereby promoting the longitudinal transport of charge carriers. In addition, the oxygen doping can improve the light transmittance of the second layer 121, allowing more light to pass through the second layer 121 and ultimately be absorbed and utilized by the front side 110 of the substrate 100. Therefore, the photoelectric conversion efficiency of the front side 110 of the photovoltaic cell can be improved from multiple aspects.

[0041] The photovoltaic cell provided in one embodiment of this disclosure will be described in more detail below with reference to the accompanying drawings.

[0042] In some embodiments, reference Figure 2 , Figure 2 This is a second partial cross-sectional view of a photovoltaic cell provided in an embodiment of the present disclosure. The photovoltaic cell may further include: a second intrinsic layer 103 located on the back side 120; a second doped layer 104 located on the side of the second intrinsic layer 103 away from the substrate 100, wherein the second doped layer 104 and the substrate 100 are doped with different types of doping elements; a first transparent conductive layer 105 located on the side of the first doped layer 102 away from the second layer 121; a first electrode 106 located on the side of the first transparent conductive layer 105 away from the first doped layer 102; a second transparent conductive layer 107 located on the side of the second doped layer 104 away from the second intrinsic layer 103; and a second electrode 108 located on the side of the second transparent conductive layer 107 away from the second doped layer 104.

[0043] Thus, the first doped layer 102, which is doped with the same type of doping element as the substrate 100, is located on the front side 110, serving as the front junction of the heterojunction cell; the second doped layer 104, which is doped with a different type of doping element than the substrate 100, is located on the back side 120, serving as the back junction of the heterojunction cell. Therefore, the PN junction is located on the back side 120, and the photovoltaic cell is a back junction heterojunction cell.

[0044] In some embodiments, reference Figure 2The substrate 100 can be made of an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium; hereinafter, we will use silicon as an example for substrate 100. The elemental semiconductor material can be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon can be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the substrate material can also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen phosphate, perovskite, cadmium telluride, and copper indium selenide.

[0045] The first doped layer 102 and the substrate 100 are doped with the same type of doping element, including at least the following two cases: In some cases, both the first doped layer 102 and the substrate 100 are doped with N-type dopants. In some examples, the substrate 100 can be an N-type silicon substrate. N-type silicon substrates have high quality and high minority carrier lifetime, and back-junction heterojunction photovoltaic cells designed based on this have higher photoelectric conversion efficiency.

[0046] Furthermore, the first doped layer 102 can be at least one of an N-type doped microcrystalline silicon film, an N-type doped amorphous silicon film, or an N-type microcrystalline-amorphous mixed doped film; the second doped layer 104 can be at least one of a P-type doped microcrystalline silicon film, a P-type doped amorphous silicon film, or a P-type microcrystalline-amorphous mixed doped film.

[0047] In other cases, both the first doped layer 102 and the substrate 100 are doped with P-type dopants.

[0048] In some examples, substrate 100 can be a P-type silicon substrate.

[0049] Furthermore, the first doped layer 102 can be at least one of a P-type doped microcrystalline silicon film, a P-type doped amorphous silicon film, or a P-type microcrystalline-amorphous mixed doped film; the second doped layer 104 can be at least one of an N-type doped microcrystalline silicon film, an N-type doped amorphous silicon film, or an N-type microcrystalline-amorphous mixed doped film.

[0050] Among them, the P-type dopant element can be at least one of the group III elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In); the N-type dopant element can be at least one of the group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As).

[0051] In some embodiments, reference Figure 1 or Figure 2In addition to oxygen, the second layer 121 can also be doped with hydrogen. Thus, the silicon dangling bonds on the surface of the first layer 111 can combine with both oxygen and hydrogen bonds to form stable silicon-hydrogen bonds or silicon-hydrogen-oxygen bonds, further improving the passivation efficiency of the interface of the first layer 111 and further reducing the defect state density on the surface of the first layer 111. Furthermore, the incorporation of hydrogen helps to increase the density of the second layer 121, reduce internal defects in the second layer 121, thereby improving the passivation capability of the second layer 121 itself, and helps to ensure that the outermost part of the first intrinsic layer 101 in contact with the first doped layer 102, i.e., the surface of the second layer 121, remains undamaged, thereby reducing the contact resistance between the first intrinsic layer 101 and the first doped layer 102.

[0052] In some cases, refer to Figure 3 , Figure 3 This is a third partial cross-sectional view of a photovoltaic cell provided in an embodiment of the present disclosure. The second intrinsic layer 103 may include a first intrinsic amorphous silicon layer 113 and a second intrinsic amorphous silicon layer 123 stacked along a first direction X. The density of the second intrinsic amorphous silicon layer 123 may be higher than that of the first intrinsic amorphous silicon layer 113. This is beneficial to improving the damage resistance of the second intrinsic amorphous silicon layer 123, thereby ensuring that the outermost part of the second intrinsic layer 103 in contact with the second doped layer 104, i.e., the surface of the second intrinsic amorphous silicon layer 123, is undamaged, thereby reducing the contact resistance between the second intrinsic layer 103 and the second doped layer 104. In addition, the higher density of the second intrinsic amorphous silicon layer 123 also facilitates the subsequent formation of the second doped layer 104 with a higher degree of crystallinity.

[0053] In some embodiments, reference Figures 1 to 3 Along the first direction X, the thickness of the second layer 121 can be less than the thickness of the first layer 111. It is worth noting that the overall thickness of the first intrinsic layer 101 should not be too thick, as this would hinder the longitudinal transport of charge carriers. Based on this, designing the thickness of the second layer 121 to be less than the thickness of the first layer 111 serves two purposes. First, it still ensures that the relatively thick first layer 111 provides good chemical passivation efficiency for the substrate 100, ensuring a low interface defect state density between the substrate 100 and the first intrinsic layer 101, and leveraging the better conductivity of the first layer 111 to ensure good longitudinal transport efficiency of charge carriers. Second, the thinner second layer 121 can minimize the thickness of the first intrinsic layer 101 while maintaining good passivation of the first layer 111 and improving the contact performance between the first intrinsic layer 101 and the first doped layer 102. This reduces the difficulty of longitudinal transport of charge carriers in the first intrinsic layer 101 and allows more light to pass through the first intrinsic layer 101 and be absorbed and utilized by the front side 110.

[0054] In some embodiments, reference Figures 1 to 3Along the first direction X, the thickness of the first layer 111 can be 5nm to 8nm, for example, it can be 5nm, 5.1nm, 5.2nm, 5.3nm, 5.4nm, 5.5nm, 5.6nm, 5.7nm, 5.8nm, 5.9nm, 6nm, 6.1nm, 6.2nm, 6.3nm, 6.4nm, 6.5nm, 6.6nm, 6.7nm, 6.8nm, 6.9nm, 7nm, 7.1nm, 7.2nm, 7.3nm, 7.4nm, 7.5nm, 7.6nm, 7.7nm, 7.8nm or 8nm, etc.

[0055] In some embodiments, reference Figures 1 to 3 Along the first direction X, the thickness of the second layer 121 can be less than 1nm, for example, it can be 0.95nm, 0.9nm, 0.85nm, 0.8nm, 0.75nm, 0.7nm, 0.65nm, 0.6nm, 0.55nm, 0.5nm, 0.45nm, 0.4nm, 0.35nm or 0.3nm, etc.

[0056] In some embodiments, reference Figures 1 to 3 The surface of the second layer 121 away from the first layer 111 has protrusions (not shown in the figure). In other words, the surface of the second layer 121 away from the first layer 111 has a higher roughness. The protrusions are beneficial to promoting the nucleation and growth of microcrystals during the subsequent manufacturing of the first doped layer 102, thereby improving the crystallinity of the first doped layer 102 and thus improving the photoelectric conversion efficiency of the photovoltaic cell.

[0057] In some embodiments, reference Figure 4 , Figure 4 This is a fourth partial cross-sectional view of a photovoltaic cell provided in an embodiment of the present disclosure. The substrate 100 also has a side 130 connecting the front side 110 and the back side 120; at least one of the first intrinsic layer 101 and the first doped layer 102 is also located on the side 130.

[0058] It is worth noting that compared to the UV attenuation on the front side 110 and the back side 120, the UV attenuation at the edges of the photovoltaic cell is more severe because there are areas that are not shielded by a film layer, such as a transparent conductive layer. Therefore, at least one of the first intrinsic layer 101 and the first doped layer 102 is designed to be located on the side side 130. By utilizing the absorption of UV light by the first intrinsic layer 101 and / or the first doped layer 102, the UV irradiation attenuation on the side side 130 can be effectively improved, thereby significantly reducing the overall UV attenuation of the photovoltaic cell.

[0059] In addition, the thickness of the first intrinsic layer 101 located on the side 130 can be designed to be smaller than the thickness of the first intrinsic layer 101 located on the front 110, and / or the thickness of the first doped layer 102 located on the side 130 can be designed to be smaller than the thickness of the first doped layer 102 located on the front 110.

[0060] In some cases, refer to Figure 4 The second intrinsic layer 103 is located on the side 130; the first intrinsic layer 101 is located on the side of the second intrinsic layer 103 away from the side 130; the first doped layer 102 is located on the side of the first intrinsic layer 101 away from the second intrinsic layer 103; and the second doped layer 104 is also located on the side of the first doped layer 102 away from the first intrinsic layer 101. In other words, along a direction perpendicular to the side 130, the second intrinsic layer 103, the first intrinsic layer 101, the first doped layer 102, and the second doped layer 104 are stacked on the side 130.

[0061] In addition, the thickness of the second intrinsic layer 103 located on the side 130 can be designed to be smaller than the thickness of the second intrinsic layer 103 located on the back 120, and / or the thickness of the second doped layer 104 located on the side 130 can be designed to be smaller than the thickness of the second doped layer 104 located on the back 120.

[0062] The following provides a detailed explanation of the thickness of some film layers in photovoltaic cells.

[0063] In some embodiments, reference Figure 1 Along the first direction X, the thickness of the first doped layer 102 can be 25nm~30nm, for example, it can be 25nm, 25.5nm, 26nm, 26.5nm, 27nm, 27.5nm, 28nm, 28.5nm, 29nm, 29.5nm or 30nm, etc.

[0064] In some embodiments, reference Figure 2 The second intrinsic layer 103 includes a first intrinsic amorphous silicon layer 113 and a second intrinsic amorphous silicon layer 123 stacked along the first direction X.

[0065] In some cases, the thickness of the first intrinsic amorphous silicon layer 113 along the first direction X can be 0.5nm to 3nm, for example, it can be 0.5nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm or 3nm, etc.

[0066] In some cases, the thickness of the second intrinsic amorphous silicon layer 123 along the first direction X can be 2nm to 3nm, for example, it can be 2nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm or 3nm, etc.

[0067] In some embodiments, reference Figure 2 Along the first direction X, the thickness of the second doped layer 104 can be 25nm~35nm, for example, it can be 25nm, 25.5nm, 26nm, 26.5nm, 27nm, 27.5nm, 28nm, 28.5nm, 29nm, 29.5nm, 30nm, 30.5nm, 31nm, 31.5nm, 32nm, 32.5nm, 33nm, 33.5nm, 34nm, 34.5nm or 35nm, etc.

[0068] In summary, the first intrinsic layer 101 located on the front side 110 includes a first layer 111 and a second layer 121 stacked along the first direction X. The material of the first layer 111 is intrinsic amorphous silicon, and the material of the second layer 121 is oxygen-doped intrinsic amorphous silicon. This is beneficial for passivating surface defects of the first layer 111, such as silicon dangling bonds, by using the second layer 121, thereby reducing carrier recombination. In addition, the second layer 121 also helps to form a first doped layer 102 with a higher degree of crystallinity, thereby enabling good contact performance between the first intrinsic layer 101 and the first doped layer 102, thus improving the photoelectric conversion efficiency of the front side 110 of the photovoltaic cell.

[0069] Another embodiment of this disclosure provides a method for manufacturing a photovoltaic cell, used to form the photovoltaic cell provided in the foregoing embodiment. The manufacturing method of the photovoltaic cell provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0070] refer to Figure 5 , Figure 5 This is a process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of the present disclosure. The method for manufacturing a photovoltaic cell includes at least the following steps: S1: Reference Figure 6 A substrate 100 is provided, the substrate 100 having a front side 110 and a back side 120 opposite to each other along a first direction X, the first direction X being the thickness direction of the substrate 100.

[0071] S2: Continue to refer to Figure 6 , Figure 6This is a partial cross-sectional view of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after the formation of an initial intrinsic layer, wherein an initial intrinsic layer 131 is formed on the front side 110.

[0072] S3: Refer to Figure 6 and Figure 1 The initial intrinsic layer 131 is oxidized on the side away from the substrate 100, so that a portion of the initial intrinsic layer 131 is transformed into a second layer 121 including oxygen-doped intrinsic amorphous silicon. The remaining unoxidized initial intrinsic layer 131 is a first layer 111 including intrinsic amorphous silicon. The first layer 111 and the second layer 121 together constitute the first intrinsic layer 101.

[0073] S4: Reference Figure 1 A first doped layer 102 is formed on the side of the second layer 121 away from the first layer 111, and the first doped layer 102 and the substrate 100 are doped with the same type of doping element.

[0074] Thus, the first layer 111 and the second layer 121 in the first intrinsic layer 101 are formed in the same step. In other words, the first layer 111 and the second layer 121 are integrally formed on the basis of the initial intrinsic layer 131. This is beneficial to improve the lattice fit between the first layer 111 and the second layer 121, thereby improving the contact performance between the first layer 111 and the second layer 121 and reducing the recombination of charge carriers at the interface between the first layer 111 and the second layer 121.

[0075] Furthermore, the oxygen-doped second layer 121 is beneficial for passivating surface defects of the first layer 111, such as silicon dangling bonds, thereby reducing carrier recombination. Moreover, the oxygen-doped second layer 121 can provide a good manufacturing reference surface for the subsequently formed first doped layer 102. When the first doped layer 102 is formed on the second layer 121, it helps to form a first doped layer 102 with a higher degree of crystallinity, thereby enabling good contact performance between the first intrinsic layer 101 and the first doped layer 102, thereby improving the photoelectric conversion efficiency of the front side 110 of the photovoltaic cell.

[0076] In some embodiments, reference Figure 6 An initial intrinsic layer 131 can be formed in the first cavity using a third deposition process; in conjunction with reference Figure 6 and Figure 1 The oxidation process may include: placing a substrate 100 with an initial intrinsic layer 131 in a transition cavity, introducing oxygen-containing gas into the transition cavity, and setting the temperature in the transition cavity to 150°C to 200°C, so that a portion of the initial intrinsic layer 131 is transformed into a second layer 121 including oxygen-doped intrinsic amorphous silicon; placing a substrate 100 with the second layer 121 in a second cavity, and forming a first doped layer 102 in the second cavity using a fourth deposition process.

[0077] In this way, the initial intrinsic layer 131, the second layer 121 and the first doped layer 102 are formed in different cavities, which is beneficial to adjust the process environment in each cavity individually and can avoid the reaction of reactants or by-products in the previous process to the subsequent process. Thus, the initial intrinsic layer 131, the second layer 121 and the first doped layer 102 with high film quality can be formed respectively.

[0078] Furthermore, by introducing oxygen-containing gas into the transition cavity and controlling the temperature within the transition cavity, a second layer 121 can be formed on the basis of the initial intrinsic layer 131. The manufacturing process of the second layer 121 is simple.

[0079] In other embodiments, after the initial intrinsic layer is formed in the first cavity and the relevant reactants and byproducts are removed, oxygen-containing gas may continue to be introduced into the first cavity, so that a portion of the initial intrinsic layer is transformed into a second layer including oxygen-doped intrinsic amorphous silicon; or, before forming the first doped layer, oxygen-containing gas is first introduced into the second cavity, so that a portion of the initial intrinsic layer is transformed into a second layer including oxygen-doped intrinsic amorphous silicon, and then the first doped layer is formed in the second cavity.

[0080] In some cases, the oxygen-containing gas introduced into the transition chamber may be CDA (Clean Dry Air).

[0081] In some cases, the temperature inside the transition cavity can be 150℃, 155℃, 160℃, 165℃, 170℃, 175℃, 180℃, 185℃, 190℃, 195℃ or 200℃, etc.

[0082] In some cases, both the third and fourth deposition processes can be PECVD (Plasma Enhanced Chemical Vapor Deposition). The RF power supply used in the PECVD process can have a frequency of 13.56 MHz.

[0083] In some cases, the step of forming the initial intrinsic layer 131 in the first cavity using a third deposition process may include: introducing hydrogen, silane, and carbon dioxide into the first cavity.

[0084] Optionally, the power of the third deposition process can be 292 W / m. 2 .

[0085] Optionally, the temperature of the third deposition process can be 200℃~230℃, for example, 200℃, 205℃, 210℃, 215℃, 220℃, 225℃ or 230℃, etc.

[0086] Optionally, the thickness of the initial intrinsic layer 131 along the first direction X can be 5nm to 8nm, for example, it can be 5nm, 5.1nm, 5.2nm, 5.3nm, 5.4nm, 5.5nm, 5.6nm, 5.7nm, 5.8nm, 5.9nm, 6nm, 6.1nm, 6.2nm, 6.3nm, 6.4nm, 6.5nm, 6.6nm, 6.7nm, 6.8nm, 6.9nm, 7nm, 7.1nm, 7.2nm, 7.3nm, 7.4nm, 7.5nm, 7.6nm, 7.7nm, 7.8nm, or 8nm, etc.

[0087] In some embodiments, reference Figure 1 After oxidation treatment and before forming the first doped layer 102, the photovoltaic cell manufacturing method may further include: treating the surface of the second layer 121 away from the first layer 111 using a very high frequency (VHF) power source, causing the surface of the second layer 121 away from the first layer 111 to have protrusions. Specifically, roughening the surface of the second layer 121 away from the first layer 111 using a VHF power source creates protrusions. During the subsequent formation of the first doped layer 102, these protrusions promote the nucleation and growth of microcrystals, thereby increasing the crystallinity of the first doped layer 102 formed on the surface of the second layer 121, and thus improving the photoelectric conversion efficiency of the photovoltaic cell. Furthermore, the protrusions enhance the light-trapping effect of the first intrinsic layer 101, allowing more light to reach the front side 110 of the substrate 100, further improving the photoelectric conversion efficiency of the front side 110.

[0088] In some cases, the power of a VHF power supply can reach 1500W / m. 2 ~2500W / m 2 For example, it can be 1500W / m 2 1600W / m 2 1700W / m 2 1800W / m 2 1900W / m 2 2000W / m 2 2100W / m 2 2200W / m 2 2300W / m 2 2400W / m 2 Or 2500W / m 2 Thus, the surface of the second layer 121 can be bombarded with the high power of the VHF power supply, making the surface of the second layer 121 rough and thus forming protrusions.

[0089] In some cases, the surface treatment time can be from 1s to 10s, for example, 1s, 2s, 3s, 4s, 5s, 6s, 7s, 8s, 9s, or 10s. It is worth noting that if the surface treatment time is less than 1s, the short treatment duration will not significantly improve the photoelectric conversion efficiency of the photovoltaic cell. If the surface treatment time is greater than 10s, the excessive processing time will lead to over-etching of the second layer 121, thereby reducing the passivation capability of the first intrinsic layer 101. Therefore, designing the surface treatment time to be between 1s and 10s is beneficial in ensuring a good gain in the photoelectric conversion efficiency of the photovoltaic cell while avoiding over-etching of the second layer 121.

[0090] In some cases, silane and hydrogen are introduced during the surface treatment step. The ratio of the hydrogen flow rate to the silane flow rate can be 150 to 300, for example, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, or 300. This allows the gas atmosphere introduced during surface treatment to have a high hydrogen-to-silicon ratio. Hydrogen migration improves the surface passivation of the first intrinsic layer 101 and reduces interface defects. Furthermore, the bombardment of the second layer 121 by hydrogen roughens its surface, facilitating the nucleation and growth of microcrystals in the subsequent fabrication of the first doped layer 102, increasing the crystallinity of the subsequently formed first doped layer 102, and thus improving the fill factor and series resistance of the photovoltaic cell.

[0091] In some cases, the surface treatment temperature can be between 150℃ and 200℃, for example, 150℃, 155℃, 160℃, 165℃, 170℃, 175℃, 180℃, 185℃, 190℃, 195℃, or 200℃. It is worth noting that if the surface treatment temperature exceeds 200℃, the excessively high temperature will cause the second layer 121 to become thicker and denser, thus creating greater resistance to the longitudinal transport of charge carriers and leading to an increase in series resistance. If the surface treatment temperature is below 150℃, it will affect the surface treatment efficiency of the second layer 121. Therefore, designing the surface treatment temperature to be between 150℃ and 200℃ is beneficial to ensure that the second layer 121 has a suitable thickness and density to improve the series resistance of the photovoltaic cell and to ensure that the surface of the second layer 121 has an appropriate number of protrusions.

[0092] It should be noted that the temperature inside the transition cavity and the surface treatment temperature can be the same.

[0093] In some cases, the frequency of a VHF power supply can be 40.68 MHz.

[0094] In some embodiments, in conjunction with reference Figure 7 and Figure 6 , Figure 7 This is a partial cross-sectional view of a photovoltaic cell manufacturing method provided in another embodiment of the present disclosure after the formation of the second intrinsic layer. Before the formation of the initial intrinsic layer 131, the photovoltaic cell manufacturing method may further include: forming a first intrinsic amorphous silicon layer 113 on the back side 120 using a first deposition process; and forming a second intrinsic amorphous silicon layer 123 on the side of the first intrinsic amorphous silicon layer 113 away from the substrate 100 using a second deposition process. The first intrinsic amorphous silicon layer 113 and the second intrinsic amorphous silicon layer 123 together constitute the second intrinsic layer 103.

[0095] In some cases, the power used in the first deposition process can be greater than that used in the second deposition process. In this way, compared with the power used in the first deposition process, it is advantageous to increase the density of the second intrinsic amorphous silicon layer 123 formed by the second deposition process by reducing the power, so that the density of the second intrinsic amorphous silicon layer 123 can be higher than that of the first intrinsic amorphous silicon layer 113.

[0096] In some cases, silane and carbon dioxide are introduced in the first deposition process, and silane, carbon dioxide, and hydrogen are introduced in the second deposition process. Thus, compared to the first deposition process which only introduces silane and carbon dioxide, the second deposition process additionally introduces hydrogen, which facilitates the dilution effect of hydrogen and increases the density of the second intrinsic amorphous silicon layer 123 formed in the second deposition process. This allows the density of the second intrinsic amorphous silicon layer 123 to be higher than that of the first intrinsic amorphous silicon layer 113.

[0097] It should be noted that, in order to make the density of the second intrinsic amorphous silicon layer 123 higher than that of the first intrinsic amorphous silicon layer 113, the power used in the second deposition process is designed to be less than that used in the first deposition process. In addition, hydrogen gas is introduced into the second deposition process. This can be done simultaneously when manufacturing the same second intrinsic layer 103, or one of them can be chosen to be done when manufacturing the same second intrinsic layer 103.

[0098] In some cases, both the first and second deposition processes can be PECVD processes. The RF power supply used in the PECVD process can have a frequency of 13.56MHz.

[0099] In some cases, silane and carbon dioxide are introduced in the first deposition process, and silane, carbon dioxide, and hydrogen are introduced in the second deposition process. The gas flow rate of silane in the first deposition process is a first flow rate, and the gas flow rate of silane in the second deposition process is a second flow rate, with the first flow rate being greater than the second flow rate. Thus, the gas flow rate of silane in the second deposition process is smaller than that in the first deposition process, which helps to reduce the deposition rate of intrinsic amorphous silicon, thereby increasing the density of the second intrinsic amorphous silicon layer 123 formed in the second deposition process. This allows the density of the second intrinsic amorphous silicon layer 123 to be higher than that of the first intrinsic amorphous silicon layer 113.

[0100] In some cases, the step of forming a first intrinsic amorphous silicon layer 113 on the back side 120 using a first deposition process may include: placing the substrate 100 into a first reaction chamber and introducing silane and carbon dioxide into it.

[0101] Optionally, the power of the first deposition process can be 365W / m. 2 ~550W / m 2 For example, it can be 365W / m 2 370W / m 2 375W / m 2 380W / m 2 385W / m 2 390W / m 2 395W / m 2 400W / m 2 405W / m 2 410W / m 2 415W / m 2 420W / m 2 425W / m 2 430W / m 2 435W / m 2 440W / m 2 445W / m 2 450W / m 2 455W / m 2 460W / m 2 465W / m 2 470W / m 2 475W / m 2 480W / m 2 485W / m 2 490W / m 2 495W / m 2 500W / m 2 505W / m 2 510W / m2 515W / m 2 520W / m 2 525W / m 2 530W / m 2 535W / m 2 540W / m 2 545W / m 2 Or 550W / m 2 wait.

[0102] Optionally, the flow rate of silane introduced in the first deposition process can be 500 sccm to 1500 sccm, for example, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, 1300 sccm, 1400 sccm or 1500 sccm, etc.

[0103] Optionally, the flow rate of carbon dioxide introduced in the first deposition process can be 10 sccm to 50 sccm, for example, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm, etc.

[0104] Optionally, the temperature of the first deposition process can be 190℃~230℃, for example, it can be 190℃, 195℃, 200℃, 205℃, 210℃, 215℃, 220℃, 225℃ or 230℃, etc.

[0105] Optionally, the thickness of the first intrinsic amorphous silicon layer 113 along the first direction X can be 0.5 nm to 3 nm.

[0106] In some cases, the step of forming a second intrinsic amorphous silicon layer 123 on the side of the first intrinsic amorphous silicon layer 113 away from the substrate 100 using a second deposition process may include: placing the substrate 100 on which the first intrinsic amorphous silicon layer 113 is formed into a second reaction chamber and introducing silane, carbon dioxide and hydrogen into it.

[0107] Optionally, the power of the second deposition process can be 73W / m. 2 ~182W / m 2 For example, it can be 73W / m 2 75W / m 2 80W / m 2 85W / m 2 90W / m 2 95W / m 2 100W / m 2 105W / m2 110W / m 2 115W / m 2 120W / m 2 125W / m 2 130W / m 2 135W / m 2 140W / m 2 145W / m 2 150W / m 2 155W / m 2 160W / m 2 165W / m 2 170W / m 2 175W / m 2 180W / m 2 Or 182W / m 2 wait.

[0108] Optionally, the flow rate of silane introduced in the second deposition process can be 200 sccm to 1000 sccm, for example, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm.

[0109] Optionally, the flow rate of carbon dioxide introduced in the second deposition process can be 10 sccm to 50 sccm, for example, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm, etc.

[0110] Optionally, the flow rate of hydrogen introduced in the second deposition process can be 200 sccm to 800 sccm, for example, 200 sccm, 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm or 800 sccm, etc.

[0111] Optionally, the temperature of the second deposition process can be 190℃~230℃, for example, it can be 190℃, 195℃, 200℃, 205℃, 210℃, 215℃, 220℃, 225℃ or 230℃, etc.

[0112] Optionally, the thickness of the second intrinsic amorphous silicon layer 123 along the first direction X can be 2nm~3nm.

[0113] In some cases, a substrate 100 with a second layer 121 is placed in a second cavity, and a first doped layer 102 is formed in the second cavity using a fourth deposition process, in which phosphine, silane, carbon dioxide and hydrogen are introduced.

[0114] In some examples, reference Figure 2 After forming the first doped layer 102, the manufacturing method of the photovoltaic cell may further include: using a fifth deposition process to form a second doped layer 104 on the side of the second intrinsic layer 103 away from the substrate 100; wherein the power of the fifth deposition process is higher than that of the fourth deposition process, and the temperature of the fifth deposition process is lower than that of the fourth deposition process.

[0115] In some examples, the substrate 100 is an N-type silicon substrate, the first doped layer 102 is doped with phosphorus, and the second doped layer 104 is doped with boron. Generally speaking, boron is more difficult to dope than phosphorus and migrates more easily at high temperatures. Therefore, the power of the fifth deposition process is designed to be higher than that of the fourth deposition process, which is beneficial to promote the incorporation of boron into the silicon material layer by using higher power. Furthermore, the temperature of the fifth deposition process is designed to be lower than that of the fourth deposition process, which is beneficial to avoid the penetration of boron into the second doped layer 104 and the resulting decrease in passivation effect by using lower temperature.

[0116] In some examples, both the fourth and fifth deposition processes can be PECVD processes. Furthermore, both the fourth and fifth deposition processes can utilize a very high frequency (VHF) power supply, for example, a VHF power supply with a frequency of 40.68 MHz.

[0117] In some examples, the power of the fourth deposition process can reach 2190 W / m. 2 ~4380W / m 2 The temperature for the fourth deposition process can be 180℃~200℃.

[0118] Optionally, the power of the fourth deposition process can be 2190 W / m. 2 2200W / m 2 2300W / m 2 2400W / m 2 2500W / m 2 2600W / m 2 2700W / m 2 2800W / m 2 2900W / m 2 3000W / m 2 3100W / m 2 3200W / m 2 3300W / m 2 3400W / m2 3500W / m 2 3600W / m 2 3700W / m 2 3800W / m 2 3900W / m 2 4000W / m 2 4100W / m 2 4200W / m 2 4300W / m 2 Or 4380W / m 2 wait.

[0119] Optionally, the temperature of the fourth deposition process can be 180℃, 185℃, 190℃, 195℃ or 200℃, etc.

[0120] Optionally, the thickness of the first doped layer 102 along the first direction X can be 25nm~30nm.

[0121] In some examples, the step of forming a second doped layer 104 on the side of the second intrinsic layer 103 away from the substrate 100 using a fifth deposition process may include: flipping the substrate 100 on which the first doped layer 102 is formed and placing it into a third cavity, and introducing diborane, hydrogen, silane and carbon dioxide into it.

[0122] Optionally, the power of the fifth deposition process can be 2920 W / m. 2 ~5840W / m 2 For example, it can be 2920W / m 2 3000W / m 2 3100W / m 2 3200W / m 2 3300W / m 2 3400W / m 2 3500W / m 2 3600W / m 2 3700W / m 2 3800W / m 2 3900W / m 2 4000W / m 2 4100W / m 2 4200W / m 2 4300W / m 2 4400W / m 2 4500W / m 2 4600W / m 2 4700W / m 2 4800W / m 2 4900W / m2 5000W / m 2 5100W / m 2 5200W / m 2 5300W / m 2 5400W / m 2 5500W / m 2 5600W / m 2 5700W / m 2 5800W / m 2 Or 5840W / m 2 wait.

[0123] Optionally, the temperature of the fifth deposition process can be 130℃~170℃, for example, it can be 130℃, 135℃, 140℃, 145℃, 150℃, 155℃, 160℃, 175℃ or 170℃, etc.

[0124] Optionally, the thickness of the second doped layer 104 along the first direction X can be 25nm~35nm.

[0125] In some examples, refer to Figure 2 After forming the second doped layer 104, the method for manufacturing a photovoltaic cell may further include: forming a first transparent conductive layer 105 and a second transparent conductive layer 107, wherein the first transparent conductive layer 105 is located on the side of the first doped layer 102 away from the second layer 121, and the second transparent conductive layer 107 is located on the side of the second doped layer 104 away from the second intrinsic layer 103; forming a first electrode 106 and a second electrode 108, wherein the first electrode 106 is located on the side of the first transparent conductive layer 105 away from the first doped layer 102, and the second electrode 108 is located on the side of the second transparent conductive layer 107 away from the second doped layer 104.

[0126] Optionally, a first transparent conductive layer 105 and a second transparent conductive layer 107 can be deposited on the surfaces of the first doped layer 102 and the second doped layer 104 using a PVD (Physical Vapor Deposition) process. The PVD deposition pressure can be 4.5 kPa; the deposition atmosphere can be oxygen, oxygen, and hydrogen; the deposition temperature can be 160°C; and the thicknesses of the first transparent conductive layer 105 and the second transparent conductive layer 107 along the first direction X can be 100 nm.

[0127] Optionally, electrode paste can be printed on the surfaces of the first transparent conductive layer 105 and the second transparent conductive layer 107 respectively using screen printing technology, followed by low-temperature drying and curing to obtain the first electrode 106 and the second electrode 108. The low-temperature drying temperature can be 180℃; the curing temperature can be 210℃.

[0128] For example, the steps of a photovoltaic cell manufacturing method provided in another embodiment of this disclosure are as follows: (1) Cleaning and texturing: The surface of the N-type silicon wafer is texturized with KOH, and then rounded and cleaned with O3 and H2O2 to obtain a textured surface structure with a base of 1μm~4μm on the surface of the N-type silicon wafer.

[0129] (2) PECVD surface coating: First, deposit the intrinsic amorphous silicon layer on the back side, i.e. the second intrinsic layer.

[0130] Specifically, the following is used: a 13.56MHz RF power supply with a power of 365W / m. 2 ~550W / m 2 Under the conditions of silane flow rate of 500 sccm to 1500 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, and temperature of 190℃ to 230℃, a porous, non-dense, first intrinsic amorphous silicon layer with a thickness of 0.5 nm to 3 nm is first deposited on the back and sides of the N-type silicon wafer.

[0131] After plating, it enters the next chamber, with a power of 73W / m. 2 A moderately dense second intrinsic amorphous silicon layer with a thickness of 2 nm to 3 nm is deposited on the first intrinsic amorphous silicon layer under the following conditions: ~182 W / m2, silane flow rate of 200 sccm to 1000 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, hydrogen flow rate of 200 sccm to 800 sccm, and temperature of 190℃ to 230℃.

[0132] (3) After the intrinsic amorphous silicon layer on the back side is deposited, the next cavity is used to deposit the intrinsic amorphous silicon layer on the front side (i.e., the first intrinsic layer) and the first doped layer. The specific deposition method is as follows: When depositing the intrinsic amorphous silicon layer on the front side, hydrogen, silane, and carbon dioxide are first introduced, with a power of 292 W / m. 2 Under the condition of 200℃~230℃, an intrinsic amorphous silicon layer with a thickness of 5nm~8nm is deposited on the front side 110, which is the initial intrinsic layer.

[0133] Next, it enters the transition cavity, where CDA is introduced and the synchronous temperature is set to 150℃~200℃. This causes a portion of the initial intrinsic layer to be transformed into a second layer containing oxygen-doped intrinsic amorphous silicon. The remaining unoxidized initial intrinsic layer becomes the first layer containing intrinsic amorphous silicon. The first and second layers together constitute the first intrinsic layer.

[0134] The next chamber is then used to deposit the first doped layer. First, a 40.68MHz VHF power supply is used to perform surface treatment on the first intrinsic layer, with a surface treatment power of 1500W / m. 2 ~2500W / m 2 The processing time is 1s to 10s, and the flow rate ratio of hydrogen to silane is 150 to 300.

[0135] Then phosphine, silane, carbon dioxide, and hydrogen are introduced, at a power of 2190W / m 2 ~4380W / m 2 Under the condition of 180℃~200℃, a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm is deposited on the surface of the first intrinsic layer, namely the first doped layer.

[0136] (4) After completing the first doped layer deposition, the next deposition chamber is entered. The second doped layer is deposited on the surface of the first amorphous silicon film, i.e., the surface on which the second intrinsic layer is formed. By introducing diborane, hydrogen, silane and carbon dioxide, at a power of 2920W / m 2 ~5840W / m 2 Under the condition of temperature of 130℃~170℃, a boron-doped microcrystalline silicon layer with a thickness of 25nm~35nm is deposited on the surface of the second intrinsic layer, namely the second doped layer.

[0137] (5) A transparent conductive layer is deposited on the surface of the N-type doped microcrystalline silicon layer (first doped layer) and the P-type doped microcrystalline silicon layer (second doped layer) using PVD technology.

[0138] (6) Electrode paste is printed on the surface of the battery cell after the transparent conductive layer has been plated by screen printing technology, and then the cell is manufactured by low-temperature drying and curing.

[0139] The following provides a detailed description of the relevant parameters used in the surface treatment in another embodiment of this disclosure. Examples 1-11 of the manufacturing method of photovoltaic cells provided in another embodiment of this disclosure are given below.

[0140] Example 1 This embodiment provides a method for manufacturing a photovoltaic cell, the method being as follows: (1) Cleaning and texturing: The surface of the N-type silicon wafer is texturized with KOH, and then rounded and cleaned with O3 and H2O2 to obtain a textured surface structure with a base of 1μm~4μm on the surface of the N-type silicon wafer.

[0141] (2) PECVD surface coating: First, deposit the intrinsic amorphous silicon layer on the back side, i.e. the second intrinsic layer.

[0142] Specifically, the following is used: a 13.56MHz RF power supply with a power of 365W / m.2 ~550W / m 2 Under the conditions of silane flow rate of 500 sccm to 1500 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, and temperature of 190℃ to 230℃, a porous, non-dense, first intrinsic amorphous silicon layer with a thickness of 0.5 nm to 3 nm is first deposited on the back and sides of the N-type silicon wafer.

[0143] After plating, it enters the next chamber, with a power of 73W / m. 2 A moderately dense second intrinsic amorphous silicon layer with a thickness of 2 nm to 3 nm is deposited on the first intrinsic amorphous silicon layer under the following conditions: ~182 W / m2, silane flow rate of 200 sccm to 1000 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, hydrogen flow rate of 200 sccm to 800 sccm, and temperature of 190℃ to 230℃.

[0144] (3) After the intrinsic amorphous silicon layer on the back side is deposited, the next cavity is used to deposit the intrinsic amorphous silicon layer on the front side (i.e., the first intrinsic layer), perform surface treatment, and deposit the first doped layer. The specific deposition method is as follows: When depositing the intrinsic amorphous silicon layer on the front side, hydrogen, silane, and carbon dioxide are first introduced, with a power of 292 W / m. 2 Under the condition of 200℃~230℃, an intrinsic amorphous silicon layer with a thickness of 5nm~8nm is deposited on the front side 110, which is the initial intrinsic layer.

[0145] Next, it enters the transition cavity, where CDA is introduced and the synchronous temperature is set to 150°C. This causes a portion of the initial intrinsic layer to be transformed into a second layer containing oxygen-doped intrinsic amorphous silicon. The remaining unoxidized initial intrinsic layer becomes the first layer containing intrinsic amorphous silicon. The first and second layers together constitute the first intrinsic layer.

[0146] Then, phosphine, silane, carbon dioxide, and hydrogen are introduced to deposit the first doped layer at a power of 2190 W / m. 2 ~4380W / m 2 Under the condition of 180℃~200℃, a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm is deposited on the surface of the first intrinsic layer, namely the first doped layer.

[0147] (4) After completing the first doped layer deposition, the next deposition chamber is entered. The second doped layer is deposited on the surface of the first amorphous silicon film, i.e., the back side of the second intrinsic layer. By introducing diborane, hydrogen, silane and carbon dioxide, at a power of 2920W / m 2 ~5840W / m 2Under the condition of temperature of 130℃~170℃, a boron-doped microcrystalline silicon layer with a thickness of 25nm~35nm is deposited on the surface of the second intrinsic layer, namely the second doped layer.

[0148] (5) A transparent conductive layer is deposited on the surface of the N-type doped microcrystalline silicon layer (first doped layer) and the P-type doped microcrystalline silicon layer (second doped layer) using PVD technology.

[0149] (6) Electrode paste is printed on the surface of the battery cell after the transparent conductive layer has been plated by screen printing technology, and then the cell is manufactured by low-temperature drying and curing.

[0150] Example 2 This embodiment provides a method for manufacturing a photovoltaic cell, the method being as follows: (1) Cleaning and texturing: The surface of the N-type silicon wafer is texturized with KOH, and then rounded and cleaned with O3 and H2O2 to obtain a textured surface structure with a base of 1μm~4μm on the surface of the N-type silicon wafer.

[0151] (2) PECVD surface coating: First, deposit the intrinsic amorphous silicon layer on the back side, i.e. the second intrinsic layer.

[0152] Specifically, the following is used: a 13.56MHz RF power supply with a power of 365W / m. 2 ~550W / m 2 Under the conditions of silane flow rate of 500 sccm to 1500 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, and temperature of 190℃ to 230℃, a porous, non-dense, first intrinsic amorphous silicon layer with a thickness of 0.5 nm to 3 nm is first deposited on the back and sides of the N-type silicon wafer.

[0153] After plating, it enters the next chamber, with a power of 73W / m. 2 A moderately dense second intrinsic amorphous silicon layer with a thickness of 2 nm to 3 nm is deposited on the first intrinsic amorphous silicon layer under the following conditions: ~182 W / m2, silane flow rate of 200 sccm to 1000 sccm, carbon dioxide flow rate of 10 sccm to 50 sccm, hydrogen flow rate of 200 sccm to 800 sccm, and temperature of 190℃ to 230℃.

[0154] (3) After the intrinsic amorphous silicon layer on the back side is deposited, the next cavity is used to deposit the intrinsic amorphous silicon layer on the front side (i.e., the first intrinsic layer) and the first doped layer. The specific deposition method is as follows: When depositing the intrinsic amorphous silicon layer on the front side, hydrogen, silane, and carbon dioxide are first introduced, with a power of 292 W / m. 2Under the condition of 200℃~230℃, an intrinsic amorphous silicon layer with a thickness of 5nm~8nm is deposited on the front side 110, which is the initial intrinsic layer.

[0155] Next, it enters the transition cavity, where CDA is introduced and the synchronous temperature is set to 150°C. This causes a portion of the initial intrinsic layer to be transformed into a second layer containing oxygen-doped intrinsic amorphous silicon. The remaining unoxidized initial intrinsic layer becomes the first layer containing intrinsic amorphous silicon. The first and second layers together constitute the first intrinsic layer.

[0156] The next chamber is then used to deposit the first doped layer. First, the first intrinsic layer is surface-treated using a 40.68MHz VHF power supply at a temperature of 150℃ and a surface treatment power of 1500W / m. 2 The processing time is 5 seconds, and the flow rate ratio of hydrogen to silane is 250.

[0157] Then phosphine, silane, carbon dioxide, and hydrogen are introduced, at a power of 2190W / m 2 ~4380W / m 2 Under the condition of 180℃~200℃, a phosphorus-doped microcrystalline silicon layer with a thickness of 25nm~30nm is deposited on the surface of the first intrinsic layer, namely the first doped layer.

[0158] (4) After completing the first doped layer deposition, the next deposition chamber is entered. The second doped layer is deposited on the surface of the first amorphous silicon film, i.e., the back side of the second intrinsic layer. By introducing diborane, hydrogen, silane and carbon dioxide, at a power of 2920W / m 2 ~5840W / m 2 Under the condition of temperature of 130℃~170℃, a boron-doped microcrystalline silicon layer with a thickness of 25nm~35nm is deposited on the surface of the second intrinsic layer, namely the second doped layer.

[0159] (5) A transparent conductive layer is deposited on the surface of the N-type doped microcrystalline silicon layer (first doped layer) and the P-type doped microcrystalline silicon layer (second doped layer) using PVD technology.

[0160] (6) Electrode paste is printed on the surface of the battery cell after the transparent conductive layer has been plated by screen printing technology, and then the cell is manufactured by low-temperature drying and curing.

[0161] Example 3 The difference between this embodiment and embodiment 2 is that in step (3) of this embodiment, the surface treatment power for the first intrinsic layer is 2000W / m. 2 .

[0162] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0163] Example 4 The difference between this embodiment and embodiment 2 is that in step (3) of this embodiment, the power of the surface treatment for the first intrinsic layer is 2500W / m. 2 .

[0164] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0165] Example 5 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the surface treatment temperature for the first intrinsic layer is 200°C.

[0166] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0167] Example 6 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the surface treatment temperature for the first intrinsic layer is 175°C.

[0168] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0169] Example 7 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the surface treatment time for the first intrinsic layer is 1 second.

[0170] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0171] Example 8 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the surface treatment time for the first intrinsic layer is 10 seconds.

[0172] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0173] Example 9 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the flow rate ratio of hydrogen to silane in the step of surface treatment of the first intrinsic layer is 150.

[0174] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0175] Example 10 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the flow rate ratio of hydrogen to silane in the step of surface treatment of the first intrinsic layer is 200.

[0176] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0177] Example 11 The difference between this embodiment and embodiment 3 is that in step (3) of this embodiment, the flow rate ratio of hydrogen to silane in the step of surface treatment of the first intrinsic layer is 300.

[0178] The remaining manufacturing methods and parameters are consistent with those in Example 2.

[0179] The photovoltaic cells manufactured in Examples 1-11 were subjected to performance tests, including short-circuit current (Isc), open-circuit voltage (Voc), fill factor (FF), photoelectric conversion efficiency (EFF), series resistance (Rs), and pseudo-fill factor (pFF); the specific test results are shown in Table 1.

[0180] Table 1. Effects of different surface treatment parameters on photovoltaic cell performance.

[0181] In summary, compared to Example 1 where no surface treatment was performed on the second layer, the photovoltaic cells obtained by performing surface treatment on the second layer in Example 2 show improvements in both fill factor and photoelectric conversion efficiency.

[0182] Furthermore, as can be seen from Table 1, firstly, compared to Example 1 where no surface treatment is performed on the second layer, when a VHF power supply is used for surface treatment, the power density in Example 3 is 2000 W / m². 2 The photoelectric conversion efficiency was improved by 0.07%, mainly due to the reduction of Rs and the improvement of pFF.

[0183] Secondly, a high hydrogen-to-silicon ratio improves the passivation of the first intrinsic layer and reduces interface defects through hydrogen migration. Simultaneously, the bombardment of the first intrinsic layer by hydrogen roughens its outer surface, which facilitates the nucleation and growth of subsequent N-type crystallites, increasing their crystallinity and thus improving pFF and Rs. Furthermore, when adjusting the hydrogen-to-silane flow ratio, the gain in photoelectric conversion efficiency initially increases and then decreases with increasing flow ratio. This is mainly because an excessively high hydrogen flow ratio can lead to over-etching of the first intrinsic layer, resulting in reduced battery performance.

[0184] Third, when the surface treatment temperature is changed, the second layer in the first intrinsic layer becomes thicker and denser due to the increase in temperature, which hinders the transport of charge carriers and thus reduces the efficiency of Rs improvement.

[0185] Fourth, when the surface treatment time is changed, a treatment time of 1 second does not significantly improve the photoelectric conversion efficiency of the battery due to its short processing time. However, a treatment time of 10 seconds results in a lower photoelectric conversion efficiency compared to a treatment time of 5 seconds. This is because an excessively long treatment time leads to over-etching of the first intrinsic layer, resulting in a decrease in its passivation capability. Simultaneously, an increase in defects in the first intrinsic layer leads to a decrease in current.

[0186] In summary, in the photovoltaic cell manufacturing method provided by another embodiment of this disclosure, the coordinated coordination of the preparation sequence and various parameters in the surface treatment, by preparing the first intrinsic layer in steps and interleaving the preparation of the first intrinsic layer and the first doped layer between the second intrinsic layer and the second doped layer, avoids the first intrinsic layer being damaged when flipping for front-side coating, and ensures that the outermost second layer in contact with the first doped layer is undamaged, thereby improving the photoelectric conversion efficiency of the photovoltaic cell.

[0187] Another embodiment of this disclosure provides a photovoltaic module, which includes a plurality of photovoltaic cells as provided in the foregoing embodiments, or photovoltaic cells formed by a method for manufacturing a plurality of photovoltaic cells as provided in the foregoing embodiments. The photovoltaic module provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated hereafter.

[0188] Reference Figure 8 , Figure 9 as well as Figure 1 The photovoltaic module includes: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided in the foregoing embodiments, or by connecting photovoltaic cells 40 formed by the manufacturing method of multiple photovoltaic cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0189] in, Figure 8 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided in yet another embodiment of this disclosure; Figure 9 This is a partial cross-sectional schematic diagram of a photovoltaic module provided in yet another embodiment of the present disclosure.

[0190] It should be noted that multiple photovoltaic cells 40 can be electrically connected to each other via solder strips 43. Figure 8 and Figure 9This illustration only shows one positional relationship between photovoltaic cells 40, where the electrodes of the photovoltaic cells 40 with the same polarity are arranged in the same direction, or in other words, the electrodes of each photovoltaic cell 40 with positive polarity are arranged facing the same side, so that the solder ribbon 43 connects different sides of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells can also be arranged with electrodes of different polarities facing the same side, that is, the electrodes of multiple adjacent photovoltaic cells are arranged in the order of first polarity, second polarity, and first polarity respectively, then the solder ribbon connects the same side of two adjacent photovoltaic cells.

[0191] In some embodiments, the photovoltaic cells 40 are electrically connected in the form of a single cell or multiple segments to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic cells 40 can be a single cell or a sliced ​​cell, where a sliced ​​cell refers to a cell formed by cutting a complete single cell.

[0192] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the photovoltaic cell 40, and the second encapsulating layer covers the other of the front or back sides of the photovoltaic cell 40. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be manufactured by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0193] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0194] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0195] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A photovoltaic cell, characterized in that, include: The substrate has a front side and a back side opposite each other along a first direction, the first direction being the thickness direction of the substrate; A first intrinsic layer is located on the front side. The first intrinsic layer includes a first layer and a second layer located on the side of the first layer away from the substrate. The material of the first layer includes intrinsic amorphous silicon, and the material of the second layer includes oxygen-doped intrinsic amorphous silicon. A first doped layer is located on the side of the second layer away from the first layer, and the first doped layer and the substrate are doped with the same type of doping element.

2. The photovoltaic cell according to claim 1, characterized in that, Also includes: The second intrinsic layer is located on the back side; The second doped layer is located on the side of the second intrinsic layer away from the substrate, and the second doped layer and the substrate are doped with different types of doping elements; A first transparent conductive layer is located on the side of the first doped layer away from the second layer; The first electrode is located on the side of the first transparent conductive layer away from the first doped layer; The second transparent conductive layer is located on the side of the second doped layer away from the second intrinsic layer; The second electrode is located on the side of the second transparent conductive layer away from the second doped layer.

3. The photovoltaic cell according to claim 2, characterized in that, The second intrinsic layer includes a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer stacked along the first direction, wherein the density of the second intrinsic amorphous silicon layer is higher than that of the first intrinsic amorphous silicon layer.

4. The photovoltaic cell according to claim 1 or 2, characterized in that, Along the first direction, the thickness of the second layer is less than the thickness of the first layer; and / or, along the first direction, the thickness of the second layer is less than 1 nm.

5. The photovoltaic cell according to claim 1 or 2, characterized in that, The surface of the second layer away from the first layer has protrusions.

6. The photovoltaic cell according to claim 1 or 2, characterized in that, The substrate also has a side surface connecting the front and the back surfaces; at least one of the first intrinsic layer and the first doped layer is also located on the side surface.

7. A method for manufacturing a photovoltaic cell, characterized in that, include: A substrate is provided having a front side and a back side opposite each other along a first direction, the first direction being the thickness direction of the substrate; An initial intrinsic layer is formed on the front side; The initial intrinsic layer is oxidized on the side away from the substrate, so that a portion of the initial intrinsic layer is transformed into a second layer including oxygen-doped intrinsic amorphous silicon, and the remaining unoxidized initial intrinsic layer is a first layer including intrinsic amorphous silicon. The first layer and the second layer together constitute the first intrinsic layer. A first doped layer is formed on the side of the second layer away from the first layer, and the first doped layer and the substrate are doped with the same type of doping element.

8. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, The initial intrinsic layer is formed in the first cavity using a third deposition process; The steps for performing the oxidation treatment include: The substrate on which the initial intrinsic layer is formed is placed in a transition cavity, oxygen-containing gas is introduced into the transition cavity, and the temperature in the transition cavity is set to 150°C to 200°C, so that a portion of the initial intrinsic layer is transformed into a second layer including oxygen-doped intrinsic amorphous silicon. The substrate with the second layer formed thereon is placed in the second cavity, and the first doped layer is formed in the second cavity using a fourth deposition process.

9. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, After the oxidation process is performed and before the first doped layer is formed, the method further includes: using a very high frequency power supply to perform surface treatment on the surface of the second layer away from the first layer, so that the surface of the second layer away from the first layer has protrusions; The power of the very high frequency power supply is 1500W / m. 2 ~2500W / m 2 ; and / or, the duration of the surface treatment is 1s to 10s; and / or, during the surface treatment step, silane and hydrogen are also introduced, and the ratio of the flow rate of the silane to the flow rate of the hydrogen is 150 to 300; and / or, the temperature of the surface treatment is 150℃ to 200℃.

10. The method for manufacturing a photovoltaic cell according to claim 7, characterized in that, Before forming the initial intrinsic layer, the method further includes: A first intrinsic amorphous silicon layer is formed on the back side using a first deposition process; A second intrinsic amorphous silicon layer is formed on the side of the first intrinsic amorphous silicon layer away from the substrate using a second deposition process. The first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer together constitute the second intrinsic layer. Wherein, the power used in the first deposition process is greater than the power used in the second deposition process; and / or, silane and carbon dioxide are introduced in the first deposition process, and silane, carbon dioxide and hydrogen are introduced in the second deposition process.

11. The method for manufacturing a photovoltaic cell according to claim 10, characterized in that, In the first deposition process, silane and carbon dioxide are introduced, and in the second deposition process, silane, carbon dioxide and hydrogen are introduced. The gas flow rate of silane introduced in the first deposition process is a first flow rate, and the gas flow rate of silane introduced in the second deposition process is a second flow rate. The first flow rate is greater than the second flow rate.

12. The method for manufacturing a photovoltaic cell according to claim 10, characterized in that, The substrate with the second layer formed thereon is placed in the second cavity, and the first doped layer is formed in the second cavity using a fourth deposition process, wherein phosphine, silane, carbon dioxide and hydrogen are introduced in the fourth deposition process.

13. The method for manufacturing a photovoltaic cell according to claim 12, characterized in that, After forming the first doped layer, the process further includes: using a fifth deposition process to form a second doped layer on the side of the second intrinsic layer away from the substrate; The power of the fifth deposition process is higher than that of the fourth deposition process, and the temperature of the fifth deposition process is lower than that of the fourth deposition process.

14. The method for manufacturing a photovoltaic cell according to claim 13, characterized in that, After forming the second doped layer, the process further includes: A first transparent conductive layer and a second transparent conductive layer are formed, wherein the first transparent conductive layer is located on the side of the first doped layer away from the second layer, and the second transparent conductive layer is located on the side of the second doped layer away from the second intrinsic layer; A first electrode and a second electrode are formed, wherein the first electrode is located on the side of the first transparent conductive layer away from the first doped layer, and the second electrode is located on the side of the second transparent conductive layer away from the second doped layer.

15. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple photovoltaic cells as described in any one of claims 1 to 6, or by connecting multiple photovoltaic cells formed by the manufacturing method of photovoltaic cells as described in any one of claims 7 to 14; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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