A light emitting diode chip and a method of manufacturing the same

Abstract

The present application relates to the technical field of semiconductor devices, and particularly relates to a light emitting diode chip and a preparation method thereof, the light emitting diode chip comprising a substrate, an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer and a composite passivation layer are sequentially stacked on the substrate; the composite passivation layer comprises a plurality of Ti-doped SiN passivation layers which are stacked along an epitaxial direction x The composite passivation layer comprises a plurality of Ti-doped SiN passivation layers which are stacked along an epitaxial direction x The Ti-doped concentration of the passivation layers increases layer by layer along the epitaxial direction, the thickness of the composite passivation layer is 40nm-1000nm; a TiN transition layer is arranged between the composite passivation layer and the P-type semiconductor layer, the thickness of the TiN transition layer is 1nm-3nm. The chip prepared by the present application has high light emitting quantum efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Third-generation semiconductors have broad application prospects, possessing excellent physical and chemical properties such as high melting point, chemical inertness, high thermal conductivity, high hardness, and high breakdown electric field. They are used to fabricate various LED light-emitting devices, exhibiting advantages such as high stability, long lifespan, and energy saving. However, in existing device fabrication processes, a large number of nitrogen vacancies (V0.05) are easily generated on the interface sidewalls after chip etching. n Defects such as dangling bonds become nonradiative recombination centers for charge carriers, severely reducing the luminescent quantum efficiency (IQE) and reliability of devices; meanwhile, traditional SiN... x The passivation layer has weak interfacial adhesion to the metal electrodes (such as Au and Ag), which can easily lead to electrode peeling during device packaging and bending. In addition, the high interfacial contact resistance results in increased device power consumption. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a light-emitting diode chip and its fabrication method, and the resulting chip has high light-emitting quantum efficiency.

[0004] To address the aforementioned issues, this invention proposes a light-emitting diode chip, comprising a substrate on which an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer, and a composite passivation layer are sequentially stacked. The composite passivation layer comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN x The Ti doping concentration of the passivation layer increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer is 40nm~1000nm; A TiN transition layer is provided between the composite passivation layer and the P-type semiconductor layer, and the thickness of the TiN transition layer is 1nm~3nm.

[0005] As an improvement to the above technical solution, the TiN transition layer is prepared by the following method: In a mixed atmosphere of Ar and N2, using a titanium target as the target material, the TiN transition layer is deposited on the P-type semiconductor layer by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0006] As an improvement to the above technical solution, the Ti-doped SiN xThe passivation layer has a Ti doping concentration of 0.5 at% to 8 at%, and the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly along the epitaxial direction.

[0007] As an improvement to the above technical solution, the composite passivation layer is prepared by the following method: The device is placed in a reaction chamber and SiH4, NH3 and TiCl4 are introduced to form the composite passivation layer; The deposition temperature of the composite passivation layer is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

[0008] As an improvement to the above technical solution, the Si doping concentration in the N-type semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The number of stacking periods of the quantum barrier layer and the quantum well layer in the multi-quantum well layer is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. The p-type semiconductor layer is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 .

[0009] Accordingly, the present invention also provides a method for fabricating a light-emitting diode chip, comprising the following steps: Provide substrate; An N-type semiconductor layer is formed on the substrate; A multi-quantum-well layer is formed on the N-type semiconductor layer; A P-type semiconductor layer is formed on the multi-quantum-well layer; A TiN transition layer is formed on the P-type semiconductor layer; A composite passivation layer is formed on the TiN transition layer; The composite passivation layer comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN xThe Ti doping concentration of the passivation layer increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer is 40nm~1000nm; The thickness of the TiN transition layer is 1 nm to 3 nm.

[0010] As an improvement to the above technical solution, forming the TiN transition layer on the P-type semiconductor layer includes the following steps: After depositing and forming a P-type semiconductor layer, a mixed gas of Ar and N2 is introduced, and a titanium target is used as the target material to deposit the TiN transition layer on the P-type semiconductor layer by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0011] As an improvement to the above technical solution, the Ti doping concentration of the composite passivation layer is 0.5 at% to 8 at%, and the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly along the epitaxial direction.

[0012] As an improvement to the above technical solution, forming a composite passivation layer on the TiN transition layer includes the following steps: The device is placed in a reaction chamber, with SiH4 and NH3 as base gases and TiCl4 as Ti source doping gas, to form the composite passivation layer; The deposition temperature of the composite passivation layer is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

[0013] As an improvement to the above technical solution, in the deposition of the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as an N-type dopant, and the growth temperature is 1000℃~1200℃. In the deposition of multiple quantum well layers, the multiple quantum well layers are formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period number ≥ 8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. When depositing the quantum barrier layer, NH3 and TEGa are used as raw materials, the growth temperature is 860°C~900°C, and the growth pressure is 150 torr~250 torr. In the deposition of the P-type semiconductor layer, NH3 and TEGa are used as raw materials, CP2Mg is used as a P-type dopant, and deposition is carried out in an H2 atmosphere; wherein the growth temperature is 980°C~1050°C.

[0014] The implementation of this invention has the following beneficial effects: The present invention provides a light-emitting diode chip having a composite passivation layer deposited on a P-type semiconductor layer, the composite passivation layer comprising multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN x The Ti doping concentration of the passivation layer increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer is 40 nm to 1000 nm. x Nitrogen vacancies are easily formed and Ti has a strong filling ability: the formation energy of N vacancies in β-Si3N4 is much lower than that of Si vacancies, making it easier to form nitrogen vacancy defects; Ti is a strong nitric acid-loving element and preferentially occupies V. n Stable Ti-N bonds are formed, reducing the defect state density. After semiconductor sidewall etching, a large amount of V2 is generated on the sidewalls. n The dangling bond is a nonradiative recombination center for charge carriers in Ti-doped SiN. x The conformal coating effectively passivates these defects and improves IQE. Meanwhile, the Ti doping concentration increases layer by layer along the epitaxial direction. The Ti doping concentration is lower near the P-type semiconductor layer, reducing the amount of movable Ti near the P-type semiconductor layer, thereby reducing interface states, leakage probability, and stress. The Ti doping concentration gradually increases in the middle layers, improving the compactness, hardness, and ESD resistance of the passivation layer. The outermost layer has the highest Ti doping concentration, increasing the refractive index, which is beneficial for light extraction and enhanced passivation protection.

[0015] Secondly, a TiN transition layer is provided between the composite passivation layer and the P-type semiconductor layer, serving as an ultra-thin in-situ transition layer. Since the TiN bonding layer is chemically bonded rather than physically adsorbed, its adhesion is extremely strong, preventing peeling or film detachment. The TiN transition layer significantly enhances the adhesion between the composite passivation layer and the P-type semiconductor layer and hinders Ti diffusion.

[0016] Therefore, the resulting chip has high quantum efficiency, low electrode stripping rate during packaging, high device reliability, and low power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a light-emitting diode chip according to another embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0019] See Figure 1 As shown, an embodiment of the present invention provides a light-emitting diode chip, including a substrate 100, on which an N-type semiconductor layer 200, a multiple quantum well layer 300, a P-type semiconductor layer 400 and a composite passivation layer 600 are sequentially stacked.

[0020] In some embodiments of the present invention, the substrate 100 may be a sapphire substrate. Sapphire is currently the most commonly used substrate material. Sapphire substrates have the advantages of mature manufacturing process, low price, easy cleaning and processing, and good stability at high temperatures.

[0021] In this embodiment of the invention, the composite passivation layer 600 comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer 601, multiple layers of Ti-doped SiN x The Ti doping concentration of the passivation layer 601 increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer 600 is 40 nm to 1000 nm. Examples of the thickness of the composite passivation layer 600 include 40 nm, 70 nm, 100 nm, 500 nm, 700 nm, 800 nm, 900 nm, and 1000 nm, but it is not limited to these. The multilayer Ti-doped SiN... x The gradient concentration design of the passivation layer 601 can gradually release the thermal stress between the epitaxial layer and the passivation layer. The thickness of the composite passivation layer 600, which is 40 nm or more, provides sufficient stress buffer space, and the upper limit of 1000 nm avoids the accumulation of internal stress due to excessive thickness. When the thickness of the composite passivation layer 600 is less than 40 nm, the passivation layer is discontinuous and cannot completely cover the surface defects of the P-type semiconductor layer 400, resulting in increased leakage current; insufficient stress buffering capacity, which easily leads to interface delamination. When the thickness of the composite passivation layer 600 is greater than 1000 nm, the internal stress increases significantly, which may induce warping or cracking of the epitaxial layer; light absorption loss is aggravated, reducing chip brightness; and excessive deposition time affects mass production efficiency.

[0022] A TiN transition layer 900 is provided between the composite passivation layer 600 and the P-type semiconductor layer 400, and the thickness of the TiN transition layer 900 is 1nm to 3nm. The thickness of the TiN transition layer 900 can be 1nm, 1.2nm, 1.7nm, 2.3nm, 2.7nm, or 3nm, but is not limited to these. The ultrathin TiN layer of 1nm to 3nm can reduce the contact resistance between the P-type semiconductor layer and the composite passivation layer, and improve the carrier injection efficiency. When the thickness of the TiN transition layer 900 is less than 1nm, it is difficult to form a continuous film layer, leading to local contact failure and increasing the risk of voltage fluctuation; the diffusion barrier capability decreases, and Mg atom migration accelerates device aging. When the thickness of the TiN transition layer 900 is greater than 3nm, light absorption is significantly enhanced, reducing the chip luminous efficiency; the lattice mismatch stress with the P-type semiconductor layer 400 increases, which may induce interface peeling.

[0023] First, in the composite passivation layer 600 SiN x Nitrogen vacancies are easily formed and Ti has a strong filling ability: the formation energy of N vacancies in β-Si3N4 is much lower than that of Si vacancies, making it easier to form nitrogen vacancy defects; Ti is a strong nitric acid-loving element and preferentially occupies V. n Stable Ti-N bonds are formed, reducing the defect state density. After semiconductor sidewall etching, a large amount of V2 is generated on the sidewalls. n The dangling bond is a nonradiative recombination center for charge carriers in Ti-doped SiN. x The conformal coating effectively passivates these defects and improves IQE. Meanwhile, the Ti doping concentration increases layer by layer along the epitaxial direction. The Ti doping concentration is lower near the P-type semiconductor layer 400, reducing the movable Ti near the P-type semiconductor layer 400, thereby reducing interface states, leakage probability, and stress. The Ti doping concentration gradually increases in the middle layers, improving the compactness, hardness, and ESD resistance of the passivation layer. The outermost layer has the highest Ti doping concentration, increasing the refractive index, which is beneficial for light extraction and enhanced passivation protection.

[0024] Secondly, a TiN transition layer 900 is provided between the composite passivation layer 600 and the P-type semiconductor layer 400, serving as an ultra-thin in-situ transition layer. Since the TiN bonding layer is chemically bonded rather than physically adsorbed, its adhesion is extremely strong, preventing peeling or film detachment. The TiN transition layer 900 significantly enhances the adhesion between the composite passivation layer 600 and the P-type semiconductor layer 400 and blocks Ti diffusion.

[0025] In some embodiments, the Ti doping concentration of the composite passivation layer 600 is 0.5 at% to 8 at%, and the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly along the epitaxial direction.

[0026] The Ti doping concentration of the composite passivation layer 600 can be 0.5at%, 1.0at%, 1.5at%, 2.0at%, 2.5at%, 3.0at%, 3.5at%, 4.0at%, 4.5at%, 5.0at%, 5.5at%, 6.0at%, 6.5at%, 7.0at%, 7.5at%, or 8.0at%, but is not limited thereto. The Ti doping concentration of the composite passivation layer 600 is further preferably 1.0at% to 6.0at%.

[0027] When the Ti doping concentration of the composite passivation layer 600 is less than 0.5 at%, the passivation effect of Ti doping on the trapped states of the passivation layer is insufficient, leading to an increase in interface recombination current and a reduction in device luminous efficiency. When the Ti doping concentration of the composite passivation layer is greater than 8 at%, Ti atoms are prone to forming clusters or precipitates, introducing additional leakage paths, increasing reverse leakage current, and potentially causing mechanical stress that leads to cracking of the passivation layer.

[0028] The linearly increasing Ti concentration creates a continuous bandgap from the P-type semiconductor layer 400 to the composite passivation layer 600, reducing the hole injection barrier and improving carrier recombination efficiency. The concentration gradient buffers the lattice mismatch between the epitaxial layer and the passivation layer, reducing the interface dislocation density. The linear gradient avoids local stress concentration caused by abrupt concentration changes, improving the crack resistance of the passivation layer.

[0029] In some embodiments, the composite passivation layer 600 is prepared by the following method: The device is placed in a reaction chamber, and SiH4, NH3 and TiCl4 are introduced to deposit the composite passivation layer 600 on the P-type semiconductor layer 400. The deposition temperature of the composite passivation layer 600 is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

[0030] The deposition temperature of the composite passivation layer 600 is, for example, 350°C, 400°C, 420°C, 430°C, or 450°C, but is not limited thereto. The deposition pressure is, for example, 100Pa, 150Pa, 200Pa, 250Pa, 300Pa, 350Pa, or 400Pa, but is not limited thereto. The radio frequency power is, for example, 800W, 900W, 950W, 1000W, 1050W, 1100W, 1150W, or 1200W, but is not limited thereto.

[0031] The TiN transition layer 900 is prepared by the following method: In a mixed atmosphere of Ar and N2, using a titanium target as the target material, the TiN transition layer 900 is deposited on the P-type semiconductor layer 400 by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0032] In some embodiments, the Si doping concentration in the N-type semiconductor layer 200 is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The exemplary doping concentration of Si is 5.1 × 10⁻⁶. 17 atoms / cm 3 6.3×10 17 atoms / cm 3 7.8×10 17 atoms / cm 3 8.8×10 17 atoms / cm 3 9.1×10 17 atoms / cm 3 1.8×10 18 atoms / cm 3 5.6×10 18 atoms / cm 3 5.8×10 18 atoms / cm 3 However, it is not limited to this. The exemplary growth thickness of the N-type semiconductor layer 200 is 1.0 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.5 μm, 2.7 μm, 3.0 μm, but it is not limited to this.

[0033] The number of stacking cycles of the quantum barrier layer and the quantum well layer in the multi-quantum well layer 300 is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. Examples of stacking cycles include 8, 9, 10, 11, 12, and 13. Examples of quantum well layer growth thickness include 2.2 nm, 2.5 nm, 2.8 nm, 3.4 nm, 3.7 nm, and 3.9 nm, but are not limited thereto. Examples of quantum barrier layer growth thickness include 8.5 nm, 8.7 nm, 8.9 nm, 10.1 nm, 10.5 nm, 11.2 nm, 12.5 nm, and 12.9 nm, but are not limited thereto.

[0034] The p-type semiconductor layer 400 is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 ; The exemplary growth thickness of the P-type semiconductor layer 400 is 15nm, 16nm, 18nm, or 20nm, but it is not limited to these. The Mg doping concentration is 5.3 × 10⁻⁶. 18 atoms / cm 3 6.8×10 18 atoms / cm 3 7.7×10 18 atoms / cm 3 8.6×10 18 atoms / cm 3 8.3×10 19 atoms / cm 3 5.6×10 20 atoms / cm 3 5.9×10 20 atoms / cm 3 3.7×10 21 atoms / cm 3 4.9×10 21 atoms / cm 3 However, it is not limited to this.

[0035] In another embodiment of the invention, see Figure 2 As shown, an ITO layer 500 is deposited on the surface of the P-type semiconductor layer 400, and a MESA mesa structure is formed by mask etching. The TiN transition layer 900 and the composite passivation layer 600 are sequentially deposited on the MESA mesa structure, and holes for forming electrodes are etched into the MESA mesa structure through ICP etching and photolithography. A P-type electrode 700 is formed on the ITO layer 500, and an N-type electrode 800 is formed on the N-type semiconductor layer 200. Both the P-type electrode 700 and the N-type electrode 800 sequentially pass through the TiN transition layer 900 and the composite passivation layer 600 and extend outwards. This process ensures that the P-type electrode 700 and the N-type electrode 800 can be led out separately, achieving effective current injection.

[0036] In the above embodiments, the Ti-doped SiN x The Ti doping concentration of the passivation layer 601 is 0.5 at% to 8 at%, and the multilayer Ti-doped SiN xThe Ti doping concentration of the passivation layer 601 increases linearly along the epitaxial direction.

[0037] The Ti-doped SiN x The Ti doping concentration of the passivation layer 601 can be 0.5at%, 1.0at%, 1.5at%, 2.0at%, 2.5at%, 3.0at%, 3.5at%, 4.0at%, 4.5at%, 5.0at%, 5.5at%, 6.0at%, 6.5at%, 7.0at%, 7.5at%, 8.0at%, but is not limited to this. The Ti-doped SiN... x The doping concentration of the passivation layer 601 is further preferably 1.0 at% to 6.0 at%.

[0038] When Ti is doped with SiN x When the Ti doping concentration in the passivation layer 601 is less than 0.5 at%, the passivation effect of Ti doping on the trapped states in the passivation layer is insufficient, leading to an increase in interface recombination current and a reduction in device luminous efficiency. When Ti-doped SiN... x When the Ti doping concentration of passivation layer 601 is greater than 8 at%, Ti atoms are prone to form clusters or precipitates, introducing additional leakage paths, increasing reverse leakage current, and may also cause mechanical stress leading to cracking of the passivation layer.

[0039] The linearly increasing Ti concentration creates a continuous bandgap from the P-type semiconductor layer 400 to the composite passivation layer 600, reducing the hole injection barrier and improving carrier recombination efficiency. The concentration gradient buffers the lattice mismatch between the epitaxial layer and the passivation layer, reducing the interface dislocation density. The linear gradient avoids local stress concentration caused by abrupt concentration changes, improving the crack resistance of the passivation layer.

[0040] In the above embodiments, the composite passivation layer 600 is prepared by the following method: The device is placed in a reaction chamber, and SiH4, NH3 and TiCl4 are introduced to deposit the composite passivation layer 600 on the P-type semiconductor layer 400. The deposition temperature of the composite passivation layer 600 is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

[0041] The deposition temperature of the composite passivation layer 600 is, for example, 350°C, 400°C, 420°C, 430°C, or 450°C, but is not limited thereto. The deposition pressure is, for example, 100Pa, 150Pa, 200Pa, 250Pa, 300Pa, 350Pa, or 400Pa, but is not limited thereto. The radio frequency power is, for example, 800W, 900W, 950W, 1000W, 1050W, 1100W, 1150W, or 1200W, but is not limited thereto.

[0042] In the above embodiments, the TiN transition layer 900 is prepared by the following method: In a mixed atmosphere of Ar and N2, using a titanium target as the target material, the TiN transition layer 900 is deposited on the P-type semiconductor layer 400 by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0043] In the above embodiment, the Si doping concentration in the N-type semiconductor layer 200 is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The exemplary doping concentration of Si is 5.1 × 10⁻⁶. 17 atoms / cm 3 6.3×10 17 atoms / cm 3 7.8×10 17 atoms / cm 3 8.8×10 17 atoms / cm 3 9.1×10 17 atoms / cm 3 1.8×10 18 atoms / cm 3 5.6×10 18 atoms / cm 3 5.8×10 18 atoms / cm 3 However, it is not limited to this. The exemplary growth thickness of the N-type semiconductor layer 200 is 1.0 μm, 1.5 μm, 1.8 μm, 2.1 μm, 2.5 μm, 2.7 μm, 3.0 μm, but it is not limited to this.

[0044] The number of stacking cycles of the quantum barrier layer and the quantum well layer in the multi-quantum well layer 300 is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. Examples of stacking cycles include 8, 9, 10, 11, 12, and 13. Examples of quantum well layer growth thickness include 2.2 nm, 2.5 nm, 2.8 nm, 3.4 nm, 3.7 nm, and 3.9 nm, but are not limited thereto. Examples of quantum barrier layer growth thickness include 8.5 nm, 8.7 nm, 8.9 nm, 10.1 nm, 10.5 nm, 11.2 nm, 12.5 nm, and 12.9 nm, but are not limited thereto.

[0045] The p-type semiconductor layer 400 is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 ; The exemplary growth thickness of the P-type semiconductor layer 400 is 15nm, 16nm, 18nm, or 20nm, but it is not limited to these. The Mg doping concentration is 5.3 × 10⁻⁶. 18 atoms / cm 3 6.8×10 18 atoms / cm 3 7.7×10 18 atoms / cm 3 8.6×10 18 atoms / cm 3 8.3×10 19 atoms / cm 3 5.6×10 20 atoms / cm 3 5.9×10 20 atoms / cm 3 3.7×10 21 atoms / cm 3 4.9×10 21 atoms / cm 3 However, it is not limited to this.

[0046] The ITO layer 500 is prepared by the following method: A tin oxide to indium oxide mass ratio of 1:(8~10) was used as the ITO target material, with a vacuum degree ≤5×10⁻⁶. -5 At an Ar atmosphere, with a deposition pressure of 0.3 Pa to 1.0 Pa and an RF sputtering power of 200 W to 300 W, an ITO layer of 500 Pa was deposited.

[0047] The N-type electrode 800 is prepared by the following method: Au is deposited and grown on an N-type semiconductor layer by vapor deposition, and the thickness of the N-type electrode 800 is 800nm~25550nm.

[0048] The P-type electrode 700 is prepared by the following method: Ti and Au alloys are vapor-deposited with a growth thickness of 150nm~600nm.

[0049] This invention also provides a method for fabricating a light-emitting diode chip, used to prepare such a chip. Figure 1 The illustrated light-emitting diode chip includes the following steps: Substrate 100 is provided; An N-type semiconductor layer 200 is formed on the substrate 100; A multiple quantum well layer 300 is formed on the N-type semiconductor layer 200; A P-type semiconductor layer 400 is formed on the multi-quantum-well layer 300; A TiN transition layer 900 is formed on the P-type semiconductor layer 400; A composite passivation layer 600 is formed on the TiN transition layer 900.

[0050] Specifically, forming the TiN transition layer 900 on the P-type semiconductor layer 400 includes the following steps: After depositing and forming the P-type semiconductor layer 400, a mixed gas of Ar and N2 is introduced into the reaction chamber, and the TiN transition layer 900 is deposited on the P-type semiconductor layer 400 by magnetron sputtering using a titanium target as the target material. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0051] In the above preparation steps, Ar provides sputtering particles, which are ionized into Ar ions under the influence of an electric field. These high-energy Ar ions bombard the titanium target under the acceleration of the electric field, ejecting titanium atoms or titanium atom clusters from the target surface. These sputtered titanium particles are the main source of material constituting the thin film. N2 provides the reactant element; the sputtered titanium particles react with the N2 introduced into the reaction chamber as they fly towards the P-type semiconductor layer 400, generating TiN. The volume ratio of N2 to Ar is controlled to control the composition, structure, and electrical properties of the thin film. When the ratio is less than 0.4, it may lead to insufficient nitrogen content in the thin film, resulting in titanium-rich TiN or Ti phase, increasing the film resistivity and decreasing stability. When the ratio is greater than 0.6, it may lead to over-nitriding, or even the formation of non-stoichiometric nitrides with extremely high resistivity, or a sharp decrease in the sputtering rate due to the formation of a thinning layer on the target surface. The volume ratio of N2 to Ar can be 0.4, 0.45, 0.48, 0.5, 0.56, or 0.6, but is not limited to these.

[0052] Specifically, forming the composite passivation layer 600 on the TiN transition layer 900 includes the following steps: The device is placed in a reaction chamber, and a mixed gas of SiH4, NH3 and TiCl4 is introduced. The temperature is controlled at 350℃~450℃, the pressure is controlled at 100Pa~400Pa, and the radio frequency power is controlled at 800W~1200W. The composite passivation layer 600 is deposited on the TiN transition layer 900.

[0053] The volume ratio of SiH4 to NH3 is 2 to 3, and the volume of TiCl4 is 0.1% to 1% of the sum of the volumes of SiH4 and NH3.

[0054] In the above preparation steps, the volume ratio of SiH4 to NH3 affects the density of Si-N bonds and the hydrogen content. When the volume ratio of SiH4 to NH3 is less than 2, excessive NH3 forms a nitrogen-rich film, reducing the refractive index, saturating the dangling bonds on the TiN surface with hydrogen atoms, and reducing interfacial recombination centers. When the volume ratio of SiH4 to NH3 is greater than 3, excessive SiH4 forms a silicon-rich film, increasing the refractive index, and silicon agglomeration increases the internal stress of the film. The volume of TiCl4 is 0.1% to 1% of the sum of the volumes of SiH4 and NH3. By controlling the volume of TiCl4, the grain size can be refined and columnar structures suppressed. A TiCl4 ratio higher than 0.1% ensures sufficient Ti doping to suppress columnar crystals. However, when the TiCl4 ratio exceeds 1%, chloride ions are difficult to completely expel, and residual chlorine will corrode the TiN transition layer interface, increasing contact resistance. In addition, the release of HCl gas during subsequent annealing can trigger film peeling.

[0055] The volume percentage of TiCl4 relative to the sum of the volumes of SiH4 and NH3 can be 0.1%, 0.21%, 0.35%, 0.45%, 0.79%, 0.88%, or 0.95%, but is not limited to these percentages.

[0056] In some embodiments, depositing the N-type semiconductor layer 200 includes the following steps: The reaction chamber temperature was controlled at 1000℃~1200℃, NH3 and TMGa were used as raw materials, SiH4 was used as the N-type dopant, and the Si doping concentration was controlled at 5×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 An N-type semiconductor layer 200 with a thickness of 1.0 μm to 3.0 μm is deposited.

[0057] Depositing the multi-quantum-well layer 300 includes the following steps: The multiple quantum well layer is formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period of ≥8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. When depositing the quantum barrier layer, NH3 and TEGa are used as raw materials, the growth temperature is 860°C~900°C, and the growth pressure is 150 torr~250 torr.

[0058] Depositing the P-type semiconductor layer includes the following steps: The reaction chamber temperature was controlled at 980℃~1050℃, NH3 and TEGa were used as raw materials, CP2Mg was used as a P-type dopant, and deposition was carried out in an H2 atmosphere.

[0059] In another embodiment of the present invention, a method for fabricating a light-emitting diode chip is also provided, for fabricating such a chip. Figure 2 The illustrated light-emitting diode chip includes the following steps: Substrate 100 is provided; An N-type semiconductor layer 200 is formed on the substrate 100; A multiple quantum well layer 300 is formed on the N-type semiconductor layer 200; A P-type semiconductor layer 400 is formed on the multi-quantum-well layer 300; An ITO layer 500 is deposited on the P-type semiconductor layer 400; A TiN transition layer 900 is deposited on the ITO layer 500; The composite passivation layer 600 is deposited on the TiN transition layer 900; Forming an N-type electrode 800 and a P-type electrode 700.

[0060] Specifically, forming the TiN transition layer 900 on the P-type semiconductor layer 400 includes the following steps: After depositing and forming the P-type semiconductor layer 400, a mixed gas of Ar and N2 is introduced into the reaction chamber, and the TiN transition layer 900 is deposited on the P-type semiconductor layer 400 by magnetron sputtering using a titanium target as the target material. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

[0061] In the above preparation steps, Ar provides sputtering particles, which are ionized into Ar ions under the influence of an electric field. These high-energy Ar ions bombard the titanium target under the acceleration of the electric field, ejecting titanium atoms or titanium atom clusters from the target surface. These sputtered titanium particles are the main source of material constituting the thin film. N2 provides the reactant element; the sputtered titanium particles react with the N2 introduced into the reaction chamber as they fly towards the P-type semiconductor layer 400, generating TiN. The volume ratio of N2 to Ar is controlled to control the composition, structure, and electrical properties of the thin film. When the ratio is less than 0.4, it may lead to insufficient nitrogen content in the thin film, resulting in titanium-rich TiN or Ti phase, increasing the film resistivity and decreasing stability. When the ratio is greater than 0.6, it may lead to over-nitriding, or even the formation of non-stoichiometric nitrides with extremely high resistivity, or a sharp decrease in the sputtering rate due to the formation of a thinning layer on the target surface. The volume ratio of N2 to Ar can be 0.4, 0.45, 0.48, 0.5, 0.56, or 0.6, but is not limited to these.

[0062] Specifically, forming the composite passivation layer 600 on the TiN transition layer 900 includes the following steps: The device is placed in a reaction chamber, and a mixed gas of SiH4, NH3 and TiCl4 is introduced. The temperature is controlled at 350℃~450℃, the pressure is controlled at 100Pa~400Pa, and the radio frequency power is controlled at 800W~1200W. The composite passivation layer 600 is deposited on the TiN transition layer 900.

[0063] The volume ratio of SiH4 to NH3 is 2 to 3, and the volume of TiCl4 is 0.1% to 1% of the sum of the volumes of SiH4 and NH3.

[0064] In the above preparation steps, the volume ratio of SiH4 to NH3 affects the density of Si-N bonds and the hydrogen content. When the ratio is less than 2, excessive NH3 forms a nitrogen-rich film, reducing the refractive index, and hydrogen atoms saturate the dangling bonds on the TiN surface, reducing interfacial recombination centers. When the ratio is greater than 3, excessive SiH4 forms a silicon-rich film, increasing the refractive index, and silicon agglomeration increases the internal stress of the film. The volume of TiCl4 is 0.1% to 1% of the sum of the volumes of SiH4 and NH3. By controlling the volume of TiCl4, grain refinement and suppression of columnar structures can be achieved. A TiCl4 ratio higher than 0.1% ensures sufficient Ti doping to suppress columnar crystals. However, when the TiCl4 ratio exceeds 1%, chloride ions are difficult to completely expel, and residual chlorine will corrode the TiN transition layer interface, increasing contact resistance. In addition, HCl gas is released during subsequent annealing, triggering film peeling.

[0065] The volume percentage of TiCl4 relative to the sum of the volumes of SiH4 and NH3 can be 0.1%, 0.21%, 0.35%, 0.45%, 0.79%, 0.88%, or 0.95%, but is not limited to these percentages.

[0066] In some embodiments, depositing the N-type semiconductor layer 200 includes the following steps: The reaction chamber temperature was controlled at 1000℃~1200℃, NH3 and TMGa were used as raw materials, SiH4 was used as the N-type dopant, and the Si doping concentration was controlled at 5×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 An N-type semiconductor layer 200 with a thickness of 1.0 μm to 3.0 μm is deposited.

[0067] Depositing the multi-quantum-well layer 300 includes the following steps: The multiple quantum well layer is formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period of ≥8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. When depositing the quantum barrier layer, NH3 and TEGa are used as raw materials, the growth temperature is 860°C~900°C, and the growth pressure is 150 torr~250 torr.

[0068] Depositing the P-type semiconductor layer includes the following steps: The reaction chamber temperature was controlled at 980℃~1050℃, NH3 and TEGa were used as raw materials, CP2Mg was used as a P-type dopant, and deposition was carried out in an H2 atmosphere.

[0069] The ITO layer 500 is prepared by the following method: A tin oxide to indium oxide mass ratio of 1:(8~10) was used as the ITO target material, with a vacuum degree ≤5×10⁻⁶. -5 At an Ar atmosphere, with a deposition pressure of 0.3 Pa to 1.0 Pa and an RF sputtering power of 200 W to 300 W, an ITO layer of 500 Pa was deposited.

[0070] The N-type electrode 800 is prepared by the following method: Au is deposited and grown on an N-type semiconductor layer by vapor deposition, and the thickness of the N-type electrode 800 is 800nm~25550nm.

[0071] The P-type electrode 700 is prepared by the following method: Ti and Au alloys are vapor-deposited with a growth thickness of 150nm~600nm.

[0072] The following specific embodiments will provide further explanation.

[0073] Example 1 (a) A light-emitting diode chip includes: a substrate, on which an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer, a TiN transition layer and a composite passivation layer are sequentially stacked; The TiN transition layer is 1.5 nm thick; The composite passivation layer has a growth thickness of 500 nm and comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly from 0.5 at% to 8 at% along the epitaxial direction.

[0074] (II) A method for fabricating a light-emitting diode chip, comprising the following steps: (1) Provide a substrate, the substrate being sapphire; (2) Deposit an N-type semiconductor layer on the substrate; The specific deposition process is as follows: the reaction chamber temperature is lowered to 1100℃, NH3 is used as the N (nitrogen) source, TMGa is used as the Ga (gallium) source, and SiH4 is used as the N-type dopant to deposit a Si-doped N-type GaN layer. The Si doping concentration is 5×10⁻⁶. 18 atoms / cm 3 The thickness of the deposited N-type GaN layer was controlled to be 2 μm.

[0075] (3) Deposit a multi-quantum-well layer on the N-type semiconductor layer; The specific deposition process is as follows: When growing the quantum well layer, the N (nitrogen) source is NH3, the Ga (gallium) source is TEGa, and the In (indium) source is TMIn. The temperature of the reaction chamber is controlled at 780℃, the pressure at 200 torr, and the thickness of the deposited InGaN quantum well layer is controlled at 3nm. When growing the quantum barrier layer, the N (nitrogen) source is NH3, the Ga (gallium) source is TEGa, the temperature of the reaction chamber is controlled at 880℃, the pressure at 200 torr, and the thickness of the deposited GaN quantum barrier layer is controlled at 10nm. The quantum well layer and the quantum barrier layer are alternately deposited and stacked 10 times to obtain a multi-quantum well layer.

[0076] (4) Deposit a P-type semiconductor layer on the multi-quantum-well layer; The specific deposition process is as follows: NH3 is used as the N (nitrogen) source, TEGa as the Ga (gallium) source, and CP2Mg as the P-type dopant. The reaction chamber temperature is controlled at 1000℃, and the deposition thickness is controlled at 17nm under an H2 atmosphere. The deposited P-type low-Mg-doped GaN layer has a thickness of 17nm, and the Mg doping concentration is 5×10⁻⁶. 20 atoms / cm 3 .

[0077] (5) A TiN transition layer is formed on the P-type semiconductor layer; The specific deposition process is as follows: In a mixed atmosphere of Ar and N2, using a titanium target as the target material, the TiN transition layer is deposited on the P-type semiconductor layer by magnetron sputtering, with a growth thickness of 1.5 nm. The volume ratio of N2 to Ar is 0.5, the deposition pressure is 0.4 Pa, and the deposition temperature is ≤150℃.

[0078] (6) A composite passivation layer is formed on the TiN transition layer; The specific deposition process is as follows: the device is placed in a reaction chamber, and a mixed gas of SiH4, NH3 and TiCl4 is introduced to form the composite passivation layer; The deposition temperature of the composite passivation layer is 400℃, the deposition pressure is 300Pa, the RF power is 1000W, the volume ratio of NH3 to SiH4 is 3, the volume of TiCl4 is 0.5% of the sum of the volumes of SiH4 and NH3, and the thickness of the deposited composite passivation layer is 500nm. The multilayer Ti-doped SiN... x The Ti doping concentration of the passivation layer increases linearly from 0.5 at% to 8 at% along the epitaxial direction.

[0079] Example 2 The difference from Example 1 is that the thickness of the composite passivation layer is 100 nm.

[0080] Example 3 The difference from Example 1 is that the thickness of the composite passivation layer is 900 nm.

[0081] Example 4 The difference from Example 1 is that the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly from 0.5 at% to 4 at% along the epitaxial direction.

[0082] Example 5 The difference from Example 1 is that the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly from 4 at% to 8 at% along the epitaxial direction.

[0083] Example 6 The difference from Example 1 is that: an ITO layer with a thickness of 50 nm is deposited on the P-type semiconductor layer, and a MESA mesa structure is formed by mask etching. A TiN transition layer and a composite passivation layer are sequentially deposited on the MESA mesa structure, and holes for forming electrodes are etched by ICP etching and photolithography. A P-type electrode is formed on the ITO layer, and an N-type electrode is formed on the N-type semiconductor. Both the P-type electrode and the N-type electrode sequentially pass through the TiN transition layer and the composite passivation layer and extend outward.

[0084] Comparative Example 1 The difference from Example 1 is that: the composite passivation layer and the TiN transition layer are not provided; a SiO2 passivation layer is deposited on the P-type semiconductor layer, and the growth thickness of the SiO2 passivation layer is 300 nm.

[0085] Comparative Example 2 The difference from Example 1 is that the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer is 5 at.

[0086] Comparative Example 3 The difference from Example 1 is that: no TiN transition layer is provided, and the composite passivation layer consists of multiple layers of undoped SiN. x Layer composition.

[0087] Performance testing: The epitaxial structures obtained in the examples and comparative examples were fabricated into 3mil × 5mil light-emitting diode (LED) chips using the same chip fabrication conditions. Their photoelectric performance was tested under a 2mA operating current using the same LED chip testing machine. The improvement in luminous efficacy was calculated based on Comparative Example 1.

[0088]

[0089] As can be seen from the above embodiments, compared with Comparative Examples 1-3, in Examples 1-6, stacking a TiN transition layer and a composite passivation layer on the P-type semiconductor layer can reduce the defect state density, effectively passivate defects, and improve IQE. Furthermore, referring to the test results of Examples 1 and Comparative Example 2, the Ti doping concentration increases layer by layer along the epitaxial direction, improving the compactness, hardness, and ESD resistance of the passivation layer, thereby improving the luminous efficiency of the device. Referring to Examples 1, 4, and 5, the Ti doping concentration is lower near the TiN transition layer, gradually increases in the middle layers, and is highest in the outermost layer; increasing the refractive index is beneficial for light extraction and enhanced passivation protection.

[0090] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A light-emitting diode chip, characterized in that, Includes a substrate, on which an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer and a composite passivation layer are sequentially stacked; The composite passivation layer comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN x The Ti doping concentration of the passivation layer increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer is 40nm~1000nm; A TiN transition layer is provided between the composite passivation layer and the P-type semiconductor layer, and the thickness of the TiN transition layer is 1nm~3nm. The TiN transition layer was prepared by the following method: In a mixed atmosphere of Ar and N2, using a titanium target as the target material, the TiN transition layer is deposited on the P-type semiconductor layer by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃. The Ti-doped SiN x The passivation layer has a Ti doping concentration of 0.5 at% to 8 at%, and the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly along the epitaxial direction. The composite passivation layer is prepared by the following method: The device is placed in a reaction chamber and SiH4, NH3 and TiCl4 are introduced to form the composite passivation layer; The deposition temperature of the composite passivation layer is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

2. The light-emitting diode chip as described in claim 1, characterized in that, The Si doping concentration in the N-type semiconductor layer is 5 × 10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 The growth thickness is 1.0 μm to 3.0 μm; The number of stacking periods of the quantum barrier layer and the quantum well layer in the multi-quantum well layer is ≥8, and the growth thickness of the quantum well layer is 2nm~4nm; the growth thickness of the quantum barrier layer is 8nm~12nm. The p-type semiconductor layer is a Mg-doped GaN layer with a growth thickness of 15nm~20nm and a Mg doping concentration of 5×10⁻⁶. 18 atoms / cm 3 ~5×10 21 atoms / cm 3 .

3. A method for fabricating a light-emitting diode chip as described in any one of claims 1 or 2, characterized in that, Includes the following steps: Provide substrate; An N-type semiconductor layer is formed on the substrate; A multi-quantum-well layer is formed on the N-type semiconductor layer; A P-type semiconductor layer is formed on the multi-quantum-well layer; A TiN transition layer is formed on the P-type semiconductor layer; A composite passivation layer is formed on the TiN transition layer; The composite passivation layer comprises multiple Ti-doped SiN layers stacked along the epitaxial direction. x Passivation layer, multiple layers of the Ti-doped SiN x The Ti doping concentration of the passivation layer increases layer by layer along the epitaxial direction, and the thickness of the composite passivation layer is 40nm~1000nm; The thickness of the TiN transition layer is 1 nm to 3 nm.

4. The method for fabricating a light-emitting diode chip as described in claim 3, characterized in that, Forming the TiN transition layer on the P-type semiconductor layer includes the following steps: After depositing and forming a P-type semiconductor layer, a mixed gas of Ar and N2 is introduced, and a titanium target is used as the target material to deposit the TiN transition layer on the P-type semiconductor layer by magnetron sputtering. The volume ratio of N2 to Ar is 0.4 to 0.6, the deposition pressure is 0.3 Pa to 0.5 Pa, and the deposition temperature is ≤150℃.

5. The method for fabricating a light-emitting diode chip as described in claim 3, characterized in that, The Ti doping concentration of the composite passivation layer is 0.5 at% to 8 at%, and the multilayer Ti-doped SiN x The Ti doping concentration of the passivation layer increases linearly along the epitaxial direction.

6. The method for fabricating a light-emitting diode chip as described in claim 3 or 5, characterized in that, Forming a composite passivation layer on the TiN transition layer includes the following steps: The device is placed in a reaction chamber, with SiH4 and NH3 as base gases and TiCl4 as Ti source doping gas, to form the composite passivation layer; The deposition temperature of the composite passivation layer is 350℃~450℃, the deposition pressure is 100Pa~400Pa, the radio frequency power is 800W~1200W, the volume ratio of NH3 to SiH4 is 2~3, and the volume of TiCl4 is 0.1%~1% of the sum of the volumes of SiH4 and NH3.

7. The method for fabricating a light-emitting diode chip as described in claim 3, characterized in that, In the deposition of the N-type semiconductor layer, NH3 and TMGa are used as raw materials, SiH4 is used as N-type dopant, and the growth temperature is 1000℃~1200℃. In the deposition of multiple quantum well layers, the multiple quantum well layers are formed by periodically alternating quantum barrier layers and quantum well layers, with a stacking period number ≥ 8; When depositing the quantum well layer, NH3, TEGa and TMIn are used as raw materials, the growth temperature is 760℃~800℃, and the growth pressure is 150 torr~250 torr. When depositing the quantum barrier layer, NH3 and TEGa are used as raw materials, the growth temperature is 860°C~900°C, and the growth pressure is 150 torr~250 torr. In the deposition of the P-type semiconductor layer, NH3 and TEGa are used as raw materials, CP2Mg is used as a P-type dopant, and deposition is carried out in an H2 atmosphere; wherein the growth temperature is 980°C~1050°C.

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