Low thermal resistance high power LED structure

Abstract

The application relates to a low-thermal-resistance high-power LED structure, which comprises a ceramic substrate and a light-emitting mechanism, wherein the light-emitting mechanism comprises a chip assembly which is mounted on the ceramic substrate. The application has the advantages of perfect function and reasonable design, and the high-thermal-resistance functional layer below a chip light-emitting layer is replaced by a low-thermal-resistance diamond layer structure, so that the high-proportion thermal resistance which is matched by the complex layer structure in the high-thermal-resistance layer is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of LED packaging technology, and more specifically to a low thermal resistance, high power LED structure. Background Technology

[0002] LED packaging is a key technology in the manufacturing of semiconductor light-emitting diodes (LEDs) that protects the chip and enables efficient light emission. It is mainly used in lighting, display and other fields. Its core functions include mechanical protection, heat dissipation optimization, luminous efficiency enhancement and power management. It requires the use of transparent and heat-resistant materials and special processes. White LEDs are mainly achieved by exciting phosphors with blue light chips.

[0003] In terms of power, the evolution of LEDs from resin substrates to ceramic substrates has consistently focused on reducing thermal resistance to increase power. Currently, the formula for calculating thermal resistance is: Thermal Resistance = Thickness / (Thermal Conductivity) The formula for thermal conductivity area was used to fit the thermal resistance of LED materials with stable thicknesses in each layer. It was found that existing ceramic LED chips have 50-70% more thermal resistance (see "Supplement to the Principles of New Generation Low Thermal Resistance Structures" for specific table data). The LED structure mainly consists of a light-emitting chip and a ceramic substrate. The structure of each layer of the ceramic substrate is basically uniform. Based on the actual heat conduction path: Heat conduction: (The LED chip is covered with a transparent polymer adhesive that is basically non-conductive to heat; most of the heat is conducted downwards.) Heat flow direction 1: PN junction (heat source) → PGaN (negligible) → P contact layer → P electrode (AuSn) (thermal resistance accounts for about 3%-5%) → substrate; Heat flow direction 2: PN junction (heat source) → PGaN (negligible) → N contact layer → N electrode (AuSn) (thermal resistance accounts for approximately 3%-5%) → substrate. The findings suggest that the current internal chip structure between the GAN and the electrodes, which is temporarily referred to as a contact layer in terms of thermal resistance, cannot meet production requirements. Summary of the Invention

[0004] This invention addresses the technical problems existing in the prior art by providing a low thermal resistance, high power LED structure.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A low thermal resistance, high power LED structure includes a ceramic substrate and a light-emitting mechanism, wherein the light-emitting mechanism includes a chip assembly mounted on the ceramic substrate.

[0006] The beneficial effects of this invention are: This invention has complete functions and a reasonable design. By introducing a low thermal resistance diamond layer structure to replace the high thermal resistance functional layer below the chip's light-emitting layer, it greatly reduces the high proportion of thermal resistance that is used to fit the complex layer structure within the high thermal resistance layer.

[0007] Based on the above technical solution, the present invention can be further improved as follows.

[0008] Furthermore, the ceramic substrate includes an upper copper electrode, a ceramic AlN layer, and a lower copper electrode. The upper copper electrode and the lower copper electrode are distributed opposite to each other on both sides of the ceramic AlN layer, and two copper pillars on the lower copper electrode penetrate the ceramic AlN layer and are respectively connected to the upper copper electrode. The chip assembly is installed on the side of the upper copper electrode away from the ceramic AlN layer.

[0009] The beneficial effect of adopting the above-mentioned further solution is that the upper copper electrode and the lower copper electrode are connected to the AlN layer by copper pillars between the AlN layers, and the upper copper electrode and the lower copper electrode have separate negative electrode regions and positive electrode regions.

[0010] Furthermore, the upper copper electrode includes an upper left copper electrode and an upper right copper electrode, with the upper left copper electrode and the upper right copper electrode distributed opposite to each other on one side of the AlN layer of the ceramic plate; the lower copper electrode includes a lower left copper electrode and a lower right copper electrode, with the lower left copper electrode and the lower right copper electrode distributed opposite to each other on the other side of the AlN layer of the ceramic plate. The two copper pillars are respectively distributed at one end of the lower left copper electrode and the lower right copper electrode, and after penetrating the AlN layer, they are respectively connected to one end of the upper left copper electrode and the upper right copper electrode.

[0011] The advantages of adopting the above-mentioned further solution are that the structure is simple, the upper copper electrode and the lower copper electrode are respectively adopted as separate structures, which are convenient to assemble and do not affect the operation of each component.

[0012] Furthermore, the chip assembly includes an ITO layer, a diamond layer, and a reflective layer. The diamond layer is distributed on the upper copper electrode. The ITO layer is distributed on the side of the diamond layer away from the upper copper electrode, and the ITO layer and the diamond layer have complementary shapes, the same height, and their two side planes are flush. The reflective layer is attached to the diamond layer and is located on the side of the ITO layer closer to the upper copper electrode.

[0013] The advantages of adopting the above-mentioned further scheme are that the structure is simple and the design is reasonable. It uses an ITO layer, a diamond layer and a reflective layer to replace the thermal resistance fitting layer and the chip AuSn layer in the traditional technology. The ITO layer is both conductive and transparent, and the diamond layer has thermal and light guiding properties.

[0014] Furthermore, the chip assembly also includes a chip Al2O3 layer and a chip GAN layer, which are stacked together. Below them are the ITO layer and the diamond layer, which are distributed in parallel. The reflective layer is bonded to the complementary and flush ITO layer and the diamond layer.

[0015] The advantages of adopting the above-mentioned further scheme are that the structure is simple and the design is reasonable. The chip Al2O3 layer has high dielectric strength and good insulation properties, and is often used as a gate dielectric layer or passivation layer to suppress gate leakage current and improve breakdown voltage. In addition, the GAN layer of the chip is a light-emitting layer material that can emit blue light and ultraviolet light.

[0016] Furthermore, the chip assembly includes a reflective diamond layer, which is bonded to the upper copper electrode.

[0017] The advantage of adopting the above-mentioned further solution is that, compared with the above-mentioned reflective layer, there is actually space left for the ITO layer to form an electrical connection with the copper electrode.

[0018] Furthermore, the chip assembly also includes a chip Al2O3 layer and a chip GAN layer, wherein the chip GAN layer, the chip Al2O3 layer and the reflective diamond layer are stacked sequentially.

[0019] The advantages of adopting the above-mentioned further scheme are that the structure is simple and the design is reasonable. The chip Al2O3 layer has high dielectric strength and good insulation properties, and is often used as a gate dielectric layer or passivation layer to suppress gate leakage current and improve breakdown voltage. In addition, the GAN layer of the chip is a light-emitting layer material that can emit blue light and ultraviolet light.

[0020] Furthermore, the light-emitting mechanism also includes two gold wires, one end of which is connected to the upper copper electrode, and the other end is used to connect to the positive and negative electrode pads on the chip.

[0021] The advantages of adopting the above-mentioned further solution are that the structure is simple and the design is reasonable, and the conductive path is directly conducted from the gold wire to the copper electrode on the upper surface.

[0022] Furthermore, the light-emitting mechanism also includes a fluorescent sheet, which is distributed on the side of the chip assembly away from the ceramic substrate.

[0023] The advantages of adopting the above-mentioned further scheme are that the structure is simple and the design is reasonable. As a special optical element, the fluorescent sheet can emit fluorescence when excited by light of a specific wavelength.

[0024] Furthermore, the upper copper electrode is filled with a white adhesive layer in the area outside the chip assembly, and a cavity for accommodating the chip assembly is formed on the white adhesive layer.

[0025] The advantages of adopting the above-mentioned further solution are that the structure is simple and the design is reasonable. The white glue layer can effectively reflect the light emitted by the chip (especially the light escaping from the side and bottom) and guide it in the direction of light emission, thereby improving the overall light efficiency. In addition, the white adhesive layer can enhance light extraction efficiency and aid in heat dissipation. Attached Figure Description

[0026] Figure 1 This is an overall assembly diagram of the flip-chip LED structure in this invention; Figure 2 This is one of the partial structural diagrams of the flip-chip LED structure in this invention; Figure 3 This is a second partial structural schematic diagram of the flip-chip LED structure in this invention; Figure 4 This is the third partial structural schematic diagram of the flip-chip LED structure in this invention; Figure 5 This is an exploded view of the flip-chip LED structure in this invention; Figure 6 This is an overall assembly diagram of the upright chip LED structure in this invention; Figure 7 This is one of the partial structural diagrams of the upright chip LED structure in this invention; Figure 8 This is a second partial structural schematic diagram of the upright chip LED structure in this invention; Figure 9 This is the third partial structural schematic diagram of the upright chip LED structure in this invention; Figure 10 This is an exploded view of the upright chip LED structure in this invention.

[0027] The attached diagram lists the components represented by each number as follows: 1. Phosphor sheet; 2. Chip Al2O3 layer; 3. Chip GAN layer; 4. ITO layer; 5. Diamond layer; 6. Reflective layer; 7. Upper copper electrode; 8. Ceramic plate AlN layer; 9. Lower copper electrode; 10. White glue layer; 11. Reflective diamond layer; 12. Gold wire. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0030] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this technology based on the specific circumstances.

[0031] In the description of this application, spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "below" or "under" or "below" of other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0032] In the description of this application, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0033] Example 1 like Figures 1 to 10 As shown, this embodiment provides a low thermal resistance, high power LED structure, including a ceramic substrate and a light-emitting mechanism. The light-emitting mechanism includes a chip assembly, which is mounted on the ceramic substrate.

[0034] This embodiment is fully functional and rationally designed. By introducing a low thermal resistance diamond layer structure to replace the high thermal resistance functional layer below the chip's light-emitting layer, it greatly reduces the high proportion of thermal resistance that serves as the fitting material for the complex layer structure within the high thermal resistance layer.

[0035] Example 2 Based on Embodiment 1, in this embodiment, the ceramic substrate includes an upper copper electrode 7, a ceramic AlN layer 8, and a lower copper electrode 9. The upper copper electrode 7 and the lower copper electrode 9 are distributed opposite to each other on both sides of the ceramic AlN layer 8, and two copper pillars on the lower copper electrode 9 penetrate the ceramic AlN layer 8 and are respectively connected to the upper copper electrode 7. The chip assembly is installed on the side of the upper copper electrode 7 away from the ceramic AlN layer 8.

[0036] The upper copper electrode 7 and the lower copper electrode 9 are connected to the ceramic plate AlN layer 8 by copper pillars between the ceramic plate AlN layer 8. The upper copper electrode 7 and the lower copper electrode 9 have separate negative electrode regions and positive electrode regions.

[0037] Example 3 Based on Embodiment 2, in this embodiment, the upper copper electrode 7 includes an upper left copper electrode and an upper right copper electrode, with the upper left copper electrode and the upper right copper electrode distributed opposite to each other on one side of the ceramic AlN layer 8; the lower copper electrode 9 includes a lower left copper electrode and a lower right copper electrode, with the lower left copper electrode and the lower right copper electrode distributed opposite to each other on the other side of the ceramic AlN layer 8. The two copper pillars are respectively distributed at one end of the lower left copper electrode and the lower right copper electrode, and after penetrating the AlN layer, they are respectively connected to one end of the upper left copper electrode and the upper right copper electrode.

[0038] The design is simple in structure, with the upper copper electrode 7 and the lower copper electrode 9 being separate structures, which are easy to assemble and do not affect the operation of each component.

[0039] Example 4 Based on any one of Examples 2 to 3, such as Figures 1 to 5 As shown, in this embodiment, the chip assembly includes an ITO layer 4, a diamond layer 5, and a reflective layer 6. The diamond layer 5 is distributed on the upper copper electrode 7. The ITO layer 4 is distributed on the side of the diamond layer 5 away from the upper copper electrode 7, and the ITO layer 4 and the diamond layer 5 have complementary shapes, the same height, and their two side planes are flush. The reflective layer 6 is attached to the diamond layer 5 and is located on the side of the ITO layer 4 close to the upper copper electrode 7.

[0040] The scheme has a simple structure and reasonable design. It uses an ITO layer 4, a diamond layer 5, and a reflective layer 6 to replace the thermal resistance fitting layer and the chip AuSn layer in the traditional technology. The ITO layer is both conductive and transparent, and the diamond layer has thermal and light-conducting properties. The artificial diamond is the same as the synthetic diamond.

[0041] In addition, the ITO layer 4 and the diamond layer 5 are in a parallel thermal resistance configuration. Heat flows through the ITO layer 4 with high thermal resistance and the diamond layer 5 with low thermal resistance on the same horizontal plane, so that heat can be conducted away from the diamond layer 5.

[0042] Example 5 Based on Example 4, in this example, the chip assembly further includes a chip Al2O3 layer 2 and a chip GAN layer 3, which are stacked together. Below them are the ITO layer 4 and the diamond layer 5, which are distributed in parallel. The reflective layer 6 is bonded to the complementary and flush ITO layer 4 and diamond layer 5.

[0043] The scheme has a simple structure and reasonable design. The Al2O3 layer 2 of the chip has high dielectric strength and good insulation properties, and is often used as a gate dielectric layer or passivation layer to suppress gate leakage current and improve breakdown voltage. In addition, the GAN layer 3 of the chip is a light-emitting layer material that can emit blue light and ultraviolet light.

[0044] Based on the above scheme, the upper copper electrode 7 and the lower copper electrode 9 have separate negative electrode regions and positive electrode regions. The upper copper electrode 7 has a space between the negative electrode region and the positive electrode region for welding the two parts of the ITO layer 4 respectively. This replaces the thermal resistance fitting layer and the chip AuSn layer functional layer structure below the light-emitting layer and above the AuSn layer. The structure consists of an ITO layer 4, a diamond layer 5, and a reflective layer 6. The ITO and diamond layers need to be kept at approximately the same thickness. The ITO layer is then cut into bonding positions that are suitable for covering the corresponding positions and shapes of the chip pads. To leave space for the reflective layer to be plated below the chip, the diamond layer is cut into complementary shapes and then merged. Preferably, the merged edge is flush with the edge of the upper copper electrode 7 to facilitate the filling of white glue. A suitable amount of large-sized reflective layer 6 is then applied outward from the center of the ITO layer that needs to cover the chip pads, without affecting the exposed bottom ITO position that forms an electrical contact with the upper copper electrode 7. This is to form a long conductive path, making it easier for heat to dissipate.

[0045] At this point, the original requirements for a thermal resistance fitting layer above AuSn beneath the LED light-emitting layer of the flip-chip, electrical connections for the AuSn layer, and light emission from the underside of the GAN layer 3 of the reflective chip are largely replaced. The LED chip is mounted inside the chip via ITO conductive paths connecting GAN-N and GAN-P in the GAN layer 3. From top to bottom, the chip consists of Al2O3 layer 2 and GAN layer 3. The chip is then heat-set onto the functional replacement layers (ITO layer 4 and diamond layer 5) using a die-bonding process. The phosphor sheet 1 is adhered to and heat-set onto the Al2O32 chip using a dispensing die-bonding process, completely covering the Al2O32 chip. A white adhesive layer 10 is filled between the chips on the upper copper electrode 7, ensuring that the white adhesive layer 10 is slightly lower than or flush with the phosphor sheet 1. Then, the chips are water-cut into individual flip-chip LEDs. Because the chip height is reduced, the ceramic AlN layer 8 can be made to slightly resist the effects of thermal warping of the ceramic substrate.

[0046] The conductive path of this scheme is: chip GAN layer 3, ITO layer 4, upper copper electrode 7, and lower copper electrode 9.

[0047] This layer of ITO needs to cover the center of the chip pads and extend outwards with a reflective layer 6 of the largest possible size, but without affecting the exposed bottom ITO position that forms an electrical contact with the upper copper electrode 7. The purpose of this is to create a long conductive path, making it easier for heat to dissipate.

[0048] Example 6 Based on any one of Examples 2 to 5, such as Figures 6 to 10 As shown, in this embodiment, the chip assembly includes a reflective diamond layer 11, which is attached to the upper copper electrode 7.

[0049] The bottom of the reflective diamond layer 11 is covered with a reflective material of the largest possible size. This is so that electroplating can be done directly without cutting the reflective layer material or using an electroplating mask to create a complex blanking process.

[0050] Example 7 Based on Example 6, in this example, the chip assembly further includes a chip Al2O3 layer 2 and a chip GAN layer 3, wherein the chip GAN layer 3, the chip Al2O3 layer 2 and the reflective diamond layer 11 are stacked sequentially.

[0051] The scheme has a simple structure and reasonable design. The Al2O3 layer 2 of the chip has high dielectric strength and good insulation properties, and is often used as a gate dielectric layer or passivation layer to suppress gate leakage current and improve breakdown voltage. In addition, the GAN layer 3 of the chip is a light-emitting layer material that can emit blue light and ultraviolet light.

[0052] Based on the above scheme, the upper copper electrode 7 and the lower copper electrode 9 have separate negative electrode regions and positive electrode regions. The upper copper electrode 7 has a spaced-out negative electrode region and a separate positive electrode region for welding the two parts of the ITO layer 4 respectively. This replaces the functional layer structure of the thermal resistance fitting layer below the chip light-emitting layer and above the AuSn layer. The bottom reflective diamond layer 11 is preferably flush with the edge of the upper copper electrode 7 to facilitate the filling of white glue. This is because the edge of the upper copper electrode is generally large, and the diamond is already very thin with a high thermal conductivity, so further increasing its size has little impact on the overall thermal resistance. Furthermore, a reflective material of as large a size as possible is covered outward from the bottom of this reflective diamond layer 11. The purpose of this is to increase the heat conduction area, making it easier for heat to dissipate.

[0053] At this point, the requirement for light emission from the underside of the reflective chip GAN layer 3, which was originally needed for the thermal resistance fitting layer above the AuSn layer under the LED light-emitting layer of the flip-chip, has been largely replaced. The LED chip is mounted inside the chip by connecting the ITO conductive paths of GAN-N and GAN-P in the chip GAN layer 3. From top to bottom, the chip consists of chip GAN layer 3 and chip Al2O3 layer 2. The chip is then heat-set onto the diamond layer 5 using a die bonding process.

[0054] Additionally, the phosphor sheet 1 is bonded to the chip GAN layer 3 via a dispensing and die-bonding process and thermally pre-shaped, completely covering the chip GAN layer 3. A white adhesive layer 10 is filled between the chips on the upper copper electrode 7, ensuring that the white adhesive layer 10 is slightly lower than or flush with the phosphor sheet 1. Then, it is water-cut into individual existing flip-chip LEDs. At this point, because the chip height is reduced, the ceramic AlN layer 8 can be made to slightly resist the effects of thermal warping of the ceramic substrate.

[0055] The conductive path of this scheme is as follows: chip GAN layer 3, chip Al2O3 layer 2, upper copper electrode 7, and lower copper electrode 9.

[0056] Example 8 Based on Embodiment 7, in this embodiment, the light-emitting mechanism further includes two gold wires 12, one end of each gold wire 12 is connected to the upper copper electrode 7, and the other end is used to connect to the positive and negative electrode pads on the chip.

[0057] The scheme has a simple structure and a reasonable design, with the conductive path directly connecting the gold wire 12 to the copper electrode on the upper surface.

[0058] Example 9 Based on any one of Embodiments 2 to 8, in this embodiment, the light-emitting mechanism further includes a fluorescent sheet 1, which is distributed on the side of the chip assembly away from the ceramic substrate.

[0059] The scheme has a simple structure and reasonable design. The fluorescent sheet 1, as a special optical element, can emit fluorescence when excited by light of a specific wavelength.

[0060] Example 10 Based on Embodiment 9, in this embodiment, the upper copper electrode 7 is filled with a white adhesive layer 10 in the area outside the chip assembly, and a cavity for accommodating the chip assembly is formed on the white adhesive layer 10.

[0061] The solution has a simple structure and a reasonable design. The main function of the white glue layer 10 is to cover and improve the appearance. It matches the color of the bottom ceramic and guides it in the direction of light, thereby improving the overall light effect. In addition, the white glue layer 10 can enhance the light extraction efficiency, but its thermal conductivity is very low, so heat does not basically escape from here.

[0062] This invention provides a low thermal resistance, high power LED structure, with the following protection points: 1. An external reflective layer is placed on the lower surface of the transparent diamond. The reflective layer is preferably a silver mirror, as its thermal resistance is negligible and can be attributed to the overall area of ​​the ITO diamond and the reflective layer, resulting in an extremely thin layer with high thermal conductivity. The transparent diamond layer must separate the silver mirror layer and the chip to truly increase the thermal conductivity area of ​​the reflective layer. The core principle is that the diamond layer cannot be too thin, as this leads to uneven heat transfer and prevents a significant increase in the thermal conductivity area; nor can it be too thick, as this increases thermal resistance and affects aesthetic requirements.

[0063] 2. An ITO transparent conductive layer is used to connect the pads and the chip's ITO electrodes. Because the reflective layer is not conductive, and conventional pads and electrodes would block the light emitted by the chip, a dielectric layer is needed to conduct electricity without affecting the propagation of light. ITO is conductive and its raw material cost is lower than that of copper.

[0064] 3. The ITO diamond is divided into two parts, which are respectively connected to the positive and negative electrodes.

[0065] 4. The lower surface of the ITO diamond layer is covered with a small piece of diamond film coated with a silver mirror, exposing a conductive area specifically for conducting electricity.

[0066] 5. The diamond film coated with silver mirror is made into a single piece to avoid incomplete reflection of chip light and is easy to process.

[0067] 6. The ITO diamond layer uses a four-point dispensing method, with two points in the conductive area and two points in the light-transmitting area. Silver paste is used in the conductive area. If the thermal conductivity of the insulating adhesive is too low, the area of ​​the reflective layer should be reduced as much as possible so that more silver paste or thermally conductive adhesive with high thermal conductivity can fill the bonding space.

[0068] 7. Conductive path: The conductive path is bypassed by ITO transparent conductive diamond and conducts electricity to the copper pillar. The long conductive path can distribute heat evenly and facilitate heat transfer.

[0069] 8. The diamond sheet here uses transparent, non-conductive synthetic diamond to reduce costs.

[0070] 9. Opening windows in the reflective diamond layer and the fluorescent film allows gold wires to connect the positive and negative electrodes of the chip and the positive and negative electrodes of the ceramic substrate.

[0071] 10. An external chip pad design can be adopted to facilitate the cutting and covering of the fluorescent film.

[0072] 11. The shape of the upper surface electrode can be made of special protruding pads to facilitate the cutting of a whole piece of transparent glass plated with silver mirror.

[0073] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the above embodiments are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A low thermal resistance, high-power LED structure, characterized in that, include: A ceramic substrate and a light-emitting mechanism, the light-emitting mechanism including a chip assembly mounted on the ceramic substrate.

2. The low thermal resistance, high power LED structure according to claim 1, characterized in that, The ceramic substrate includes an upper copper electrode (7), a ceramic AlN layer (8), and a lower copper electrode (9). The upper copper electrode (7) and the lower copper electrode (9) are distributed on opposite sides of the ceramic AlN layer (8), and two copper pillars on the lower copper electrode (9) penetrate the ceramic AlN layer (8) and are connected to the upper copper electrode (7) respectively. The chip assembly is installed on the side of the upper copper electrode (7) away from the ceramic AlN layer (8).

3. The low thermal resistance, high power LED structure according to claim 2, characterized in that, The upper copper electrode (7) includes an upper left copper electrode and an upper right copper electrode, the upper left copper electrode and the upper right copper electrode being distributed opposite to each other on one side of the ceramic plate AlN layer (8); the lower copper electrode (9) includes a lower left copper electrode and a lower right copper electrode, the lower left copper electrode and the lower right copper electrode being distributed opposite to each other on the other side of the ceramic plate AlN layer (8); The two copper pillars are respectively distributed at one end of the lower left copper electrode and the lower right copper electrode, and after penetrating the AlN layer, they are respectively connected to one end of the upper left copper electrode and the upper right copper electrode.

4. The low thermal resistance, high power LED structure according to claim 2, characterized in that, The chip assembly includes an ITO layer (4), a diamond layer (5), and a reflective layer (6). The diamond layer (5) is distributed on the upper copper electrode (7). The ITO layer (4) is distributed on the side of the diamond layer (5) away from the upper copper electrode (7), and the ITO layer (4) and the diamond layer (5) have complementary shapes, consistent heights, and flush sides. The reflective layer (6) is attached to the diamond layer (5) and is located on the side of the ITO layer (4) close to the upper copper electrode (7).

5. The low thermal resistance, high power LED structure according to claim 4, characterized in that, The chip assembly also includes a chip Al2O3 layer (2) and a chip GAN layer (3), which are stacked together. Below them are the ITO layer (4) and the diamond layer (5) in parallel. The reflective layer (6) is attached to the complementary and flush ITO layer (4) and the diamond layer (5).

6. The low thermal resistance, high power LED structure according to claim 2, characterized in that, The chip assembly includes a reflective diamond layer (11) which is attached to the upper copper electrode (7).

7. The low thermal resistance, high power LED structure according to claim 6, characterized in that, The chip assembly also includes a chip Al2O3 layer (2) and a chip GAN layer (3), wherein the chip GAN layer (3), the chip Al2O3 layer (2) and the reflective diamond layer (11) are stacked sequentially.

8. The low thermal resistance, high power LED structure according to claim 7, characterized in that, The light-emitting mechanism also includes two gold wires (12), one end of which is connected to the upper copper electrode (7) respectively, and the other end is used to connect to the positive and negative electrode pads on the chip respectively.

9. The low thermal resistance, high power LED structure according to any one of claims 2-8, characterized in that, The light-emitting mechanism further includes a fluorescent sheet (1), which is distributed on the side of the chip assembly away from the ceramic substrate.

10. The low thermal resistance, high power LED structure according to claim 9, characterized in that, The upper copper electrode (7) is filled with a white adhesive layer (10) in the area outside the chip assembly, and a cavity for accommodating the chip assembly is formed on the white adhesive layer (10).

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