Wafer level mini rgb package structure and preparation method thereof

Abstract

The application relates to the field of photoelectric semiconductor technology, and discloses a wafer-level Mini RGB packaging structure which comprises, from bottom to top, a ball mounting welding spot, a base layer, a rewiring layer, a bump, a chip, a DAF film and a glass carrier; the chip comprises one driving chip and three LED chips, an insulating layer is deposited between the driving chip and the LED chips, a cofferdam is covered on the surface of the insulating layer and away from the chip; the ball mounting welding spot is electrically connected with the rewiring layer, and the bump is located between the chip and the rewiring layer. By adopting the light-transmitting glass as the carrier and combining the DAF film with a specific thickness, the light-emitting area of the LED chip is arranged in the recessed cavity, an effective physical light shielding barrier is constructed, the lateral light leakage between the chips can be obviously blocked, the crosstalk between different color light sources is greatly reduced, and the color purity and contrast of the display module are improved.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic semiconductor technology, and in particular to a wafer-level Mini RGB packaging structure and its fabrication method. Background Technology

[0002] The demand for "RGB with driver" is increasing in two major scenarios: automotive ambient lighting and high-end TV and e-sports display. As the size of LED chips continues to shrink, market competition is also intensifying. RGB devices with integrated lighting and driver need to meet the requirements of high color purity, low crosstalk, and thin and light size.

[0003] Currently, RGB devices on the market use relatively traditional packaging structures, with a BT substrate as the carrier and a transparent plastic encapsulation as the protective shell. However, such packaging structures have problems such as high crosstalk between optical and electrical signals, current congestion, large size, and thick packaging. Summary of the Invention

[0004] This invention provides a wafer-level Mini RGB packaging structure and its fabrication method to solve existing technical problems, thereby addressing the issues of high optical / electrical signal crosstalk, current congestion, and large package size and thickness caused by structural limitations in traditional RGB LED packaging.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a wafer-level MiniRGB packaging structure, comprising, from bottom to top: ball solder joints, a base layer, a redistribution layer, bumps, a chip, a DAF film, and a glass carrier;

[0006] The chip includes a driver chip and three LED chips, wherein an insulating layer is deposited between the driver chip and the LED chips, and a dike covers the surface of the insulating layer away from the chip.

[0007] The ball-mounted solder joints are electrically connected to the redistribution layer, and the bumps are located between the chip and the redistribution layer.

[0008] Furthermore, the glass carrier serves as both a mechanical support and a light-transmitting material;

[0009] A cofferdam is formed on the surface of the glass carrier, constituting an independent cavity structure;

[0010] DAF film is attached to the chip surface;

[0011] The LED chip includes at least three discrete RGB LED chips and a driver IC chip. The RGB LED chips are bonded and fixed to the independent cavity formed by the dam through the DAF film.

[0012] An insulating layer covers the chip and the surrounding structure;

[0013] A rewiring layer is formed on the insulating layer to achieve electrical interconnection;

[0014] A bump is located between the chip and the redistribution layer;

[0015] Ball-mounted solder joints are formed at the pad locations of the redistribution layer.

[0016] Furthermore, the thickness of the DAF film is 30-50 micrometers, which makes the light-emitting area of ​​the LED chip recessed 30-50 micrometers relative to the surface of the glass carrier.

[0017] Furthermore, the redistribution layer is a copper conductor layer, and the ground terminal of each LED chip of each emitting color is led out through the redistribution layer to an independent input or output port.

[0018] Furthermore, the material of the bump is SnAg alloy, wherein the height of the bump for the LED chip is 2-5 micrometers, and the height of the bump for the driver chip is 5-20 micrometers.

[0019] Furthermore, the cofferdam is patterned using photoresist.

[0020] A method for fabricating a wafer-level Mini RGB package structure, specifically including:

[0021] S1. Provide a glass substrate and perform cleaning treatment;

[0022] S2. Photoresist is spin-coated onto the surface of a glass substrate, and the pattern of the dam is formed by exposure and development.

[0023] S3. Based on the shape of the cofferdam, grooves are cut into the glass carrier;

[0024] S4. Transfer and fix the LED chip and driver chip with DAF film attached to the corresponding cavity and groove formed by the cofferdam respectively;

[0025] S5. Perform vacuum compression molding to form an insulating layer covering the chip and the surrounding dam;

[0026] S6. Thin and polish the molding compound to expose the bumps on the chip surface;

[0027] S7. Perform a rewiring process on the polished surface to form a rewiring layer for interconnect lines;

[0028] S8. Coat, expose and develop the polyimide layer, and define the pad windows;

[0029] S9. Form a UBM layer on the pad window;

[0030] S10. Place solder balls on the UBM layer to form an array of solder balls and solder joints.

[0031] Furthermore, in step S4, the DAF film of the LED chip is attached to its light-emitting surface, and the DAF film of the driver chip is attached to its wafer back side.

[0032] Furthermore, the surface roughness after polishing in step S6 is at the nanometer level.

[0033] Furthermore, in step S7, the rewiring process includes: spin coating of photoresist, exposure and development to form a circuit pattern, chemical copper plating to form a copper conductor layer, and removal of photoresist.

[0034] Furthermore, in step S9, the UBM layer is formed into a titanium-tungsten or copper stacked structure through physical vapor deposition.

[0035] This invention provides a wafer-level Mini RGB packaging structure and its fabrication method. Compared with existing technologies, the advantages achieved by this method are:

[0036] 1. This invention uses transparent glass as a carrier and combines it with a DAF film of a specific thickness, so that the light-emitting area of ​​the LED chip is placed in a recessed cavity. This design creates an effective physical light-shielding barrier, which can significantly block lateral light leakage between chips, thereby greatly reducing crosstalk between different color light sources and improving the color purity and contrast of the display module.

[0037] 2. This invention replaces the traditionally shared grounding port with an independent lead-out for each LED color channel, completely isolating the signal loop and effectively suppressing electrical signal crosstalk. Simultaneously, the optimized bump size increases the current conduction cross-sectional area, smoothing the current density distribution and thus mitigating the current congestion effect and reducing the risk of localized hotspots. This not only improves the stability of electrical performance but also enhances the long-term reliability and heat dissipation capacity of the device.

[0038] 3. This invention achieves interconnection between chips and to the outside by performing high-density rewiring on the surface of the reshaped insulating layer, greatly saving horizontal space. In the vertical direction, the ultra-thin glass carrier and integrated stacking significantly reduce the thickness of the package, ultimately achieving miniaturization and thinning of the overall device size, providing key support for the miniaturization design of devices.

[0039] 4. This invention achieves precise passive alignment of the chip by defining the dam and slot using photolithography, and improves placement efficiency by combining it with mass transfer technology. The unique "molding first, wiring later" sequence ensures process compatibility and yield, while subsequent thinning and polishing provide a flat substrate for high-precision wiring. This wafer-level batch processing mode not only ensures the consistency of product performance but also significantly improves production efficiency. Attached Figure Description

[0040] Figure 1 This is a top view of the present invention;

[0041] Figure 2 For the present invention Figure 1 Cross-sectional view along the AA direction;

[0042] Figures 3 to 11 The diagram shows the structural schematics corresponding to each step of the preparation method of the present invention.

[0043] In the diagram: 1. Glass carrier; 2. Cofferdam; 3. DAF membrane; 4. LED chip; 5. Insulating layer; 6. Rewiring layer; 7. Bump; 8. Base layer; 9. Ball-mounted solder joint; 10. Driver chip. Detailed Implementation

[0044] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] Example 1

[0046] like Figures 1-2 As shown, according to one aspect of the present invention, a wafer-level Mini RGB package structure is provided, comprising, from bottom to top: ball solder joints 9, a base layer 8, a redistribution layer 6, bumps 7, a chip, a DAF film 3, and a glass carrier 1;

[0047] The chip includes a driver chip 10 and three LED chips 4 with different emitting colors, wherein an insulating layer 5 is deposited between the driver chip 10 and the LED chips 4, and a dike 2 is covered on the surface of the insulating layer 5 away from the chip.

[0048] Among them, the ball solder joint 9 is electrically connected to the redistribution layer 6, and the bump 7 is located between the chip and the redistribution layer 6.

[0049] Furthermore, the glass carrier 1 serves as a mechanical support and light-transmitting material; the dike 2 is formed on the surface of the glass carrier 1, constituting an independent cavity structure; the DAF film 3 is attached to the chip surface; the LED chip 4 includes at least three discrete RGB LED chips and a driver IC chip, with the RGB LED chips bonded and fixed to the independent cavity formed by the dike 2 via the DAF film 3; the insulating layer 5 covers the chip and the dike structure; the redistribution layer 6 is formed on the insulating layer 5 to achieve electrical interconnection; the bump 7 is located between the chip and the redistribution layer 6; and the ball-mounted solder joint 9 is formed at the pad position of the redistribution layer 6.

[0050] In this embodiment, the DAF film 3 has a thickness of 30-50 micrometers, causing the light-emitting area of ​​the LED chip 4 to be recessed 30-50 micrometers relative to the glass carrier surface. The redistribution layer 6 is a copper conductor layer, and the ground terminal of each LED chip 4 of each emitting color is led out to an independent input or output port through the redistribution layer 6. The bump 7 is made of SnAg alloy, wherein the height of the bump 7 used for the LED chip 4 is 2-5 micrometers, and the height of the bump 7 used for the driver chip 10 is 5-20 micrometers. The dam 2 is formed into a patterned structure using photoresist.

[0051] Using transparent glass as a mechanical substrate, a dam is formed on its surface through photolithography to construct an independent chip cavity. An RGB LED chip is bonded to the cavity using a DAF film of a specific thickness, causing its light-emitting surface to be recessed, forming a physical light-shielding structure. An insulating layer, a redistribution layer, and ball-mounted solder joints are sequentially constructed above the chip. The redistribution layer independently leads out the ground terminals of the three-color LEDs and uses large bumps to connect the chip and the redistribution layer. This structure integrates optical isolation, electrical separation, and high-density interconnection functions from bottom to top.

[0052] This structural design offers several significant advantages: First, the synergistic effect of the glass substrate and the recessed LED light-emitting area effectively blocks side light, expected to reduce optical crosstalk by approximately 20% and improve color purity. Second, independent grounding lines and optimized bump contact areas respectively address signal crosstalk and current congestion issues, improving electrical performance and heat dissipation. Finally, by eliminating the traditional lead frame and BT substrate, wafer-level redistribution enables ultra-high-density interconnection, ultimately achieving breakthroughs in optical performance, electrical reliability, and miniaturization of the package.

[0053] Example 2

[0054] like Figures 3-11 As shown, according to one aspect of the present invention, a method for fabricating a wafer-level Mini RGB package structure is provided, specifically comprising:

[0055] Step 1: Provide glass substrate 1 and clean it.

[0056] like Figure 3 As shown, this step specifically includes incoming glass appearance / packaging inspection, filtering out glass products with numerous scratches; glass cleaning solvent to remove dust from the wafer surface, and high-frequency etching to remove oxides from the wafer insulating layer and aluminum pad surface. This includes incoming raw glass inspection, cleaning, and drying. It ensures that the incoming glass is free of obvious scratches, and that the two-fluid cleaning surface is smooth and free of other debris and impurities.

[0057] Step 2: Spin-coat photoresist onto the surface of glass carrier 1, and then expose and develop it to form the pattern of the dam 2;

[0058] Step 3: According to the diagram of cofferdam 2, grooves are cut on glass carrier 1;

[0059] like Figure 4 , 5 As shown, this step involves using a blade to cut grooves in the glass based on the pattern after the cofferdam adhesive has been developed. The groove width and depth are usually set according to the size of the driver IC (groove width ≥ corresponding chip edge size + 50um, groove depth = driver IC thickness - RGB IC thickness and groove depth ≤ 1 / 3 of the glass thickness).

[0060] Step 4: Transfer and fix the LED chip 4 and driver chip 10 with DAF film 3 to the corresponding cavity and groove formed by the cofferdam 2 respectively;

[0061] like Figure 6 , 7 As shown, this step specifically involves using industry-standard laser mass transfer technology to position and bond the RGB LED IC (LED chip 4) within a separate groove enclosed by a cofferdam adhesive (fixed by the adhesiveness of the DAF film); then, using a wafer-level chip mounter, the driver IC (driver chip 10) is bonded into a glass groove. These actions complete the placement of 3 RGB ICs + 1 driver IC in specific positions.

[0062] Step 5: Perform vacuum compression molding to form an insulating layer 5 covering the chip and the surrounding dam 2;

[0063] This step uses glass as a carrier and black plastic encapsulation as an insulating layer 5. The encapsulation body needs to cover the entire chip.

[0064] Step 6: Thin and polish the molding compound to expose the bumps 7 on the chip surface;

[0065] like Figure 8 As shown, the glass + encapsulated body completed in this step is thinned by grinding on the encapsulated surface using a thinning machine. The grinding thickness must be calculated carefully to ensure that the bump cross-sections of the 3 RGB-ICs + 1 driver IC are exposed on a flat surface. Then, a surface chemical mechanical polishing (CMP) process is performed to make the substrate and encapsulation interface have a nanoscale roughness.

[0066] Step 7: Perform a rewiring process on the polished surface to form a rewiring layer 6 for interconnect lines;

[0067] like Figure 9 As shown, this step involves recoating the photoresist onto the polished molded surface using a coating machine, removing the edges, baking, and cooling to ensure a uniform layer of photoresist on the polished surface. Using a mask, exposure machine, and developer, the circuit pattern is pre-defined. The circuit is then plating in a chemical plating tank using conventional copper plating solutions, with copper as the main metal conductor of the circuit. Finally, the photoresist is removed to complete the rewiring process.

[0068] Step 8: Coat, expose, and develop the polyimide layer, and define the pad windows;

[0069] like Figure 10 As shown, this step involves spin-coating, baking, and cooling the PI adhesive using a coating machine to ensure that the rewiring surface is coated with a uniform thickness of PI adhesive. Then, the final device PAD size pattern is completed using an exposure machine and a developing machine.

[0070] Step 9: Form the UBM layer on the pad window;

[0071] This step involves using physical vapor deposition (PVD) to form a dense and strongly adherent titanium-tungsten thin film on the PI window of the wiring, thus creating a sputtered UBM titanium and copper layer.

[0072] Step 10: Place solder balls on the UBM layer to form an array of solder ball solder joints (9 arrays).

[0073] like Figure 11 As shown, this step involves first applying flux to the UBM, then using a wafer-level ball-mounting machine to place solder balls onto the UBM, and finally soldering the solder balls onto the UBM using a reflow oven.

[0074] Starting with a glass wafer, microfabrication techniques such as photolithography and grooving are used to pre-form dikes and grooves for precise chip placement. Then, mass transfer technology is employed to efficiently and accurately place the chip with a DAF film into a designated cavity. Next, wafer-level planarization is achieved through vacuum molding, thinning, and polishing. Finally, on the exposed bumps, rewiring, passivation layer opening, UBM deposition, and balling are performed sequentially to complete the entire package manufacturing. The core of this method is a fan-out wafer-level packaging route of "molding first, then wiring."

[0075] This fabrication method boasts significant process and product advantages: Firstly, wafer-level batch processing greatly improves production efficiency, consistency, and scalability, while reducing the manufacturing cost per device. Secondly, the method achieves passive chip alignment through dike-based grooving, ensuring packaging precision; the thinning and polishing process provides a perfectly flat surface for subsequent high-precision rewiring; and the innovative rewiring design directly solves the problem of uneven current distribution in traditional packaging. The overall process achieves a closed loop of structural innovation from design to manufacturing, providing a reliable technical path for the mass production of high-performance, ultra-thin Mini RGB devices.

[0076] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A wafer-level Mini RGB packaging structure, characterized in that, From bottom to top, the components are: ball bonding pad (9), base layer (8), redistribution layer (6), bump (7), chip, DAF film (3), and glass carrier (1). The chip includes a driver chip (10) and three LED chips (4) of different colors, wherein an insulating layer (5) is deposited between the driver chip (10) and the LED chips (4), and a dike (2) is covered on the surface of the insulating layer (5) away from the chip. Among them, the ball-mounted solder joint (9) is electrically connected to the redistribution layer (6), and the bump (7) is located between the chip and the redistribution layer (6).

2. The wafer-level Mini RGB packaging structure according to claim 1, characterized in that: The thickness of the DAF film (3) is 30-50 micrometers, which makes the light-emitting area of ​​the LED chip (4) recessed by 30-50 micrometers relative to the surface of the glass carrier.

3. The wafer-level Mini RGB packaging structure according to claim 1, characterized in that: The redistribution layer (6) is a copper conductor layer, and the ground terminal of each LED chip (4) of each luminous color is led out through the redistribution layer (6) to an independent input or output port.

4. The wafer-level Mini RGB packaging structure according to claim 1, characterized in that: The material of the bump (7) is SnAg alloy, wherein the height of the bump (7) used for the LED chip (4) is 2-5 micrometers, and the height of the bump (7) used for the driver chip (10) is 5-20 micrometers.

5. The wafer-level Mini RGB packaging structure according to claim 1, characterized in that: The cofferdam (2) is patterned using photoresist.

6. A method for fabricating a wafer-level Mini RGB package structure, characterized in that, The wafer-level Mini RGB packaging structure described in any one of claims 1-5, wherein the method for fabricating the wafer-level Mini RGB packaging structure specifically includes: S1. Provide a glass carrier (1) and perform cleaning treatment; S2. Photoresist is spin-coated onto the surface of the glass carrier (1), and the pattern of the dam (2) is formed by exposure and development. S3. According to the shape of the cofferdam (2), grooves are made on the glass carrier (1); S4. The LED chip (4) with DAF film (3) attached and the driver chip (10) are transferred and fixed into the corresponding cavity and groove formed by the cofferdam (2); S5. Perform vacuum compression molding to form an insulating layer (5) covering the chip and the dam (2). S6. Thin and polish the molding compound to expose the bumps (7) on the chip surface; S7. Perform a rewiring process on the polished surface to form a rewiring layer of interconnect lines (6). S8. Coat, expose and develop the polyimide layer, and define the pad windows; S9. Form a UBM layer on the pad window; S10. Balls are placed on the UBM layer to form an array of solder ball solder joints (9).

7. The method for fabricating a wafer-level Mini RGB packaging structure according to claim 6, characterized in that: In step S4, the DAF film of the LED chip (4) is attached to its light-emitting surface, and the DAF film of the driver chip (10) is attached to its wafer back side.

8. The method for fabricating a wafer-level Mini RGB packaging structure according to claim 6, characterized in that: In step S6, the surface roughness after polishing is at the nanometer level.

9. The method for fabricating a wafer-level Mini RGB packaging structure according to claim 6, characterized in that: In step S7, the rewiring process includes: spin coating of photoresist, exposure and development to form circuit patterns, chemical copper plating to form copper conductor layers, and removal of photoresist.

10. The method for fabricating a wafer-level Mini RGB packaging structure according to claim 6, characterized in that: In step S9, the UBM layer is formed into a titanium-tungsten or copper stacked structure through physical vapor deposition.

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