Display device and method for manufacturing a display device

Abstract

A display device and a method for manufacturing the same are disclosed. The display device according to an embodiment of the disclosure can include a substrate, a first pad disposed on the substrate, a bonding layer disposed on the first pad, a second pad disposed on the bonding layer and electrically connected to the first pad, a first light emitting element disposed on the second pad and having a first electrode electrically connected to the second pad, a first partition wall disposed between the substrate and the first light emitting element and disposed to connect one side of the first pad, one side of the bonding layer, and one side of the second pad, and a second partition wall disposed between the substrate and the first light emitting element and disposed to connect the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and a method for manufacturing the display device. Background Technology

[0002] Typically, in conventional display panel manufacturing methods, a panel substrate is formed, and then light-emitting elements are bonded to the substrate. This process is sequential, and it may be difficult to shorten the process time.

[0003] Recently, development is underway to enable mass production or large-scale panel manufacturing for display devices, shorten panel manufacturing time, and achieve environmentally friendly panel manufacturing.

[0004] The descriptions provided in the Background section should not be considered prior art simply because they are mentioned in or related to that section. The Background section may include information describing one or more aspects of the subject matter, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0005] Embodiments of this disclosure can provide a display device that can reduce panel manufacturing time and enable mass production, and a method for manufacturing the display device.

[0006] Embodiments of this disclosure can provide a display device for manufacturing environmentally friendly panels and a method for manufacturing the display device.

[0007] The embodiments of this disclosure can provide a display device that can reduce the panel defect rate and a method for manufacturing the display device.

[0008] Embodiments of this disclosure can provide a display device that can reduce or prevent short circuits between pads and a method for manufacturing the display device.

[0009] The benefits of the embodiments disclosed herein are not limited to those set forth herein, and other benefits not mentioned herein will be apparent to those skilled in the art from the following description.

[0010] Embodiments of this disclosure may provide a display device comprising: a substrate; a first pad disposed on the substrate; a bonding layer disposed on the first pad; a second pad disposed on the bonding layer and electrically connected to the first pad; a first light-emitting element disposed on the second pad and having a first electrode (e.g., an anode electrode) electrically connected to the second pad; a first partition wall disposed between the substrate and the first light-emitting element and configured to connect to one side of the first pad, one side of the bonding layer, and one side of the second pad; and a second partition wall disposed between the substrate and the first light-emitting element and configured to connect to the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

[0011] Embodiments of this disclosure provide a method for manufacturing a display device, the method comprising the following steps: forming a lower layer portion by sequentially forming a first sacrificial layer, a substrate, and a first pad on a first glass; forming an upper layer portion by sequentially forming a second sacrificial layer, a first light-emitting element, and a second pad on a second glass; bonding the upper layer portion to the lower layer portion; and removing the first glass, the first sacrificial layer, the second sacrificial layer, and the second glass, wherein, after the step of bonding the upper layer portion to the lower layer portion, the first pad and the second pad are electrically connected to each other through a bonding layer disposed between the first pad and the second pad, and after the step of bonding the upper layer portion to the lower layer portion, a first partition wall and a second partition wall are formed, the first partition wall being disposed between the substrate and the first light-emitting element and configured to connect to one side of the first pad, one side of the bonding layer, and one side of the second pad, and the second partition wall being disposed between the substrate and the first light-emitting element and configured to connect to the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

[0012] According to embodiments of this disclosure, a display device capable of reducing panel manufacturing time and enabling mass production can be provided.

[0013] According to embodiments of this disclosure, a display device capable of reducing greenhouse gases by optimizing panel manufacturing processes can be provided.

[0014] Embodiments of this disclosure can provide a display device that can reduce the defect rate of a display panel by including partition walls in the display panel, and a method for manufacturing the display device.

[0015] The effects of this disclosure are not limited to the foregoing benefits, and other effects will be apparent to those skilled in the art from the following detailed description.

[0016] Other systems, methods, features, and advantages will be apparent to those skilled in the art, or will become apparent, upon review of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this specification, within the scope of this disclosure, and protected by the appended claims. The contents of this section should not be construed as limiting these claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0017] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0018] This disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0019] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment of the present disclosure;

[0020] Figure 2 This is a diagram illustrating the circuit structure of a sub-pixel according to an embodiment of the present disclosure;

[0021] Figure 3 This is a cross-sectional view illustrating a display panel according to an embodiment of the present disclosure;

[0022] Figure 4 This is a diagram illustrating the sequence of manufacturing a display panel according to an embodiment of the present disclosure;

[0023] Figures 5 to 7 An example of a manufacturing process for forming a partition wall on the lower portion of a panel according to an embodiment of the present disclosure is illustrated.

[0024] Figure 8 An example of the joining upper portion and according to an embodiment of the present disclosure is illustrated. Figure 7 The process of the lower layer;

[0025] Figures 9 to 11 A manufacturing process for forming a partition wall on the upper portion of a panel according to an embodiment of the present disclosure is illustrated.

[0026] Figure 12 An example of the joining lower layer portion and according to an embodiment of the present disclosure is illustrated. Figure 11 The process of the upper part of the process; and

[0027] Figure 13 An example is illustrated of a process for joining an upper portion having a partition wall and a lower portion having a partition wall according to an embodiment of the present disclosure.

[0028] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0029] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where it is determined that such detailed descriptions unnecessarily obscure the essential points of the inventive concept. The progression of the described processing steps and / or operations is illustrative; however, the order of steps and / or operations is not limited to that described herein and can be varied as is known in the art, except for steps and / or operations that need to occur in a specific order. Similar reference numerals always denote similar elements. The names of corresponding elements used in the following explanation may have been chosen merely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0030] The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0031] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are shown by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted or may be provided briefly where it is determined that the description might make the subject matter of some embodiments of this disclosure considerably unclear. Unless terms are used with the term “only,” terms such as “comprising,” “having,” “containing,” “constituting,” “forming,” “component,” and “form” as used herein are generally intended to allow for the addition of additional components. When used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0032] Any implementation described as an "example" in this article is not necessarily to be interpreted as being more preferred or advantageous than other implementations.

[0033] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0034] When it is mentioned that the first element is "connected to or linked to," "contacts with or overlaps" the second element, it can be understood that not only can the first element be "directly connected to or linked to" or "directly contact or overlaps" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected to or linked to," "contacts with or overlaps" each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected to or linked to," "contacts with," or "overlaps" each other.

[0035] When time-relative terms such as “after,” “following,” “next,” “before,” etc., are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation unless the terms “directly” or “immediately” are used together.

[0036] Additionally, when referring to any size, relative size, etc., it can be assumed that the numerical or corresponding information of a component or feature (e.g., level, range, etc.) includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even if no relevant description is specified. Furthermore, the term "may" fully encompasses all the meanings of the term "able to".

[0037] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first, second, and third elements, or any combination or all combinations of the first, second, and third elements. By way of example, A, B, and / or C can refer to only A; only B; only C; any combination or some combination of A, B, and C; or all of A, B, and C.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0039] Instead, these embodiments may be provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0040] Those skilled in the art will understand that various modifications and variations can be made to the display device and the method for manufacturing the display device without departing from the technical concept or scope of this disclosure. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

[0041] Various embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a diagram illustrating the configuration of a display device 100 according to an embodiment of the present disclosure.

[0043] Reference Figure 1 The display device 100 may include a display panel 110, a data driving circuit 130, a gating driving circuit 120, and a controller 140.

[0044] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images.

[0045] The display panel 110 may include a substrate 111, a plurality of sub-pixels SP disposed on the substrate 111, and various types of signal lines for driving the plurality of sub-pixels SP. The plurality of sub-pixels SP may be disposed in a display area DA.

[0046] Various types of signal lines can include multiple data lines (DL) that transmit data signals (also known as data voltages or image signals) and multiple gating lines (GL) that transmit gating signals (also known as scan signals). The multiple data lines (DL) and multiple gating lines (GL) can intersect each other.

[0047] Each of the multiple data lines DL can be set while extending in a first direction. Each of the multiple gating lines GL can be set while extending in a second direction. Here, the first direction can be a column direction and the second direction can be a row direction. For ease of description, it is assumed below that the data lines DL are set in the column direction and the gating lines GL are set in the row direction.

[0048] The data drive circuit 130 is used to drive the data line DL and can output a data signal to the data line DL. The gating drive circuit 120 is used to drive the gating line GL and can output a gating signal to the gating line GL. The controller 140 is a device for controlling the data drive circuit 130 and the gating drive circuit 120 and can control the driving timing of the data line DL and the driving timing of the gating line GL.

[0049] The controller 140 can supply a data drive control signal DCS to the data drive circuit 130 to control the data drive circuit 130, and can supply a gating drive control signal GSC to the gating drive circuit 120 to control the gating drive circuit 120.

[0050] The data drive circuit 130 can supply the data signal DATA to multiple data lines DL according to the timing control of the controller 140. The data drive circuit 130 can receive digital image data from the controller 140 and can convert the received image data into analog data signals and output them to multiple data lines DL.

[0051] The gating drive circuit 120 can supply gating signals to multiple gating lines GL according to the timing control of the controller 140. The gating drive circuit 120 can receive a first gating voltage corresponding to the on level voltage and a second gating voltage corresponding to the off level voltage, as well as various gating drive control signals (e.g., start signal and reset signal), generate gating signals, and supply the generated gating signals to the multiple gating lines GL.

[0052] For example, the data drive circuit 130 can be connected to the display panel 110 via tape-on-brush (TAB) method, or to the bonding pads of the display panel 110 via chip-on-glass (COG) or chip-on-panel (COP) method, or it can be implemented and connected to the display panel 110 via chip-on-film (COF) method. For ease of description, it is assumed below that the data drive circuit 130 is connected to the display panel 110 as a chip-on-film (COF) type.

[0053] The gate drive circuit 120 can be connected to the display panel 110 via the TAB method, or to the bonding pads of the display panel 110 via the COG or COP method, or it can be connected to the display panel 110 via the COF method. Alternatively, the gate drive circuit 120 can be formed as a gate in panel (GIP) type in the non-display area or display area of ​​the display panel 110.

[0054] Furthermore, at least one of the data driving circuit 130 and the gating driving circuit 120 may be disposed in the display area of ​​the display panel 110. For example, at least one of the data driving circuit 130 and the gating driving circuit 120 may not overlap with the sub-pixel SP, or all or part of at least one of the data driving circuit 130 and the gating driving circuit 120 may overlap with the sub-pixel SP.

[0055] The data driving circuit 130 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving scheme or panel design, the data driving circuit 130 can be connected to both sides (e.g., the top and bottom sides) of the display panel 110 or two or more of the four sides of the display panel 110.

[0056] The gating drive circuit 120 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving scheme or panel design, the gating drive circuit 120 can be connected to both sides (e.g., the left and right sides) of the display panel 110 or two or more of the four sides of the display panel 110.

[0057] The controller 140 can be implemented as a component separate from the data drive circuitry 130, or the controller 140 and the data drive circuitry 130 can be integrated into an integrated circuit (IC). The controller 140 can be a timing controller used in typical display technologies, a control device capable of performing other control functions as well as the functions of a timing controller, or a control device other than a timing controller, or it can be circuitry within a control device. The controller 140 can be implemented as various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0058] The controller 140 can be mounted on a printed circuit board or flexible printed circuit board and can be electrically connected to the data drive circuit 130 and the strobe drive circuit 120 via the printed circuit board or flexible printed circuit board. The controller 140 can send / receive signals to / from the data drive circuit 130 according to one or more predetermined interfaces. The interfaces may include, for example, a low-voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0059] Figure 2 This is a diagram illustrating the circuit structure of a sub-pixel SP disposed on a display device 100 according to an embodiment of the present disclosure.

[0060] Reference Figure 2 According to embodiments of the present disclosure, a sub-pixel SP disposed on a display panel 110 of a display device 100 may include one or more transistors and capacitors and may have a light-emitting element ED disposed therein. For example, a sub-pixel SP may include a driving transistor DRT, a scanning transistor SCT, a storage capacitor Cst, and a light-emitting element ED.

[0061] The driving transistor DRT is a transistor used to drive the light-emitting element ED, and may include a first node N1, a second node N2 and a third node N3.

[0062] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and the first node N1 of the driving transistor DRT can be electrically connected to the source node or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT can be the source node or drain node of the driving transistor DRT, and the second node N2 of the driving transistor DRT can be electrically connected to the pixel electrode PE of the light-emitting element ED. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that supplies the driving voltage EVDD.

[0063] The scanning transistor SCT can be controlled by a scan pulse SCAN, which serves as a gating signal, and can be connected between the first node N1 of the driving transistor DRT and the data line DL. In other words, the scanning transistor SCT can be turned on or off according to the scan pulse SCAN supplied from the scan line SCL, which serves as a gating line GL, thereby controlling the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0064] The scanning transistor SCT can be turned on by the scanning pulse SCAN with a turn-on voltage and transmit the data signal Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0065] If the scanning transistor SCT is an n-type transistor, the on-state voltage of the scanning pulse SCAN can be a high-level voltage. If the scanning transistor SCT is a p-type transistor, the on-state voltage of the scanning pulse SCAN can be a low-level voltage.

[0066] A storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference between its two ends and is used to maintain the voltage difference between its two ends for a predetermined frame time. Therefore, the corresponding sub-pixel SP can emit light during the predetermined frame time.

[0067] Figure 2 An example is shown of a light-emitting element ED in a display panel 110 according to an embodiment of the present disclosure.

[0068] Each of the plurality of light-emitting elements ED disposed in the display panel 110 according to embodiments of the present disclosure may be a light-emitting diode (LED) based on inorganic materials. For example, each of the plurality of light-emitting elements ED may be a miniature light-emitting diode (micro-LED). For example, each of the plurality of light-emitting elements ED may be a vertical light-emitting diode.

[0069] Each of the plurality of light-emitting elements ED may include a first electrode E1, a first semiconductor layer 210, an active layer 215, a second semiconductor layer 220, and a second electrode E2.

[0070] For example, the first electrode E1 can be an anode electrode, and the second electrode E2 can be a cathode electrode. As another example, the first electrode E1 can be a cathode electrode, and the second electrode E2 can be an anode electrode.

[0071] For example, the first electrode E1 may include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). For example, the second electrode E2 may be formed of a transparent metallic material (transparent conductive material: TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that can transmit light.

[0072] The first semiconductor layer 210 may be disposed on the first electrode E1. For example, the first semiconductor layer 210 may be a p-type semiconductor and may include a semiconductor material having the formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), but this disclosure is not limited thereto. For example, the semiconductor material included in the first semiconductor layer 210 may be any one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with p-type dopant, but this disclosure is not limited thereto. The first semiconductor layer 210 may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, Se, Ba, etc., but this disclosure is not limited thereto. For example, the first semiconductor layer 210 may be p-type GaN doped with p-type Mg, but this disclosure is not limited thereto.

[0073] Furthermore, the light-emitting element (ED) may also include an electron blocking layer disposed on the first semiconductor layer 210. The electron blocking layer may be a layer used to suppress or prevent excessive electron flow to the active layer 215. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg, but this disclosure is not limited thereto. The electron blocking layer may be omitted.

[0074] The active layer 215 can be disposed on the first semiconductor layer 210 or the electron blocking layer. The active layer 215 can emit light through electron-hole recombination based on an electrical signal applied through the first semiconductor layer 210 and the second semiconductor layer 220. The active layer 215 can emit one of a first color light, a second color light, and a third color light. For example, the first color light can be red light, the second color light can be green light, and the third color light can be blue light.

[0075] The active layer 215 may comprise a material having a single quantum well structure or a multiple quantum well structure. When the active layer 215 comprises a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers can be alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but this disclosure is not limited thereto.

[0076] Alternatively, the active layer 215 may have a structure in which semiconductor materials with high bandgap energy and semiconductor materials with low bandgap energy are alternately stacked, or may include group III to group V semiconductor materials that vary depending on the wavelength of the emitted light. For example, when indium is included among the semiconductor materials included in the active layer 215, the color of the emitted light can vary depending on the indium content. For example, as the indium content increases, longer wavelength light can be emitted. For example, if the indium content is about 15%, the active layer 215 can emit blue wavelength light; if the indium content is about 25%, the active layer 215 can emit green wavelength light; and if the indium content is about 35% or more, the active layer 215 can emit red wavelength light.

[0077] Furthermore, the light-emitting element (ED) may also include a superlattice layer disposed on the active layer 215. The superlattice layer may be a layer used to alleviate stress between the second semiconductor layer 220 and the active layer 215. For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0078] The second semiconductor layer 220 may be disposed on the active layer 215 or the superlattice layer. For example, the second semiconductor layer 220 may be an n-type semiconductor and may include semiconductor materials having the formula AlxGayIn1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), but this disclosure is not limited thereto. For example, the semiconductor material included in the second semiconductor layer 220 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with n-type dopant, but this disclosure is not limited thereto. For example, the second semiconductor layer 220 may be doped with an n-type dopant, and the n-type dopant may be Si, Ge, Sn, etc., but this disclosure is not limited thereto. For example, the second semiconductor layer 220 may be an n-type GaN doped with n-type Si, but this disclosure is not limited thereto.

[0079] The second electrode E2 can be disposed on the second semiconductor layer 220.

[0080] The light-emitting element ED may also include an insulating film 230 for protecting the light-emitting element ED.

[0081] The insulating film 230 can be disposed on the side surface of the first electrode E1.

[0082] The insulating film 230 can be disposed on the side surfaces of the first semiconductor layer 210, the second semiconductor layer 220, and the active layer 215.

[0083] For example, the insulating film 230 may be formed of any one of silicon oxide film (SiOx) and silicon nitride film (SiNx) or a stacked structure thereof.

[0084] Figure 3 This is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0085] The first pad 310 can be disposed on the substrate 300.

[0086] The first pad can be made of metal.

[0087] The bonding layer 330 can be disposed on the first pad 310.

[0088] The second pad 320 is disposed on the bonding layer 330 and can be electrically connected to the first pad 310.

[0089] The first light-emitting element ED1 is disposed on the second pad 320 and may have a first electrode E1 electrically connected to the second pad 320. For example, the first electrode E1 may be an anode electrode.

[0090] The first partition wall 340 can be disposed between the substrate 300 and the first light-emitting element ED1, and can be configured to be connected to one side of the first pad 310, one side of the bonding layer 330, and one side of the second pad 320.

[0091] The second partition wall 350 can be disposed between the substrate 300 and the first light-emitting element ED1, and can be configured to connect to the other side of the first pad 310, the other side of the bonding layer 330, and the other side of the second pad 320.

[0092] The above explanation also applies to the second light-emitting element ED2 and the third light-emitting element ED3.

[0093] The bonding layer 330 may include an anisotropic conductive film (ACF).

[0094] It may also include an optical layer 390 surrounding the first light-emitting element ED1. The optical layer 390 may include fine particles.

[0095] The optical layer 390 may include an organic insulating material with dispersed fine particles, but embodiments of the present disclosure are not limited thereto. For example, the optical layer 390 may be formed of a siloxane containing dispersed fine metal particles, such as titanium dioxide (TiO2) particles, but embodiments of the present disclosure are not limited thereto. Light from the multiple light-emitting elements (EDs) can be scattered and emitted to the outside of the display device 100 by the fine particles dispersed in the optical layer 390. Therefore, the optical layer 390 can improve the extraction efficiency of light emitted from the multiple light-emitting elements (EDs).

[0096] A transparent insulating layer 380 can be disposed on the light-emitting element ED. The transparent insulating layer 380 can be formed of an organic material.

[0097] The adhesive layer 360 can be disposed between the light-emitting element ED and the transparent insulating layer 380.

[0098] The common electrode 370 can be disposed on the light-emitting element ED and can be electrically connected to the second electrode E2 of the light-emitting element ED.

[0099] The adhesive layer 360 can be disposed between the light-emitting element ED and the common electrode 370, and the common electrode 370 can be electrically connected to the second electrode E2 of the light-emitting element through the holes of the adhesive layer 360. The adhesive layer 360 may include a conductive material.

[0100] The common electrode 370 can be electrically connected to the second electrode E2 of the light-emitting element ED through the adhesive layer 360.

[0101] Figure 4 This is a diagram illustrating the sequence of manufacturing the display panel 110 according to an embodiment of the present disclosure.

[0102] It may include a lower layer forming step S10, an upper layer forming step S20, a step S30 of joining the upper layer to the lower layer, and a step S40 of removing the sacrificial layer and the glass.

[0103] The process can be performed simultaneously in both the lower layer forming step S10 and the upper layer forming step S20.

[0104] In order to create the formation of such Figure 3 The display panel 110 of the partition wall shown can be used to describe three embodiments of this disclosure. The method of forming the partition wall is not limited thereto.

[0105] The partition wall may be formed only in the lower part, only in the upper part, or in both the lower and upper parts.

[0106] Figures 5 to 7 A manufacturing process for forming a partition wall on the lower layer of a panel according to an embodiment of the present disclosure is illustrated.

[0107] exist Figure 5 In the lower layer, the sacrificial layer 510, the substrate 300, and the insulating layer 520 can be sequentially formed on the first glass 500.

[0108] exist Figure 6 In the process, the insulating layer 520 of the lower layer can be etched to form a partition wall including a first partition wall 340 and a second partition wall 350.

[0109] exist Figure 7 In this process, the first pad 310 can be formed between the first partition wall 340 and the second partition wall 350.

[0110] Figure 8 This illustrates an embodiment of the present disclosure of a superstructure and a portion thereof having an upper layer. Figure 7 A diagram illustrating the process of joining the lower part of the partition wall.

[0111] The steps of forming the lower layer may include forming a first partition wall 340 and a second partition wall 350 on the substrate 300.

[0112] In the upper layer, a sacrificial layer 810, an adhesive layer 360, a light-emitting element ED, and a second pad 320 can be sequentially formed on the second glass 800. An optical layer 390 can also be formed between the light-emitting elements ED.

[0113] The upper part can be joined to, for example Figure 7 The lower portion of the partition wall shown is formed, comprising a first partition wall and a second partition wall.

[0114] The first pad in the lower layer and the second pad in the upper layer can be electrically connected via a bonding layer. The bonding layer may include anisotropic conductive film (ACF).

[0115] Figures 9 to 11 This is a diagram illustrating the process of manufacturing a partition wall on the upper portion of a panel according to an embodiment of the present disclosure.

[0116] exist Figure 9 In the upper part, a sacrificial layer, an adhesive layer, a light-emitting element, and an insulating layer can be formed on the second glass.

[0117] The steps of forming the upper part may include forming an optical layer 390 surrounding the first light-emitting element ED1 and forming a first partition wall 340 and a second partition wall 350 on the optical layer 390.

[0118] An optical layer 390 can be formed around the light-emitting elements ED, including the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3.

[0119] exist Figure 10 In this process, the partition walls, including the first partition wall 340 and the second partition wall 350, can be formed by etching the upper insulating layer 900. The etched area may be the area corresponding to the first electrode on the light-emitting element. The first partition wall 340 and the second partition wall 350 may include organic materials.

[0120] exist Figure 11 In this process, the second pad 320 can be formed between the first partition wall 340 and the second partition wall 350.

[0121] Figure 12 This illustrates an embodiment of the present disclosure in which a [structure / formation] is formed. Figure 11 A diagram illustrating the process of joining the upper part of the partition wall to the lower part.

[0122] In the lower layer, the sacrificial layer 510, the substrate 300, and the first pad 310 can be sequentially formed on the first glass 500.

[0123] Among them, there are Figure 11 The upper portion of the partition wall can be bonded to the lower portion. The first pad 310 of the lower portion and the second pad 320 of the upper portion can be electrically connected to each other through a bonding layer 330. The bonding layer 330 may include anisotropic conductive film (ACF).

[0124] Figure 13 This is a diagram illustrating a process for joining an upper portion having a partition wall and a lower portion having a partition wall according to an embodiment of the present disclosure.

[0125] The sacrificial layer 510, substrate 300, first pad 310, first lower partition wall 1320 and second lower partition wall 1330 can be sequentially formed on the first glass 500.

[0126] In the upper layer, a sacrificial layer 810, an adhesive layer 360, a light-emitting element ED, a second pad 320, a first upper partition wall 1300, and a second upper partition wall 1310 can be formed on the second glass 800. An optical layer can also be formed between the first light-emitting element ED1 and the second light-emitting element ED2. An optical layer 390 can be formed between the light-emitting elements ED.

[0127] The lengths of the first lower partition wall 1320, the second lower partition wall 1330, the first upper partition wall 1300, and the second upper partition wall 1310 may be half the lengths of the first partition wall 340 and the second partition wall 350. The first lower partition wall 1320, the second lower partition wall 1330, the first upper partition wall 1300, and the second upper partition wall 1310 may include organic materials.

[0128] The upper portion having the first upper partition wall 1300 and the second upper partition wall 1310 can be joined to the lower portion having the first lower partition wall 1320 and the second lower partition wall 1330.

[0129] The lower and upper portions can be electrically connected to each other via bonding layer 330. The first pad 310 and the second pad 320 can be electrically connected to each other via bonding layer 330. Bonding layer 330 may include anisotropic conductive film (ACF).

[0130] According to the embodiments described above in this disclosure, process time can be reduced by manufacturing the lower and upper portions separately. Process productivity can be improved by shortening the process time.

[0131] In addition, short circuits that may occur between pads can be reduced or prevented by forming a partition wall between the first pad 310 and the second pad 320.

[0132] The display device according to embodiments of the present disclosure can be described as follows.

[0133] A display device according to an embodiment of the present disclosure may include: a first pad disposed on a substrate; a bonding layer disposed on the first pad; a second pad disposed on the bonding layer and electrically connected to the first pad; a first light-emitting element disposed on the second pad and having a first electrode electrically connected to the second pad; a first partition wall disposed between the substrate and the first light-emitting element and configured to connect to one side of the first pad, one side of the bonding layer, and one side of the second pad; and a second partition wall disposed between the substrate and the first light-emitting element and configured to connect to the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

[0134] For example, the first electrode can be the anode electrode.

[0135] The first and second partition walls may include organic materials.

[0136] The bonding layer may include anisotropic conductive film (ACF).

[0137] The display device may also include an optical layer surrounding the first light-emitting element.

[0138] The optical layer may include fine particles.

[0139] The display device may also include a transparent insulating layer disposed on the first light-emitting element.

[0140] The display device may also include an adhesive layer disposed between the light-emitting element and the transparent insulating layer.

[0141] The display device may also include a common electrode disposed on the light-emitting element and electrically connected to the second electrode of the light-emitting element.

[0142] The display device may also include an adhesive layer disposed between the light-emitting element and the common electrode.

[0143] The common electrode can be electrically connected to the second electrode of the light-emitting element through the holes in the adhesive layer.

[0144] The display device may also include an adhesive layer disposed between the light-emitting element and the common electrode and comprising a conductive material.

[0145] The common electrode can be electrically connected to the second electrode of the light-emitting element through an adhesive layer.

[0146] According to embodiments of this disclosure, a method for manufacturing a display device may include the following steps: forming a lower layer portion by sequentially forming a first sacrificial layer, a substrate, and a first pad on a first glass; forming an upper layer portion by sequentially forming a second sacrificial layer, a first light-emitting element, and a second pad on a second glass; bonding the upper layer portion to the lower layer portion; and removing the first glass, the first sacrificial layer, the second sacrificial layer, and the second glass, wherein, after the step of bonding the upper layer portion to the lower layer portion, the first pad and the second pad can be electrically connected to each other through a bonding layer disposed between the first pad and the second pad, and after the step of bonding the upper layer portion to the lower layer portion, a first partition wall and a second partition wall can be formed, the first partition wall being disposed between the substrate and the first light-emitting element and configured to connect to one side of the first pad, one side of the bonding layer, and one side of the second pad, and the second partition wall being disposed between the substrate and the first light-emitting element and configured to connect to the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

[0147] The steps of forming the lower layer may include forming a first partition wall and a second partition wall on the substrate.

[0148] The steps of forming the upper part may include forming an optical layer surrounding the first light-emitting element, and forming a first partition wall and a second partition wall on the optical layer.

[0149] The steps of forming the lower layer may include forming a first lower partition wall and a second lower partition wall on a substrate. The steps of forming the upper layer may include forming an optical layer surrounding the first light-emitting element, and forming a first upper partition wall and a second upper partition wall on the optical layer. After the steps of bonding the upper layer to the lower layer, the first lower partition wall and the first upper partition wall may contact each other to form a first partition wall, and the second lower partition wall and the second upper partition wall may contact each other to form a second partition wall.

[0150] The method may further include the following steps: after removing the first glass, forming a common electrode on the first light-emitting element, and forming a transparent insulating layer on the common electrode.

[0151] In the step of bonding the upper layer to the lower layer, the first pad and the second pad can be bonded to each other through anisotropic conductive film (ACF).

[0152] The foregoing description has been presented to enable those skilled in the art to make and use the technical concepts of this disclosure, and the foregoing description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the technical concepts and scope of this disclosure. The foregoing description and figures are provided as examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

[0153] Cross-reference to related applications

[0154] This application claims priority to Korean Patent Application No. 10-2024-0186264, filed on December 13, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: substrate; A first pad is disposed on the substrate; A bonding layer is disposed on the first pad; The second pad is disposed on the bonding layer and electrically connected to the first pad; A first light-emitting element is disposed on the second pad and has a first electrode electrically connected to the second pad; as well as A first partition wall is disposed between the substrate and the first light-emitting element and is configured to connect to one side of the first pad, one side of the bonding layer, and one side of the second pad. as well as A second partition wall is disposed between the substrate and the first light-emitting element and is configured to connect to the other side of the first pad, the other side of the bonding layer, and the other side of the second pad.

2. The display device according to claim 1, wherein, The first and second partition walls comprise organic materials.

3. The display device according to claim 1, wherein, The bonding layer includes an anisotropic conductive film.

4. The display device according to claim 1, wherein the display device further comprises an optical layer surrounding the first light-emitting element.

5. The display device according to claim 4, wherein, The optical layer comprises fine particles.

6. The display device according to claim 1, wherein the display device further comprises a transparent insulating layer disposed on the first light-emitting element.

7. The display device according to claim 6, further comprising an adhesive layer disposed between the light-emitting element and the transparent insulating layer.

8. The display device according to claim 1, further comprising a common electrode disposed on the light-emitting element and electrically connected to the second electrode of the light-emitting element.

9. The display device according to claim 8, further comprising an adhesive layer disposed between the light-emitting element and the common electrode. in, The common electrode is electrically connected to the second electrode of the light-emitting element through the holes in the adhesive layer.

10. The display device according to claim 8, further comprising an adhesive layer disposed between the light-emitting element and the common electrode and comprising a conductive material. in, The common electrode is electrically connected to the second electrode of the light-emitting element through the adhesive layer.

11. A method for manufacturing a display device, the method comprising the following steps: The lower layer is formed by sequentially forming a first sacrificial layer, a substrate, and a first pad on the first glass. The upper layer is formed by sequentially forming a second sacrificial layer, a first light-emitting element, and a second pad on the second glass. The upper portion is joined to the lower portion; as well as Remove the first glass, the first sacrificial layer, the second sacrificial layer, and the second glass. After the step of bonding the upper layer portion to the lower layer portion, the first pad and the second pad are electrically connected to each other through a bonding layer disposed between the first pad and the second pad, and After the step of bonding the upper layer to the lower layer, a first partition wall and a second partition wall are formed. The first partition wall is disposed between the substrate and the first light-emitting element and is configured to connect to one side of the first pad, one side of the bonding layer and one side of the second pad. The second partition wall is disposed between the substrate and the first light-emitting element and is configured to connect to the other side of the first pad, the other side of the bonding layer and the other side of the second pad.

12. The method according to claim 11, wherein, The steps of constituting the lower layer include forming the first partition wall and the second partition wall on the substrate.

13. The method according to claim 11, wherein, The steps constituting the upper layer include the following: Forming an optical layer surrounding the first light-emitting element; and The first partition wall and the second partition wall are formed on the optical layer.

14. The method according to claim 11, wherein, The steps constituting the lower layer include the following: Forming a first lower partition wall and a second lower partition wall on the substrate, wherein the steps constituting the upper layer portion include the following steps: Forming an optical layer surrounding the first light-emitting element; and A first upper partition wall and a second upper partition wall are formed on the optical layer, and In this process, after the step of joining the upper portion to the lower portion, the first lower partition wall and the first upper partition wall come into contact with each other to form the first partition wall, and the second lower partition wall and the second upper partition wall come into contact with each other to form the second partition wall.

15. The method according to claim 11, further comprising the step of: After the step of removing the first glass, a common electrode is formed on the first light-emitting element; and A transparent insulating layer is formed on the common electrode.

16. The method according to claim 11, wherein, In the step of bonding the upper portion to the lower portion, the first pad and the second pad are bonded to each other via an anisotropic conductive film (ACF).

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