A laminated battery and a method for manufacturing the same, a photovoltaic module, and a photovoltaic system

Abstract

The application relates to the technical field of solar cells, and particularly discloses a laminated cell, a preparation method thereof, a photovoltaic module and a photovoltaic system. The laminated cell comprises a bottom cell and a top cell. The bottom cell comprises a silicon substrate with a first surface and a second surface arranged oppositely. The second surface is provided with a first area and a second area. The first area surrounds the second area and has a higher surface than the second area, thereby forming a height difference. The top cell is arranged in the second area. The application constructs a high-low step structure on the surface of the same substrate. Without adding an additional protective layer and sacrificing the effective power generation area, the solution bypassing problem in the preparation of a perovskite layer by slit coating is effectively solved, the leakage current is significantly reduced, and the photoelectric conversion efficiency of the cell and the production yield are improved. The application further provides a preparation method of the laminated cell, a photovoltaic module comprising the laminated cell and a photovoltaic system. The application has a simple process and controllable cost, and is suitable for large-scale industrial production.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a tandem solar cell and its preparation method, photovoltaic module, and photovoltaic system. Background Technology

[0002] Perovskite / crystalline silicon tandem solar cells have become a research hotspot in the photovoltaic field due to their ability to more effectively utilize the solar spectrum and break through the efficiency limit of single-junction cells. During the fabrication of the top-mounted cell, the film quality of the perovskite absorber layer directly affects the device performance. For large-area perovskite tandem cells, the slot coating method has become the most widely used method due to its advantages such as precise control of the coating area, adjustment of coating speed and coating amount.

[0003] However, the existing technology has the following technical problems: Due to the good fluidity of the perovskite solution, during the slot coating process, the solution is prone to "liquid entanglement"—that is, the perovskite solution flows to the side or even the bottom surface of the bottom cell, contaminating the non-deposition area of ​​the bottom cell. Liquid entanglement contamination leads to short circuits between the top and bottom cells, significantly increasing leakage current and severely reducing photoelectric conversion efficiency and production yield.

[0004] To address the aforementioned issues, existing technologies, such as CN118284072A, disclose a perovskite tandem solar cell. This cell utilizes a first carrier transport layer on a bottom cell and a closed-frame-shaped side protective layer at the upper surface edge of the first carrier transport layer to block the flow of the perovskite solution. However, this approach has the following drawbacks: First, the fabrication of the side protective layer requires additional processes such as mask evaporation, atomic layer deposition, inkjet printing, screen printing, or transfer printing, resulting in complex processes and significantly increased costs. Second, the side protective layer occupies the effective power generation area of ​​the cell, leading to a decrease in power density. Third, the interface matching problem between the protective layer material and the perovskite layer may introduce new carrier recombination centers, affecting cell performance.

[0005] Therefore, developing a tandem battery structure and fabrication method that can effectively prevent perovskite solution from swirling around the liquid without adding extra structures or sacrificing the effective power generation area is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] This invention aims to solve the technical problem that when preparing the perovskite layer in a slit coating process for existing perovskite / crystalline silicon tandem solar cells, the solution wrapping causes contamination of the bottom cell's side and bottom surfaces, resulting in leakage current, short circuits, reduced photoelectric conversion efficiency, and lower yield. At the same time, it overcomes the shortcomings of existing side protection layer solutions, such as complex processes, high costs, and sacrifice of effective power generation area.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a stacked battery, comprising:

[0009] A bottom battery, and a top battery disposed on the bottom battery;

[0010] The bottom cell includes a silicon substrate having a first side and a second side disposed opposite to each other;

[0011] The second surface includes a first region and a second region, the first region is disposed around the second region, and the surface of the first region is higher than the surface of the second region, forming a height difference Y;

[0012] The top battery is disposed in the second region.

[0013] This invention constructs a stepped structure with a height difference directly on the second surface of the bottom cell, using this stepped structure as a physical barrier during perovskite solution coating. When the perovskite top cell is fabricated in the second region using the slot coating method, this stepped structure effectively prevents the perovskite solution from flowing outward to the sides and bottom of the bottom cell, thereby avoiding liquid contamination and the resulting leakage and short circuit problems.

[0014] Further, the height difference Y is 1μm-5μm; and / or, the width X of the first region is 0.1mm-2.9mm.

[0015] Furthermore, the surface of the second region has a velvety structure with a height of 0.5μm-1.2μm.

[0016] Furthermore, the top battery includes a transparent conductive layer, a hole transport layer, a light-absorbing layer, an electron transport layer, and a carrier recombination layer stacked sequentially; the upper surface of the light-absorbing layer is not higher than the upper surface of the first region.

[0017] Furthermore, the bottom cell structure includes, but is not limited to, TOPCon cells, HJT cells, PERC cells, POLO and other crystalline silicon cells; the top cell is a perovskite cell.

[0018] In a second aspect, the present invention provides a method for preparing a tandem battery, comprising the following steps:

[0019] S1. Preparation of the bottom cell:

[0020] A silicon substrate having a first side and a second side arranged opposite to each other is provided;

[0021] A mask layer is formed on the second surface of the silicon substrate, wherein the edge region of the second surface of the silicon substrate covered by the mask layer is defined as a first region, and the central region of the exposed second surface of the silicon substrate is defined as a second region;

[0022] The second region is etched so that the surface of the second region is lower than the surface of the first region, forming a height difference Y;

[0023] S2. Formation of the top cell: A top cell is formed in the second region.

[0024] Furthermore, the mask layer includes SiO2. X Layer, SiN X Layer or Al2O X At least one of the layers has a thickness of 10nm-100nm, and the designed width of the first region is 0.2mm-3mm; the etching process for the second region is alkaline etching, the concentration of the etching solution is 0.5wt%-10wt%, and after etching, the height difference Y between the first region and the second region is 1μm-5μm, and the width X of the first region after etching is 0.1mm-2.9mm.

[0025] Furthermore, the etching process further includes a second texturing step on the second region, using a low-concentration alkaline solution to etch and form a texturing structure with a texturing height of 0.5μm-1.2μm.

[0026] Furthermore, the process after removing the mask layer also includes a passivation step: depositing a passivation layer on the surface and sidewalls of the first region, the passivation layer comprising SiO2. X Layers and / or SiN X Layer; hydrogen passivation is performed in the second region, wherein the hydrogen passivation is performed in an NH3 atmosphere with an NH3 flow rate of 6000ml~20000ml.

[0027] Thirdly, the present invention provides a photovoltaic module, including a battery string, the battery string being formed by connecting multiple stacked cells as described above or stacked cells prepared by the above-described method for preparing stacked cells; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0028] Fourthly, the present invention provides a photovoltaic system including the photovoltaic module described above.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The present invention constructs a stepped structure with the first region higher than the second region on the second side of the same crystalline silicon bottom cell, forming a physical dam during slit coating, effectively blocking the outward flow of perovskite solution, completely solving the problem of contamination on the side and bottom of the bottom cell caused by solution entanglement, significantly reducing leakage current, and improving the photoelectric conversion efficiency and production yield of the cell.

[0031] (2) Compared with the existing technology that solves the liquid wrapping problem by adding an extra side protective layer, the present invention does not require any new battery structure materials, reduces additional processes such as mask evaporation and atomic layer deposition, and significantly reduces process costs. At the same time, the present invention does not occupy the effective power generation area, the effective power generation area of ​​the bottom battery remains unchanged, and the battery power density is higher.

[0032] (3) This invention has optimized the key parameters of the stepped structure through a large number of experiments: when the height difference is controlled between 1μm and 5μm and the width is controlled between 0.1mm and 2.9mm, the best balance can be achieved between completely blocking the liquid and retaining the effective power generation area to the maximum extent. If it is lower than the lower limit, the blocking effect will be insufficient, and if it is higher than the upper limit, it will cause excessive etching or loss of effective area.

[0033] (5) The present invention further provides a small pyramid textured surface structure in the second region, which on the one hand compensates for the current loss caused by etching and on the other hand improves the uniformity of the perovskite solution; a passivation layer is provided in the first region, which effectively maintains the passivation characteristics of the step region and avoids surface defects introduced by etching.

[0034] (6) The method of the present invention is highly compatible with the existing TOPCon battery production line process. Only mask deposition and selective etching steps need to be inserted into the existing process. There is no need to replace the core equipment, and it has good industrialization prospects. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A process flow diagram for fabricating the bottom cell of a tandem battery provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the structure of the bottom battery in the stacked battery provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the overall structure of the stacked battery provided in an embodiment of the present invention;

[0039] Figure 4 This is a top view of the second surface of the bottom battery in a stacked battery provided in an embodiment of the present invention;

[0040] Figure 5 This is a cross-sectional view of the second surface of the bottom cell in a stacked battery provided in an embodiment of the present invention.

[0041] Explanation of key figure labels:

[0042] 100. Bottom cell; 101. Silicon substrate; 102. First region; 103. Second region; 104. Tunneling oxide layer; 105. Phosphorus doped layer; 106. Passivation layer; 107. Boron doped layer; 108. Second passivation layer; 109. Metal electrode; 200. Top cell; 201. Transparent conductive layer; 202. Hole transport layer; 203. Light-absorbing layer; 204. Electron transport layer; 205. Carrier recombination layer; 206. Top electrode. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other embodiments, well-known materials or methods have not been specifically described in order to avoid obscuring the invention.

[0044] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “an embodiment,” “an example,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0045] Unless otherwise specified, in this invention:

[0046] TOPCon: Tunnel Oxide Passivated Contact;

[0047] ALD: Atomic Layer Deposition;

[0048] PECVD: Plasma Enhanced Chemical Vapor Deposition.

[0049] LPCVD: Low-Pressure Chemical Vapor Deposition;

[0050] TCO: Transparent Conductive Oxides;

[0051] PSG: Phosphosilicate Glass.

[0052] BSG: Boron Silicate Glass;

[0053] The first surface refers to the boron diffusion surface of the crystalline silicon bottom cell;

[0054] The second side refers to the phosphorus diffusion surface of the crystalline silicon bottom cell;

[0055] First region: refers to the annular region on the second surface 0.1mm-2.9mm from the edge of the silicon wafer, including the upper surface and sidewalls of this region;

[0056] Second region: refers to the central region on the second surface that is surrounded by the first region;

[0057] Height difference Y: refers to the vertical distance between the surfaces of the first region and the second region.

[0058] In a first aspect, the present invention provides a stacked battery, comprising: a bottom battery 100, and a top battery 200 disposed on the bottom battery 100; the bottom battery 100 includes a silicon substrate 101 having a first surface and a second surface disposed opposite to each other; the second surface includes a first region 102 and a second region 103, the first region 102 being disposed around the second region 103, and the surface of the first region 102 being higher than the surface of the second region 103, forming a height difference Y; the top battery 200 is disposed within the second region 103.

[0059] In one specific embodiment, the height difference Y is 1μm-5μm; and / or, the width X of the first region 102 is 0.1mm-2.9mm. For example, the height difference Y can be 1μm, 2μm, 3μm, 4μm, 5μm, or any two of the above values; the width X of the first region 102 can be 0.1mm, 0.6mm, 1mm, 1.5mm, 2mm, 2.9mm, or any two of the above values.

[0060] In one specific embodiment, the surface of the second region 103 has a velvety structure with a height of 0.5 μm to 1.2 μm. For example, the height of the velvety structure can be 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.2 μm, or between any two of the above values.

[0061] In one specific embodiment, the top battery 200 includes a transparent conductive layer 201, a hole transport layer 202, a light-absorbing layer 203, an electron transport layer 204, and a carrier recombination layer 205 stacked sequentially; wherein, the upper surface of the light-absorbing layer 203 is not higher than the upper surface of the first region 102, ensuring that the perovskite forming the light-absorbing layer can be easily blocked by the first region 102, and that no plating around it occurs.

[0062] In one specific embodiment, the bottom cell 100 further includes: a tunneling oxide layer 104 located on the second surface of the silicon substrate 101, and a phosphorus doped layer 105 and a passivation layer 106 sequentially stacked on the side of the tunneling oxide layer 104 away from the silicon substrate 101; a boron doped layer 107 located on the first surface of the silicon substrate 101, and a second passivation layer 108 and a metal electrode 109 located on the side of the boron doped layer 107 away from the silicon substrate 101.

[0063] In one specific embodiment, the thickness of the tunneling oxide layer 104 is 1nm-5nm; for example, the thickness of the tunneling oxide layer 104 can be 1nm, 2nm, 3nm, 4nm, 5nm or between any two of the above values.

[0064] In one specific embodiment, the battery structure of the bottom cell 100 includes, but is not limited to, TOPCon cells, HJT cells, PERC cells, POLO and other crystalline silicon cells; the top cell 200 is a perovskite cell.

[0065] In one specific embodiment, the silicon substrate 101 is an N-type monocrystalline silicon wafer with a thickness of 100μm-200μm and a resistivity of 0.5Ω / cm. 2 -10Ω / cm 2 For example, the thickness of the silicon wafer can be 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 180μm, 200μm, or between any two of the above values, and the resistivity can be 0.5Ω / cm. 2 1Ω / cm 2 2Ω / cm 2 5Ω / cm 2 6Ω / cm 2 7Ω / cm 2 8.5Ω / cm 2 9Ω / cm 2 10Ω / cm 2 Or it may be between any two of the above values.

[0066] Secondly, this application provides a method for preparing the above-mentioned stacked battery, comprising the following steps:

[0067] S1. Preparation of bottom cell 100:

[0068] A silicon substrate 101 having a first side and a second side arranged opposite to each other is provided;

[0069] A mask layer is formed on the second surface of the silicon substrate 101. The edge region of the second surface of the silicon substrate 101 covered by the mask layer is defined as the first region 102, and the central region of the exposed second surface of the silicon substrate 101 is defined as the second region 103.

[0070] The second region 103 is etched so that the surface of the second region 103 is lower than the surface of the first region 102, forming a height difference Y;

[0071] S2. Formation of top cell 200: Top cell 200 is formed in the second region 103.

[0072] In one specific embodiment, the design width of the first region 102 is 0.2mm-3mm. For example, the design width of the first region 102 can be 0.2mm, 0.6mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm or between any two of the above values.

[0073] The mask layer includes SiO X Layer, SiN X Layer or Al2O X At least one of the layers, the thickness of which is 10nm-100nm. For example, the thickness of the mask layer can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or between any two of the above values.

[0074] The etching process for the second region 103 is alkaline etching, with an etching solution concentration of 0.5wt%-10wt%. After etching, the thickness difference between the first region 102 and the second region 103 is 1μm-5μm, and the width X of the first region 102 after etching is 0.1mm-2.9mm. For example, the etching solution concentration can be 0.5wt%, 2wt%, 3.5wt%, 5wt%, 6.5wt%, 8wt%, 9wt%, 10wt%, or between any two of the above values, the etching thickness difference can be 1μm, 2μm, 3μm, 4μm, 5μm, or between any two of the above values, and the width X of the first region 102 can be 0.1mm, 0.6mm, 1mm, 1.5mm, 2mm, 2.9mm, or between any two of the above values.

[0075] In one specific embodiment, after etching, the process further includes a second texturing step on the second region 103, using a low-concentration alkaline solution to etch and form a texturing structure with a texturing height of 0.5μm-1.2μm; for example, the texturing height of the texturing structure can be 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.1μm, 1.2μm or between any two of the above values.

[0076] In one specific embodiment, after removing the mask layer, a passivation step is further included: depositing a passivation layer 106 on the surface and sidewalls of the first region 102, the passivation layer 106 comprising SiO X Layers and / or SiN X Layer; in the second region 106, hydrogen passivation is performed using an NH3 atmosphere with an NH3 flow rate of 6000ml~20000ml. For example, the NH3 flow rate can be 6000ml, 8000ml, 10000ml, 12000ml, 14000ml, 16000ml, 18000ml, 20000ml or between any two of the above values.

[0077] In a specific implementation, such as Figure 1 As shown, in step S1, the preparation method of the bottom cell 100 includes the following steps:

[0078] S1-1. Texturing: An N-type silicon substrate 101 with a first side and a second side is provided, and an alkaline solution is used to etch a uniformly sized pyramid structure on both sides of the silicon substrate 101.

[0079] S1-2. Boron diffusion: Boron diffusion is performed on silicon substrate 101 to form a boron-doped layer 107;

[0080] S1-3. BSG Removal: Remove the boron-doped layer and borosilicate glass layer from the second and side surfaces of the silicon substrate 101;

[0081] S1-4. Deposit mask on the surface of the first region 102: Deposit mask layer on the second side of silicon substrate 101 using PECVD. The edge region covered by the mask layer is defined as the first region 102, and the exposed central region is defined as the second region 103.

[0082] S1-5. Alkali etching: The second surface of the silicon substrate 101 is etched using a high-concentration alkaline solution to create a height difference Y between the first region 102 and the second region 103.

[0083] S1-6. Secondary texturing to prepare the second region small textured surface structure: A low-concentration alkaline solution is used to perform secondary etching on the second region 103 of the second surface of the silicon substrate 101 to form a small pyramid textured surface structure of uniform size.

[0084] S1-7. Deposit tunneling oxide layer 104 and intrinsic polysilicon layer: Using LPCVD technology, tunneling oxide layer 104 and intrinsic polysilicon layer are sequentially deposited on the second surface of silicon substrate 101.

[0085] S1-8. Phosphorus diffusion: Using POCl3 as a diffusion source, a phosphorus-doped layer 105 is formed by doping the intrinsic polycrystalline silicon layer.

[0086] S1-9. Removal of PSG and Removal of Wrap-around Plating on the First Surface: The wrap-around plating on the first surface of the silicon substrate 101 is removed using high-concentration HF, and the polycrystalline silicon on the first surface is etched away using alkaline solution. Subsequently, the silicon substrate 101 is cleaned using a mixture of HF / H2O2 and NH3 / H2O2 and then dried.

[0087] S1-10. Deposit passivation layer 106 and hydrogen passivation treatment: deposit passivation layer 106 on the surface and side of the first region 102 on the first and second sides of silicon substrate 101; and perform hydrogen passivation on the second region 103 on the second side of silicon substrate 101 in NH3 atmosphere.

[0088] S1-11. Printing and sintering: Print metal electrodes 110 on the first surface and sinter them.

[0089] In a specific embodiment, in steps S1-2, BCl3 is used as the diffusion source, and the diffusion temperature is 500℃-900℃. For example, the diffusion temperature can be 500℃, 600℃, 700℃, 800℃, 900℃, or any two of the above values. The diffusion resistance of the boron-doped layer 105 is 200Ω / cm. 2 ~500Ω / cm 2 For example, the diffusion resistance of the boron-doped layer 105 can be 200 Ω / cm. 2 250Ω / cm 2 300Ω / cm 2 350Ω / cm 2 400Ω / cm 2 450Ω / cm 2 500Ω / cm 2 Or it may be between any two of the above values.

[0090] In one specific embodiment, in steps S1-3, the second side of the silicon substrate 101 is coated with a high-concentration HF solution to remove the plating, wherein the concentration of the HF solution is controlled between 5 and 20 wt%. For example, the concentration of the HF solution can be 5 wt%, 10 wt%, 15 wt%, 20 wt%, or between any two of the above values.

[0091] In a specific embodiment, in steps S1-5, the high-concentration alkaline solution is NaOH, KOH, or a combination of the two, and the concentration is controlled between 0.5-10 wt%. For example, the concentration of the alkaline solution can be 0.5 wt%, 2 wt%, 4 wt%, 5 wt%, 6 wt%, 8 wt%, 10 wt%, or between any two of the above values.

[0092] In a specific embodiment, in steps S1-8, POCl3 is used as the diffusion source, the diffusion temperature is 700℃-900℃, and the doping concentration is 1~5E20cm. -3 For example, the diffusion temperature can be 700℃, 750℃, 800℃, 850℃, 900℃, or any two of the above values, and the doping concentration can be 1E20cm⁻¹. -3 2E20cm -3 3E20cm -3 4E20cm -3 5E20cm -3 Or it may be between any two of the above values.

[0093] In a specific embodiment, in steps S1-9, the alkaline solution is one or a mixture of NaOH and KOH, the concentration of the alkaline solution is 0.5wt%-10wt%, and the etching time is 10s-150s. For example, the concentration of the alkaline solution can be 0.5wt%, 2wt%, 4wt%, 5wt%, 6wt%, 8wt%, 10wt%, or between any two of the above values, and the etching time can be 10s, 40s, 70s, 100s, 120s, 150s, or between any two of the above values.

[0094] In one specific embodiment, in steps S1-10, SiO is deposited using PECVD. X Or SiN X One or more of the films form a passivation layer 106; the second region 103 of the second side of the silicon substrate 101 is hydrogen passivated using PECVD.

[0095] In one specific embodiment, step S2, the step of forming the top battery 200 includes:

[0096] S2-1 Preparation of transparent conductive layer 201: Deposit ITO transparent conductive layer 201 in the second region 103 of the second side of silicon wafer 101;

[0097] S2-2. Preparation of hole transport layer 202: A hole transport layer 202 is prepared on the transparent conductive layer 201;

[0098] S2-3. Preparation of light-absorbing layer 203: Preparation of light-absorbing layer 203 on hole transport layer 202;

[0099] S2-4. Fabrication of electron transport layer 204: Electron transport layer 204 is fabricated on light-absorbing layer 203;

[0100] S2-5. Preparation of carrier recombination layer 205: Preparation of carrier recombination layer 205 on electron transport layer 204;

[0101] S2-6: A top electrode 206 is formed on the surface of the carrier recombination layer 205.

[0102] In a specific embodiment, in step S2-1, the transparent conductive layer 201 can be one of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), and cerium-doped indium oxide (ICO), or multiple films stacked together; the thickness of the transparent conductive layer 201 is 10-100 nm, and the sheet resistance is 125 Ω / Sq. For example, the thickness of the transparent conductive layer 201 can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or between any two of the above values; under an atmosphere with a pressure ≤1 Pa and an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3 W / cm². 2 The transparent conductive layer 201 can be formed by magnetron sputtering, vapor deposition, or a combination of both.

[0103] In a specific embodiment, in step S2-2, a dense TiO2 hole transport layer 202 with a thickness of 30nm-100nm is prepared at a high temperature of 400℃-550℃ using an overspray pyrolysis method. For example, the thickness of the hole transport layer 202 can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm or between any two of the above values.

[0104] In a specific embodiment, in steps S2-3, the light-absorbing layer 203 has a band gap width of 1.3 eV-1.8 eV and is made of perovskite material. Exemplarily, the band gap width can be 1.3 eV, 1.4 eV, 1.5 eV, 1.6 eV, 1.7 eV, 1.8 eV, or any two of the above values. The material structure of the light-absorbing layer 203 is ABX3, where A is a mixture of one or more cations selected from methylamine, formamidinium, and Cs; B is Pb or Sn; and X is a mixture of one or three anions selected from Cl, Br, and I. The thickness of the light-absorbing layer 203 is 800 nm-1200 nm. Exemplarily, the thickness can be 800 nm, 900 nm, 1000 nm, 1100 nm, or 1200 nm, or any two of the above values. After the light-absorbing layer 203 is prepared, its position should not be higher than the first region 102 of the bottom cell 100.

[0105] In a specific embodiment, in steps S2-4, the electron transport layer 204 is made of SnO2 and has a thickness of 15nm-40nm; for example, the thickness of the electron transport layer 204 can be 15nm, 20nm, 25nm, 30nm, 35nm, 40nm or between any two of the above values.

[0106] In a specific embodiment, in steps S2-5, the carrier recombination layer 205 is made of ITO (indium tin oxide) and has a thickness of 30-100 nm. For example, the thickness of the carrier recombination layer 205 can be 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or between any two of the above values.

[0107] In a specific embodiment, in steps S2-6, a low-temperature Ag gate electrode is formed on the surface of the carrier composite layer 205 as the top electrode 206 by printing and low-temperature curing.

[0108] Thirdly, this application provides a photovoltaic module, including a battery string, which is formed by connecting multiple stacked cells as described above or stacked cells prepared by the above-described method for preparing stacked cells; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0109] Exemplarily, the tandem solar cells are electrically connected in a single sheet or in multiple segments to form multiple cell strings, which are then electrically connected in series and / or parallel. Specifically, in some embodiments, the multiple cell strings can be electrically connected through conductive links. An encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or other light-transmitting cover plate.

[0110] Fourthly, this application also provides a photovoltaic system, including the photovoltaic module described in the third aspect.

[0111] Specifically, photovoltaic (PV) systems can be applied in PV power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user-installed solar power supplies, solar streetlights, solar-powered cars, and solar-powered buildings. Of course, it's understandable that the application scenarios for PV systems are not limited to these; that is, PV systems can be applied in all areas that require solar energy for power generation. Taking a PV power grid as an example, a PV system can include PV arrays, combiner boxes, and inverters. A PV array can be a combination of multiple PV modules; for example, multiple PV modules can form multiple PV arrays. The PV arrays are connected to combiner boxes, which collect the current generated by the PV arrays. The collected current then flows through an inverter, converting it into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0114] Example 1

[0115] like Figure 2-4 As shown, this embodiment provides a stacked battery, which includes a bottom battery 100 and a top battery 200;

[0116] The bottom cell 100 is a TOPCon cell, including an N-type silicon substrate 101;

[0117] The silicon substrate 101 has a first surface (P surface) and a second surface (N surface) disposed opposite to each other.

[0118] The second surface includes a first region 102 and a second region 103. The surface of the second region 103 has a velvety structure. The first region 102 is an annular region surrounding the edge of the second region 103. The surface of the first region 102 is higher than the surface of the second region 103, forming a height difference Y.

[0119] On the surface of the silicon substrate 101 in the second region 103, a tunneling oxide layer 104 and a phosphorus doped layer 105 are sequentially formed. The tunneling oxide layer 104 covers the entire second surface, and the phosphorus doped layer 105 covers the tunneling oxide layer 104. A passivation layer 106 is covered on the surface and sidewalls of the first region 102 and on the first surface of the silicon substrate 101.

[0120] On the first side of the silicon substrate 101, on the side of the passivation layer 106 away from the silicon substrate 101, a boron doped layer 107 is formed, and a second passivation layer 108 and a metal electrode 109 are sequentially stacked and covered thereon.

[0121] The top cell 200 is located in the second region 103 of the bottom cell 100; the top cell 200 is located on the side away from the silicon substrate 101, and from bottom to top it includes: a transparent conductive layer 201, a hole transport layer 202, a light-absorbing layer 203, an electron transport layer 204, a carrier recombination layer 205 and a top electrode 206; the light-absorbing layer 203 is disposed in the second region 103, and the upper surface of the light-absorbing layer 203 is not higher than the upper surface of the first region 102.

[0122] This embodiment also provides a method for preparing the above-mentioned stacked battery, which includes the following steps:

[0123] (1) such as Figure 1 As shown: Preparation of bottom cell 100

[0124] S1-1. Texturing: Select an N-type single crystal silicon wafer (silicon substrate) 101 with a resistivity of 4Ω·m and a thickness of 150μm. Place the N-type single crystal silicon wafer 101 in a 1.3wt% sodium hydroxide alkaline solution for etching. The etching time is 500s and the etching temperature is 70℃. A 1.1μm pyramid structure is formed on both sides of the silicon wafer 101. After texturing, the silicon wafer 101 is cleaned with deionized water.

[0125] S1-2. Boron Diffusion: Boron diffusion was carried out in a diffusion furnace using BCl3 as the diffusion source. The diffusion temperature was controlled at 900℃, and the diffusion sheet resistance was controlled between 250 Ω / □. A layer with a thickness of 0.7 μm and a doping concentration of 3E18 cm⁻¹ was formed on the surface of silicon wafer 101. -3 The boron-doped layer 107.

[0126] S1-3. BSG Removal: Use a 13wt% HF solution to remove the wrap-around plating on the second side (N side) of silicon wafer 101.

[0127] S1-4. Deposition mask on the surface of the first region 102: SiO2 is deposited on the second surface using PECVD. X The mask layer defines the first region 102 as a ring-shaped region with a width of 1.5 mm from the edge through the mask plate; the thickness of the mask layer is controlled at 70 nm.

[0128] S1-5. Alkali etching: The second region 103 on the second surface is etched using a 10wt% NaOH alkaline solution for 100s. The etching thickness difference (height difference Y) is controlled to be around 3μm. After etching, the width X of the first region 102 from the edge is 1.6mm.

[0129] S1-6. Secondary texturing to prepare the small textured surface structure of the second region: The second region 103 of the second surface is etched twice with a NaOH alkaline solution with a concentration of 0.8wt% to form a small pyramid textured surface structure of uniform size, with the textured surface height controlled at about 1μm;

[0130] S1-7. Deposition of tunneling oxide layer 104 and intrinsic polycrystalline silicon layer: Using LPCVD technology, a 2nm thick tunneling oxide layer (SiO2) 104 is deposited on the second surface, and a 100nm thick intrinsic polycrystalline silicon thin film is deposited on the surface of the tunneling oxide layer 104.

[0131] S1-8. Phosphorus Diffusion: POCl3 was used as the diffusion source, and phosphorus diffusion was carried out in a diffusion furnace. The diffusion temperature was controlled at 850℃, and the doping concentration was controlled at 3E20cm⁻¹. -3 A phosphorus-doped layer 105 with a doping thickness of 15 nm is formed by doping the intrinsic polycrystalline silicon layer.

[0132] S1-9. Removal of PSG and Removal of Wrap-on Plating on the First Surface: The wrap-on plating on the first surface is removed using a 13wt% HF solution; then, the polysilicon on the first surface is removed using an alkaline solution, which is a 5wt% NaOH solution, with an etching time of 70s; after etching, the silicon wafer 101 is cleaned using a mixture of HF / H2O2 and NH3 / H2O2 and then dried.

[0133] S1-10. Deposition of passivation layer and hydrogen passivation treatment: SiN is deposited on the surface and sidewalls of the first region on the first and second sides of the silicon wafer using PECVD. X Passivation layer 106, with a deposition thickness of about 70nm; hydrogen passivation of the second region 103 on the second side of silicon wafer 101 is performed by PECVD in an NH3 atmosphere, with the NH3 flow rate controlled at 10000ml.

[0134] S1-11. Printing and sintering: Metal electrodes 109 are printed on the first side of silicon wafer 101 and sintered to form ohmic contacts.

[0135] (2) Preparation of top cell 200

[0136] S2-1 Fabrication of the transparent conductive layer 201: In the second region 103 of the second side of the silicon wafer 101, an ITO transparent conductive layer 201 is deposited by magnetron sputtering at a sputtering power density of 2 W / cm². 2The argon-oxygen ratio is 1:0.05, the gas pressure is 0.8 Pa, the film thickness is controlled at 20 nm, and the sheet resistance is controlled at around 125 Ω / Sq.

[0137] S2-2. Preparation of hole transport layer 202: A dense TiO2 hole transport layer 202 with a thickness of 30-100 nm was prepared on the transparent conductive layer 201 by spray pyrolysis at a high temperature of 450℃.

[0138] S2-3. Preparation of light-absorbing layer 203: Light-absorbing layer 203 is prepared on hole transport layer 202 using slit coating method; the material of light-absorbing layer 203 is FA. 0.8 MA 0.2 PbI3, with a band gap of approximately 1.55 eV and a coating thickness of 1000 nm; after the light-absorbing layer 203 is prepared, the position of the light-absorbing layer 203 should not be higher than the first region 102 of the bottom cell 100.

[0139] S2-4. Preparation of electron transport layer 204: SnO2 electron transport layer 204 with a thickness of 25 nm was prepared on light-absorbing layer 203 by atomic layer deposition.

[0140] S2-5. Preparation of carrier composite layer 205: An ITO carrier composite layer 205 with a thickness of 50 nm was prepared on electron transport layer 204 by magnetron sputtering.

[0141] S2-6. Post-processing: Low-temperature Ag gate electrode 206 is formed on the surface of ITO carrier composite layer 205 by printing and low-temperature curing.

[0142] Example 2

[0143] like Figure 2-4 As shown, this embodiment provides a stacked battery and its preparation method. The structure of the stacked battery is basically the same as that of Embodiment 1, except that the step structure of the second region 103 is lower and narrower. Specifically, the difference in polishing and etching thickness (height difference Y) of the second region 103 is controlled at about 1 μm; the width X of the first region 102 from the edge after etching is 0.1 mm.

[0144] Its preparation method is basically the same as that in Example 1, except that: S1-4. Deposit mask on the surface of the first region 102: SiO is deposited using PECVD. X The mask layer has a first region 102 with a width of 0.1 mm from the edge; the thickness of the mask layer for the bottom cell 100 is controlled at 70 nm.

[0145] S1-5. Alkali etching: The second surface is etched using a high-concentration alkaline solution. The 10 wt% NaOH solution is used for etching for 100 seconds. The difference in polishing and etching thickness in the second region 103 is controlled to be around 1 μm. After etching, the remaining width of the first region 102 from the edge is 0.2 mm.

[0146] The remaining process steps and parameters are consistent with those in Example 1.

[0147] Example 3

[0148] like Figure 2-4 As shown, this embodiment provides a stacked battery and its fabrication method. The structure of the stacked battery is basically the same as that of Embodiment 1, except that the step structure of the second region 103 is higher and wider. Specifically, the difference in polishing and etching thickness (height difference Y) of the second region 103 is controlled at about 5μm; the width X of the first region 102 from the edge after etching is 2.9mm.

[0149] Its preparation method is basically the same as that in Example 1, except that: S1-4. Deposit mask on the surface of the first region 102: SiO is deposited using PECVD. X The mask layer has a first region 102 with a width of 2.9 mm from the edge; the thickness of the mask layer for the bottom cell 100 is controlled at 70 nm.

[0150] S1-5. Alkali etching: The second surface is etched using a high-concentration alkaline solution. The 10 wt% NaOH solution is used for etching for 100 seconds. The difference in polishing and etching thickness in the second region 103 is controlled to be around 5 μm. After etching, the remaining width of the first region 102 from the edge is 3 mm.

[0151] The remaining process steps and parameters are consistent with those in Example 1.

[0152] Example 4

[0153] This embodiment provides a tandem solar cell and its fabrication method, which differs from Embodiment 1 in that the step height difference is too low (0.5 μm). Specifically, in step S1-5, the alkaline etching time is adjusted to 50 s, and the etching thickness difference (height difference Y) is controlled to 0.5 μm. The remaining process steps and parameters are consistent with those of Embodiment 1.

[0154] Example 5

[0155] This embodiment provides a tandem battery and its fabrication method, which differs from Embodiment 1 in that the step height difference is too high (10 μm). Specifically, in step S1-5, the alkaline etching time is adjusted to 300 s, and the etching thickness difference (height difference Y) is controlled to 10 μm. The remaining process steps and parameters are consistent with those in Embodiment 1.

[0156] Example 6

[0157] This embodiment provides a tandem battery and its preparation method, which differs from Embodiment 1 in that the step width is too narrow (50μm).

[0158] Specifically: Step S1-4: Deposit a mask in the first region with a designed width of 30μm and a mask layer thickness of 70nm; Step S1-5: Alkali etching, etch with 10wt% NaOH for 100s, and after etching, the width X of the first region from the edge is 50μm.

[0159] The remaining process steps and parameters are consistent with those in Example 1.

[0160] Example 7

[0161] This embodiment provides a stacked battery and its preparation method, which differs from Embodiment 1 in that the step width is too wide (5mm).

[0162] Specifically: Step S1-4: Deposit a mask in the first region with a designed width of 5.1 mm and a mask layer thickness of 70 nm; Step S1-5: Alkali etching, etch with 10 wt% NaOH for 100 s, and after etching, the width X of the first region from the edge is 5 mm.

[0163] The remaining process steps and parameters are consistent with those in Example 1.

[0164] Comparative Example 1

[0165] This comparative example provides a stacked battery and its preparation method. The difference between this and Example 1 is that the height difference step structure of the present invention is not used, but a side protection layer scheme of the prior art is used instead.

[0166] Specifically, the process involves: providing a bottom cell; after the bottom cell is fabricated, preparing a closed-frame SiO2 side protective layer on the edge of the top surface of the bottom cell using a mask evaporation method, with a width of 0.5 mm and a height of 1.0 μm; and fabricating a perovskite top cell within the closed-frame structure of the side protective layer.

[0167] The remaining process steps and parameters are consistent with those in Example 1.

[0168] Comparative Example 2

[0169] This comparative example provides a stacked battery and its preparation method, which differs from Example 1 in that no anti-winding liquid structure is provided.

[0170] Specifically, during the fabrication of the bottom cell, steps S1-4, the first region mask deposition, and step S5, alkaline etching, are omitted. After step S1-3, BSG removal, step S6, secondary texturing to prepare the second surface texture, is performed directly: a low-concentration alkaline solution is used for etching to form uniformly sized small pyramid structures on the second surface of the silicon wafer, with the texture height controlled at around 1 μm.

[0171] The remaining process steps and parameters are consistent with those in Example 1.

[0172] Performance testing

[0173] The photoelectric performance of the tandem battery samples prepared in all the above embodiments and comparative examples was tested.

[0174] Test conditions: Standard test conditions (AM 1.5G spectrum, 1000W / m) 2 Irradiance, battery temperature at 25°C);

[0175] Test equipment: Keithley 2400 digital source meter, solar simulator (AAA grade).

[0176] Test parameters: Open circuit voltage (Uoc, V), short circuit current (Isc, mA), fill factor (FF, %), photoelectric conversion efficiency (Eta, %), reverse leakage current (IRev@-1.5V, A);

[0177] The sample size for each test group was 20 pieces, and the average value was taken. The test results are shown in Table 1:

[0178] Table 1. Photovoltaic performance test results of the tandem cells in the examples and comparative examples.

[0179] Examples / Comparative Examples Eta (%) Uoc(V) Isc(A) FF (%) IRev(A) Example 1 30.51 1.753 25.86 78.91 0.0438 Example 2 28.52 1.739 24.69 77.71 0.1156 Example 3 27.38 1.718 23.96 76.36 0.0968 Example 4 24.07 1.718 23.69 69.35 0.4136 Example 5 23.99 1.754 19.13 76.76 0.3642 Example 6 25.65 1.726 23.95 72.75 0.3703 Example 7 24.17 1.712 21.57 76.27 0.2492 Comparative Example 1 23.86 1.713 20.72 72.11 0.1056 Comparative Example 2 22.06 1.728 20.19 72.89 0.7926

[0180] Performance test data conclusions analysis:

[0181] As shown in the test data in the table above, the tandem solar cells prepared using the technical solution of this invention in Examples 1-7 have a photoelectric conversion efficiency (Eta) ≥ 30.5%, which is significantly higher than all comparative examples. Among them, Example 1 (step height difference 3 μm, width 1.6 mm) achieved the best overall performance: an efficiency as high as 30.51% and a leakage current as low as 0.0438 A. This result shows that this invention effectively solves the problem of perovskite solution entanglement by constructing a high and low step structure on the same bottom cell surface, without adding an additional protective layer or sacrificing the effective power generation area, thus achieving a significant improvement in cell performance.

[0182] Comparing Examples 1, 2, and 3, it is evident that Example 1 exhibits significantly superior performance compared to Examples 2 and 3. This result demonstrates that when the height difference is controlled at approximately 3 μm and the step width at approximately 1.6 mm (Example 1), an optimal balance can be achieved between "sufficiently blocking the surrounding liquid" and "maximizing the retention of effective area," resulting in the best overall battery performance. These optimized parameters were not arbitrarily selected but rather represent the results of experimental screening.

[0183] Compared with Example 1, Examples 4 and 5 show that the protective layer step structure in the second region is either too low or too high. In Example 4, the step structure is too low (height difference 0.5 μm), resulting in insufficient physical damming effect and inability to effectively block the flow of the perovskite solution, leading to plating still occurring and higher leakage current than in Example 1. In Example 5, the step structure is too high (height difference 10 μm), resulting in excessive silicon removal by alkaline etching, significant thinning of the silicon wafer in the first region, decreased optical absorption, and severe current loss. It is evident that both excessively high and excessively low protective layer structures in the second region affect the subsequent perovskite solar cells, reducing the conversion efficiency of the perovskite-silicon tandem solar cells.

[0184] Compared with Example 1, Examples 6 and 7 have protective layer step structures in the second region that are either too narrow or too wide. In Example 6, the step structure is too narrow, resulting in insufficient blocking area and inability to completely cover the flow path of the perovskite solution. The liquid swirling is not completely blocked, leading to higher leakage current than in Example 1. In Example 7, the step structure is too wide, significantly reducing the effective coating area of ​​the second region and causing a decrease in the light-receiving area of ​​the perovskite top cell. At the same time, the excessive width of the first region also increases the lateral transport distance of charge carriers, resulting in a decrease in the turn-on voltage, current, and filling capacity of the perovskite-silicon tandem cell, causing recombination losses.

[0185] Comparative Example 1 employs a prior art side protection layer scheme, achieving an efficiency of 23.86% and a leakage current of 0.1056A. Compared to Example 1, Comparative Example 1 exhibits a 6.65 percentage point lower efficiency (absolute difference) and approximately 2.4 times higher leakage current. This comparison fully demonstrates that the "surface morphology reconstruction" technical approach of this invention possesses non-obvious advantages over the prior art's "adding a side protection layer" approach. This invention achieves superior anti-winding fluid performance and higher photoelectric conversion efficiency without adding additional film layers or increasing process complexity.

[0186] Comparative Example 2, without any anti-wrap liquid structure, exhibited a leakage current as high as 0.7926A, 18 times that of Example 1; its efficiency was only 22.06%, 8.45 percentage points lower than Example 1. This comparative example directly demonstrates that the problem of perovskite solution wrapping does indeed exist and is severely detrimental to battery performance. The technical solution of this invention can reduce the leakage current to an extremely low level below 0.05A, fully demonstrating its technical effectiveness.

[0187] In summary, this invention successfully solves the short-circuit problem caused by perovskite solution winding by constructing a stepped structure with a specific height difference and width on the surface of the crystalline silicon bottom cell, without adding extra materials or sacrificing the effective power generation area. This significantly improves the photoelectric conversion efficiency and yield of the tandem cell and has good prospects for industrial application.

[0188] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A stacked battery, characterized in that, Includes a bottom battery and a top battery disposed on the bottom battery; The bottom cell includes a silicon substrate having a first side and a second side disposed opposite to each other; The second surface includes a first region and a second region, the first region is disposed around the second region, and the surface of the first region is higher than the surface of the second region, forming a height difference Y; The top battery is disposed in the second region.

2. The stacked battery according to claim 1, characterized in that, The height difference Y is 1μm-5μm; and / or the width X of the first region is 0.1mm-2.9mm.

3. The stacked battery according to claim 1 or 2, characterized in that, The surface of the second region has a velvety structure with a height of 0.5μm-1.2μm.

4. The stacked battery according to claim 1, characterized in that, The top battery comprises a transparent conductive layer, a hole transport layer, a light-absorbing layer, an electron transport layer, and a carrier recombination layer stacked sequentially. The upper surface of the light-absorbing layer is not higher than the upper surface of the first region.

5. A method for preparing a tandem battery as described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1. Preparation of the bottom cell: A silicon substrate having a first side and a second side arranged opposite to each other is provided; A mask layer is formed on the second surface of the silicon substrate, wherein the edge region of the second surface of the silicon substrate covered by the mask layer is defined as a first region, and the central region of the exposed second surface of the silicon substrate is defined as a second region; The second region is etched so that the surface of the second region is lower than the surface of the first region, forming a height difference Y; S2. Formation of the top cell: A top cell is formed in the second region.

6. The method for preparing a stacked battery according to claim 5, characterized in that, The mask layer is SiO₂ X Layer, SiN X Layer or Al2O X At least one of the layers has a thickness of 10nm-100nm, and the designed width of the first region is 0.2mm-3mm; the etching process for the second region is alkaline etching, and the concentration of the etching solution is 0.5wt%-10wt%, so that the height difference Y between the first region and the second region is 1μm-5μm after etching, and the width X of the first region after etching is 0.1mm-2.9mm.

7. The method for preparing a stacked battery according to claim 5, characterized in that, The etching process also includes: The second region is subjected to a secondary texturing step, in which a low-concentration alkaline solution is used to etch and form a texturing structure with a texturing height of 0.5μm-1.2μm.

8. The method for preparing a stacked battery according to claim 5, characterized in that, The process after removing the mask layer also includes a passivation step: A passivation layer is deposited on the surface and sidewalls of the first region, the passivation layer comprising SiO2. X Layers and / or SiN X layer; The second region is subjected to hydrogen passivation in an NH3 atmosphere with a flow rate of 6000 ml to 20000 ml.

9. A photovoltaic module, characterized in that, The battery string is formed by connecting multiple stacked batteries as described in any one of claims 1-4 or by the method of preparing stacked batteries as described in any one of claims 5-8; and an encapsulation layer for covering the surface of the battery string. A cover plate for covering the surface of the encapsulation layer away from the battery string.

10. A photovoltaic system, characterized in that, The photovoltaic system includes the photovoltaic module as described in claim 9.

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