Resistive random access memory and methods of making the same

Abstract

The application relates to the technical field of resistive random access memory, and particularly relates to a resistive random access memory and a preparation method thereof, the preparation method comprising the following steps: providing an insulating substrate, the insulating substrate being provided with a plurality of through holes which are arranged in an array and penetrate through the insulating substrate, the through holes having nanoscale apertures and having oppositely arranged first ends and second ends; alternately depositing transition metals and inert metals in the through holes to form an initial nanowire array in the insulating substrate, and the first layer and the last layer of the initial nanowire array being transition metal layers; oxidizing the initial nanowire array in an oxidizing atmosphere, at least one transition metal layer close to the second end being completely oxidized, the formed oxide overflowing the through hole and covering the opening of the through hole to form a current-limiting layer, and the remaining transition metal layers being incompletely oxidized. In the above preparation method, the current-limiting layer and the storage material are synchronously formed in the oxidation process, the preparation process is simplified, and the preparation efficiency of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of resistive switching memory technology, and specifically to a resistive switching memory and its fabrication method. Background Technology

[0002] Resistive random access memory (RRAM) has attracted widespread attention as a novel type of non-volatile memory. RRAM offers advantages such as small cell size, fast read / write speed, low programming voltage, low power consumption, compatibility with CMOS fabrication processes, and simple device structure. RRAM relies on the electroresistive switching effect of resistive materials. This effect refers to the reversible change in resistance between a high-resistivity state (HRS) and a low-resistivity state (LRS) of a solid dielectric material under an applied electric field. The high-resistivity state represents logic "1" and the low-resistivity state represents logic "0" to achieve data storage. Furthermore, its specific resistance state can be maintained for a long time after the power is cut off, exhibiting non-volatility.

[0003] Electro-induced resistive switching is related to the formation and breakage of conductive filaments in resistive switching materials. During the switching process between high and low resistive states, overgrowth of conductive filaments can easily occur due to uncontrolled current, leading to device breakdown and reduced cycle stability. To address this, a current-limiting structure can be incorporated into the resistive switching memory to limit the operating current of the device, suppress overcurrent breakdown, constrain the formation and breakage of conductive filaments, and improve the uniformity, cycle stability, and reliability of the resistive switching.

[0004] However, the process of forming current-limiting structures in resistive random access memory (RRAM) has technical limitations, which affects the fabrication efficiency of the devices. Summary of the Invention

[0005] This invention provides a resistive switching memory and its fabrication method to improve the fabrication efficiency of the device.

[0006] In a first aspect, the present invention provides a method for fabricating a resistive switching memory, the method comprising: An insulating substrate is provided, the insulating substrate having a plurality of through holes arranged in an array and penetrating the insulating substrate, the through holes having a nanometer-scale pore size and having a first end and a second end disposed opposite to each other; Along the direction from the first end to the second end, transition metals and inert metals are alternately deposited in the through-hole to form an initial nanowire array in the insulating substrate, wherein the first and last layers of the initial nanowire array are both transition metal layers; The initial nanowire array is oxidized in an oxidizing atmosphere, at least one of the transition metal layers near the second end is completely oxidized and the resulting oxide overflows from the via and covers the opening of the via to form a flow-limiting layer, while the remaining transition metal layers are incompletely oxidized.

[0007] In some alternative embodiments, the inert metal includes at least one of platinum and gold.

[0008] In some alternative embodiments, the transition metal includes at least one of nickel and cobalt.

[0009] In some optional embodiments, during the oxidation of the initial nanowire array in an oxidizing atmosphere, the oxidation temperature is 400 °C to 800 °C; and / or the oxidation time is 5 h to 20 h; and / or the volume fraction of oxygen in the oxidizing atmosphere is 5% to 30%.

[0010] In some alternative embodiments, an electrochemical deposition process is used to alternately deposit transition metals and inert metals within the via, wherein the electrolyte contains transition metal sources and inert metal sources, and the deposition potential alternates between the deposition potential of the transition metal and the deposition potential of the inert metal during the deposition process.

[0011] In some alternative embodiments, the thickness of the single-layer transition metal layer is 5 nm to 100 nm.

[0012] In some alternative implementations, the thickness of the single-layer inert metal layer is 10 nm to 20 nm.

[0013] In some alternative embodiments, the number of inert metal layers is 50 to 200.

[0014] In some alternative embodiments, the side surface of the last layer of the initial nanowire array that faces away from the first layer of the initial nanowire array is flush with the second end.

[0015] In some alternative embodiments, in one of the transition metal layers, a portion of the thickness is completely oxidized and overflows the via, while another portion of the thickness is incompletely oxidized and remains within the via.

[0016] In some optional embodiments, the fabrication method further includes: depositing a bottom electrode at the first end before alternately depositing transition metal and inert metal within the via; depositing the first layer of the initial nanowire array on the surface of the bottom electrode; and depositing a top electrode on the side of the current-limiting layer opposite to the insulating substrate after oxidizing the initial nanowire array in an oxidizing atmosphere.

[0017] In a second aspect, the present invention provides a resistive switching memory, the resistive switching memory comprising: An insulating substrate having an array of through holes that penetrate the insulating substrate, the through holes having a nanometer-scale pore size and having a first end and a second end that are disposed opposite to each other; The nanowire array comprises alternating transition metal oxide layers and inert metal layers arranged along a direction from the first end to the second end, wherein the first and last layers are both transition metal oxide layers, at least one of the transition metal oxide layers near the second end is a fully oxidized layer, and the remaining transition metal oxide layers are incompletely oxidized layers. The oxygen content in the incompletely oxidized layers gradually decreases along the direction from the second end to the first end. The incompletely oxidized layers are located within the plurality of through-holes, forming a partial structure of the nanowire array, and the fully oxidized layers are located outside the through-holes and cover the openings of the through-holes, forming at least a partial structure of the current-limiting layer.

[0018] In some optional embodiments, the film layer corresponding to the first layer in the nanowire array is the incomplete oxide layer, and the film layer and the current-limiting layer are an integral structure.

[0019] In some alternative implementations, the thickness of the current-limiting layer is 100 nm to 600 nm.

[0020] In some alternative embodiments, the flow-limiting layers at the multiple through-hole openings are connected to form a continuous film layer.

[0021] The technical solution of the present invention has the following beneficial effects: 1. The method for fabricating a resistive switching memory provided by this invention involves oxidizing the initial nanowire array. During this oxidation process, the inert metal remains in its elemental state, while the transition metal undergoes oxidation and volume expansion. This causes the oxide of at least one transition metal layer near the second end to overflow from the via, forming a current-limiting layer at the opening of the via. Because the at least one transition metal layer near the second end has more sufficient contact with the oxidizing atmosphere, the aforementioned film layer undergoes complete oxidation. However, the oxidizing atmosphere enters the via relatively late, and the formation of the current-limiting layer also affects the further entry of the oxidizing atmosphere into the via. Therefore, the remaining transition metal layers undergo incomplete oxidation to form the storage material, and the degree of oxidation gradually decreases along the direction from the second end to the first end. Thus, in the above fabrication method, the current-limiting layer and the storage material are formed simultaneously during the oxidation process, eliminating the need to separately fabricate the current-limiting layer after obtaining the storage material. This simplifies the fabrication process and improves the device fabrication efficiency.

[0022] 2. The method for fabricating a resistive switching memory provided by the present invention includes at least one of nickel and cobalt as the transition metal. Along the direction from the second end to the first end, the degree of oxidation of the incompletely oxidized transition metal layer gradually decreases, resulting in the presence of a transition metal element in at least one transition metal oxide layer near the first end. Both nickel and cobalt are magnetic materials. When an external electric field is applied, the magnetic material can act as a precursor for the conductive wire, facilitating the migration of oxygen ions to form the conductive wire. This reduces the operating voltage of the resistive switching memory, and eliminates the need for an electrical excitation process before resistive switching testing, effectively reducing energy consumption.

[0023] Furthermore, at least one transition metal oxide layer near the first end contains a transition metal element. In this case, the transition metal oxide in the transition metal oxide layer exhibits a resistive switching effect, enabling electrical write-to-nonvolatile storage. It serves as the storage material and, together with the inert metal, constitutes the resistive switching memory cell. The transition metal element in the transition metal oxide layer and the inert metal together constitute the magnetosensitive unit, which can utilize its magnetoresistance effect to achieve magnetic field modulation reading. Therefore, the above preparation method enables the current-limiting layer, the resistive switching memory cell, and the magnetosensitive unit to be formed simultaneously during the oxidation process, thereby obtaining a resistive switching memory that combines resistive switching effect, magnetoresistance effect, and current-limiting capability. This resistive switching memory supports dual-mode control of electric and magnetic fields, possesses multi-dimensional manipulation capabilities, and integrates storage, sensing, and potential logic functions, providing a highly integrated hardware platform for information processing systems such as in-memory computing and sensor-memory computing fusion.

[0024] 3. The method for fabricating resistive switching memory provided by the present invention, after oxidizing the initial nanowire array, in one of the transition metal layers, a portion of the thickness is completely oxidized and overflows from the via to form part of the current-limiting layer structure, while another portion of the thickness is incompletely oxidized and located within the via to form the storage material. Therefore, the current-limiting layer and the storage material are interconnected as a whole, which not only has a high connection strength and improves the structural stability of the device, but also avoids the interface defects and performance fluctuations introduced by the additional fabrication of the current-limiting layer, providing a solid structural foundation for high-density integration.

[0025] 4. In the resistive switching memory provided by the present invention, the film layer corresponding to the first layer in the nanowire array is the incomplete oxide layer, and the film layer and the current limiting layer are integrally structured, which makes the connection strength between the current limiting layer and the nanowire array greater and can improve the structural stability of the device. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the fabrication process of a resistive switching memory according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of forming a bottom electrode at the first end of an insulating substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the initial nanowire array formed in the insulating substrate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the initial nanowire array after oxidation according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the top electrode formed on the surface of the current-limiting layer according to an embodiment of the present invention; Figure 6 This is a scanning electron microscope image of the current-limiting layer in Embodiment 1 of the present invention; Figure 7 This is a cross-sectional scanning electron microscope image of the structure of the initial nanowire array after oxidation, as shown in Example 1 of the present invention. Figure 8 This is a line scan elemental distribution map of the cross-sectional structure of the initial nanowire array after oxidation, as shown in Example 1 of the present invention. Figure 9 The X-ray diffraction patterns of the initial nanowire array before and after oxidation are shown in Example 1 of this invention. Figure 10 This is a logarithmic current-voltage curve of the resistive switching memory of Embodiment 1 of the present invention under different cycle numbers; Figure 11 The magnetoresistance diagrams of the resistive switching memory of Embodiment 1 of the present invention are shown in the low-resistance and high-resistance states, parallel to the nanowire extension direction. Figure 12 This is a magnetoresistive diagram of the resistive switching memory of Embodiment 1 of the present invention in a low-resistivity state, in both the direction parallel to and perpendicular to the nanowire extension direction. Figure 13 This is a magnetoresistive diagram of the resistive switching memory of Embodiment 1 of the present invention in a high-resistivity state, in both the direction parallel to and perpendicular to the nanowire extension direction. Figure 14 This is a logarithmic current-voltage curve of the resistive switching memory in Embodiment 2 of the present invention under different cycle numbers; Figure 15 This is a magnetoresistive diagram of the resistive switching memory of Embodiment 2 of the present invention in a low-resistivity state, in both the direction parallel to and perpendicular to the nanowire extension direction. Figure 16 This is a magnetoresistive diagram of the resistive switching memory of Embodiment 2 of the present invention in a high-resistivity state, in both directions parallel and perpendicular to the nanowire extension direction.

[0028] Explanation of reference numerals in the attached figures: 1-Insulating substrate; 11-Through hole; 2-Initial nanowire; 21-Transition metal layer; 22-Inert metal layer; 3-Nanowire; 31-Transition metal oxide layer; 4-Current limiting layer; 5-Bottom electrode; 6-Top electrode. Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] As described in the background section, related technologies require additional fabrication steps for current-limiting structures during device fabrication to form current-limiting structures in resistive switching memory, which complicates the device fabrication process and reduces device fabrication efficiency.

[0032] Firstly, reference Figure 1 This invention provides a method for fabricating a resistive switching memory, the method comprising: Step S1, Reference Figure 2 An insulating substrate 1 is provided, the insulating substrate 1 having a plurality of through holes 11 arranged in an array and penetrating the insulating substrate 1, the through holes 11 having a nanometer-scale pore size and having a first end and a second end disposed opposite to each other; Step S2, Reference Figure 3 Along the direction from the first end to the second end, transition metals and inert metals are alternately deposited in the vias 11 to obtain initial nanowires 2, thereby forming an initial nanowire array in the insulating substrate 1. The first and last layers of the initial nanowire array are both transition metal layers 21, and inert metal layers 22 are located between two adjacent transition metal layers 21. The initial nanowire array is composed of transition metals and inert metals located in multiple vias 11, and the transition metals and inert metals in each via 11 constitute the initial nanowire 2. Step S3, Reference Figure 4 The initial nanowire array is oxidized in an oxidizing atmosphere. At least one of the transition metal layers 21 near the second end is completely oxidized and the resulting oxide overflows from the through hole 11 and covers the opening of the through hole 11 to form a flow-limiting layer 4. The remaining transition metal layers 21 are incompletely oxidized.

[0033] During the oxidation of the initial nanowire array, the inert metal remains in its elemental state, while the transition metal undergoes oxidation and volume expansion. This causes the oxide of at least one transition metal layer 21 near the second end to overflow from the via 11, forming a current-limiting layer 4 at the opening of the via 11. Because the at least one transition metal layer 21 near the second end has more sufficient contact with the oxidizing atmosphere, the aforementioned film layer undergoes complete oxidation. However, the oxidizing atmosphere enters the via 11 relatively late, and the formation of the current-limiting layer 4 also affects the further entry of the oxidizing atmosphere into the via 11. Therefore, the remaining transition metal layers 21 undergo incomplete oxidation to form the storage material, and the degree of oxidation gradually decreases along the direction from the second end to the first end. Thus, in the above preparation method, the current-limiting layer 4 and the storage material are formed simultaneously during the oxidation process, eliminating the need to separately prepare the current-limiting layer 4 after the storage material is obtained, simplifying the preparation process and improving the device preparation efficiency. Furthermore, the formation region of the conductive wire in the resistive switching memory is controlled within the nanowire 3, which reduces the randomness of conductive wire formation and improves the stability of the electro-resistive switching. The nanowire array structure can also increase the storage density.

[0034] Specifically, the entire thickness of the single-layer transition metal layer 21 can be completely oxidized to form part of the current-limiting layer 4, or a portion of the thickness of the single-layer transition metal layer 21 can be completely oxidized, while another portion is incompletely oxidized. For example, refer to... Figure 4 After the initial nanowire array is oxidized, a portion of the thickness of one of the transition metal layers 21 is completely oxidized and overflows from the via 11 to form part of the current limiting layer 4, while another portion is incompletely oxidized and located within the via 11 to form storage material. Therefore, the current limiting layer 4 and the storage material are interconnected as a whole, which not only has a strong connection and improves the structural stability of the device, but also avoids interface defects and performance fluctuations introduced by the additional fabrication of the current limiting layer 4, providing a solid structural foundation for high-density integration.

[0035] Furthermore, when the oxides of the multiple transition metal layers 21 overflow through the via 11, the inert metal layer 22 between the multiple transition metal layers 21 also constitutes part of the current limiting layer 4.

[0036] The following is a complete explanation of the fabrication method of resistive random access memory: Step S1, Reference Figure 2 An insulating substrate 1 is provided, the insulating substrate 1 having a plurality of through holes 11 arranged in an array and penetrating the insulating substrate 1, the through holes 11 having a nanometer-scale pore size and having a first end and a second end disposed opposite to each other.

[0037] Specifically, the insulating substrate 1 can be a double-hole porous anodized aluminum template.

[0038] Further references are available. Figure 2Before alternating deposition of transition metal and inert metal within the via 11, a bottom electrode 5 is deposited at the first end. The material of the bottom electrode 5 includes, but is not limited to, at least one of platinum (Pt) and gold (Au). The bottom electrode 5 can be deposited using a magnetron sputtering process, and its thickness can be 50 nm to 150 nm.

[0039] Step S2, Reference Figure 3 Along the direction from the first end to the second end, transition metals and inert metals are alternately deposited in the through-hole 11 to form an initial nanowire array in the insulating substrate 1, and the first layer and the last layer are both transition metal layers 21.

[0040] Specifically, the first layer of the initial nanowire array is deposited on the surface of the bottom electrode 5.

[0041] Specifically, the inert metal includes, but is not limited to, at least one of platinum (Pt) and gold (Au).

[0042] Specifically, the transition metal includes, but is not limited to, at least one of nickel (Ni) and cobalt (Co). In some embodiments, the transition metal is Ni, and the material of the current-limiting layer 4 is NiO, the material formed by its incomplete oxidation being NiO. x 0≤x<1; In some embodiments, the transition metal is Co, the material of the current-limiting layer 4 is Co2O3, and the material formed by its incomplete oxidation is Co2O y , 0≤y<3.

[0043] NiO and Co2O3, as typical nonlinear threshold switching materials, possess high resistivity characteristics. As a current-limiting layer 4, they can effectively suppress the overgrowth of the conductive wire during resistive switching, reduce the risk of device breakdown due to current runaway, and improve the device's cycle stability.

[0044] Meanwhile, along the direction from the second end to the first end, the degree of oxidation of the incompletely oxidized transition metal layer 21 gradually decreases, so that at least one transition metal oxide layer 31 near the first end contains a transition metal element. Both Ni and Co are magnetic materials. When an external electric field is applied, the magnetic material can act as a precursor for the conductive wire, which helps the migration of oxygen ions to form the conductive wire, thereby reducing the operating voltage of the resistive switching memory. Furthermore, no electrical excitation process is required for activation before resistive switching testing, effectively reducing energy consumption.

[0045] Furthermore, at least one transition metal oxide layer 31 near the first end contains a transition metal element. In this case, the transition metal oxide in the transition metal oxide layer 31 exhibits a resistive switching effect, enabling electrical write-to-nonvolatile storage. It serves as the storage material and, together with the inert metal, constitutes the resistive switching memory cell. The transition metal element in the transition metal oxide layer 31 and the inert metal together constitute the magnetosensitive unit, which can utilize its magnetoresistance effect to achieve magnetic field modulation reading. Therefore, the above preparation method enables the current-limiting layer 4, the resistive switching memory cell, and the magnetosensitive unit to be formed simultaneously during the oxidation process, thereby obtaining a resistive switching memory that combines resistive switching effect, magnetoresistance effect, and current-limiting capability. This resistive switching memory supports dual-mode control of electric and magnetic fields, possesses multi-dimensional manipulation capabilities, and integrates storage, sensing, and potential logic functions, providing a highly integrated hardware platform for information processing systems such as in-memory computing and in-sensor-in-memory computing fusion.

[0046] In some optional embodiments, an electrochemical deposition process is used to alternately deposit transition metals and inert metals within the via 11. Specifically, deposition is performed using a three-electrode system of an electrochemical workstation. An insulating substrate 1 with a bottom electrode 5 is fixed to the surface of a conductive material using conductive adhesive as the working electrode, a platinum (Pt) electrode as the counter electrode, and a saturated calomel electrode as the reference electrode. The three electrodes are immersed in an electrolyte containing both transition metal and inert metal sources. The three electrodes are connected to the electrochemical workstation, and deposition begins. During deposition, the deposition potential alternates between the deposition potential of the transition metal and the deposition potential of the inert metal. For example, when the inert metal is Pt and the transition metal is Ni, the electrolyte contains 0.5 mol / L~1 mol / L NiSO4·6H2O, 1 mmol / L~2 mmol / L H2PtCl4, and 0.3 mol / L~0.5 mol / L H3BO3; the deposition potential of Ni is -1.2 V, the deposition potential of Pt is -0.3 V, and the deposition temperature is 25 ℃.

[0047] Specifically, the thickness of the single-layer transition metal layer 21 can be 5 nm to 100 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc. The thickness of the single-layer inert metal layer 22 can be 10 nm to 20 nm, such as 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, etc.

[0048] The number of inert metal layers 22 can be 50 to 200, such as 50, 75, 100, 125, 150, 175, 200, etc. Since transition metals and inert metals are deposited alternately, and the first and last layers are both transition metal layers 21, the number of transition metal layers 21 is one more than that of inert metal layers 22.

[0049] In some alternative implementations, the side surface of the last layer of the initial nanowire array that faces away from the first layer of the initial nanowire array is flush with the second end, where "flush" means strictly flush or substantially flush.

[0050] Step S3, Reference Figure 4 The initial nanowire array is oxidized in an oxidizing atmosphere. At least one of the transition metal layers 21 near the second end is completely oxidized and the resulting oxide overflows from the through hole 11 and covers the opening of the through hole 11 to form a flow-limiting layer 4. The remaining transition metal layers 21 are incompletely oxidized.

[0051] Specifically, during the oxidation of the initial nanowire array in an oxidizing atmosphere, the heating rate can be 5 ℃ / min to 20 ℃ / min, such as 5 ℃ / min, 10 ℃ / min, 15 ℃ / min, 20 ℃ / min, etc.; the oxidation temperature can be 400 ℃ to 800 ℃, such as 400 ℃, 500 ℃, 600 ℃, 700 ℃, 800 ℃, etc.; the oxidation time can be 5 h to 20 h, such as 5 h, 10 h, 15 h, 20 h, etc.; the oxidizing atmosphere contains oxygen, and the volume fraction of oxygen in the oxidizing atmosphere can be 5%-30%, such as 5%, 10%, 15%, 20%, 25%, 30%, etc. The oxidation process can be carried out in a tube furnace. The proportions of the resistive switching memory unit, the current limiting layer 4, and the magnetic sensitive unit in the resistive switching memory can be controlled by controlling the degree of oxidation.

[0052] For example, when the transition metal layer 21 is made of Ni and has a thickness of 50 nm, the tube furnace is heated to 800 °C at a heating rate of 20 °C / min, and oxidized at 800 °C for 5 h to produce NiO. x The thickness of the first layer is 70 nm, and the thickness of the current-limiting layer 4 is 600 nm.

[0053] Step S4, Reference Figure 5 A top electrode 6 is deposited on the surface of the current limiting layer 4 on the side opposite to the insulating substrate 1.

[0054] The material of the top electrode 6 includes, but is not limited to, at least one of platinum (Pt) and gold (Au). The top electrode 6 can be deposited using a magnetron sputtering process, and the thickness of the top electrode 6 can be 50 nm to 150 nm.

[0055] Secondly, refer to Figure 5 The present invention provides a resistive random access memory (RRAM), the RRAM comprising: An insulating substrate 1 has a plurality of through holes 11 arranged in an array and penetrating the insulating substrate 1. The through holes 11 have a nanometer-scale pore size and have a first end and a second end arranged opposite to each other. A transition metal oxide layer 31 and an inert metal layer 22 are alternately arranged along a direction from the first end to the second end, wherein the first and last layers are both transition metal oxide layers 31, and the inert metal layers 22 are located between two adjacent transition metal oxide layers 31. At least one transition metal oxide layer 31 near the second end is a fully oxidized layer, and the remaining transition metal oxide layers 31 are incompletely oxidized layers. Along the direction from the second end to the first end, the oxygen content in the incompletely oxidized layers gradually decreases. The incompletely oxidized layers are located within the plurality of through holes 11, forming part of the structure of the nanowire array, while the fully oxidized layers are located outside the through holes 11 and cover the openings of the through holes 11, forming at least part of the structure of the current-limiting layer 4. The nanowire array is composed of transition metal oxide layers 31 and inert metal layers 22 located within the plurality of through holes 11, and the transition metal oxide layers 31 and inert metal layers 22 within each through hole 11 form nanowires 3.

[0056] It should be noted that the features (such as materials, thickness, etc.) and effects described in the fabrication method of the resistive switching memory in the first aspect also apply to this resistive switching memory, and will not be repeated here.

[0057] Specifically, the thickness of the current-limiting layer 4 can be 100 nm to 600 nm, such as 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, etc.

[0058] In some alternative implementations, refer to Figure 5 The film layer corresponding to the first layer in the nanowire array is the incomplete oxide layer. The film layer and the current limiting layer 4 are an integral structure, which makes the connection strength between the current limiting layer 4 and the nanowire array greater and can improve the structural stability of the device.

[0059] In some alternative implementations, refer to Figure 6 The flow-limiting layers 4 at the openings of the multiple through holes 11 are connected to form a continuous membrane layer, which has a better flow-limiting effect.

[0060] The following provides the specific fabrication method and related tests for resistive random access memory.

[0061] Example 1 This embodiment provides a method for fabricating a resistive random access memory (RAD), including: A double-through porous anodized aluminum template is provided as an insulating substrate 1, which has a plurality of through holes 11 arranged in an array, wherein the through holes 11 have a first end and a second end disposed opposite to each other; A 50 nm thick Pt layer was deposited as the bottom electrode 5 in the through hole 11 located at the first end using a magnetron sputtering process. An electrolyte was prepared containing 1 mol / L NiSO4·6H2O, 2 mmol / L H2PtCl4, and 0.5 mol / L H3BO3. An insulating substrate 1 with a bottom electrode 5 was fixed to the surface of a conductive material using silver conductive adhesive as the working electrode, a Pt electrode as the counter electrode, and a saturated calomel electrode as the reference electrode. The three electrodes were immersed in the electrolyte and connected to an electrochemical workstation. Deposition was performed at a deposition temperature of 25 °C. During deposition, the deposition potential alternated between -1.2 V (Ni deposition potential) and -0.3 V (Pt deposition potential) to alternately deposit Ni layers (as transition metal layer 21) and Pt layers (as inert metal layer 22) within the through-hole 11 to obtain an initial nanowire array. Both the first and last layers were Ni layers. The thickness of a single Pt layer was 20 nm, the thickness of a single Ni layer was 50 nm, and there were 200 Pt layers. The upper surface of the last layer was flush with the second end. The insulating substrate 1 was placed in a tube furnace, and oxygen was introduced into the tube furnace to make the oxygen content in the tube furnace 20%. The temperature in the tube furnace was raised to 600 ℃ at a heating rate of 10 ℃ / min, and oxidized at 600 ℃ for 10 h to obtain a current-limiting layer 4 with a thickness of 300 nm on the surface of the insulating substrate 1. A 50 nm thick Pt layer was deposited on the surface of the current-limiting layer 4 using magnetron sputtering as the top electrode 6 to obtain a resistive switching memory.

[0062] Example 2 This embodiment provides a method for fabricating a resistive switching memory, which differs from Embodiment 1 only in the oxidation process. Specifically, the tube furnace is heated to 400 °C at a heating rate of 5 °C / min, and oxidized at 400 °C for 20 h. The thickness of the current limiting layer 4 is 200 nm.

[0063] The following test methods were used to test the performance of the resistive switching memory prepared in Examples 1-2.

[0064] 1. After oxidizing the initial nanowire array, the cross-sectional morphology of the formed structure and the surface morphology of the current-limiting layer 4 were obtained by scanning electron microscopy, and line scanning analysis was performed by EDS energy dispersive spectroscopy.

[0065] Figure 6 This is a scanning electron microscope image of the current-limiting layer 4 in Example 1. Figure 7 This is a cross-sectional scanning electron microscope image of the structure of the initial nanowire array after oxidation in Example 1. Figure 7The diagram shows a bottom electrode 5 (Pt), a current-limiting layer 4 (NiO), and a nanowire array located between the bottom electrode 5 (Pt) and the current-limiting layer 4 (NiO). The nanowire array consists of nanowires 3 arranged in an array within the through-holes 11 of the double-porous anodic alumina template. The nanowires 3 are composed of alternating NiO nanowires. x It consists of layers of Pt and Pt. Figure 6 and Figure 7 As can be seen, in Example 1, after oxidizing the initial nanowire array, a continuous and dense current-limiting layer 4 was obtained.

[0066] Figure 8 This is a line scan elemental distribution map of the cross-sectional structure of the initial nanowire array after oxidation, as shown in Example 1. The horizontal axis represents the line scan position, and the vertical axis represents the signal intensity of the characteristic X-rays of the corresponding element. Figure 8 The signal intensities of characteristic X-rays for Ni, O, and Al are shown along a one-dimensional scan path from the bottom (0 µm) to the top (approximately 12 µm) of the sample. Figure 8 It can be seen that from the bottom near the bottom electrode 5 to the top near the top electrode 6, the content of Ni and O elements in the current limiting layer 4 increases significantly, that is, the current limiting layer 4 contains nickel oxide and almost no Al element.

[0067] 2. X-ray diffraction was used to scan the initial nanowire array before and after oxidation.

[0068] Figure 9 The images show the X-ray diffraction patterns of the initial nanowire array before and after oxidation in Example 1, where the horizontal axis represents the diffraction angle and the vertical axis represents the diffraction intensity. Figure 9 It can be seen that after the initial nanowire array is oxidized, in addition to Al2O3 (from insulating substrate 1), Pt, and NiO, a small amount of Ni also exists in the device structure.

[0069] 3. Electro-resistivity performance testing of the resistive switching memory was performed using a semiconductor parameter analyzer and a probe station: the probes were contacted with the top electrode 6 and the bottom electrode 5 of the device, respectively, with the bottom electrode 5 grounded, and a voltage was applied to the top electrode 6; the device was subjected to a cyclic set-reset operation to achieve repeated switching between high and low resistance states; DC IV scanning was performed at the set number of cycle nodes, with the voltage scanned in the order of 0 → forward set voltage → 0 → reverse reset voltage → 0, and the original voltage-current data were recorded synchronously; the original current was logarithmically scaled and plotted against the voltage as a log (I)-V curve, where the horizontal axis represents the voltage applied across the device and the vertical axis represents the response current generated by the device under the corresponding voltage.

[0070] Figure 10This is a logarithmic current-voltage curve of the resistive switching memory in Example 1 at different cycle numbers: 1, 5, 10, and 15. Figure 10 It can be seen that the set voltage V of this device SET The reset voltage is 1.4 ± 0.2 V. RESET The voltage is -1.8 ± 0.14 V, and the switching ratio is approximately 1 × 10⁻⁶. 4 Furthermore, no electrical excitation process is required to activate the device before resistive switching testing.

[0071] Figure 14 This is a logarithmic current-voltage curve of the resistive switching memory in Example 2 at different cycle numbers: 1, 5, and 10. Figure 14 It can be seen that the set voltage V of this device SET The reset voltage is 0.9 ± 0.2 V. RESET The voltage is 0.88 ± 0.2 V, and the switching ratio is approximately 1 × 10⁻⁶. 2 Furthermore, no electrical excitation process is required to activate the device before resistive switching testing.

[0072] 4. Perform magnetoresistive tests on the resistive random access memory (RRAM) under low and high resistance states.

[0073] Figure 11 This is a magnetoresistive plot of the resistive switching memory of Example 1 in the low-resistivity (LRS) and high-resistivity (HRS) states, parallel to the extension direction (OP) of nanowire 3. The horizontal axis represents the applied magnetic field strength, and the vertical axis represents the device resistance. Figure 11 It can be seen that the resistive random access memory (RRAM) has a significant magnetoresistive effect in the low-resistivity state, but no significant magnetoresistive effect in the high-resistivity state. Therefore, the magnetoresistive effect of the RRAM changes before and after the electro-resistive switching.

[0074] Figure 12 and Figure 15 The magnetoresistive diagrams of the resistive switching memory in Examples 1 and 2 are shown in the low-resistivity state (LRS) in the direction parallel to the extension direction of nanowire 3 (OP) and perpendicular to the extension direction of nanowire 3 (IP), respectively. The horizontal axis represents the applied magnetic field strength, and the vertical axis represents the resistance value of the device. Figure 13 and Figure 16 The figures show the magnetoresistive plots of the resistive switching memory in Examples 1 and 2, respectively, in the high-resistivity (HRS) state, parallel to the extension direction (OP) and perpendicular to the extension direction (IP) of nanowire 3. The horizontal axis represents the applied magnetic field strength, and the vertical axis represents the device resistance. Figures 12-13 , Figures 15-16 It can be seen that, regardless of whether it is in the high-resistivity state or the low-resistivity state, the magnetoresistance perpendicular to the extension direction of nanowire 3 is significantly different in both magnitude and direction from the magnetoresistance parallel to the direction of nanowire 3. This indicates that the magnetoresistance effect of the resistive switching memory has obvious directional anisotropy.

[0075] The above results show that the resistive switching memory provided in Examples 1 and 2 not only has self-limiting electro-resistive switching performance, but also electro-magnetic resistance effect, and has storage, sensing and potential logic operation functions.

[0076] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items. In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0077] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a resistive random access memory (RAD), characterized in that, The preparation method includes: An insulating substrate is provided, the insulating substrate having a plurality of through holes arranged in an array and penetrating the insulating substrate, the through holes having a nanometer-scale pore size and having a first end and a second end disposed opposite to each other; Along the direction from the first end to the second end, transition metals and inert metals are alternately deposited in the through-hole to form an initial nanowire array in the insulating substrate, wherein the first and last layers of the initial nanowire array are both transition metal layers, and the transition metal includes at least one of nickel and cobalt. The initial nanowire array is oxidized in an oxidizing atmosphere, at least one of the transition metal layers near the second end is completely oxidized and the resulting oxide overflows from the via and covers the opening of the via to form a flow-limiting layer, while the remaining transition metal layers are incompletely oxidized.

2. The method for fabricating a resistive random access memory according to claim 1, characterized in that, The inert metal includes at least one of platinum and gold.

3. The method for fabricating a resistive switching memory according to claim 2, characterized in that, During the oxidation of the initial nanowire array in an oxidizing atmosphere, the oxidation temperature is 400 ℃~800 ℃; and / or, the oxidation time is 5 h~20 h; and / or, the volume fraction of oxygen in the oxidizing atmosphere is 5%-30%.

4. The method for fabricating a resistive random access memory according to claim 1, characterized in that, An electrochemical deposition process is used to alternately deposit transition metals and inert metals in the through-hole. The electrolyte contains transition metal sources and inert metal sources. During the deposition process, the deposition potential alternates between the deposition potential of the transition metal and the deposition potential of the inert metal.

5. The method for fabricating a resistive random access memory according to any one of claims 1 to 4, characterized in that, The thickness of the single-layer transition metal layer is 5 nm to 100 nm; And / or, the thickness of the single inert metal layer is 10 nm to 20 nm; And / or, the number of inert metal layers is 50 to 200.

6. The method for fabricating a resistive random access memory according to any one of claims 1 to 4, characterized in that, The surface of the last layer of the initial nanowire array that faces away from the first layer of the initial nanowire array is flush with the second end. And / or, in one of the transition metal layers, a portion of the thickness is completely oxidized and overflows the via, while another portion of the thickness is incompletely oxidized and remains within the via.

7. The method for fabricating a resistive random access memory according to any one of claims 1 to 4, characterized in that, The preparation method further includes: A bottom electrode is deposited at the first end before alternating deposition of transition metal and inert metal within the via; the first layer of the initial nanowire array is deposited on the surface of the bottom electrode. After oxidizing the initial nanowire array in an oxidizing atmosphere, a top electrode is deposited on the surface of the current-limiting layer on the side opposite to the insulating substrate.

8. A resistive random access memory, characterized in that, The resistive switching memory includes: An insulating substrate having an array of through holes that penetrate the insulating substrate, the through holes having a nanometer-scale pore size and having a first end and a second end that are disposed opposite to each other; The nanowire array comprises alternating transition metal oxide layers and inert metal layers arranged along a direction from the first end to the second end, wherein the first and last layers are both transition metal oxide layers, at least one of the transition metal oxide layers near the second end is a fully oxidized layer, and the remaining transition metal oxide layers are incompletely oxidized layers. Along the direction from the second end to the first end, the oxygen content in the incompletely oxidized layers gradually decreases. The transition metal element in the transition metal oxide layers includes at least one of nickel and cobalt. The incompletely oxidized layers are located within the plurality of through-holes, forming a partial structure of the nanowire array, and the fully oxidized layers are located outside the through-holes and cover the openings of the through-holes, forming at least a partial structure of the current-limiting layer.

9. The resistive random access memory according to claim 8, characterized in that, The film layer corresponding to the first layer in the nanowire array is the incomplete oxide layer, and the film layer and the current-limiting layer are an integral structure. And / or, the thickness of the current-limiting layer is 100 nm to 600 nm.

10. The resistive random access memory according to claim 8, characterized in that, The flow-limiting layers at the openings of the multiple through holes are connected to form a continuous film layer.

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