Semiconductor structure and method of manufacturing the same, chip
By forming trenches in the dielectric layer and setting contact plugs, the problems of high difficulty in fabricating three-dimensional MIM structures and void defects were solved, thereby improving capacitor performance and production efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN CHUXING TECH CO LTD
- Filing Date
- 2024-12-16
- Publication Date
- 2026-06-16
AI Technical Summary
The existing fabrication process for three-dimensional MIM structures is difficult, resulting in void defects in capacitors, reduced performance, and low production efficiency.
By forming trenches in the dielectric layer and placing a first contact plug in the trench to contact the second electrode of the capacitor structure, the aspect ratio of the capacitor structure is reduced. The preparation process is optimized by chemical mechanical polishing, which avoids void defects and improves deposition uniformity.
This improved the performance of the capacitor structure, reduced the difficulty of the fabrication process, increased production efficiency, reduced the number of photolithography steps, and lowered the fabrication cost.
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Figure CN122227870A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a chip. Background Technology
[0002] Passive components such as capacitors, resistors, and inductors are required in integrated circuit design. Capacitors typically employ either a metal-insulator-metal (MIM) structure or a metal-oxide-metal (MOM) structure. MIM structures are widely used because they offer higher capacitance density.
[0003] With the development of semiconductor chip technology, the demand for higher capacitance density is gradually increasing. One method to achieve higher capacitance density is to fold planar MIM structures into three-dimensional MIM structures. However, the fabrication process of three-dimensional MIM structures is more difficult, leading to void defects in the capacitors and reducing their performance. Furthermore, the fabrication process of three-dimensional MIM structures is more challenging and has lower production efficiency. Summary of the Invention
[0004] This disclosure provides a semiconductor structure, its fabrication method, and a chip to improve capacitor performance and production efficiency.
[0005] In a first aspect, a semiconductor structure is provided, including a substrate, a dielectric layer, a capacitor structure, an insulating layer, and at least one first contact plug. The dielectric layer is disposed on the substrate and has trenches extending through it. The capacitor structure includes a first electrode, a dielectric layer, and a second electrode, with the first electrode, the dielectric layer, and the second electrode sequentially covering the inner wall of the trench. The insulating layer at least covers the surface of the second electrode away from the substrate. The first contact plug penetrates the insulating layer located within the trench and contacts the second electrode, thereby increasing the width of the capacitor structure, i.e., reducing the aspect ratio of the capacitor structure. This allows for more uniform deposition of the capacitor structure during fabrication, avoiding void defects and improving device performance. Furthermore, a smaller aspect ratio helps reduce the difficulty of the thin-film deposition process for the capacitor structure, thereby improving production efficiency.
[0006] In some embodiments, the surface of the dielectric layer away from the substrate is a first surface, and the surface of the capacitor structure away from the substrate is located on the first surface.
[0007] In some embodiments, a plurality of the first contact plugs are spaced apart within the trench and contact the second electrode plate of the same capacitor structure.
[0008] In some embodiments, the shape of the orthographic projection of the capacitor structure onto the substrate includes any one of a rectangle, a circle, and an ellipse.
[0009] In some embodiments, the semiconductor structure further includes a connection layer and a second contact plug. The connection layer is embedded within the substrate and contacts the first electrode. The second contact plug penetrates the insulating layer and the dielectric layer and contacts the connection layer.
[0010] In some embodiments, the semiconductor structure further includes a barrier layer disposed between the dielectric layer and the substrate, and at least covering the interconnect layer, wherein the trench extends through the barrier layer.
[0011] In a second aspect, a chip is provided, the chip comprising: the semiconductor structure provided in the first aspect.
[0012] The aforementioned chip has the same structure and beneficial technical effects as the semiconductor structure provided in the first aspect, and will not be described in detail here.
[0013] Thirdly, a method for fabricating a semiconductor structure is provided, for fabricating the semiconductor structure as provided in the first direction. The method includes: providing a substrate; forming a dielectric layer on the substrate; forming a trench on the dielectric layer, the trench penetrating the dielectric layer; forming a capacitor structure and an insulating layer, the capacitor structure including a first electrode, a dielectric layer, and a second electrode, the first electrode, the dielectric layer, and the second electrode sequentially covering the inner wall of the trench, the insulating layer at least covering the surface of the second electrode away from the substrate; and forming at least one first contact plug within the trench, the first contact plug penetrating the insulating layer located within the trench and contacting the second electrode.
[0014] In some embodiments, forming the capacitor structure and insulating layer includes: sequentially depositing a first electrode film, a dielectric layer film, and a second electrode film on the inner wall of the trench, wherein the second electrode film surrounds a first sub-groove within the trench; forming a first insulating film that fills the first sub-groove and covers the second electrode film; simultaneously removing the first electrode film, dielectric layer film, second electrode film, and first insulating film located above the surface of the dielectric layer, leaving the remaining first insulating film within the first sub-groove to form a second insulating portion; forming a first insulating portion that covers the dielectric layer, the capacitor structure, and the second insulating portion, wherein the first insulating portion and the second insulating portion together form the insulating layer.
[0015] In some embodiments, between providing the substrate and forming the dielectric layer on the substrate, the fabrication method further includes forming a connection layer and a barrier layer within the substrate, the connection layer contacting the first electrode plate. The barrier layer is disposed between the dielectric layer and the substrate and at least covers the connection layer. And / or, during the formation of at least one first contact plug within the trench, a second contact plug is simultaneously formed, the second contact plug penetrating the insulating layer and the dielectric layer and contacting the connection layer.
[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.
[0018] Figure 1 A block diagram of a chip according to some embodiments;
[0019] Figure 2 This is a cross-sectional view of a semiconductor structure according to some embodiments;
[0020] Figure 3 This is a cross-sectional view of yet another semiconductor structure according to some embodiments;
[0021] Figure 4 This is a top view of a semiconductor structure according to some embodiments;
[0022] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;
[0023] Figure 6 This is a flowchart of another method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation
[0024] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0025] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0026] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0027] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.
[0028] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0029] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0030] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.
[0031] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0032] like Figure 1 As shown, some embodiments of this disclosure provide a chip 1000 that can be applied to and packaged into different types of electronic products. Examples include mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and other electronic devices.
[0033] The chip 1000 may include at least one of a processor 200, a memory 300, and a controller 400. Furthermore, the chip 1000 may also include a cache, etc., but this disclosure does not specifically limit its inclusion in these embodiments.
[0034] It should be noted that processor 200 is used to interpret computer instructions from electronic devices and process data in computer software. This processor 200 may be, for example, a Central Processing Unit (CPU). Memory 300 is used to store the code of computer programs and provide space for exchanging data between running programs. Controller 400 is used to manage the data stored in memory 300 and to communicate with external devices (e.g., a host computer).
[0035] In some embodiments, see Figure 2 and Figure 3 The chip 1000 includes a semiconductor structure 100. The semiconductor structure 100 includes a substrate 10, a dielectric layer 20, a capacitor structure 30, an insulating layer 40, and at least one first contact plug 50. The dielectric layer 20 is disposed on the substrate 10 and has a trench 21 extending through it. The capacitor structure 30 includes a first electrode 31, a dielectric layer 33, and a second electrode 32, which sequentially cover the inner wall of the trench 21. The insulating layer 40 at least covers the surface of the second electrode 32 away from the substrate 10, and the first contact plug 50 contacts the second electrode 32.
[0036] See in some examples Figure 2 and Figure 3 The first electrode 31, the dielectric layer 33, and the second electrode 32 sequentially cover the inner wall of the trench 21, and the first electrode 31, the dielectric layer 33, and the second electrode 32 have the same shape.
[0037] It should be noted that the material of the substrate 10 includes at least one of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), and gallium arsenide (GaAs).
[0038] In related technologies, during the fabrication of the first electrode, dielectric layer, and second electrode in a capacitor structure, the large depth-to-width ratio (i.e., a large depth and a small width) can lead to uneven material deposition, resulting in voids and defects within the capacitor structure and consequently reducing device performance. Furthermore, the complex fabrication process of the capacitor structure results in low production efficiency.
[0039] Based on this, such as Figure 2 and Figure 3As shown, in some embodiments of the semiconductor structure 100 provided in this disclosure, the first contact plug 50 penetrates the insulating layer 40 located in the trench 21 and contacts the second electrode 32, thereby increasing the width of the capacitor structure 30, i.e., reducing the aspect ratio of the capacitor structure 30. This allows the capacitor structure 30 to be deposited more uniformly during fabrication, avoiding void defects and thus improving device performance. Furthermore, a smaller aspect ratio helps reduce the difficulty of the thin film deposition process of the capacitor structure 30, thereby improving production efficiency.
[0040] In some embodiments, such as Figure 2 As shown, the surface of the dielectric layer 20 away from the substrate 10 is the first surface 22, and the surface of the capacitor structure 30 away from the substrate 10 is located on the first surface 22. It should be noted that this structure can be fabricated using a chemical mechanical planarization (CMP) process; details can be found in the preparation method described below, and will not be repeated here.
[0041] In this case, by using chemical mechanical polishing (CMP) during the fabrication of capacitor structure 30, one photolithography (PH) step can be eliminated, thus reducing the fabrication cost.
[0042] In some embodiments, such as Figure 4 As shown, multiple first contact plugs 50 are spaced apart within the trench 21 and connected to the second electrode plate 32 of the same capacitor structure 30. This allows the same capacitor structure 30 to be connected to different circuits via multiple first contact plugs 50, increasing the flexibility of circuit design. Furthermore, connecting the same capacitor structure 30 to different circuits reduces the number of capacitor structures used, thereby lowering production costs. Additionally, the multiple first contact plugs 50 and the first electrode plate 31 can form multiple capacitor structures, effectively adding multiple capacitor structures to the original capacitor structure 30, increasing the total capacitance, thereby improving capacitance density and device performance.
[0043] It should be noted that capacitance density refers to the capacitance per unit volume or unit area. Capacitance density is an important indicator for measuring the charge storage capacity of the capacitor structure 30, and it can intuitively reflect the efficiency of the capacitor structure 30 in storing charge within a limited space.
[0044] In some examples, such as Figure 4As shown, the plurality of first contact plugs 50 include first sub-plugs 51 and second sub-plugs 52, which are spaced apart and connected to the second electrode plate 32 of the same capacitor structure 30. In this case, the first sub-plugs 51 and second sub-plugs 52 can be connected to two circuits, increasing the flexibility of circuit design. Furthermore, it reduces the number of capacitor structures 30 used, lowering production costs.
[0045] In some embodiments, such as Figure 4 As shown, the shape of the orthographic projection of the capacitor structure 30 onto the substrate 10 includes any one of rectangle, circle, and ellipse. The rectangular structure facilitates regular and compact arrangement on the substrate 10, increasing the area ratio of the capacitor structure 30 on the substrate 10. This, in turn, increases the contact area between the first contact plug 50 and the second electrode 32, reduces the contact resistance between the first contact plug 50 and the second electrode 32, and improves the device's quality factor (Q-factor). Circular and elliptical structures offer better thin film deposition effects and are easier to fabricate.
[0046] It should be noted that the orthographic projection of the capacitor structure 30 onto the substrate 10 can also be other shapes. This disclosure does not impose specific limitations on the embodiments, as long as the design concept is the same.
[0047] In some embodiments, such as Figure 2 and Figure 3 As shown, the semiconductor structure 100 also includes a connection layer 60 and a second contact plug 70. The connection layer 60 is embedded in the substrate 10 and contacts the first electrode 31. The second contact plug 70 penetrates the insulating layer 40 and the dielectric layer 20 and contacts the connection layer 60. In this case, the second contact plug 70 is connected to the first electrode 31 of the capacitor structure 30 through the connection layer 60, without needing to be connected to the sidewall of the first electrode 31 in the dielectric layer 20, thereby reducing the manufacturing complexity.
[0048] It should be noted that when the second contact plug 70 is connected to the side wall of the first electrode plate 31, the contact may be insufficient due to the difficulty of the manufacturing process, which may increase the contact resistance between the second contact plug 70 and the first electrode plate 31, or excessive contact may affect the structure of the first electrode plate 31, thereby affecting the performance of the device.
[0049] In some examples, such as Figure 2 and Figure 3 As shown, the surface of the interconnect layer 60 near the capacitor structure 30 and the surface of the substrate 10 near the capacitor structure 30 are located on the same plane. The material of the interconnect layer 60 includes metals; for example, the material of the interconnect layer 60 includes at least one of copper (Cu), tungsten (W), and titanium nitride (TiN).
[0050] In some embodiments, such as Figure 2 and Figure 3 As shown, the semiconductor structure 100 further includes a barrier layer 80, which is disposed between the dielectric layer 20 and the substrate 10 and at least covers the interconnect layer 60. The trench 21 also penetrates the barrier layer 80. The barrier layer 80 is used to prevent the metal of the interconnect layer 60 from diffusing into the dielectric layer 20, thereby avoiding leakage.
[0051] It should be noted that the material of the aforementioned barrier layer 80 includes silicon nitride (SiN) and / or silicon carbonitride (SiCN).
[0052] In some embodiments, the dielectric layer 33 is made of hafnium oxide and / or zirconium oxide. The first electrode 31 and the second electrode 32 are made of at least one of titanium nitride (TiN), tantalum nitride (TaN), and tantalum (Ta). Exemplarily, the dielectric layer 33 is made of hafnium dioxide (HfO2) and / or zirconium dioxide (ZrO2).
[0053] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, such as... Figure 5 As shown, the preparation method includes steps S100 to S500.
[0054] S100: Provides substrate 10.
[0055] In the above steps, the substrate 10 is made of at least one of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), and gallium arsenide (GaAs).
[0056] S200: A dielectric layer 20 is formed on the substrate 10.
[0057] In the above steps, a dielectric layer 20 is formed on the substrate 10 by a thin film deposition process.
[0058] It should be noted that thin film deposition processes include any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).
[0059] S300: A trench 21 is formed on the dielectric layer 20, and the trench 21 penetrates the dielectric layer 20.
[0060] In the above steps, the side of the dielectric layer 20 away from the substrate 10 is etched to form a trench 21.
[0061] S400: A capacitor structure 30 and an insulating layer 40 are formed. The capacitor structure 30 includes a first electrode 31, a dielectric layer 33, and a second electrode 32. The first electrode 31, the dielectric layer 33, and the second electrode 32 sequentially cover the inner wall of the trench 21. The insulating layer 40 at least covers the surface of the second electrode 32 away from the substrate 10.
[0062] In the above steps, a capacitor structure 30 and an insulating layer 40 are formed on the dielectric layer 20 with trench 21 by a thin film deposition process.
[0063] S500: At least one first contact plug 50 is formed in the trench 21. The first contact plug 50 penetrates the insulating layer 40 located in the trench 21 and contacts the second electrode plate 32.
[0064] In the above steps, the insulating layer 40 located in the trench 21 is etched to form at least one second sub-groove; and a first contact plug 50 is formed in the second sub-groove by a thin film deposition process.
[0065] In some embodiments, such as Figure 6 As shown, in S400, the above preparation method includes S410 to S440.
[0066] S410: A first electrode film, a dielectric layer film, and a second electrode film are sequentially deposited on the inner wall of the trench 21, and the second electrode film surrounds the trench 21 to form a first sub-groove.
[0067] In the above steps, a first electrode film, a dielectric layer film, and a second electrode film are sequentially formed on the inner wall of the trench using a thin film deposition process.
[0068] S420: Form a first insulating film, which fills the first sub-groove and covers the second electrode film.
[0069] In the above steps, a first insulating film is formed in the first sub-tank through a thin film deposition process.
[0070] S430: Simultaneously remove the first electrode film, dielectric layer film, second electrode film and first insulating film located above the surface of dielectric layer 20, and the remaining first insulating film located in the first sub-groove forms the second insulating part.
[0071] S430 may specifically include: simultaneously removing the first electrode film, dielectric layer film, second electrode film, and second insulating film located above the dielectric layer 20 through a chemical mechanical polishing process to form a first electrode 31, a dielectric layer 33, a second electrode 32, and a second insulating portion.
[0072] S440: A first insulating portion is formed, which covers the dielectric layer 20, the capacitor structure 30, and the second insulating portion. The first insulating portion and the second insulating portion together form an insulating layer 40.
[0073] In the above steps, a first insulating portion is formed on the side of the dielectric layer 20 and the capacitor structure 30 away from the substrate 10 by a thin film deposition process, and the first insulating portion and the second insulating portion together form the insulating layer 40.
[0074] In some embodiments, between S100 and S200, the above preparation method further includes S110.
[0075] S110: A connection layer 60 and a barrier layer 80 are formed within the substrate 10. The connection layer 60 is in contact with the first electrode plate 31, and the barrier layer 80 is disposed between the dielectric layer 20 and the substrate 10, and at least covers the connection layer 60.
[0076] In the above steps, a third sub-groove is formed on the substrate 10 using a photolithography process. A connecting layer 60 is formed within the third sub-groove using a thin film deposition process. A barrier layer 80 is formed above the substrate 10 and the connecting layer 60 using a thin film deposition process.
[0077] In some embodiments, during process S500, the above preparation method further includes the simultaneous formation of a second contact plug 70, the second contact plug 70 penetrating the insulating layer 40 and the dielectric layer 20, and contacting the connecting layer 60.
[0078] In the above steps, a fourth sub-groove is formed on the insulating layer 40 and the dielectric layer 20 using a photolithography process. A second contact plug 70 is then formed within the fourth sub-groove using a thin-film deposition process.
[0079] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0080] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A dielectric layer is disposed on the substrate; The dielectric layer is provided with grooves that penetrate the dielectric layer; A capacitor structure includes a first electrode plate, a dielectric layer, and a second electrode plate, wherein the first electrode plate, the dielectric layer, and the second electrode plate sequentially cover the inner wall of the trench; An insulating layer, at least covering the surface of the second electrode plate away from the substrate; At least one first contact plug penetrates the insulating layer located within the trench and contacts the second electrode plate.
2. The semiconductor structure according to claim 1, characterized in that, The surface of the dielectric layer away from the substrate is a first surface, and the surface of the capacitor structure away from the substrate is located on the first surface.
3. The semiconductor structure according to claim 1, characterized in that, Multiple first contact plugs are spaced apart within the trench and contact the second electrode plate of the same capacitor structure.
4. The semiconductor structure according to claim 1, characterized in that, The shape of the orthographic projection of the capacitor structure onto the substrate includes any one of a rectangle, a circle, and an ellipse.
5. The semiconductor structure according to claim 1, characterized in that, Also includes: A connecting layer is embedded in the substrate and is in contact with the first electrode plate; The second contact plug penetrates the insulating layer and the dielectric layer and is in contact with the connecting layer.
6. The semiconductor structure according to claim 5, characterized in that, Also includes: A barrier layer is disposed between the dielectric layer and the substrate, and at least covers the interconnect layer; The trench also penetrates the barrier layer.
7. A chip, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 6.
8. A method for fabricating a semiconductor structure, characterized in that, For preparing the semiconductor structure as described in any one of claims 1 to 6, comprising: Provide substrate; A dielectric layer is formed on the substrate; A trench is formed on the dielectric layer, the trench penetrating the dielectric layer; A capacitor structure and an insulating layer are formed. The capacitor structure includes a first electrode, a dielectric layer, and a second electrode, wherein the first electrode, the dielectric layer, and the second electrode sequentially cover the inner wall of the trench; the insulating layer at least covers the surface of the second electrode away from the substrate. At least one first contact plug is formed in the trench, the first contact plug penetrating the insulating layer located in the trench and contacting the second electrode plate.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The formation of the capacitor structure and insulating layer includes: A first electrode film, a dielectric layer film, and a second electrode film are sequentially deposited on the inner wall of the trench, and the second electrode film is arranged in the trench to form a first sub-groove. A first insulating film is formed, which fills the first sub-groove and covers the second electrode film. Simultaneously remove the first electrode film, dielectric layer film, second electrode film, and first insulating film located above the surface of the dielectric layer; the remaining first insulating film located in the first sub-groove forms the second insulating portion. A first insulating portion is formed, which covers the dielectric layer, the capacitor structure, and the second insulating portion. The first insulating portion and the second insulating portion together form the insulating layer.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Between providing the substrate and forming the dielectric layer on the substrate, the fabrication method further includes forming a connection layer and a barrier layer within the substrate, the connection layer being in contact with the first electrode plate; the barrier layer being disposed between the dielectric layer and the substrate, and at least covering the connection layer; And / or, during the process of forming at least one first contact plug in the trench, a second contact plug is simultaneously formed, the second contact plug penetrating the insulating layer and the dielectric layer and contacting the connecting layer.