Chip package 3D heterogeneous integration package structure and method

Abstract

The application discloses a kind of 3D heterogeneous integration package structure and method of chip package, including substrate layer pretreatment, microfluid cooling channel production, through hole and micro bump preparation, and the standardized preparation of operation, HBM memory, photoelectric conversion die, 6 layers and above die stacking are realized by Cu-Cu hybrid bonding, then vertical photonic via array is prepared and photoelectric alignment and overall package are completed;Structure is composed of substrate layer, heterogeneous die stacking layer, vertical photonic via array and copper-tungsten alloy package cover layer, total package layer is provided with microfluid cooling network that is connected to the whole world, and node temperature≤85 ℃ is realized by DTM dynamic temperature control algorithm;Vertical photonic via array realizes low-loss optical interconnection, interlayer is filled with high thermal conductivity TIM material, and high reliability is ensured by combining Cu-Cu hybrid bonding.Optical, electrical and thermal three-dimensional heterogeneous integration is realized, and the electrical interconnection, optical interconnection and thermal management performance are excellent, and the number of stacked layers and transmission bandwidth break through the limitation of traditional technology.

Description

Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging and optoelectronic integration technology, and relates to a 3D heterogeneous integrated packaging structure and method for high-performance chip packaging with embedded microfluidic cooling paths and vertical photonic vias. Background Technology

[0002] As Moore's Law slows its pace of development, the semiconductor industry is turning to 3D heterogeneous integration technology to improve system performance, which involves vertically stacking dies with different functions and process nodes. However, this technology faces two major challenges: thermal management and high-speed interconnects.

[0003] In terms of thermal management, traditional top or bottom heat dissipation methods experience an exponential increase in thermal resistance when the number of die stacks exceeds three layers. Each additional die layer increases the thermal resistance by 15%-30%, easily causing the core area temperature to exceed 100°C (the safe operating threshold for semiconductor devices is typically 85-95°C), leading to timing errors, decreased reliability, and even permanent damage. Although external microfluidic cooling solutions have been proposed, their cooling efficiency is limited, and they occupy additional space, making it difficult to meet the heat dissipation requirements of high-power stacks with eight or more layers.

[0004] In terms of electrical signal transmission, traditional copper-based through-silicon vias (TSVs) are limited by RC delay, crosstalk, and electromagnetic interference, with a single-channel bandwidth of only about 100Gb / s. Attenuation is severe over long distances (1-2dB attenuation per centimeter in 100Gbps PAM4 mode), making it difficult to exceed 100Gbps in frequency and thus unable to meet the demands of next-generation TB-level or even Tbps-level data throughput. Although there is research on vertical optical interconnect technology, existing solutions often suffer from high optical coupling loss, material thermal expansion coefficient mismatch, and poor compatibility with standard CMOS processes, and have not yet been able to seamlessly integrate with 3D packaging processes.

[0005] Current mainstream solutions in the industry, such as Intel Foveros and TSMC CoWoS platforms, mostly adopt strategies that limit the number of stacked layers and interconnect distances to circumvent the aforementioned bottlenecks. Although TSMC's Coupe platform has achieved early mass production of vertical photonic vias, it has extremely stringent temperature control requirements (temperature rise control <2°C) and lacks an efficient active cooling solution, making it difficult to support the long-term full-speed operation of high-performance chips. Therefore, the industry urgently needs an innovative packaging structure that can simultaneously overcome the two major challenges of heat dissipation and high-speed transmission, while also being highly compatible with existing processes. Summary of the Invention

[0006] The purpose of this invention is to provide a 3D heterogeneous integrated packaging structure and method for chip packaging, which solves the thermal management bottleneck and electrical signal transmission delay problems caused by high-density chip stacks by integrating embedded microfluidic cooling paths with vertical photonic via arrays.

[0007] The objective of this invention is achieved through the following technical solution: 1. A 3D heterogeneous integration packaging method for chip packaging, comprising the following steps: S1. Substrate layer pretreatment: Using a silicon wafer as the substrate, a Ti / Cu layer is deposited on the surface of the silicon wafer using the SPT stress proximity technique, and then an electrical signal RDL line with a linewidth / spacing of less than 1μm is prepared on the Ti / Cu layer; the DRIE deep reactive ion etching process is used to etch interconnected cooling inlets and outlets and main cooling channels inside the silicon wafer. S2. Fabrication of Microfluidic Cooling Channels: Using a temporary substrate as the support, a first BCB dielectric layer of the same size as the silicon wafer is spin-coated. After depositing a SiO2 insulating layer using PECVD, microfluidic cavities and vertical cooling channels are formed by simultaneous etching using photolithography and RIE processes. A copper thin film is sputtered on the inner wall of the cooling channel, and then the first BCB dielectric layer is sealed and fixed to the pre-treated silicon wafer using AuSi adhesive, so that the main cooling channel and the microfluidic cavity are precisely aligned. S3. Preparation of Through-Silicon Vias and Microbumps: The assembly obtained in step 2 is etched using the DRIE process to form the first through-silicon via. The etching path avoids the microfluidic cooling channel. Copper is electroplated to fill the first through-silicon via to form a void-free first copper pillar. After polishing, the first copper microbumps electrically connected to the first copper pillars are electroplated on the end face of the assembly. Finally, a SiO2 insulating layer is deposited using the PECVD process to achieve electrical isolation, thus completing the preparation of the substrate layer. S4. Fabrication of computing die: Select a logic wafer with the same size as the silicon wafer and the second BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the surface metal layer and circuit pretreatment of the substrate, microfluidic cooling channel fabrication, through-silicon via, second copper pillar and second microbump fabrication to obtain the computing die. S5. Preparation of HBM memory die: Select an HBM wafer with the same size as the silicon wafer and the third BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the pretreatment of the metal layer and circuit on the substrate surface, the preparation of microfluidic cooling channels, through-silicon vias, the preparation of the third copper pillar and the third microbump, and obtain the HBM memory die. S6. Photoelectric conversion bare die preparation: Select a photoelectric wafer with the same size as the silicon wafer and the fourth BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the surface metal layer and circuit pretreatment of the substrate, microfluidic cooling channel preparation, silicon via, fourth copper pillar and fourth microbump preparation to obtain the photoelectric conversion bare die. S7, 3D die hybrid bonding stacking: Using Cu-Cu hybrid bonding process, the photoelectric conversion die is precisely aligned and bonded to the substrate layer, and then 4 HBM memory dies and computing dies are stacked in sequence to achieve 6 or more layers of die stacking; after bonding, electrical testing is performed, and after passing the test, high thermal conductivity TIM material is filled between each die layer and the substrate layer, and then airtightness testing is performed. S8. Fabrication of Vertical Photonic Via Array: The stacked product is etched through the DRIE process to form a vertical photonic via array, with the etching path avoiding microfluidic cooling channels and interconnect structures; SiO2 insulating layer is deposited on the inner wall of the via using PECVD process, and Si3N4 waveguide material is filled using LPCVD process. S9. Optoelectronic Alignment and Overall Packaging: The VCSEL / PD is precisely aligned with the vertical photonic via array, with an alignment error of ≤±0.5μm. The VCSEL / PD is fixed with low-temperature eutectic AuSn curing adhesive, and a copper-tungsten alloy encapsulation cap is installed. High thermal conductivity TIM material is filled between the encapsulation cap and the top die, and encapsulation is performed to form the overall encapsulation layer. A microfluidic cooling network connected to the microfluidic cooling channel is reserved in the overall encapsulation layer. After encapsulation, the entire assembly is mounted on the PCB substrate.

[0008] As a further improvement of the present invention, in step 2, the temporary substrate can be a glass substrate or a quartz substrate; the first BCB dielectric layer can be replaced with PI or PSPI high-temperature resistant dielectric material; the SiO2 insulating layer can be replaced with a SiN insulating layer; the copper film can be replaced with an aluminum film or a silver film; the annealing temperature can be adjusted within the range of 180-220°C and the annealing time can be adjusted within the range of 25-35 minutes; and the AuSi adhesive can be replaced with an AuSn adhesive.

[0009] As a further improvement of the present invention, in step 4, the logic chip can be replaced with an arithmetic chip of the same size; the height of the second BCB dielectric layer can be adjusted in the range of 80-120μm; and the height of the logic chip can be adapted in the range of 180-220μm.

[0010] As a further improvement of the present invention, in step 5, the HBM wafer can be replaced with a memory wafer of the same size and function; the height of the third BCB dielectric layer can be adjusted in the range of 80-120μm; and the height of the HBM wafer can be adapted in the range of 180-220μm.

[0011] As a further improvement of the present invention, in step 6, the optoelectronic chip can be replaced with an optoelectronic conversion chip of the same size and function; the height of the fourth BCB dielectric layer can be adjusted in the range of 80-120μm; and the height of the optoelectronic chip can be adapted in the range of 180-220μm.

[0012] As a further improvement of the present invention, the optical waveguide material of the vertical photon through-hole array in step 8 can adopt a polymer material filling scheme, specifically: modified epoxy resin, PI or BCB is selected as the waveguide material, and it is filled by vacuum-assisted spin coating or capillary impregnation at 3000-6000 rpm. After low-temperature pre-baking and high-temperature curing treatment at 180-350℃, the end face of the through hole is polished by chemical mechanical polishing.

[0013] As a further improvement of the present invention, the optical waveguide material of the vertical photonic via array in step 8 can adopt a silicon-based silicon nitride filling scheme, specifically: Si3N4 is deposited by LPCVD at 400-600℃ or PECVD at 200-300℃, and after annealing at 500℃ to improve the material density, the via size is finely adjusted by CMP polishing + reactive ion etching.

[0014] A 3D heterogeneous integrated packaging structure for chip packaging is prepared by the above method. It consists of a substrate layer, a heterogeneous die stack layer, a vertical photonic via array, and a copper-tungsten alloy packaging cap layer. The substrate layer, heterogeneous die stack layer, and vertical photonic via array below the packaging cap layer are encapsulated to form the total packaging layer. The heterogeneous die stack is formed by vertically stacking computing dies, HBM memory dies, and photoelectric conversion dies through Cu-Cu hybrid bonding, using a high / low power die staggered arrangement. High thermal conductivity TIM material is placed between the die layers; the Cu-Cu hybrid bonding has an accuracy of <±0.5μm, a bonding strength of >50MPa, an interlayer resistance of <10mΩ, and no bonding voids; the thermal conductivity of the TIM material is >10W / (m・K), and the number of stacked layers in the heterogeneous die stack is 6 or more. The vertical photonic via array is formed by DRIE etching to form through-holes. The inner wall of the via is deposited with a SiO2 insulating layer by PECVD. The via is filled with optical waveguide material. The vertical photonic via array is precisely aligned and integrated with VCSEL / PD optoelectronic devices. The overall packaging layer is equipped with a microfluidic cooling network, which is connected to the microfluidic cooling channels in the substrate layer, computing die, HBM memory die, and photoelectric conversion die. The microfluidic cooling network is equipped with a DTM dynamic temperature control algorithm. The DTM algorithm dynamically adjusts the flow rate and pressure of the cooling medium according to the temperature of the stacked die nodes. The flow rate range is 1-5 mL / min, and the pressure range is 0.1-0.3 MPa.

[0015] As a further improvement of the present invention, the temperature control logic of the DTM dynamic temperature control algorithm is as follows: real-time temperature of each node of the stacked die is collected by a sensor; when the node temperature is ≥75℃, the cooling medium flow rate is increased by 5% gradient; when the node temperature is ≥80℃, the flow rate and pressure are simultaneously increased to the upper limit of the threshold; when the node temperature is ≤60℃, the cooling medium flow rate is decreased by 5% gradient; the response delay of the DTM algorithm is ≤100ms, and it can ensure that the node temperature of the stacked die is stable at ≤85℃.

[0016] As a further improvement of the present invention, a highly thermally conductive TIM medium is filled between the encapsulation cap and the top die to achieve gapless bonding and seamless heat conduction; the encapsulation cap and the microfluidic cooling network cooperate to form a double-layer heat dissipation structure.

[0017] As a further improvement of the present invention, the core characteristic parameters of the structure meet the following requirements: RDL linewidth / spacing for electrical interconnection <1μm, interlayer resistance <10mΩ; 1550nm band loss for optical interconnection <0.1dB / cm, coupling efficiency ≥85%; TIM thermal conductivity for thermal management >10W / (m・K); and in terms of reliability, hybrid bonding strength >50MPa, effective electromagnetic shielding, and high long-term stability are achieved.

[0018] The above technical solution has the following beneficial effects: 1. Embedded microfluidic cooling network with full coverage: Breaking through the traditional single top / bottom heat dissipation method, microfluidic cooling channels are fabricated in the substrate layer, computing die, HBM memory die, and photoelectric conversion die, and full connectivity is achieved through the microfluidic cooling network of the overall packaging layer. The cooling medium can directly contact the core area of ​​each heat-generating die, avoiding the accumulation of thermal resistance layer by layer.

[0019] 2. Dynamic temperature control + dual-layer heat dissipation for dual protection: Equipped with DTM dynamic temperature control algorithm, it can adjust the flow and pressure of cooling medium in real time according to the die junction temperature to ensure that the junction temperature is stable at ≤85℃ (in line with the safety threshold of semiconductor devices) and the algorithm response latency is ≤100ms; combined with copper-tungsten alloy packaging capping layer + interlayer high thermal conductivity TIM material to form a dual-layer heat dissipation structure, gapless heat conduction, to solve the heat dissipation requirements of high power stack.

[0020] 3. The introduction of Vertical Photonic Through-Via (VP-TSVs) enables vertical transmission of optical signals. Compared with the single-channel 100Gb / s bandwidth and severe attenuation over long distances of traditional copper-based silicon through-vias, this significantly improves transmission bandwidth and distance, meeting the next generation of TB-level and even Tbps-level data requirements. Attached Figure Description

[0021] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0022] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0023] Figure 1 This is a schematic diagram of the process provided by the present invention.

[0024] Figure 2 This is a schematic diagram of the product structure prepared in step 1 of the present invention.

[0025] Figure 3 This is a schematic diagram of the structure of a portion of the product prepared in step 2 of the present invention.

[0026] Figure 4 This is a schematic diagram of the product structure prepared in step 2 of the present invention.

[0027] Figure 5 This is a schematic diagram of the product structure prepared in step 3 of the present invention.

[0028] Figure 6 This is a schematic diagram of the product structure prepared in step 4 of the present invention.

[0029] Figure 7 This is a schematic diagram of the product structure prepared in step 5 of the present invention.

[0030] Figure 8 This is a schematic diagram of the product structure prepared in step 6 of the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of a portion of the product prepared in step 7 of the present invention.

[0032] Figure 10 This is a schematic diagram of the product structure prepared in step 7 of the present invention.

[0033] Figure 11 This is a schematic diagram of the product structure prepared in step 8 of the present invention.

[0034] Figure 12 This is a schematic diagram of the product structure prepared in step 9 of the present invention.

[0035] In the picture: 100. Substrate layer; 101. Computational die; 102. HBM memory die; 103. Photoelectric conversion die; 11. Silicon wafer; 12. Ti / Cu layer; 13. RDL circuit; 14. Cooling inlet and outlet; 15. Main cooling channel; 21. Temporary substrate; 22. First BCB dielectric layer; 23, 29. SiO2 insulating layer; 24. Microchannel cavity; 25. Vertical cooling channel; 26. Copper thin film; 27. First through-silicon via; 28. First microbump; 31. Logic chip; 32. Second BCB dielectric layer; 33. Second copper pillar; 34. Second microbump; 41. HBM wafer; 42. Third BCB dielectric layer; 43. Third copper pillar; 44. Third microbump; 51. Optoelectronic chip; 52. Fourth BCB dielectric layer; 53. Fourth copper pillar; 54. Fourth microbump; 61. First TIM layer; 62. Second TIM layer; 71. Vertical photonic aperture array; 72. Vertical cavity surface-emitting laser; 73. Photodetector; 81. Encapsulation cap; 82. Overall encapsulation layer; 83. PCB substrate. Detailed Implementation

[0036] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0037] like Figure 1-12 As shown, a 3D heterogeneous integration packaging method for chip packaging includes the following steps: Step 1: Using silicon wafer 11 as a substrate, a Ti / Cu layer 12 is first deposited on the surface of silicon wafer 11 using SPT (Strain Proximity Technique). The Ti layer serves as an adhesion and barrier layer, while the Cu layer serves as a conductive seed layer, enhancing interlayer bonding and conductivity reliability. Subsequently, electrical signal RDL lines 13 are fabricated on the Ti / Cu layer 12 through photolithography, electroplating, and etching processes. This achieves fan-out and redistribution of chip electrical signals, controlling the RDL linewidth / spacing to be less than 1 μm to meet high-density interconnect requirements.

[0038] The DRIE (Deep Reactive Ion Etching) process is used to etch interconnected cooling inlets / outlets 14 and main cooling channels 15 inside the silicon wafer 11. The diameter of the cooling inlets / outlets 14 is 1 mm, and the width of the main cooling channels 15 is 500 μm, ensuring smooth flow of the cooling medium. After etching, the inner walls of the channels are polished and cleaned to remove etching residues, debris, and impurities, ensuring a smooth and clean inner wall, reducing the flow resistance of the cooling medium, and improving heat dissipation efficiency.

[0039] The product prepared in step 1 is as follows Figure 2 As shown.

[0040] Step 2, Microfluidic Cooling Channel Fabrication Stage: Using a temporary substrate 21 as the support, a BCB dielectric layer (defined as the first BCB dielectric layer) 22 is coated onto the surface of the temporary substrate 21 using a spin-coating process. The dimensions of the first BCB dielectric layer 22 are completely consistent with those of the silicon wafer 11, and the thickness is controlled to 100 μm, serving as the basic function of insulation, support, and the formation of the microfluidic channel cavity. After spin-coating, a SiO2 insulating layer 23 is deposited on the surface of the first BCB dielectric layer 22 using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process to further improve the insulation performance and avoid leakage interference between the subsequent conductive structure and the cooling channel.

[0041] Subsequently, photolithography + RIE (reactive ion etching) process is used to simultaneously etch the first BCB dielectric layer 22 and SiO2 insulating layer 23 to form microfluidic cavity 24 and vertical cooling channel 25 connected to the microfluidic cavity 24 vertically. The microfluidic cavity 24 and the vertical cooling channel 25 cooperate with each other to provide a channel for the flow of cooling medium.

[0042] To improve the thermal conductivity and structural stability of the cooling channel, a 100nm thick copper thin film 26 was deposited on the inner wall of the microfluidic cooling channel using a sputtering process. After sputtering, the entire structure was annealed at 200℃ for 30 minutes. Annealing eliminated internal stress in the copper thin film 26, enhanced the adhesion between the copper thin film 26 and the inner wall of the microfluidic cooling channel, and prevented detachment during subsequent use. The resulting product structure is shown below. Figure 3 As shown.

[0043] After annealing, the first BCB dielectric layer 22 is sealed and fixed to the silicon wafer prepared in step 1 using AuSi adhesive. During the sealing process, it is ensured that the main cooling channel 15 and the microfluidic cavity 24 are precisely aligned, forming a complete and interconnected microfluidic cooling channel after docking. After fixing, a comprehensive inspection of the integrity, sealing performance, and dimensional accuracy of the microfluidic cooling channel is conducted using precision testing equipment to ensure no damage, no leakage, and that the dimensions meet design requirements. The structure of the prepared product is as follows: Figure 4 As shown.

[0044] As an equivalent implementation, the temporary substrate can be a glass substrate, a quartz substrate, etc.; the BCB dielectric layer can be replaced with high-temperature resistant dielectric materials such as PI and PSPI; the SiO2 insulating layer can be replaced with a SiN insulating layer; the copper film can be replaced with conductive and thermally conductive materials such as aluminum film and silver film; the annealing temperature and time can be adjusted within the range of 180-220℃ and 25-35min; the AuSi adhesive can be replaced with AuSn adhesive, etc., all of which can achieve the same sealing, fixing, and cooling functions.

[0045] Step 3 involves the fabrication of through-silicon vias (TSVs) and microbumps. Based on the layout design, the assembly obtained in Step 2 is etched using the DRIE process to form the first TSV 27. The etching path strictly avoids microfluidic cooling channels to prevent structural damage and leakage. Subsequently, copper is electroplated into the first TSV 27 to form a void-free first copper pillar. The exposed portion of the copper pillar is then chemically and mechanically polished to make it flush with the end face of the assembly, ensuring the accuracy of subsequent interconnects.

[0046] After polishing, a copper micro-bump 28 that is electrically connected to the first copper pillar is made on the end face of the assembly by electroplating. Finally, a SiO2 insulating layer 29 is deposited by PECVD to fully cover the micro-bump 28 and the end face, achieving electrical isolation.

[0047] The preparation of the substrate 100 is completed through the above steps 1, 2 and 3.

[0048] Step 4, Fabrication of the computational die 101: To achieve subsequent die bonding and overall chip functionality, two core substrates are first selected: a logic wafer 31 and a BCB dielectric layer (defined as the second BCB dielectric layer) 32. The size of the logic wafer 31 is completely consistent with that of the silicon wafer 11 of the substrate layer, and its height is controlled at 200μm. As the core functional layer of the computational die, it undertakes the chip's computational processing tasks. The size of the second BCB dielectric layer 32 is consistent with that of the silicon wafer 11 and the logic wafer 31, and its height is 100μm. It mainly serves to insulate, support, and form a cooling channel.

[0049] After selecting the substrate, the logic wafer 31 and the second BCB dielectric layer 32 are combined using the same process as in steps 1, 2, and 3. Specifically, the surface metal layer and circuit pretreatment of the substrate are completed according to the fabrication process in step 1, and the vertical cooling channel and microfluidic cooling channel are fabricated on the combined substrate according to the microfluidic cooling channel fabrication process in step 2 to ensure the heat dissipation requirements of the computing die during operation.

[0050] Simultaneously, referring to the silicon via and microbump fabrication process in step 3, silicon vias are etched on the composite substrate, and a copper layer is filled to form a second copper pillar 33. After polishing, the end face of the copper pillar is made flush with the end face of the composite substrate. Then, a second microbump 34 electrically connected to the second copper pillar 33 is fabricated, completing the entire structure fabrication of the computing die. This ensures that its dimensions and process parameters match the previously prepared assembly, making full preparations for the subsequent die bonding process.

[0051] The product prepared in step 4 is as follows Figure 6 As shown.

[0052] As an equivalent implementation, the logic wafer can be replaced with an arithmetic wafer of the same size; the height of the second BCB dielectric layer can be adjusted in the range of 80-120μm; the height of the logic wafer can be adapted in the range of 180-220μm; and the process used can be an alternative process with the same function as steps 1-3, all of which can realize the preparation of the arithmetic die and subsequent bonding requirements.

[0053] Step 5, Fabrication of HBM Memory Die 102: To meet the chip's storage function requirements and ensure compatibility with subsequent die bonding, two core substrates are selected: HBM wafer 41 and BCB dielectric layer (defined as the third BCB dielectric layer) 42. Both have dimensions identical to the silicon wafer 11 of the substrate layer, ensuring overall structural matching. The HBM wafer 41 has a height of 200 μm and serves as the core functional layer of the HBM memory die, undertaking the chip's data storage and retrieval tasks. The third BCB dielectric layer 42 has a height of 100 μm and primarily functions as insulation and support, while also providing a foundation for the subsequent fabrication of cooling channels.

[0054] After the substrate selection is completed, the HBM wafer 41 and the third BCB dielectric layer 42 are combined and processed using the same process as steps 1, 2, and 3. Specifically, the surface metal layer and circuitry of the substrate are pre-treated according to the fabrication process in step 1; vertical cooling channels and microfluidic cooling channels are fabricated on the combined substrate according to the microfluidic cooling channel fabrication process in step 2 to ensure that the heat generated by the HBM memory die during operation can be dissipated in a timely manner, thus ensuring its operational stability.

[0055] Simultaneously, referring to the silicon via and microbump fabrication process in step 3, silicon vias are etched on the composite substrate, and a copper layer is filled to form a third copper pillar 43. After polishing, the end face of the copper pillar is made flush with the end face of the composite substrate. Then, a third microbump 44 electrically connected to the third copper pillar 43 is fabricated, completing the entire structure fabrication of the HBM memory die. This ensures that its process parameters and size specifications are compatible with the composite and computing die prepared above, making full preparations for the subsequent die bonding process.

[0056] The product prepared in step 5 is as follows Figure 7As shown.

[0057] As an equivalent implementation, the HBM wafer can be replaced with a memory wafer of the same size and function; the height of the third BCB dielectric layer can be adjusted in the range of 80-120μm; the height of the HBM wafer can be adapted in the range of 180-220μm; and the processing technology used can be an alternative process with the same function as steps 1-3, all of which can meet the requirements for the preparation of HBM memory dies and subsequent bonding.

[0058] Step 6: Fabrication of the photoelectric conversion die 103: To realize the photoelectric signal conversion function of the chip and ensure the size compatibility of subsequent die bonding, two core substrates are selected: the photoelectric wafer 51 and the BCB dielectric layer (defined as the fourth BCB dielectric layer) 52. Both have dimensions completely consistent with the silicon wafer 11 of the substrate layer, ensuring matching with the previously prepared assembly, computing die, and HBM memory die structure. The photoelectric wafer 51 has a height of 200 μm and serves as the core functional layer of the photoelectric conversion die, undertaking the task of converting optical signals to electrical signals. The fourth BCB dielectric layer 52 has a height of 100 μm and mainly serves as insulation and support, while also providing a basic carrier for the fabrication of cooling channels and interconnect structures.

[0059] After the substrate selection is completed, the same process as in steps 1, 2, and 3 is used to assemble the optoelectronic wafer 51 and the fourth BCB dielectric layer 52. Specifically, referring to the fabrication process in step 1, the pretreatment of the metal layer and circuitry on the substrate surface is completed; referring to the microfluidic cooling channel fabrication process in step 2, vertical cooling channels and microfluidic cooling channels are fabricated on the assembled substrate to dissipate the heat generated during photoelectric conversion in a timely manner and ensure the working stability of the bare wafer.

[0060] Simultaneously, referring to the silicon via and microbump fabrication process in step 3, silicon vias are etched on the composite substrate, and a copper layer is filled to form the fourth copper pillar 53. After polishing, the end face of the copper pillar is made flush with the end face of the composite substrate. Then, the fourth microbump 54, which is electrically connected to the fourth copper pillar 53, is fabricated to complete the fabrication of the entire structure of the photoelectric conversion die. This ensures that its process parameters and size specifications are compatible with the structures described above, and makes full preparations for the subsequent die bonding process.

[0061] The product prepared in step 6 is as follows Figure 8 As shown.

[0062] As an equivalent implementation, the optoelectronic wafer can be replaced with an optoelectronic conversion wafer of the same size and function; the height of the fourth BCB dielectric layer can be adjusted in the range of 80-120μm; the height of the optoelectronic wafer can be adapted in the range of 180-220μm; the processing technology used can adopt a substitute process with the same function as steps 1-3, all of which can realize the preparation of the optoelectronic conversion die and subsequent bonding requirements.

[0063] Step 7, 3D Die Hybrid Bonding and Stacking Stage: To achieve 3D heterogeneous chip integration, a Cu-Cu hybrid bonding process is used for die stacking. First, the photoelectric conversion die prepared in Step 7 is precisely aligned and bonded to the substrate layer prepared in Step 3, ensuring precise alignment and reliable electrical connection between the fourth microbump of the photoelectric conversion die and the first microbump of the substrate layer. Then, following the preset stacking order, four HBM memory dies prepared in Step 5 are stacked sequentially. Finally, the computing dies prepared in Step 4 are stacked, ultimately achieving a stable stack of six dies. The resulting product structure is shown below. Figure 9 As shown.

[0064] The bonding process strictly controls process parameters, including a bonding temperature of 300℃, a bonding pressure of 5MPa, and a bonding time of 60 minutes. This combination of parameters effectively improves the bonding strength of Cu-Cu bonds, ensuring the stability and conductivity of interlayer interconnects and avoiding problems such as poor bonding and contact. Immediately after bonding, the overall stack structure undergoes electrical testing. Professional testing equipment verifies the electrical signal connectivity between each die layer, identifies interconnect faults, and ensures interconnect reliability. By employing Cu-Cu hybrid bonding technology, an RDL linewidth / spacing of <1μm, interlayer resistance <10mΩ, and bonding strength >50MPa are achieved, guaranteeing efficient and stable electrical signal transmission.

[0065] After passing electrical testing, to improve overall heat dissipation performance and enhance the integrity of the stacked structure, the gaps between the photoelectric conversion wafers and the substrate layer, as well as all gaps between the six wafer layers, were filled with high thermal conductivity TIM (thermal interface material) to form the first TIM layer 61. The filling process ensured no voids or air bubbles, forming a tight integral structure between all wafers and the substrate layer. After filling, an airtightness test was performed, focusing on verifying the sealing of the microfluidic cooling channels to prevent cooling medium leakage and ensure the normal operation of the cooling system. By filling the interlayer with high thermal conductivity TIM material, a tight integral structure was formed, enhancing mechanical strength and thermal conductivity efficiency. The resulting product structure is as follows. Figure 10 As shown.

[0066] Step 8, Vertical Photonic Through-Via Array Fabrication Stage: To achieve vertical transmission of photonic signals between the wafer layers, based on the layout design, the DRIE (Deep Reactive Ion Etching) process is used to perform through-etching on the 6-layer wafer stack product prepared in Step 7, forming a vertical photonic through-via array 71 (VP-TSVs). During the etching process, the etching path is strictly controlled to avoid microfluidic cooling channels and the interconnect structures of each wafer layer, preventing damage to existing structures and ensuring that the photonic through-vias do not interfere with other structures.

[0067] After etching, a SiO2 insulating layer is deposited on the inner wall of the vertical photonic via array using PECVD (plasma-enhanced chemical vapor deposition) to provide electrical isolation and structural protection, preventing interference with photonic signal transmission. Subsequently, Si3N4 waveguide material is filled into the vias using LPCVD (low-pressure chemical vapor deposition) at 500℃ and a deposition rate of 3 nm / min. This material effectively ensures low-loss transmission of photonic signals.

[0068] After filling, the entire product is annealed at 500℃ for 60 minutes to eliminate internal stress in the waveguide material, improve the bonding force between the waveguide material and the inner wall of the via, and ensure structural stability. After annealing, the end faces of both ends of the via are polished using CMP (chemical mechanical polishing) to ensure that the end faces of the via are flat with the upper and lower surfaces of the stacked product, laying the foundation for subsequent signal transmission and packaging processes.

[0069] The product prepared in step 8 is as follows Figure 11 As shown.

[0070] The core parameters for this stage are controlled as follows: the diameter of the vertical photonic aperture is 10μm and the depth is 300μm, the array grid spacing is 100μm, and the waveguide loss is controlled within 0.1dB / cm to ensure efficient and stable transmission of photonic signals.

[0071] This solution introduces vertical photonic through-hole arrays (VP-TSVs) to transmit optical signals vertically (loss <0.1dB / cm in the 1550nm band), which has lower loss and higher bandwidth compared to pure electrical interconnects.

[0072] Step 9, Optoelectronic Alignment and Overall Packaging Stage: To achieve the input and output of photonic signals, the VCSEL / PD (Vertical Cavity Surface Emitting Laser 72 / Photodetector 73) is first precisely aligned with the vertical photonic via array 71 prepared in Step 8. The alignment process uses high-precision alignment equipment, and the alignment error is strictly controlled to be ≤±0.5μm to ensure that the VCSEL / PD and the vertical photonic via array are accurately connected, ensuring the accuracy and stability of photonic signal transmission and avoiding signal loss or transmission failure due to alignment deviation.

[0073] After alignment, a low-temperature eutectic (AuSn) curing adhesive is used to fix the VCSEL / PD to the top and bottom of the die. The low-temperature eutectic adhesive cures at a lower temperature, avoiding damage to the internal structure of the die from high temperatures, while ensuring a firm fixation of the VCSEL / PD and improving structural stability. Subsequently, a copper-tungsten alloy encapsulation layer 81 is installed. Copper-tungsten alloy possesses excellent thermal conductivity and structural strength, effectively dissipating heat from the encapsulation and protecting the internal die structure.

[0074] A second TIM layer 62 is formed by filling the space between the encapsulation cap layer 81 and the top die with a highly thermally conductive TIM material, further improving heat dissipation efficiency, reducing interlayer thermal resistance, and ensuring long-term stable operation of the chip. The entire structure is then encapsulated to form the overall encapsulation layer 82. The encapsulation process ensures no gaps or air bubbles. A microfluidic cooling network, connected to microfluidic cooling channels, is pre-installed within the overall encapsulation layer 82 to ensure normal flow of the cooling medium and continuous heat dissipation.

[0075] After packaging, the entire package structure is mounted on the PCB substrate 83 to achieve electrical connection between the chip and external circuits. Then, a comprehensive system test is performed to verify the chip's electrical performance, optical performance, heat dissipation performance, and overall reliability.

[0076] The product prepared in step 9 is as follows Figure 12 As shown.

[0077] This invention designs two optical waveguide material filling schemes for different application scenarios and for vertical photonic via array optical waveguide materials, both of which are compatible with mature semiconductor processes. The specific filling processes and parameters are as follows: Polymer material filling: Suitable for low-to-medium loss and low-cost applications, modified epoxy resin, PI or BCB are selected as waveguide materials; filling is completed by vacuum-assisted spin coating (3000-6000rpm) or capillary impregnation, followed by low-temperature pre-baking + high-temperature curing (180-350℃) treatment, and finally the end face of the through hole is polished by chemical mechanical polishing (CMP) to ensure the optical signal coupling accuracy.

[0078] Silicon-based silicon nitride (Si3N4) filling: suitable for low-loss, high-temperature applications; Si3N4 is deposited using low-pressure chemical vapor deposition (LPCVD, 400-600℃) or plasma-enhanced chemical vapor deposition (PECVD, 200-300℃), followed by annealing at 500℃ to improve material density, and finally fine-tuning of via size using CMP polishing and reactive ion etching (RIE) to ensure waveguide performance.

[0079] like Figure 12 As shown, a 3D heterogeneous integrated packaging structure for chip packaging, fabricated using the above method, comprises a substrate layer 100, a heterogeneous die stack layer, a vertical photonic via array 71, and a copper-tungsten alloy encapsulation cap layer 81. The substrate layer, heterogeneous die stack layer, and vertical photonic via array below the encapsulation cap layer 81 are encapsulated to form a total encapsulation layer 82; wherein: The heterogeneous die stack is formed by vertically stacking computing dies 101, HBM memory dies, and photoelectric conversion dies 103 through Cu-Cu hybrid bonding, using a high / low power chip staggered arrangement, and high thermal conductivity TIM material is placed between the die layers; the hybrid bonding accuracy is <±0.5μm, the bonding strength is >50MPa, the interlayer resistance is <10mΩ and there are no bonding voids; the thermal conductivity of the TIM material is >10W / (m·K), and the number of stacked layers in the heterogeneous die stack is 6 or more; The vertical photonic via array 71 is formed by DRIE etching to form through-holes. The inner wall of the via is deposited with a SiO2 insulating layer by PECVD. The via is filled with optical waveguide material. The vertical photonic via array 71 is precisely aligned and integrated with VCSEL / PD optoelectronic devices. A microfluidic cooling network is provided within the overall packaging layer 82. This microfluidic cooling network is connected to the microfluidic cooling channels in the substrate layer 100, the microfluidic cooling channels in the computing die 101, the microfluidic cooling channels in the HBM memory die 102, and the microfluidic cooling channels in the photoelectric conversion die 103. The microfluidic cooling network adopts the DTM dynamic temperature control algorithm. The DTM algorithm dynamically adjusts the flow rate and pressure of the cooling medium according to the temperature of the stacked die nodes. The flow rate range is 1-5 mL / min, and the pressure range is 0.1-0.3 MPa.

[0080] Furthermore, the DTM dynamic temperature control algorithm collects the real-time temperature of each node of the stacked die through sensors. When the node temperature is ≥75℃, the cooling medium flow rate is increased by 5% gradient. When the node temperature is ≥80℃, the flow rate and pressure are increased simultaneously to the upper limit of the threshold. When the node temperature is ≤60℃, the cooling medium flow rate is reduced by 5% gradient to achieve closed-loop temperature control, ensuring that the node temperature is stable at ≤85℃ and the algorithm response delay is ≤100ms.

[0081] In this solution, a high thermal conductivity TIM medium is filled between the encapsulation cap 81 and the top die to achieve gapless bonding and seamless heat conduction; the encapsulation cap, together with a microfluidic cooling network, achieves double-layer heat dissipation, improves the overall heat dissipation capacity, and solves the heat dissipation problem of high-power chips.

[0082] The overall packaging test of the above-mentioned 3D heterogeneous integrated packaging structure revealed the following characteristics:

[0083] The 3D heterogeneous integrated packaging structure and method for chip packaging provided by this invention focuses on overcoming two major industry pain points: thermal management and high-speed interconnection. It also considers process compatibility, structural reliability, and application scalability. Compared with traditional 3D packaging technologies and mainstream industry solutions, it has significant advantages in multiple dimensions, which can be specifically divided into five categories: heat dissipation performance, interconnection transmission, structural process, reliability, and application adaptability, as detailed below: I. Significantly improved heat dissipation efficiency, solving the problem of thermal resistance in high-layer stacking. 1. Embedded microfluidic cooling network with full coverage: Breaking through the traditional single top / bottom heat dissipation method, microfluidic cooling channels are fabricated in the substrate layer, computing die, HBM memory die, and photoelectric conversion die, and full connectivity is achieved through the microfluidic cooling network of the overall packaging layer. The cooling medium can directly contact the core area of ​​each heat-generating die, avoiding the accumulation of thermal resistance layer by layer.

[0084] 2. Dynamic temperature control + dual-layer heat dissipation for dual protection: Equipped with DTM dynamic temperature control algorithm, it can adjust the flow rate (1-5mL / min) and pressure (0.1-0.3MPa) of cooling medium in real time according to the die junction temperature, ensuring that the junction temperature is stable at ≤85℃ (meeting the safety threshold of semiconductor devices), and the algorithm response delay is ≤100ms; combined with copper tungsten alloy packaging capping layer + interlayer high thermal conductivity TIM material (thermal conductivity >10W / (m・K)) to form a dual-layer heat dissipation structure, with gapless heat conduction, completely solving the heat dissipation requirements of high power stacks with eight or more layers.

[0085] 3. Integrated heat dissipation structure and packaging design: The cooling channel is embedded and does not require additional packaging space. This overcomes the space disadvantage of external microfluidic cooling solutions and achieves a high degree of integration between heat dissipation and packaging.

[0086] II. Significantly improved interconnect transmission performance to meet TB / Tbps level data throughput requirements. 1. Optoelectronic interconnection synergy, breaking through the bandwidth bottleneck of electrical interconnection: The introduction of vertical photonic through-hole arrays (VP-TSVs) enables vertical transmission of optical signals, with a loss of <0.1dB / cm and coupling efficiency of ≥85% in the 1550nm band. Compared with the single-channel 100Gb / s bandwidth and severe attenuation over long distances (1-2dB attenuation per centimeter in 100Gbps PAM4 mode) of traditional copper-based silicon through-holes, this significantly improves the transmission bandwidth and distance, meeting the data requirements of the next generation of TB-level and even Tbps-level data.

[0087] 2. High-density electrical interconnects enable low-resistance and high-efficiency transmission: RDL linewidth / spacing is achieved with SPT stress proximity technology and fine photolithography electroplating process, and Cu-Cu hybrid bonding technology is combined to achieve interlayer resistance of <10mΩ, which is far superior to the transmission efficiency of traditional electrical interconnects, while ensuring the high-density requirements of electrical signal fan-out and redistribution.

[0088] 3. Seamless integration of optical interconnect and 3D packaging processes: The vertical photonic via array is fabricated using DRIE etching, with the etching path avoiding cooling channels and electrical interconnect structures. Furthermore, the optical waveguide material filling scheme (Si3N4 / polymer) is compatible with standard CMOS processes, solving the industry problems of high optical coupling loss and material thermal expansion coefficient mismatch in existing vertical optical interconnect technologies.

[0089] III. Advanced structural and process design, strong compatibility and high scalability 1. Standardized fabrication of heterogeneous dies, adaptable to multi-layer stacking: The computing, HBM memory, and optoelectronic conversion dies are all fabricated using the same process and size standards as the substrate layer. Furthermore, the height of the dielectric layer and functional wafers (functional wafers refer to logic wafers, HBM wafers, and optoelectronic wafers) of each die can be adjusted within the adaptation range (e.g., BCB dielectric layer 80-120μm, functional wafer 180-220μm), supporting stable stacking of 6 or more dies, breaking through the bottleneck of the industry's mainstream solution that limits the number of stacking layers.

[0090] 2. Core processes are replaceable and adaptable to different production needs: There are equivalent implementation methods for microfluidic cooling channels, core substrates (temporary substrate, dielectric layer, insulating layer) in bare die preparation, conductive and thermally conductive materials, adhesives, etc. Process parameters (annealing temperature / time, bonding parameters) can be finely adjusted as needed, and are highly compatible with existing mature semiconductor processes without the need for large-scale production line modifications.

[0091] 3. High / low power chip staggered arrangement: This layout of heterogeneous die stacking layers can optimize the overall heat distribution, avoid local heat concentration, and further improve the heat dissipation rationality and working stability of the stacking structure.

[0092] IV. Structural reliability and interconnect stability are significantly enhanced. 1. Cu-Cu hybrid bonding achieves high bonding strength: precise control of bonding parameters (300℃, 5MPa, 60min) achieves bonding accuracy <±0.5μm and bonding strength >50MPa, with no bonding voids, no poor contact or interlayer interconnection, ensuring the mechanical stability and electrical signal connectivity of the multilayer stacked structure.

[0093] 2. Multi-stage testing and stress relief process: After the microfluidic cooling channel is fabricated, integrity / sealing is tested; after the bare die is bonded, electrical and airtightness tests are performed; after the waveguide material and copper thin film are fabricated, they are annealed to eliminate internal stress, avoid problems such as material detachment, structural damage, and cooling medium leakage, and improve long-term operational reliability.

[0094] 3. Multiple insulation and electromagnetic shielding: Each structural layer is electrically isolated by PECVD deposition of SiO2 / SiN insulating layers. The entire package has an effective electromagnetic shielding effect, avoiding interference between electrical and optical signals and ensuring transmission accuracy.

[0095] V. It has broad applicability to various application scenarios, supporting the needs of cutting-edge high-computing fields. 1. Dual optical waveguide material solutions to suit different application requirements: The Si3N4 filling solution is suitable for low-loss, high-temperature operating scenarios, while the polymer material (modified epoxy resin / PI / BCB) filling solution is suitable for medium-low loss, low-cost scenarios. Both solutions are compatible with the manufacturing process and can be flexibly selected according to the actual application.

[0096] 2. Three-dimensional heterogeneous integration of optical, electrical, and thermal components: It realizes the full-domain integration of efficient transmission of electrical and optical signals and thermal management, perfectly adapting to cutting-edge high-computing and high-bandwidth application scenarios such as high-performance computing, AI accelerators, and high-speed optical interconnects, and can support the chip to operate at full speed for a long time.

[0097] 3. Core advantages compared to mainstream industry solutions: Compared to the obstacle avoidance strategies of Intel Foveros and TSMC CoWoS, which limit the number of layers / distance, and the shortcomings of TSMC's COUPE platform in terms of strict temperature rise control (<2℃) and lack of active cooling, this solution does not need to limit the number of stacked layers and interconnection distance. Moreover, the active dynamic heat dissipation can support the long-term stable operation of high-power chips, and has higher technical maturity and practical value.

[0098] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0099] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 3D heterogeneous integration packaging method for chip packaging, characterized in that: Includes the following steps: S1. Substrate layer pretreatment: Using a silicon wafer as the substrate, a Ti / Cu layer is deposited on the surface of the silicon wafer using the SPT stress proximity technique, and then an electrical signal RDL line with a linewidth / spacing of less than 1μm is fabricated on the Ti / Cu layer. The DRIE (Deep Reactive Ion Etching) process is used to etch interconnected cooling inlets and outlets and main cooling channels inside the silicon wafer. S2. Fabrication of Microfluidic Cooling Channels: Using a temporary substrate as the support, a first BCB dielectric layer of the same size as the silicon wafer is spin-coated. After depositing a SiO2 insulating layer using PECVD, microfluidic cavities and vertical cooling channels are formed by simultaneous etching using photolithography and RIE processes. A copper thin film is sputtered on the inner wall of the cooling channel, and then the first BCB dielectric layer is sealed and fixed to the pre-treated silicon wafer using AuSi adhesive, so that the main cooling channel and the microfluidic cavity are precisely aligned. S3. Preparation of Through-Silicon Vias and Microbumps: The assembly obtained in step 2 is etched using the DRIE process to form the first through-silicon via. The etching path avoids the microfluidic cooling channel. Copper is electroplated to fill the first through-silicon via to form a void-free first copper pillar. After polishing, the first copper microbumps electrically connected to the first copper pillars are electroplated on the end face of the assembly. Finally, a SiO2 insulating layer is deposited using the PECVD process to achieve electrical isolation, thus completing the preparation of the substrate layer. S4. Fabrication of computing die: Select a logic wafer with the same size as the silicon wafer and the second BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the surface metal layer and circuit pretreatment of the substrate, microfluidic cooling channel fabrication, through-silicon via, second copper pillar and second microbump fabrication to obtain the computing die. S5. Preparation of HBM memory die: Select an HBM wafer with the same size as the silicon wafer and the third BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the pretreatment of the metal layer and circuit on the substrate surface, the preparation of microfluidic cooling channels, through-silicon vias, the preparation of the third copper pillar and the third microbump, and obtain the HBM memory die. S6. Photoelectric conversion bare die preparation: Select a photoelectric wafer with the same size as the silicon wafer and the fourth BCB dielectric layer as the substrate. Use the same process as in steps 1-3 to complete the surface metal layer and circuit pretreatment of the substrate, microfluidic cooling channel preparation, silicon via, fourth copper pillar and fourth microbump preparation to obtain the photoelectric conversion bare die. S7, 3D die hybrid bonding stacking: Using Cu-Cu hybrid bonding process, the photoelectric conversion die is precisely aligned and bonded to the substrate layer, and then 4 HBM memory dies and computing dies are stacked in sequence to achieve 6 or more layers of die stacking; after bonding, electrical testing is performed, and after passing the test, high thermal conductivity TIM material is filled between each die layer and the substrate layer, and then airtightness testing is performed. S8. Fabrication of Vertical Photonic Via Array: The stacked product is etched through the DRIE process to form a vertical photonic via array, with the etching path avoiding microfluidic cooling channels and interconnect structures; SiO2 insulating layer is deposited on the inner wall of the via using PECVD process, and Si3N4 waveguide material is filled using LPCVD process. S9. Optoelectronic Alignment and Overall Packaging: The VCSEL / PD is precisely aligned with the vertical photonic via array, with an alignment error of ≤±0.5μm. The VCSEL / PD is fixed with low-temperature eutectic AuSn curing adhesive, and a copper-tungsten alloy encapsulation cap is installed. High thermal conductivity TIM material is filled between the encapsulation cap and the top die, and encapsulation is performed to form the overall encapsulation layer. A microfluidic cooling network connected to the microfluidic cooling channel is reserved in the overall encapsulation layer. After encapsulation, the entire assembly is mounted on the PCB substrate.

2. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 2, the temporary substrate can be a glass substrate or a quartz substrate; the first BCB dielectric layer can be replaced with PI or PSPI high-temperature resistant dielectric material; the annealing temperature can be adjusted within the range of 180-220℃ and the annealing time can be adjusted within the range of 25-35min.

3. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 4, the height of the second BCB dielectric layer can be adjusted within the range of 80-120μm; the height of the logic wafer can be adapted within the range of 180-220μm.

4. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 5, the height of the third BCB dielectric layer can be adjusted within the range of 80-120μm; the height of the HBM wafer can be adapted within the range of 180-220μm.

5. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 6, the height of the fourth BCB dielectric layer can be adjusted within the range of 80-120μm; the height of the optoelectronic wafer can be adapted within the range of 180-220μm.

6. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 8, the optical waveguide material for the vertical photonic via array can be a polymer material filling scheme. Specifically, modified epoxy resin, PI, or BCB is selected as the waveguide material, and it is filled by vacuum-assisted spin coating or capillary impregnation at 3000-6000 rpm. After low-temperature pre-baking and high-temperature curing at 180-350℃, the via end face is polished by chemical mechanical polishing.

7. The 3D heterogeneous integration packaging method for chip packaging according to claim 1, characterized in that, In step 8, the optical waveguide material for the vertical photonic via array can be a silicon-based silicon nitride filling scheme. Specifically, Si3N4 is deposited using LPCVD at 400-600℃ or PECVD at 200-300℃. After annealing at 500℃ to improve the material density, the via size is finely adjusted by CMP polishing and reactive ion etching.

8. A 3D heterogeneous integrated packaging structure for chip packaging, characterized in that, It is prepared by any one of the methods described in claims 1-7, and consists of a substrate layer, a heterogeneous die stack layer, a vertical photonic via array, and a copper-tungsten alloy encapsulation cap layer. The substrate layer, heterogeneous die stack layer, and vertical photonic via array below the encapsulation cap layer are encapsulated to form the total encapsulation layer. The heterogeneous die stack is formed by vertically stacking computing dies, HBM memory dies, and photoelectric conversion dies through Cu-Cu hybrid bonding, using a high / low power die staggered arrangement. High thermal conductivity TIM material is placed between the die layers; the Cu-Cu hybrid bonding has an accuracy of <±0.5μm, a bonding strength of >50MPa, an interlayer resistance of <10mΩ, and no bonding voids; the thermal conductivity of the TIM material is >10W / (m・K), and the number of stacked layers in the heterogeneous die stack is 6 or more. The vertical photonic via array is formed by DRIE etching to form through-holes. The inner wall of the via is deposited with a SiO2 insulating layer by PECVD. The via is filled with optical waveguide material. The vertical photonic via array is precisely aligned and integrated with VCSEL / PD optoelectronic devices. The overall packaging layer is equipped with a microfluidic cooling network, which is connected to the microfluidic cooling channels in the substrate layer, computing die, HBM memory die, and photoelectric conversion die. The microfluidic cooling network is equipped with a DTM dynamic temperature control algorithm, which dynamically adjusts the flow rate and pressure of the cooling medium according to the temperature of the stacked die nodes. The flow rate range is 1-5 mL / min, and the pressure range is 0.1-0.3 MPa.

9. The 3D heterogeneous integrated packaging structure for chip packaging according to claim 8, characterized in that, The temperature control logic of the DTM dynamic temperature control algorithm is as follows: real-time temperature of each node of the stacked die is collected by sensors. When the node temperature is ≥75℃, the cooling medium flow rate is increased by 5% gradient. When the node temperature is ≥80℃, the flow rate and pressure are increased simultaneously to the upper limit of the threshold. When the junction temperature is ≤60℃, the cooling medium flow rate is reduced by 5% gradient; the response delay of the DTM algorithm is ≤100ms, and it can ensure that the junction temperature of the stacked die is stable at ≤85℃.

10. The 3D heterogeneous integrated packaging structure for chip packaging according to claim 8, characterized in that, The encapsulation cap and the top die are filled with a high thermal conductivity TIM medium to achieve gapless bonding and seamless heat conduction; the encapsulation cap and the microfluidic cooling network work together to form a double-layer heat dissipation structure.

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