A high-heat-dissipation high-power device packaging structure and a preparation method thereof
By using a silicon carbide interposer and a heat sink packaging structure, the problem of insufficient heat dissipation performance of GaN power devices is solved, achieving rapid heat dissipation and high reliability packaging effects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN GUOXIN SEMICON TECH CO LTD
- Filing Date
- 2026-04-20
- Publication Date
- 2026-06-16
AI Technical Summary
Existing GaN power device packaging methods suffer from insufficient heat dissipation performance, especially WLCSP and LGA packaging methods, which have low heat dissipation performance, and wire bonding has inductance issues.
The packaging structure employs a silicon carbide interposer and a heat sink, and achieves rapid heat dissipation between the chip and the substrate through flip-chip packaging and copper dielectric vias, combined with the use of highly thermally conductive materials.
It improves the heat dissipation capacity of high-power devices, reduces heat accumulation, and enhances the reliability and performance of the packaging structure.
Smart Images
Figure CN122227983A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a high-heat-dissipation, high-power device packaging structure and its fabrication method. Background Technology
[0002] Power electronic products are evolving towards high performance, multifunctionality, miniaturization, and portability, placing increasingly higher demands on both the performance of semiconductor devices and their packaging. In the field of power semiconductors, GaN power devices, as a new generation of semiconductor devices, have become a key focus of research and development due to their excellent power characteristics. Currently, the main packaging methods for GaN power devices include DFN, TOLL, QFN, TO, WLCSP, and LGA.
[0003] In existing technologies, discrete packaging basically employs two process approaches. The first approach involves mounting the GaN power chip onto a copper lead frame. Then, through wire bonding, the source (S), drain (D), and gate (G) of the GaN power chip are electrically connected to the designed terminals via gold or copper wires, followed by molding. However, wire bonding introduces inductance issues. The second approach, based on FCQFN, WLCSP, and LGA packaging methods, avoids wire bonding, thus addressing the inductance problem inherent in wire bonding in high-frequency, high-speed circuits. However, these packaging methods each have their own drawbacks. For example, WLCSP (Wafer Lever Chip Scale Packaging) is a wafer-level packaging method with relatively low module voltage withstand and poor heat dissipation; LGA packaging uses a PCB substrate, resulting in relatively poor heat dissipation; and so on, requiring further improvement. Summary of the Invention
[0004] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing a high-power device packaging structure with excellent heat dissipation capabilities in all aspects, thereby improving the heat dissipation problem during the packaging of high-power devices such as GaN power devices and enhancing packaging performance.
[0005] To achieve the above objectives, the present invention provides a high heat dissipation, high-power device packaging structure, including a silicon carbide interlayer, a chip, a molding compound, and a heat sink. The silicon carbide interposer has a groove, and a silicon carbide through hole is provided in the groove. The silicon carbide through hole penetrates the lower surface of the silicon carbide interposer and the bottom surface of the groove. An upper solder layer and a lower solder layer are respectively provided at the ends of the silicon carbide through hole. The chip is disposed in the groove and the chip adopts flip-chip packaging. The chip electrode of the chip corresponds to the bottom of the groove. The chip electrode of the chip is electrically connected to the upper solder layer, and the lower solder layer is electrically connected to the substrate or PCB. The molding layer is disposed above the silicon carbide interlayer; The heat sink is disposed above the plastic seal layer and is made of metal.
[0006] Furthermore, the chip includes a GaN power chip, a gallium oxide power chip, and a SOC chip.
[0007] Furthermore, the dimensions of the groove are matched to those of the chip.
[0008] Furthermore, the heat sink is made of copper.
[0009] Furthermore, the molding compound is distributed on the upper surface of the silicon carbide interposer, the upper surface of the chip, the groove opening, and the interior of the groove.
[0010] Furthermore, the molding compound is distributed on the upper surface of the silicon carbide interposer and inside the groove, and a heat sink solder layer is provided on the upper surface of the chip, and the heat sink is connected to the chip through the heat sink solder layer.
[0011] The present invention also provides another high heat dissipation high power device packaging structure, including a silicon carbide interposer, a heat dissipation frame, a chip, a molding compound, and a heat sink; A silicon carbide through-hole is provided in the central region of the silicon carbide interposer. The silicon carbide through-hole penetrates the lower and upper surfaces of the silicon carbide interposer. An upper solder layer and a lower solder layer are respectively provided at the ends of the silicon carbide through-hole. The heat dissipation frame is supported by a metal material, and the heat dissipation frame is connected to the upper surface of the silicon carbide interposer layer, and the silicon carbide through holes are aligned with the central area of the heat dissipation frame. The chip is disposed in the central area of the heat dissipation frame and is packaged in a flip-chip manner. The chip electrodes are electrically connected to the upper solder layer and the lower solder layer is electrically connected to the substrate or PCB. The molding layer is disposed above the silicon carbide interlayer; The heat sink is disposed above the plastic seal layer and is made of metal.
[0012] This invention also provides a method for fabricating a high-heat-dissipation, high-power device packaging structure, comprising the following steps: S1. An insulating silicon carbide wafer is used to fabricate a silicon carbide interposer. Grooves are etched into the silicon carbide interposer by chemical reaction or etching method. Silicon carbide vias are then fabricated in the grooves by etching method. Silicon dioxide is deposited on the inner wall of the silicon carbide via as an insulating layer. Then a diffusion barrier layer is deposited. Finally, copper is electroplated in the silicon carbide via to complete the formation of the silicon carbide via. S2, the silicon carbide interlayer is thinned by chemical mechanical polishing to expose the end of the silicon carbide through-hole, and the upper and lower solder layers are fabricated. S3, through flip-chip bonding or copper pillar bonding process, the chip is packaged in the groove, and the chip electrode is bonded to the upper solder layer to form an electrical connection; S4, Perform the molding process at the molding layer location; S5 has a heat sink attached above the plastic seal layer.
[0013] The above-described solution of the present invention has the following beneficial effects: The high-heat dissipation high-power device packaging structure and preparation method provided by this invention achieve faster heat dissipation through the high thermal conductivity of the silicon carbide interlayer, which will greatly improve the working performance of the high-power device packaging structure. The high-power chip can dissipate heat quickly from multiple directions, especially downward heat dissipation to avoid heat accumulation. In addition, the high-power chip is electrically connected to the substrate, PCB, etc. through the silicon carbide through-hole of the silicon carbide interlayer. The silicon carbide interlayer itself also has sufficient hardness and thermal deformation rate that is relatively consistent with the chip, which further improves the reliability of the high-power device packaging structure. Other beneficial effects of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the overall structure of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a silicon carbide interposer unit according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the groove for processing the silicon carbide interposer layer in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of silicon carbide through-hole forming in the silicon carbide interposer layer according to Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the silicon carbide interposer layer fabrication in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of a GaN power chip package according to Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the molding process in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the heat sink packaging according to Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the overall structure of Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the overall structure of Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of the overall structure of Embodiment 4 of the present invention.
[0015] [Explanation of Labels in the Attached Image] 1-Silicon carbide interposer; 2-GaN power chip; 3-Lower solder layer; 4-Groove; 5-GaN power chip electrode; 6-Upper solder layer; 7-Silicon carbide via; 8-Plastic encapsulation layer; 9-Heat sink; 10-Heat sink solder layer; 11-U-shaped heat sink frame; 12-Frame solder layer; 13-Driver IC chip. Detailed Implementation
[0016] To make the technical problems, solutions, and advantages of this invention clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0017] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0018] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0019] Example 1: like Figure 1As shown, an embodiment of the present invention provides a high-heat-dissipation, high-power device packaging structure, including a silicon carbide interposer 1 and a high-power chip. This embodiment uses a GaN power chip 2 as an example, but other high-power chip packaging structures can also be applied. The GaN power chip 2 is packaged on the silicon carbide interposer 1, and the silicon carbide interposer 1 is then directly electrically connected to the substrate or PCB via a lower solder layer 3 or solder balls. The silicon carbide interposer 1 has a recess 4, and the GaN power chip 2 is disposed in the recess 4. The GaN power chip 2 is flip-chip mounted, meaning the GaN power chip electrode 5 is located below the GaN power chip 2 and is directly electrically connected to the upper solder layer 6 of the silicon carbide interposer 1.
[0020] Based on this configuration, the silicon carbide interposer 1 in this embodiment has silicon carbide vias 7, and the vias 7 are filled with copper dielectric to enable the GaN power chip 2 to be electrically connected to the substrate or PCB through the silicon carbide vias 7. The silicon carbide vias 7 are located at corresponding positions within the grooves, i.e., the silicon carbide vias 7 are positioned at the minimum thickness of the silicon carbide interposer 1, and penetrate the lower surface of the silicon carbide interposer 1 and the bottom surface of the groove. Therefore, when the GaN power chip 2 uses a flip-chip process, the GaN power chip electrode 5 can be directly soldered to the upper bonding layer 6 to form an electrical connection. It should be noted that the GaN power chip 2 has multiple electrodes, including a source (S), a drain (D), and a gate (G), all located on the front side of the GaN power chip 2. Therefore, in the flip-chip process, when only GaN power chip 2 needs to be packaged in the groove, the upper bonding layer 6 can be set for the source, drain, and gate electrodes to ensure that GaN power chip 2 can be packaged smoothly, and avoids excessive openings in the silicon carbide interposer 1, which would cause process complexity and reduced structural strength.
[0021] As described above, in the packaging structure provided by this embodiment, the lower surface (front side) of the GaN power chip 2 is in direct contact with the silicon carbide interposer 1. The silicon carbide interposer 1 itself is made of silicon carbide material, which has a thermal conductivity as high as 490 W / (m•K), higher than the 400 W / (m•K) of common thermally conductive material copper, thus possessing better heat dissipation capabilities. Therefore, the heat generated by the GaN power chip 2 can be directly conducted from below to the silicon carbide interposer 1, and then dissipated outward through the silicon carbide interposer 1, which has a larger heat dissipation area.
[0022] Meanwhile, the upper surface (back side) of the GaN power chip 2 does not require connection and can be directly protected by molding compound. Therefore, in this embodiment, a molding layer 8 is also provided above the silicon carbide interposer 1. The molding layer 8 is used to fill and protect the upper surface of the GaN power chip 2, the slot opening of the groove 4, and the interior. In addition, a heat sink 9 is provided above the molding layer 8. The heat sink 9 is attached to the upper surface of the molding layer 8 and is made of copper. The high thermal conductivity of copper allows heat to be quickly dissipated from the heat sink 9 into the environment. It is understood that under the action of temperature gradient, the heat generated by the GaN power chip 2 (especially the upper part) can also be conducted upward and dissipated through the molding layer 8 and the heat sink 9. Based on this, the thermal resistance of the molding layer 8 itself can also have a significant impact on the upward conduction of heat. When the molding compound uses materials such as organosilicon, its thermal conductivity is significantly improved compared to conventional molding compounds. It also has the characteristics of a wide temperature range and excellent insulation performance, and can be used for sealing and filling protection of the upper part of the package structure and auxiliary heat dissipation.
[0023] The heat generated on the side of the GaN power chip 2 can also be dissipated through the thermal conduction channel between it and the inner wall of the recess 4. In actual packaging, the size of the recess 4 is usually matched to the GaN power chip 2 or other high-power chips, so the thickness of the molding compound between the GaN power chip 2 and the inner wall of the recess 4 is very small. When a high thermal conductivity material is used for the molding compound, the lateral heat conduction effect of the GaN power chip 2 is also quite significant, which allows the heat to be quickly conducted to the silicon carbide interposer 1, and then dissipated through the silicon carbide interposer 1.
[0024] The present invention will be further described below by a specific preparation method, which includes the following steps: S1, using an insulating silicon carbide wafer to fabricate a silicon carbide interposer 1, where each silicon carbide interposer 1 unit on the silicon carbide wafer is as follows: Figure 2 As shown. The process for fabricating the silicon carbide interposer 1 is similar to that of a conventional silicon interposer, specifically: grooves 4 are etched into the silicon carbide interposer 1 (unit) using a chemical reaction or etching method, such as... Figure 3 As shown, a high aspect ratio silicon carbide through-hole 7 is then fabricated in the groove 4 by etching. Silicon dioxide is deposited on the inner wall of the silicon carbide through-hole 7 as an insulating layer, followed by the deposition of a diffusion barrier layer. Finally, copper is electroplated inside the silicon carbide through-hole 7 to complete the forming of the silicon carbide through-hole 7. Figure 4 As shown.
[0025] S2, the silicon carbide interposer 1 is thinned using chemical mechanical polishing to expose the end of the silicon carbide via 7. The upper solder layer 6 is fabricated first, followed by the lower solder layer 3. Figure 5 As shown.
[0026] S3, using flip-chip bonding or copper pillar bonding processes, the GaN power chip 2 is packaged in a recess, and the GaN power chip electrode 5 is welded to the upper solder layer 6 to form an electrical connection, such as... Figure 6 As shown.
[0027] S4, Perform the molding process at position 8 of the molding layer, such as Figure 7 As shown.
[0028] S5, attach a heat sink 9 above the molding layer 8 to obtain a high-heat-dissipation, high-power device packaging structure, such as... Figure 1 As shown.
[0029] Example 2: Considering that the thermal conductivity of molding compound is still significantly lower than that of metals such as copper, as a further improvement, based on Example 1, after completing the molding process, the molding compound on top of the GaN power chip 2 can be removed by a grinding process, such as... Figure 8 As shown. Because the depth of groove 4 was designed to match the height of GaN power chip 2, the upper surface of GaN power chip 2 can be flush with the upper surface of silicon carbide interposer 1. Then, as... Figure 9 As shown, a heat sink solder layer 10 is laid on the upper surface of the GaN power chip 2 (and the silicon carbide interposer 1), and then directly soldered to the heat sink 9 through the heat sink solder layer 10. This method reduces the upward thermal resistance of the GaN power chip 2, further improving the heat dissipation performance of the package structure. Furthermore, more heat from the sides of the GaN power chip 2 can be dissipated upwards and downwards.
[0030] Example 3: like Figure 10 As shown, considering the inherent technical challenges of first creating grooves in the silicon carbide interposer 1 and then fabricating the silicon carbide vias 7, this embodiment first directly fabricates a horizontally complete silicon carbide interposer 1. Then, silicon carbide vias 7 are fabricated in a predetermined area of the horizontally complete silicon carbide interposer 1. After completion, a U-shaped heat dissipation frame 11 matching the size of the silicon carbide interposer 1 is prepared. A frame solder layer 12 is fabricated at a predetermined position on the upper surface of the silicon carbide interposer 1, and then the U-shaped heat dissipation frame 11 is welded and fixed to the silicon carbide interposer 1. The U-shaped heat dissipation frame 11 can be made of materials such as copper. Finally, encapsulation with plastic molding and the heat sink 9 results in a simpler encapsulation structure for the silicon carbide vias 7. Alternatively, a grinding process can be performed as described in Embodiment 2, followed by the fabrication of the heat sink solder layer 10 to further improve heat dissipation performance.
[0031] Example 4: The main difference between Embodiment 4 of the present invention and Embodiments 1 and 3 is that a high-power chip and a low-power chip are simultaneously packaged within the groove 4 of the silicon carbide interposer 1 or at the center of the U-shaped heat dissipation frame 11. For example, when the high-power chip is a GaN power chip 2, the low-power chip can be a driver IC chip 13; when the high-power chip is a gallium oxide power chip 2, the low-power chip can be a driver IC chip 13; when the high-power chip is a SOC chip, the low-power chip can be a memory chip, etc. Simultaneously, the low-power chip can be vertically stacked to increase packaging density; for example, multiple memory chips can be vertically stacked to increase storage capacity. Correspondingly, the upper solder layer 6 within the groove 4 is configured one-to-one with the electrodes of the high-power chip and the electrodes of the lower low-power chip, enabling communication with the substrate or PCB through the silicon carbide vias 7 of the silicon carbide interposer 1.
[0032] In summary, the solutions provided in the above embodiments are all improvements made to the heat dissipation performance and process simplification of high-power device packaging structures. This allows the high-power chip in the fabricated high-power device packaging structure to dissipate heat rapidly from multiple directions, especially downward heat dissipation to avoid heat accumulation. The high thermal conductivity of the silicon carbide interposer 1 creates even faster heat dissipation, significantly improving the performance of the high-power device packaging structure. Furthermore, the high-power chip is electrically connected to the substrate, PCB, etc., through the silicon carbide through-holes 7 in the silicon carbide interposer 1. The silicon carbide interposer 1 itself also possesses sufficient hardness and a thermal deformation rate relatively consistent with the chip, further enhancing the reliability of the high-power device packaging structure.
[0033] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0034] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A high-heat-dissipation, high-power device packaging structure, characterized in that, This includes a silicon carbide interposer, a chip, a molding compound, and a heat sink. The silicon carbide interposer has a groove, and a silicon carbide through hole is provided in the groove. The silicon carbide through hole penetrates the lower surface of the silicon carbide interposer and the bottom surface of the groove. An upper solder layer and a lower solder layer are respectively provided at the ends of the silicon carbide through hole. The chip is disposed in the groove and the chip adopts flip-chip packaging. The chip electrode of the chip corresponds to the bottom of the groove. The chip electrode of the chip is electrically connected to the upper solder layer, and the lower solder layer is electrically connected to the substrate or PCB. The molding layer is disposed above the silicon carbide interlayer; The heat sink is disposed above the plastic seal layer and is made of metal.
2. The high-heat-dissipation, high-power device packaging structure according to claim 1, characterized in that, The chip includes a GaN power chip, a gallium oxide power chip, and a SOC chip.
3. The high-heat-dissipation, high-power device packaging structure according to claim 1, characterized in that, The dimensions of the groove are matched to those of the chip.
4. The high-heat-dissipation, high-power device packaging structure according to claim 1, characterized in that, The heat sink is made of copper.
5. The high-heat-dissipation, high-power device packaging structure according to claim 1, characterized in that, The molding compound is distributed on the upper surface of the silicon carbide interposer, the upper surface of the chip, the groove opening, and inside the groove.
6. The high-heat-dissipation, high-power device packaging structure according to claim 1, characterized in that, The molding compound is distributed on the upper surface of the silicon carbide interposer and inside the groove. A heat sink solder layer is provided on the upper surface of the chip, and the heat sink is connected to the chip through the heat sink solder layer.
7. A high-heat-dissipation, high-power device packaging structure, characterized in that, This includes a silicon carbide interposer, a heat dissipation frame, a chip, a molding compound, and a heat sink. A silicon carbide through-hole is provided in the central region of the silicon carbide interposer. The silicon carbide through-hole penetrates the lower and upper surfaces of the silicon carbide interposer. An upper solder layer and a lower solder layer are respectively provided at the ends of the silicon carbide through-hole. The heat dissipation frame is supported by a metal material, and the heat dissipation frame is connected to the upper surface of the silicon carbide interposer layer, and the silicon carbide through holes are aligned with the central area of the heat dissipation frame. The chip is disposed in the central area of the heat dissipation frame and is packaged in a flip-chip manner. The chip electrodes are electrically connected to the upper solder layer and the lower solder layer is electrically connected to the substrate or PCB. The molding layer is disposed above the silicon carbide interlayer; The heat sink is disposed above the plastic seal layer and is made of metal.
8. A method for fabricating a high-heat-dissipation, high-power device packaging structure, characterized in that, Includes the following steps: S1. An insulating silicon carbide wafer is used to fabricate a silicon carbide interposer. Grooves are etched into the silicon carbide interposer by chemical reaction or etching method. Silicon carbide vias are then fabricated in the grooves by etching method. Silicon dioxide is deposited on the inner wall of the silicon carbide via as an insulating layer. Then a diffusion barrier layer is deposited. Finally, copper is electroplated in the silicon carbide via to complete the formation of the silicon carbide via. S2, the silicon carbide interlayer is thinned by chemical mechanical polishing to expose the end of the silicon carbide through-hole, and the upper and lower solder layers are fabricated. S3, through flip-chip bonding or copper pillar bonding process, the chip is packaged in the groove, and the chip electrode is bonded to the upper solder layer to form an electrical connection; S4, Perform the molding process at the molding layer location; S5 has a heat sink attached above the plastic seal layer.