Electrical interconnect structure and method of forming the same, panel level package structure

Abstract

An electrical interconnection structure and a method for forming the same, and a panel level package structure, wherein the electrical interconnection structure comprises a plurality of first conductive structures and a plurality of second conductive structures; the first conductive structure comprises a plurality of first sub-conductive parts stacked in sequence; the second conductive structure comprises a plurality of second sub-conductive parts stacked in sequence; the first conductive structure and the second conductive structure have opposite deformation trends under external stress. By decomposing the first conductive structure and the second conductive structure into a plurality of first sub-conductive parts and a plurality of second sub-conductive parts stacked in sequence respectively, the height of the finally formed first conductive structure and the second conductive structure can be significantly improved. The first conductive structure and the second conductive structure have opposite deformation trends under external stress, effectively offsetting the warping deformation caused by a single structure layout, thereby significantly improving the overall flatness and long-term reliability of the electrical interconnection structure, and providing more excellent mechanical stability guarantee for high integration packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrical interconnect structure and its formation method, and a panel-level packaging structure. Background Technology

[0002] CoPoS (Chip-on-Panel-on-Substrate) is a next-generation advanced panel-level packaging technology. Its core innovation lies in replacing the traditional circular wafer as the interposer with a square panel, achieving a paradigm shift in manufacturing by "turning the circle into a square." This technology uses novel materials such as glass or sapphire to construct the redistribution layer, and forms a fine interconnect structure through panel-level photolithography and electroplating processes. This supports the integration of larger-sized multi-chips and effectively addresses the rapidly increasing demand for packaging area from AI chips.

[0003] In the interconnection between chips and panels, high-copper pillars play a crucial role as high-density interconnect interfaces pre-fabricated on the chip. They are formed during chip manufacturing by electroplating to create a three-dimensional structure with a significantly higher aspect ratio than traditional bumps, topped with a tin-silver alloy solder cap, enabling high-density flip-chip connections between the bare chip and the panel. High-copper pillars not only inherit the excellent electrical properties and mechanical reliability of copper, but also provide greater thermal cycling stress buffer space by increasing the pillar height, significantly reducing the risk of solder joint fatigue failure. Simultaneously, they meet the stringent requirements for power integrity and signal integrity in fine-pitch interconnect scenarios. This combination leverages the cost and size advantages of panel-level packaging while utilizing the enhanced characteristics of high-copper pillars to provide an efficient interconnect foundation for 2.5D / 3D integration and chip-to-chip architectures, becoming a mainstream development direction in high-performance computing and artificial intelligence accelerators.

[0004] However, the high copper pillars in the existing panel-level packaging structure still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an electrical interconnect structure and its formation method, as well as a panel-level packaging structure, which can improve the height of the conductive structure while resisting warping deformation.

[0006] To address the aforementioned problems, the present invention provides an electrical interconnect structure, comprising: a plurality of first conductive structures and a plurality of second conductive structures; wherein, the first conductive structure comprises a plurality of first sub-conductive portions stacked sequentially, any two adjacent first sub-conductive portions being in contact with each other, and the projected areas of any two adjacent first sub-conductive portions facing the stacking direction having an overlapping area; the second conductive structure comprises a plurality of second sub-conductive portions stacked sequentially, any two adjacent second sub-conductive portions being in contact with each other, and the projected areas of any two adjacent second sub-conductive portions facing the stacking direction having an overlapping area; the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress.

[0007] Optionally, along the stacking direction, in any two adjacent first sub-conductive parts of the first conductive structure, the projection area of ​​the upper first sub-conductive part toward the stacking direction is located within the projection area of ​​the lower first sub-conductive part toward the stacking direction; in any two adjacent second sub-conductive parts of the second conductive structure, the projection area of ​​the lower second sub-conductive part toward the stacking direction is located within the projection area of ​​the upper second sub-conductive part toward the stacking direction.

[0008] Optionally, the shape of the projection area of ​​the first sub-conductive part facing the stacking direction includes: a circle, a rectangle, or a polygon; the shape of the projection area of ​​the second sub-conductive part facing the stacking direction includes: a circle, a rectangle, or a polygon.

[0009] Optionally, when the shape of the projection area of ​​the first sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the first sub-conductive parts is in the range of 10 micrometers to 15 micrometers; when the shape of the projection area of ​​the second sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the second sub-conductive parts is in the range of 10 micrometers to 15 micrometers.

[0010] Optionally, along the stacking direction, the height range of the first conductive structure is greater than 380 micrometers; the height range of the second conductive structure is greater than 380 micrometers.

[0011] Optionally, along the stacking direction, the height range of the first sub-conductive part is 100 micrometers to 140 micrometers; the height range of the second sub-conductive part is 100 micrometers to 140 micrometers.

[0012] Optionally, the number of layers of the first sub-conductive part in the first conductive structure ranges from 2 to 6 layers; the number of layers of the second sub-conductive part in the second conductive structure ranges from 2 to 6 layers.

[0013] Optionally, along the stacking direction, each of the first sub-conductive parts in the first conductive structure is coaxially stacked; along the stacking direction, each of the second sub-conductive parts in the second conductive structure is coaxially stacked.

[0014] Optionally, it may also include: a molding compound layer that covers the sidewalls of the first conductive structure and the second conductive structure.

[0015] Optionally, the number and position of the first conductive structure and the second conductive structure are configured according to the stress equalization requirements.

[0016] Accordingly, the present invention also provides a method for forming an electrical interconnect structure, comprising: forming a plurality of first conductive structures and a plurality of second conductive structures; wherein, the first conductive structure comprises a plurality of first sub-conductive portions stacked sequentially, any two adjacent first sub-conductive portions being in contact with each other, and the projection areas of any two adjacent first sub-conductive portions toward the stacking direction having an overlapping area; the second conductive structure comprises a plurality of second sub-conductive portions stacked sequentially, any two adjacent second sub-conductive portions being in contact with each other, and the projection areas of any two adjacent second sub-conductive portions toward the stacking direction having an overlapping area; the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress.

[0017] Optionally, the method for forming the first conductive structure and the second conductive structure includes: providing a substrate; forming a seed material layer on the substrate; and forming sequentially stacked first sub-conductive portions and second sub-conductive portions by employing a plurality of photolithography electroplating processes; wherein each photolithography electroplating process forms one layer of the first sub-conductive portion and the second sub-conductive portion.

[0018] Optionally, the first photolithography electroplating process includes: forming a first photoresist layer on the seed material layer; exposing and developing the first photoresist layer to form a first via and a second via, the first via and the second via exposing the seed material layer; forming a first sub-conductive portion located at the bottom layer in the first via and forming a second sub-conductive portion located at the bottom layer in the second via using an electroplating process; and removing the first photoresist layer after forming the first sub-conductive portion and the second sub-conductive portion located at the bottom layer.

[0019] Optionally, each subsequent photolithography electroplating process includes: forming a second photoresist layer on the substrate, the second photoresist layer covering the formed first sub-conductive portion and the second sub-conductive portion; performing an exposure and development process on the second photoresist layer to form a third via and a fourth via, the third via exposing the formed first sub-conductive portion located on the upper layer, and the fourth via exposing the formed second sub-conductive portion located on the upper layer; forming the first sub-conductive portion in the third via and the second sub-conductive portion in the fourth via using an electroplating process; and removing the second photoresist layer after forming the first sub-conductive portion and the second sub-conductive portion.

[0020] Optionally, along the stacking direction, in any two adjacent first sub-conductive parts of the first conductive structure, the projection area of ​​the upper first sub-conductive part toward the stacking direction is located within the projection area of ​​the lower first sub-conductive part toward the stacking direction; in any two adjacent second sub-conductive parts of the second conductive structure, the projection area of ​​the lower second sub-conductive part toward the stacking direction is located within the projection area of ​​the upper second sub-conductive part toward the stacking direction.

[0021] Optionally, after forming the first conductive structure and the second conductive structure, the method further includes: forming a molding layer that covers the sidewalls of the first conductive structure and the second conductive structure.

[0022] Accordingly, the present invention also provides a panel-level packaging structure, comprising: an electrical interconnection structure as described in any of the above technical solutions, the electrical interconnection structure comprising a first side and a second side opposite to each other; a first rewiring layer located on the first side, the first rewiring layer being electrically connected to one end of the first conductive structure and the second conductive structure respectively; and a second rewiring layer located on the second side, the second rewiring layer being electrically connected to the other end of the first conductive structure and the second conductive structure opposite to each other.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages: In the electrical interconnect structure of this invention, the first conductive structure and the second conductive structure are respectively decomposed into multiple sequentially stacked first sub-conductive parts and second sub-conductive parts, thereby overcoming the process bottleneck of limited photoresist thickness in a single coating, and significantly increasing the height of the final first conductive structure and the second conductive structure. Any adjacent first sub-conductive parts are in contact with each other and their projected areas overlap, as are any adjacent second sub-conductive parts, ensuring electrical connectivity and structural stability between the interconnected first sub-conductive parts and between the second sub-conductive parts. The formed first conductive structure and the second conductive structure can meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits. Furthermore, the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress, creating a counterbalancing relationship that effectively offsets the warpage caused by a single structural layout, thereby significantly improving the overall flatness and long-term reliability of the electrical interconnect structure, and providing superior mechanical stability for high-integration packaging.

[0024] Furthermore, along the stacking direction, in any two adjacent first sub-conductive parts of the first conductive structure, the projection area of ​​the upper first sub-conductive part facing the stacking direction is located within the projection area of ​​the lower first sub-conductive part facing the stacking direction; similarly, in any two adjacent second sub-conductive parts of the second conductive structure, the projection area of ​​the lower second sub-conductive part facing the stacking direction is located within the projection area of ​​the upper second sub-conductive part facing the stacking direction. By designing the upper first sub-conductive part of the first conductive structure to be recessed within the projection area of ​​the lower first sub-conductive part, and the lower second sub-conductive part of the second conductive structure to be recessed within the projection area of ​​the upper second sub-conductive part, both structural designs effectively reduce the stringent requirements for photolithographic alignment accuracy, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0025] Furthermore, when the projection area of ​​the first sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the first sub-conductive parts is in the range of 10 micrometers to 15 micrometers; when the projection area of ​​the second sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the second sub-conductive parts is in the range of 10 micrometers to 15 micrometers. This 10-15 micrometer range ensures sufficient alignment tolerance space, reducing the stringent requirements for photolithography overlay accuracy and effectively lowering the process difficulty. It also avoids excessively large diameter reductions during the layer-by-layer stacking process, preventing a significant reduction in the size of the first sub-conductive part at the top layer, ensuring effective contact with external circuits and meeting electrical connection area requirements, preventing a surge in contact resistance or even connection failure. Simultaneously, it avoids excessively large diameter increases, preventing a significant increase in the size of the second sub-conductive part at the top layer, preventing encroachment on surrounding wiring space, effectively suppressing the risk of interlayer short circuits, and ensuring wiring density.

[0026] Furthermore, along the stacking direction, each of the first sub-conductive parts in the first conductive structure is coaxially stacked; and along the stacking direction, each of the second sub-conductive parts in the second conductive structure is coaxially stacked. By arranging each of the first and second sub-conductive parts coaxially along the stacking direction, the geometric centers of the multi-layer structure are completely coincident, ensuring uniform force transmission in each layer, avoiding lateral stress concentration and structural tilting risks caused by eccentric stacking, and significantly improving the overall mechanical stability and deformation resistance of the stack.

[0027] In the method for forming the electrical interconnect structure of the present invention, the first conductive structure and the second conductive structure are respectively decomposed into multiple sequentially stacked first sub-conductive parts and second sub-conductive parts, thereby overcoming the process bottleneck of limited photoresist thickness in a single coating, and significantly increasing the height of the final first conductive structure and the second conductive structure. Any adjacent first sub-conductive parts are in contact with each other and their projected areas overlap, as are any adjacent second sub-conductive parts, thereby ensuring electrical connectivity and structural stability between the interconnected first sub-conductive parts and between the second sub-conductive parts. The formed first conductive structure and the second conductive structure can meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits. Furthermore, the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress, creating a counterbalancing relationship between them, effectively offsetting the warpage caused by a single structural layout, thereby significantly improving the overall flatness and long-term reliability of the electrical interconnect structure, and providing superior mechanical stability for high-integration packaging. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a tall copper column structure; Figures 2 to 9 This is a schematic diagram of the steps in the method for forming the electrical interconnect structure according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the panel-level packaging structure according to an embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, the high copper pillars in existing panel-level packaging structures still present numerous problems. These will be explained in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of a tall copper column structure.

[0031] Please refer to Figure 1 Currently, the fabrication of high copper pillars 100 in panel-level packaging structures mainly employs traditional semiconductor processes such as photoresist coating, photolithography, electroplating, resist stripping, and etching, followed by height measurement using a 3D height measuring machine. However, this conventional process has significant limitations. The industry's ability to coat photoresist in a single pass is limited, and the resulting high copper pillars 100 cannot directly achieve a height of over 200 micrometers, making it difficult to meet the ever-increasing demand for stacking height. As the size of large-scale integrated circuits and very large-scale integrated circuits continues to increase, the height requirements for high copper pillars 100 continue to rise, and existing single-layer fabrication technologies can no longer meet the future packaging needs for higher integration.

[0032] Based on this, the present invention provides an electrical interconnect structure and its formation method, as well as a panel-level packaging structure. By decomposing the first conductive structure and the second conductive structure into multiple sequentially stacked first sub-conductive parts and second sub-conductive parts, the process bottleneck of limited photoresist thickness in a single coating is overcome, allowing for a significant increase in the height of the final first and second conductive structures. Any adjacent first sub-conductive parts are in contact with each other and their projected areas overlap, as are any adjacent second sub-conductive parts, ensuring electrical connectivity and structural stability between the interconnected first and second sub-conductive parts. The formed first and second conductive structures can meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits. Furthermore, the first and second conductive structures exhibit opposite deformation trends under external stress, creating a counterbalancing relationship that effectively offsets warpage caused by a single structural layout. This significantly improves the overall flatness and long-term reliability of the electrical interconnect structure, providing superior mechanical stability for high-integration packaging.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 2 to 9 This is a schematic diagram of the steps in the method for forming the electrical interconnect structure according to an embodiment of the present invention.

[0035] A plurality of first conductive structures and a plurality of second conductive structures are formed. Each first conductive structure comprises a plurality of first sub-conductive parts stacked sequentially, with any two adjacent first sub-conductive parts in contact with each other, and the projected areas of any two adjacent first sub-conductive parts facing the stacking direction overlapping. Each second conductive structure comprises a plurality of second sub-conductive parts stacked sequentially, with any two adjacent second sub-conductive parts in contact with each other, and the projected areas of any two adjacent second sub-conductive parts facing the stacking direction overlapping. The first and second conductive structures exhibit opposite deformation trends under external stress. For details of the formation process, please refer to [reference needed]. Figures 2 to 8 .

[0036] Please refer to Figure 2 Substrate 200 is provided.

[0037] In this embodiment, the substrate 200 uses a rectangular shape as the basic support platform for subsequent process technologies. Unlike the circular silicon wafers used in traditional wafer-level packaging, the rectangular shape of the substrate 200 is specifically designed for the requirements of CoPoS (Chip-on-Panel-on-Substrate) processes, facilitating efficient production of large-area panel-level packaging. The substrate 200 provides stable mechanical support and process reference during the fabrication of the first and second conductive structures. After the high-copper pillars are fabricated, the substrate 200 is removed, allowing the formed first and second conductive structures to be directly integrated into the target package structure.

[0038] Please refer to Figure 3 A seed material layer 201 is formed on the substrate 200.

[0039] In this embodiment, the seed material layer 201 is typically formed on the surface of the substrate 200 using a physical vapor deposition process, forming a titanium-copper composite structure as a conductive substrate for subsequent electroplating processes. The seed material layer 201 has good conductivity and adhesion, providing a uniform current distribution path for the electrochemical reaction and ensuring selective deposition of electroplated metal in designated areas.

[0040] After forming the seed material layer 201, the first and second sub-conductive portions located on the bottom layer are formed using a first photolithography electroplating process. Please refer to [link / reference needed] for the specific formation process. Figures 4 to 6 .

[0041] Please refer to Figure 4A first photoresist layer 202 is formed on the seed material layer 201; the first photoresist layer 202 is exposed and developed to form a first through hole 203 and a second through hole 204, the first through hole 203 and the second through hole 204 exposing the seed material layer 201.

[0042] In this embodiment, the first photoresist layer 202 is uniformly coated onto the surface of the seed material layer 201 by spin coating or spray coating, and a dense photosensitive film is formed after solvent removal by soft baking. The first photoresist layer 202 serves as a medium for pattern transfer, forming the first through-hole 203 and the second through-hole 204 with specific morphologies after exposure and development, precisely defining the deposition areas of the first sub-conductive portion and the second sub-conductive portion located on the bottom layer, and realizing selective growth of electroplated metal.

[0043] Please refer to Figure 5 An electroplating process is used to form a first sub-conductive portion 205 located at the bottom layer in the first through hole 203, and a second sub-conductive portion 206 located at the bottom layer in the second through hole 204.

[0044] In this embodiment, an electroplating process is used to deposit metal material in the first through hole 203 and the second through hole 204. By controlling the current density and electroplating time, metal ions are reduced and deposited on the exposed surface of the seed material layer 201, filling the first through hole 203 and the second through hole 204 from bottom to top to form the first sub-conductive portion 205 and the second sub-conductive portion 206 located at the bottom layer.

[0045] Please refer to Figure 6 After forming the first sub-conductive portion 205 and the second sub-conductive portion 206 located on the bottom layer, the first photoresist layer 202 is removed.

[0046] In this embodiment, after the first sub-conductive portion 205 and the second sub-conductive portion 206 located at the bottom layer are electroplated, the first photoresist layer 202 is removed by a photoresist removal process, exposing the first sub-conductive portion 205 and the second sub-conductive portion 206 at the bottom layer. The seed material layer 201 is still retained and continues to serve as the conductive substrate for subsequent electroplating processes.

[0047] Please refer to Figure 7 After the first photolithography electroplating process, several more photolithography electroplating processes are used to sequentially form the remaining stacked first sub-conductive portions 205 and second sub-conductive portions 206.

[0048] In this embodiment, each subsequent photolithography electroplating process includes: forming a second photoresist layer on the substrate 200, the second photoresist layer covering the already formed first sub-conductive portion 205 and second sub-conductive portion 206; performing an exposure and development process on the second photoresist layer to form a third through-hole and a fourth through-hole, the third through-hole exposing the already formed and upper-layer first sub-conductive portion 205, and the fourth through-hole exposing the already formed and upper-layer second sub-conductive portion 206; using an electroplating process to form the first sub-conductive portion 205 in the third through-hole and the second sub-conductive portion 206 in the fourth through-hole; and after forming the first sub-conductive portion 205 and the second sub-conductive portion 206, removing the second photoresist layer (not shown).

[0049] In this embodiment, the stacking direction is the surface normal direction of the substrate 200.

[0050] In this embodiment, the specific operation process of photoresist layer formation and removal, as well as electroplating deposition, involved in each subsequent photolithography electroplating process can refer to the process of the first photolithography electroplating process, and will not be repeated here.

[0051] Along the stacking direction, the height of the first sub-conductive part 205 ranges from 100 micrometers to 140 micrometers; the number of layers of the first sub-conductive part 205 in the first conductive structure ranges from 2 to 6 layers; along the stacking direction, the height of the second sub-conductive part 206 ranges from 100 micrometers to 140 micrometers; the number of layers of the first sub-conductive part 205 in the second conductive structure ranges from 2 to 6 layers.

[0052] In this embodiment, each photolithography electroplating process forms one layer of the first sub-conductive portion 205 and the second sub-conductive portion 206. Taking four layers of the first sub-conductive portion 205 and the second sub-conductive portion 206 as an example, four photolithography electroplating processes are required. The height of the first sub-conductive portion 205 and the second sub-conductive portion 206 is 120 micrometers each time.

[0053] In this embodiment, the first sub-conductive part 205 and the second sub-conductive part 206 are made of copper.

[0054] In this embodiment, the height range of the first conductive structure and the second conductive structure along the stacking direction is greater than 380 micrometers.

[0055] In this embodiment, along the stacking direction, in any two adjacent first sub-conductive parts 205 of the first conductive structure, the projection area of ​​the upper first sub-conductive part 205 toward the stacking direction is located within the projection area of ​​the lower first sub-conductive part 205 toward the stacking direction; in any two adjacent second sub-conductive parts 206 of the second conductive structure, the projection area of ​​the lower second sub-conductive part 206 toward the stacking direction is located within the projection area of ​​the upper second sub-conductive part 206 toward the stacking direction.

[0056] By incorporating the upper first sub-conductive portion 205 of the first conductive structure into the projection range of the lower first sub-conductive portion 205, and the lower second sub-conductive portion 206 of the second conductive structure into the projection range of the upper second sub-conductive portion 206, both structural designs can effectively reduce the stringent requirements on photolithography alignment accuracy, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0057] In this embodiment, the projection area of ​​the first sub-conductive part 205 facing the stacking direction is circular, and the diameter difference between any two adjacent circular projections of the first sub-conductive parts 205 is in the range of 10 micrometers to 15 micrometers; the projection area of ​​the second sub-conductive part 206 facing the stacking direction is also circular, and the diameter difference between any two adjacent circular projections of the second sub-conductive parts 206 is in the range of 10 micrometers to 15 micrometers. This 10-15 micrometer range ensures sufficient alignment tolerance space, reducing the stringent requirements for photolithography overlay accuracy and effectively reducing process difficulty. It also avoids excessively large diameter reductions during the layer-by-layer stacking process, preventing a significant reduction in the size of the top-layer first sub-conductive part 205, ensuring effective contact with external circuits and meeting electrical connection area requirements, preventing a surge in contact resistance or even connection failure. Simultaneously, it avoids excessively large diameter increases, preventing significant encroachment on surrounding wiring space, effectively suppressing the risk of interlayer short circuits and ensuring wiring density.

[0058] In other embodiments, the shape of the projection area of ​​the first sub-conductive part and the second sub-conductive part toward the stacking direction may also include: rectangle or polygon, specifically such as regular pentagon or regular hexagon.

[0059] In this embodiment, along the stacking direction, each of the first sub-conductive parts 205 in the first conductive structure is coaxially stacked; along the stacking direction, each of the second sub-conductive parts 206 in the second conductive structure is coaxially stacked. By arranging each of the first sub-conductive parts 205 and the second sub-conductive parts 206 coaxially along the stacking direction, the geometric centers of the multi-layer structure are completely coincident, ensuring uniform force transmission in each layer, avoiding lateral stress concentration and structural tilting risks caused by eccentric stacking, and significantly improving the overall mechanical stability and deformation resistance of the stack.

[0060] Thus, the fabrication of the first conductive structure and the second conductive structure is completed. By decomposing the first conductive structure and the second conductive structure into multiple sequentially stacked first sub-conductive portions 205 and second sub-conductive portions 206, the process bottleneck of limited photoresist thickness in a single coating is overcome, allowing for a significant increase in the height of the final first conductive structure and the second conductive structure. Any adjacent first sub-conductive portions 205 are in contact with each other and their projected areas overlap, as are any adjacent second sub-conductive portions 206, ensuring electrical connectivity and structural stability between the interconnected first sub-conductive portions 205 and the second sub-conductive portions 206. The formed first conductive structure and the second conductive structure can meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits. Furthermore, the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress, creating a counterbalancing relationship that effectively offsets the warpage caused by a single structural layout. This significantly improves the overall flatness and long-term reliability of the electrical interconnect structure, providing superior mechanical stability for high-integration packaging.

[0061] In this embodiment, the number and position of the first conductive structure and the second conductive structure are configured according to the stress equalization requirements.

[0062] Specifically, in some implementation scenarios, the first and second conductive structures are configured symmetrically, meaning they are arranged in a mirror-symmetrical manner with the center line as a reference, with equal numbers and spaced apart. When external stress is applied to this structure, the two symmetrically distributed conductive structures undergo deformations of equal magnitude and opposite directions. These deformation trends cancel each other out in the central region, effectively suppressing overall warping. This configuration is particularly suitable for areas requiring high flatness, ensuring the long-term reliability of electrical interconnects through a balanced stress distribution.

[0063] In some implementation scenarios, the first and second conductive structures can also be configured in a gradient distribution. The number and spatial density of the first and second conductive structures can be flexibly adjusted according to the differences in stress concentration in different regions of the structure. In edge regions with severe stress concentration, the distribution density of the first or second conductive structures can be appropriately increased to achieve gradual stress release and balanced transition through local reinforcement. In the central region where stress is relatively mild, the total number or distribution density of the first and second conductive structures can be reduced to optimize space utilization. This gradient configuration allows for adaptive design based on specific thermomechanical characteristics, achieving a better balance between stress equalization and process complexity, making it suitable for packaging scenarios with non-uniform thermal distribution or complex geometries.

[0064] Please refer to Figure 8 After the first conductive structure and the second conductive structure are formed, a molding layer 207 is formed, which covers the sidewalls of the first conductive structure and the second conductive structure.

[0065] In this embodiment, the molding compound 207 is made of epoxy resin, which is applied to the substrate 200 through coating or injection molding to cover the first conductive structure and the second conductive structure. Subsequently, the molding compound 207 is ground to gradually remove the surface material until the end surfaces of the first and second conductive structures are exposed, forming a smooth molding compound 207. Epoxy resin has good insulation, adhesion, and process compatibility, and after grinding, it can achieve high coplanarity with the surfaces of the first and second conductive structures.

[0066] Please refer to Figure 9 After the molding layer 207 is formed, the substrate 200 and the seed material layer 201 are removed.

[0067] In this embodiment, the removal of the substrate 200 can be achieved by a debonding process, that is, by separating the temporarily bonded substrate 200 through thermal, optical or mechanical means, while the removal of the seed material layer 201 can be achieved by etching or grinding processes.

[0068] Accordingly, this invention also provides an electrical interconnection structure, please refer to the following embodiments. Figure 9The system includes: a plurality of first conductive structures and a plurality of second conductive structures; wherein, the first conductive structure includes a plurality of first sub-conductive parts 205 stacked sequentially, any two adjacent first sub-conductive parts 205 are in contact with each other, and the projection areas of any two adjacent first sub-conductive parts 205 toward the stacking direction have an overlapping area; the second conductive structure includes a plurality of second sub-conductive parts 206 stacked sequentially, any two adjacent second sub-conductive parts 206 are in contact with each other, and the projection areas of any two adjacent second sub-conductive parts 206 toward the stacking direction have an overlapping area; the first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress.

[0069] By decomposing the first and second conductive structures into multiple sequentially stacked first sub-conductive portions 205 and second sub-conductive portions 206, the process bottleneck of limited photoresist thickness in a single coating is overcome, significantly increasing the height of the final first and second conductive structures. Any adjacent first sub-conductive portions 205 are in contact with each other and their projected areas overlap, as are any adjacent second sub-conductive portions 206, ensuring electrical connectivity and structural stability between the interconnected first sub-conductive portions 205 and second sub-conductive portions 206. The resulting first and second conductive structures meet the design requirements of large-scale integrated circuits and very large-scale integrated circuits. Furthermore, the first and second conductive structures exhibit opposite deformation trends under external stress, creating a counterbalancing relationship that effectively offsets warpage caused by a single structural layout. This significantly improves the overall flatness and long-term reliability of the electrical interconnect structure, providing superior mechanical stability for high-integration packaging.

[0070] In this embodiment, along the stacking direction, in any two adjacent first sub-conductive portions 205 of the first conductive structure, the projection area of ​​the upper first sub-conductive portion 205 facing the stacking direction is located within the projection area of ​​the lower first sub-conductive portion 205 facing the stacking direction; similarly, in any two adjacent second sub-conductive portions 206 of the second conductive structure, the projection area of ​​the lower second sub-conductive portion 206 facing the stacking direction is located within the projection area of ​​the upper second sub-conductive portion 206 facing the stacking direction. By designing the upper first sub-conductive portion 205 in the first conductive structure to be recessed within the projection area of ​​the lower first sub-conductive portion 205, and the lower second sub-conductive portion 206 in the second conductive structure to be recessed within the projection area of ​​the upper second sub-conductive portion 206, both structural designs effectively reduce the stringent requirements for photolithographic alignment accuracy, thereby relaxing the control window for overlay accuracy and significantly improving the tolerance for alignment errors during multilayer stacking.

[0071] Along the stacking direction, the height of the first sub-conductive part 205 ranges from 100 micrometers to 140 micrometers; the number of layers of the first sub-conductive part 205 in the first conductive structure ranges from 2 to 6 layers; along the stacking direction, the height of the second sub-conductive part 206 ranges from 100 micrometers to 140 micrometers; the number of layers of the first sub-conductive part 205 in the second conductive structure ranges from 2 to 6 layers.

[0072] In this embodiment, the first sub-conductive part 205 and the second sub-conductive part 206 are made of copper.

[0073] In this embodiment, the height range of the first conductive structure and the second conductive structure along the stacking direction is greater than 380 micrometers.

[0074] In this embodiment, the projection area of ​​the first sub-conductive part 205 facing the stacking direction is circular, and the diameter difference between any two adjacent circular projections of the first sub-conductive parts 205 is in the range of 10 micrometers to 15 micrometers; the projection area of ​​the second sub-conductive part 206 facing the stacking direction is also circular, and the diameter difference between any two adjacent circular projections of the second sub-conductive parts 206 is in the range of 10 micrometers to 15 micrometers. This 10-15 micrometer range ensures sufficient alignment tolerance space, reducing the stringent requirements for photolithography overlay accuracy and effectively reducing process difficulty. It also avoids excessively large diameter reductions during the layer-by-layer stacking process, preventing a significant reduction in the size of the top-layer first sub-conductive part 205, ensuring effective contact with external circuits and meeting electrical connection area requirements, preventing a surge in contact resistance or even connection failure. Simultaneously, it avoids excessively large diameter increases, preventing significant encroachment on surrounding wiring space, effectively suppressing the risk of interlayer short circuits and ensuring wiring density.

[0075] In other embodiments, the shape of the projection area of ​​the first sub-conductive part and the second sub-conductive part toward the stacking direction may also include: rectangle or polygon, specifically such as regular pentagon or regular hexagon.

[0076] In this embodiment, along the stacking direction, each of the first sub-conductive parts 205 in the first conductive structure is coaxially stacked; along the stacking direction, each of the second sub-conductive parts 206 in the second conductive structure is coaxially stacked. By arranging each of the first sub-conductive parts 205 and the second sub-conductive parts 206 coaxially along the stacking direction, the geometric centers of the multi-layer structure are completely coincident, ensuring uniform force transmission in each layer, avoiding lateral stress concentration and structural tilting risks caused by eccentric stacking, and significantly improving the overall mechanical stability and deformation resistance of the stack.

[0077] In this embodiment, it further includes a molding layer 207, which covers the sidewalls of the first conductive structure and the second conductive structure.

[0078] Figure 10 This is a schematic diagram of the panel-level packaging structure according to an embodiment of the present invention.

[0079] Please refer to Figure 10The present invention also provides a panel-level packaging structure, comprising: an electrical interconnection structure as described in any of the above embodiments, the electrical interconnection structure comprising a first side and a second side opposite to each other; a first redistribution layer 300 located on the first side, the first redistribution layer 300 being electrically connected to one end of the first conductive structure and the second conductive structure respectively; and a second redistribution layer 301 located on the second side, the second redistribution layer 301 being electrically connected to the other end opposite to the first conductive structure and the second conductive structure respectively.

[0080] In this embodiment, the panel-level packaging structure integrates the aforementioned electrical interconnect structure to form a through-type vertical conductive channel. The electrical interconnect structure has opposing first and second sides. The first side has a first rewiring layer 300 that is electrically connected to one end of both the first and second conductive structures. The second side has a second rewiring layer 301 that is electrically connected to the other end of both the first and second conductive structures. This double-sided rewiring design enables electrical interconnection between the upper and lower surfaces of the packaging structure. The first and second conductive structures act as high-density interconnect bridges, effectively shortening the signal transmission path, improving packaging integration and electrical performance, and meeting the stringent requirements of high bandwidth and low loss for the panel-level packaging.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrical interconnection structure, characterized in that, include: Several first conductive structures and several second conductive structures; wherein, The first conductive structure includes a plurality of first sub-conductive parts stacked sequentially, any two adjacent first sub-conductive parts are in contact with each other, and the projection areas of any two adjacent first sub-conductive parts toward the stacking direction have an overlapping area. The second conductive structure includes a plurality of second sub-conductive parts stacked sequentially, any two adjacent second sub-conductive parts are in contact with each other, and the projection areas of any two adjacent second sub-conductive parts toward the stacking direction have an overlapping area. The first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress.

2. The electrical interconnection structure as described in claim 1, characterized in that, Along the stacking direction, in any two adjacent first sub-conductive parts in the first conductive structure, the projection area of ​​the upper first sub-conductive part toward the stacking direction is located within the projection area of ​​the lower first sub-conductive part toward the stacking direction; in any two adjacent second sub-conductive parts in the second conductive structure, the projection area of ​​the lower second sub-conductive part toward the stacking direction is located within the projection area of ​​the upper second sub-conductive part toward the stacking direction.

3. The electrical interconnection structure as described in claim 1, characterized in that, The shape of the projection area of ​​the first sub-conductive part facing the stacking direction includes: a circle, a rectangle, or a polygon; the shape of the projection area of ​​the second sub-conductive part facing the stacking direction includes: a circle, a rectangle, or a polygon.

4. The electrical interconnection structure as described in claim 2, characterized in that, When the shape of the projection area of ​​the first sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the first sub-conductive parts is in the range of 10 micrometers to 15 micrometers; when the shape of the projection area of ​​the second sub-conductive part facing the stacking direction is circular, the diameter difference between any two adjacent circular projections of the second sub-conductive parts is in the range of 10 micrometers to 15 micrometers.

5. The electrical interconnection structure as described in claim 1, characterized in that, Along the stacking direction, the height of the first conductive structure is greater than 380 micrometers; the height of the second conductive structure is greater than 380 micrometers.

6. The electrical interconnection structure as described in claim 1, characterized in that, Along the stacking direction, the height range of the first sub-conductive part is 100 micrometers to 140 micrometers; the height range of the second sub-conductive part is 100 micrometers to 140 micrometers.

7. The electrical interconnection structure as described in claim 1, characterized in that, The number of layers of the first sub-conductive part in the first conductive structure ranges from 2 to 6 layers; the number of layers of the second sub-conductive part in the second conductive structure ranges from 2 to 6 layers.

8. The electrical interconnection structure as described in claim 1, characterized in that, Along the stacking direction, each of the first sub-conductive parts in the first conductive structure is coaxially stacked; along the stacking direction, each of the second sub-conductive parts in the second conductive structure is coaxially stacked.

9. The electrical interconnection structure as described in claim 1, characterized in that, Also includes: A molding compound that covers the sidewalls of the first conductive structure and the second conductive structure.

10. The electrical interconnection structure as claimed in claim 1, characterized in that, The number and position of the first conductive structure and the second conductive structure are configured according to the stress equalization requirements.

11. A method for forming an electrical interconnect structure, characterized in that, include: Several first conductive structures and several second conductive structures are formed; wherein, The first conductive structure includes a plurality of first sub-conductive parts stacked sequentially, any two adjacent first sub-conductive parts are in contact with each other, and the projection areas of any two adjacent first sub-conductive parts toward the stacking direction have an overlapping area. The second conductive structure includes a plurality of second sub-conductive parts stacked sequentially, any two adjacent second sub-conductive parts are in contact with each other, and the projection areas of any two adjacent second sub-conductive parts toward the stacking direction have an overlapping area. The first conductive structure and the second conductive structure exhibit opposite deformation trends under external stress.

12. The method for forming an electrical interconnect structure as described in claim 11, characterized in that, The method for forming the first conductive structure and the second conductive structure includes: providing a substrate; forming a seed material layer on the substrate; and forming sequentially stacked first sub-conductive portions and second sub-conductive portions by employing a plurality of photolithography electroplating processes; wherein each photolithography electroplating process forms one layer of the first sub-conductive portion and the second sub-conductive portion.

13. The method for forming the electrical interconnect structure as described in claim 12, characterized in that, The first photolithography electroplating process includes: forming a first photoresist layer on the seed material layer; exposing and developing the first photoresist layer to form a first through-hole and a second through-hole, wherein the first through-hole and the second through-hole expose the seed material layer; forming a first sub-conductive portion located at the bottom layer in the first through-hole and forming a second sub-conductive portion located at the bottom layer in the second through-hole using an electroplating process; and removing the first photoresist layer after forming the first sub-conductive portion and the second sub-conductive portion located at the bottom layer.

14. The method for forming the electrical interconnect structure as described in claim 13, characterized in that, Each subsequent photolithography electroplating process includes: forming a second photoresist layer on the substrate, the second photoresist layer covering the formed first sub-conductive portion and the second sub-conductive portion; exposing and developing the second photoresist layer to form a third via and a fourth via, the third via exposing the formed first sub-conductive portion located on the upper layer, and the fourth via exposing the formed second sub-conductive portion located on the upper layer; forming the first sub-conductive portion in the third via and the second sub-conductive portion in the fourth via using an electroplating process; and removing the second photoresist layer after forming the first sub-conductive portion and the second sub-conductive portion.

15. The method for forming an electrical interconnect structure as described in claim 11, characterized in that, Along the stacking direction, in any two adjacent first sub-conductive parts in the first conductive structure, the projection area of ​​the upper first sub-conductive part toward the stacking direction is located within the projection area of ​​the lower first sub-conductive part toward the stacking direction; in any two adjacent second sub-conductive parts in the second conductive structure, the projection area of ​​the lower second sub-conductive part toward the stacking direction is located within the projection area of ​​the upper second sub-conductive part toward the stacking direction.

16. The method for forming an electrical interconnect structure as described in claim 11, characterized in that, After forming the first conductive structure and the second conductive structure, the method further includes: forming a molding layer that covers the sidewalls of the first conductive structure and the second conductive structure.

17. A panel-level packaging structure, characterized in that, include: The electrical interconnect structure according to any one of claims 1 to 10, wherein the electrical interconnect structure includes opposing first and second sides; A first rewiring layer is located on the first side, and the first rewiring layer is electrically connected to one end of the first conductive structure and one end of the second conductive structure, respectively. The second wiring layer is located on the second side and is electrically connected to the other end of the first conductive structure and the second conductive structure, respectively.

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