Fan-out chip stack package structure and processing method thereof

Abstract

The application provides a fan-out chip stack packaging structure and a manufacturing method thereof. In the fan-out chip stack packaging structure, a second chip and a second heat sink are stacked on the back side of a first chip, the front side of the second chip faces away from the first chip, the second chip at least partially overlaps the first heat sink, the first chip at least partially overlaps the second heat sink, the first heat sink and the second heat sink each comprise a metal heat conduction structure and a plastic sealing material for plastic sealing the metal heat conduction structure, a first re-wiring layer is electrically connected to the front side of the second chip and contacts the metal heat conduction structure of the second heat sink, and a second re-wiring layer is electrically connected to the front side of the first chip and contacts the metal heat conduction structure of the first heat sink. In this way, the first heat sink and the second heat sink serve as double-sided heat sinks, which helps to improve the heat dissipation effect of the chips in the packaging structure. The manufacturing method of the fan-out chip stack can be used to manufacture the above-mentioned fan-out chip stack packaging structure.

Description

Technical Field

[0001] This invention relates to the field of packaging technology, and in particular to a fan-out type chip stacking packaging structure and its processing method. Background Technology

[0002] In board-level fan-out packaging, when fabricating the chip stacking package structure, two layers of chips are usually bonded together on the back. Figures 1 to 6 This is a step-by-step schematic diagram of a fabrication method for a board-level fan-out package structure. The fabrication method for this board-level fan-out package structure includes the following steps: Figure 1 As shown, attach the front-side chip 1 face down onto the carrier board 2; as... Figure 2 As shown, the reverse chip 3 is pasted onto the back of the front chip 1 with its front side facing up. Both the front chip 1 and the reverse chip 3 have chip pads or bumps on their front sides. Figure 3 As shown, a molding compound 4 is formed on the carrier 2, which encapsulates the front chip 1 and the back chip 3; as Figure 4 As shown, a TMV via structure 5 is fabricated in the molding compound 4. The TMV via structure 5 includes a via penetrating the molding compound 4 and a metal layer covering the sidewalls of the via; the carrier board 2 is removed to expose the chip pads or bumps on the front side of the chip 1; as shown. Figure 5 As shown, a front wiring layer 6 is formed on one side of the front side of the front chip 1, and the front wiring layer 6 is electrically connected to the front chip 1; a plastic encapsulation protective layer 7 is formed on one side of the front side of the front chip 1 to protect the front wiring layer 6; as shown Figure 6 As shown, a reverse redistribution layer 8 is formed on the front side of the reverse chip 3. The reverse redistribution layer 8 is electrically connected to the reverse chip 3. The reverse redistribution layer 8 is interconnected with the front redistribution layer 6 through the TMV via structure 5.

[0003] While the chip stacking method described above can reduce the overall package size and achieve the required stacking structure, the back sides of the two chips are completely bonded together. The heat dissipation channels are limited to the pads on the front of the chips and the redistribution layer connected to the chips. This limited heat dissipation channel prevents effective heat dissipation from the chip substrates, leading to heat accumulation. If the chip load power is too high, excessive heat generation will result in heat buildup, affecting chip lifespan. Furthermore, the TMV via structure 5 in the above solution is fabricated after molding, making its fabrication difficult. Due to the fabrication difficulty, the overall depth of the TMV via structure 5 cannot support excessive package thickness, and the interior of the TMV via structure 5 cannot be filled with copper, only allowing for copper plating on the via walls, resulting in poor conductivity and heat dissipation. Summary of the Invention

[0004] One of the objectives of this invention is to improve the heat dissipation effect of chips in fan-out chip stacking packaging structures.

[0005] To achieve the above objectives, the present invention provides a fan-out chip stacking package structure. The fan-out chip stacking package structure includes: a first chip; a first heat sink located on the side of the first chip; a first molding compound layer covering at least the sidewalls of the first chip and the first heat sink; a second chip and a second heat sink stacked on the back side of the first chip, with the front side of the second chip facing away from the first chip, the second chip and the first heat sink at least partially overlapping, and both the first and second heat sinks include a metal thermally conductive structure and a molding compound material encapsulating the metal thermally conductive structure; a second molding compound layer connected to the first molding compound layer and covering at least the sidewalls of the second chip and the second heat sink; a first redistribution layer located on the front side of the second chip and electrically connected to the front side of the second chip, the first redistribution layer contacting the metal thermally conductive structure of the second heat sink; and a second redistribution layer located on the front side of the first chip and electrically connected to the front side of the first chip, the second redistribution layer contacting the metal thermally conductive structure of the first heat sink.

[0006] Optionally, the fan-out chip stacked package structure further includes: a first interconnect located in the first molding compound; and a second interconnect located in the second molding compound and corresponding to the position of the first interconnect; wherein the first interconnect and the second interconnect both include a conductive structure and an insulating material that isolates the conductive structure, one end of the conductive structure of the first interconnect is electrically connected to one end of the conductive structure of the second interconnect, the other end of the conductive structure of the first interconnect is electrically connected to the second redistribution layer, and the other end of the conductive structure of the second interconnect is electrically connected to the first redistribution layer.

[0007] Optionally, a metal interconnect layer is provided between the first molding layer and the second molding layer. The metal interconnect layer includes a first metal pad and a second metal pad. The first chip and the first heat sink are located on one side surface of the first metal pad, and the second chip and the second heat sink are located on the other side surface of the first metal pad. The second metal pad is located between the conductive structures of the first interconnect and the second interconnect.

[0008] Optionally, the first metal pad is in direct contact with the back of the first chip and the metal thermally conductive structure of the first heat sink, and the back of the second chip and the metal thermally conductive structure of the second heat sink are in direct contact with the first metal pad.

[0009] Optionally, an insulating thermally conductive adhesive is provided between the back of the first chip and the first metal pad, and / or, an insulating thermally conductive adhesive is provided between the back of the second chip and the first metal pad.

[0010] Optionally, the first heat sink is electrically insulated from the second chip, and the second heat sink is electrically insulated from the first chip.

[0011] Optionally, the first redistribution layer includes a first thermal pad, the second redistribution layer includes a second thermal pad, the metal thermally conductive structure of the first heat sink is in contact with the second thermal pad, and the metal thermally conductive structure of the second heat sink is in contact with the first thermal pad; or, the first redistribution layer includes a first thermal pad, the metal thermally conductive structure of the second heat sink is in contact with the first thermal pad, and the metal thermally conductive structure of the first heat sink is connected to a metal trace of an independent network in the second redistribution layer; or, the second redistribution layer includes a second thermal pad, the metal thermally conductive structure of the first heat sink is in contact with the second thermal pad, and the metal thermally conductive structure of the second heat sink is connected to a metal trace of an independent network in the first redistribution layer.

[0012] Optionally, the end face of the first heat sink near the second chip is provided with insulating thermally conductive adhesive, the end face of the second heat sink near the first chip is provided with insulating thermally conductive adhesive, the metal thermally conductive structure of the first heat sink is connected to the metal trace of an independent network in the second redistribution layer, and the metal thermally conductive structure of the second heat sink is connected to the metal trace of an independent network in the first redistribution layer.

[0013] Optionally, the fan-out chip stacked package structure further includes a passive component, a third heat sink, a third molding compound, and a thermal pad. The third heat sink includes a metal thermally conductive structure and a molding compound that encapsulates the metal thermally conductive structure. The passive component and the third heat sink are located on the second redistribution layer. The third heat sink overlaps with both the first chip and the first heat sink. An insulating thermally conductive adhesive is disposed between the third heat sink and the second redistribution layer. The passive component is electrically connected to the second redistribution layer. The third molding compound encapsulates the passive component and the third heat sink. The thermal pad is located on the third molding compound and is in contact with the metal thermally conductive structure of the third heat sink.

[0014] This invention also provides a method for processing a fan-out type chip stacked package structure. The method includes: providing a first heat sink and a second heat sink, both the first and second heat sinks comprising a metal thermally conductive structure and a molding compound encapsulating the metal thermally conductive structure; mounting a first chip and a first heat sink onto a first carrier substrate, with the front side of the first chip facing the first carrier substrate; forming a first molding compound layer on the first carrier substrate, the first molding compound layer at least covering the sidewalls of the first chip and the sidewalls of the first heat sink; mounting a second chip and a second heat sink onto the first molding compound layer, with the front side of the second chip facing away from the first chip; and mounting the second chip and the first heat sink onto the first molding compound layer. The heat sinks at least partially overlap with the first chip; a second molding compound is formed on the first molding compound, the second molding compound at least covering the sidewalls of the second chip and the sidewalls of the second heat sink; a first redistribution layer is formed on the second molding compound, the first redistribution layer being electrically connected to the front side of the second chip and in contact with the metal thermally conductive structure of the second heat sink; and the first carrier board is removed; a second redistribution layer is formed on the surface of the first molding compound away from the second molding compound, the second redistribution layer being electrically connected to the front side of the first chip and in contact with the metal thermally conductive structure of the first heat sink.

[0015] Optionally, the step of mounting the first chip and the first heat sink on the first carrier board includes mounting at least one first interconnect on the first carrier board; the step of mounting the second chip and the second heat sink on the first molding compound includes mounting at least one second interconnect on the first interconnect; wherein the first interconnect and the second interconnect both include a conductive structure and an insulating material that isolates the conductive structure, one end of the conductive structure of the first interconnect is electrically connected to one end of the conductive structure of the second interconnect, the other end of the conductive structure of the first interconnect is electrically connected to the second redistribution layer, and the other end of the conductive structure of the second interconnect is electrically connected to the first redistribution layer.

[0016] Optionally, after forming the first molding compound on the first substrate and before mounting the second chip and the second heat sink on the first molding compound, a metal interconnect layer is formed on the first molding compound. The metal interconnect layer includes a first metal pad and a second metal pad. The first metal pad covers the first chip and the first heat sink, and the second metal pad is electrically connected to the conductive structure of the first interconnect. In the step of mounting the second chip and the second heat sink on the first molding compound, the second chip and the second heat sink are mounted on the first metal pad, and the conductive structure of the second interconnect is soldered to the second metal pad.

[0017] Optionally, the metal thermally conductive structure is a thermally conductive pillar; in a heat sink, both ends of the thermally conductive pillar are exposed from the encapsulation material.

[0018] Optionally, in the step of mounting the second chip and the second heat sink on the first molding layer, the back side of the second chip is fixed by adhesive bonding with insulating thermally conductive adhesive; and / or, in the step of attaching the first chip and the first heat sink to the first carrier board, the back side of the first chip has insulating thermally conductive adhesive.

[0019] Optionally, the processing method of the fan-out chip stacked package structure further includes: after forming a second redistribution layer on the surface of the first molding layer away from the second molding layer, mounting a third heat sink and a passive component on the second redistribution layer, the third heat sink including a metal thermally conductive structure and a molding material encapsulating the metal thermally conductive structure, the third heat sink having overlapping areas with both the first chip and the first heat sink, an insulating thermally conductive adhesive being disposed between the third heat sink and the second redistribution layer, and the passive component being electrically connected to the second redistribution layer; forming a third molding layer on the second redistribution layer, the third molding layer at least covering the sidewalls of the passive component and the sidewalls of the third heat sink and at least exposing the metal thermally conductive structure of the third heat sink; and forming a thermal pad on the third molding layer, the thermal pad being in contact with the metal thermally conductive structure of the third heat sink.

[0020] In the fan-out chip stacked packaging structure and its processing method provided by the present invention, a second chip and a second heat sink are stacked on the back side of a first chip, with the second chip and the first heat sink at least partially overlapping. Both the first and second heat sinks include a metal thermally conductive structure and a molding compound that isolates the metal thermally conductive structure. The metal thermally conductive structure of the first heat sink is in contact with the second redistribution layer, and the metal thermally conductive structure of the second heat sink is in contact with the first redistribution layer. Thus, the first and second heat sinks, as double-sided heat sinks, can increase the overall thermal capacity of the packaging structure and reduce the thermal resistance of the packaging structure, thereby effectively dissipating the heat from the first and second chips, especially effectively dissipating the heat from the substrate located on the back side of the chip. This reduces heat accumulation in the chip, avoids heat buildup, solves the heat dissipation problem when the chip power is too high, and helps to improve chip lifespan and the reliability of the packaging structure. In addition, the first and second heat sinks can be prepared before the packaging structure is processed and can be installed together with the chip, which helps to improve packaging efficiency.

[0021] Furthermore, the fan-out chip stacked package structure also includes a first interconnect located in the first molding compound and a second interconnect located in the second molding compound. Both the first and second interconnects include conductive structures and isolation materials that isolate the conductive structures. One end of the conductive structure of the first interconnect is electrically connected to one end of the conductive structure of the second interconnect, and the other end of the conductive structure of the first interconnect is electrically connected to the second redistribution layer. The other end of the conductive structure of the second interconnect is electrically connected to the first redistribution layer. That is, the first and second redistribution layers are interconnected through the stacked first and second interconnects. This avoids the process of fabricating TMV via structures in a thick molding compound, reducing the difficulty of interconnecting the two redistribution layers. In addition, the fabrication of the thermal conductive structures in the first and second interconnects is not limited by the thickness of the molding compound. The conductive structure can be a solid conductive pillar instead of being limited to the copper plating of the via wall, which helps to improve the heat dissipation effect and conductivity reliability of the package structure. Attached Figure Description

[0022] Figures 1 to 6 This is a step-by-step schematic diagram of a fabrication method for a board-level fan-out packaging structure.

[0023] Figure 7 A flowchart illustrating a method for fabricating a fan-out chip stacked packaging structure according to an embodiment of the present invention.

[0024] Figures 8 to 12 This is a step-by-step schematic diagram of a processing method for a fan-out chip stacked packaging structure provided in an embodiment of the present invention.

[0025] Figures 13 to 18 This is a step-by-step schematic diagram of a processing method for a fan-out chip stacked packaging structure provided in another embodiment of the present invention.

[0026] Figure 19 This is a schematic diagram of a fan-out chip stacking package structure provided in an embodiment of the present invention.

[0027] Figure 20 This is a schematic diagram showing the connection between the heat-conducting structure of the first heat sink and the metal traces of the second redistribution layer in one embodiment of the present invention.

[0028] Figure 21 This is a schematic diagram showing that, in one embodiment of the present invention, the metal thermally conductive structures of both the first and second heat sinks are connected to the metal traces of the redistribution layer.

[0029] Figures 22 to 23 This is a schematic diagram illustrating the process of encapsulating a passive component and a third heat sink on a redistribution layer in one embodiment of the present invention.

[0030] Figure 24 This is a schematic diagram of a fan-out chip stacking package structure provided in another embodiment of the present invention.

[0031] Figure labeling: 1-Front side chip; 2-Carrier board; 3-Back side chip; 4-Molded package; 5-TMV via structure; 6-Front side redistribution layer; 7-Molded package protective layer; 8-Back side redistribution layer;

[0032] 101-First carrier board; 102-First adhesive layer; 103a-First original molding compound layer; 103-First molding compound layer; 104a-First metal pad; 104b-Second metal pad; 105a-Second original molding compound layer; 105b-Laser via; 105-Second molding compound layer; 106-First redistribution layer; 106a-First thermal pad; 107-Top pad; 108-First resin film; 109-Second carrier board; 110-Second adhesive layer; 111-Second redistribution layer; 1 11a - Second heat dissipation pad; 112 - Bottom pad; 113 - Second resin film; 114 - Passive component; 115a - Third original molding layer; 115 - Third molding layer; 116 - Heat dissipation pad; 21 - First chip; 31 - First heat sink; 301 - Metal thermally conductive structure; 302 - Molding material; 32 - Second heat sink; 33 - Third heat sink; 41 - First interconnect; 401 - Conductive structure; 402 - Isolation material; 42 - Second interconnect; 50 - Insulating thermally conductive adhesive. Detailed Implementation

[0033] The fan-out chip stacking packaging structure and its processing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0034] Figure 7 This is a flowchart illustrating a fabrication method for a fan-out chip stacked package structure according to an embodiment of the present invention. Figure 7 As shown, the processing method of the fan-out chip stacked package structure provided in this application includes:

[0035] Step S1: Provide a first heat sink and a second heat sink, both of which include a metal thermally conductive structure and a molding compound for the metal thermally conductive structure.

[0036] Step S2: Mount the first chip and the first heat sink onto the first carrier board, with the front of the first chip facing the first carrier board;

[0037] Step S3: A first molding compound is formed on the first substrate. The first molding compound at least covers the sidewall of the first chip and the sidewall of the first heat sink.

[0038] Step S4: Install a second chip and a second heat sink on the first molding compound, with the front of the second chip facing away from the first chip, and the second chip and the first heat sink at least partially overlapping each other.

[0039] Step S5: A second molding layer is formed on the first molding layer, the second molding layer at least covering the sidewall of the second chip and the sidewall of the second heat sink;

[0040] Step S6: A first redistribution layer is formed on the second molding compound layer. The first redistribution layer is electrically connected to the front side of the second chip and in contact with the metal thermally conductive structure of the second heat sink; and

[0041] Step S7: Remove the first carrier board;

[0042] Step S8: A second redistribution layer is formed on the surface of the first molding layer away from the second molding layer. The second redistribution layer is electrically connected to the front side of the first chip and in contact with the metal thermally conductive structure of the first heat sink.

[0043] It should be understood that, although Figure 7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 7 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0044] Figures 8 to 12 This is a step-by-step schematic diagram of a processing method for a fan-out chip stacked packaging structure provided in an embodiment of the present invention. Figures 13 to 18 This is a step-by-step schematic diagram of a processing method for a fan-out chip stacked packaging structure provided in another embodiment of the present invention. Figure 19 This is a schematic diagram of a fan-out chip stacking package structure provided in an embodiment of the present invention.

[0045] The following combination Figures 7 to 19 The processing method of the fan-out type chip stacked package structure provided in this application is described.

[0046] First, prepare the first heat sink 31 and the second heat sink 32.

[0047] refer to Figure 8 and Figure 12As shown, both the first heat sink 31 and the second heat sink 32 may include a metal thermally conductive structure 301 and a molding compound 302 encapsulating the metal thermally conductive structure 301; in one heat sink, the two ends of the metal thermally conductive structure 301 are exposed from two opposite surfaces of the molding compound 302. For example, the metal thermally conductive structure 301 can be a solid thermally conductive pillar, which provides better thermal conductivity and simplifies the manufacturing process. The material of the thermally conductive pillar includes, but is not limited to, copper. In other embodiments, the metal thermally conductive structure 301 may also include interconnected metal layers. The molding compound 302 may be an epoxy molding compound (EMC), but is not limited thereto.

[0048] In this application, the heat sink can be fabricated before the encapsulation structure is processed. For example, a method for fabricating the heat sink may include: forming a molding compound on the top surface of a first support plate, with the back side of the molding compound facing the first support plate; forming a conductive layer on the front side of the molding compound, covering the front side of the molding compound; setting a second support plate on the side of the conductive layer away from the molding compound, and removing the first support plate to expose the back side of the molding compound; forming multiple through holes in the molding compound, the multiple through holes penetrating the molding compound and exposing a portion of the conductive layer; using the conductive layer as a conductive seed layer, electroplating multiple heat-conducting pillars from the bottom of the multiple through holes toward the openings to form multiple heat-conducting pillars filling the corresponding through holes; removing the second support plate and cutting the molding compound to form multiple heat sinks.

[0049] The cross-sectional shape of the heat-conducting pillars in the heat sink can be circular, but is not limited to this. The cross-sectional shape of the heat-conducting pillars can also be square or elliptical, etc. The dimensions of the heat sink (e.g., length, width, and height) and the dimensions of its internal heat-conducting pillars can be designed according to product requirements, and the number of heat-conducting pillars in the heat sink can also be set as needed.

[0050] In this embodiment, before the packaging process of the fan-out chip stacked package structure begins, the first interconnect 41 and the second interconnect 42 can be prepared in advance. (See reference...) Figure 8 and Figure 12 As shown, both the first interconnect 41 and the second interconnect 42 may include a conductive structure 401 and an insulating material 402 that isolates the conductive structure 401. In one interconnect, the two ends of the conductive structure 401 are exposed from opposite surfaces of the insulating material 402. In this embodiment, the insulating material 402 can be an epoxy molding compound. In this embodiment, the conductive structure 401 can be a solid conductive pillar. To meet the product requirements of multi-chip, multi-pin, and complex interconnect structures, specially designed circuits can be made within the interconnect to complete the fabrication of double-sided interconnects. That is, the conductive structure 401 can include multiple interconnected circuit layers, increasing the product diversity of advanced board-level packaging.

[0051] In this embodiment, the manufacturing methods of the interconnect and the heat sink are similar.

[0052] After preparing the heat sink and interconnects, as Figure 8 As shown, the first chip 21 and the first heat sink 31 are mounted on the first carrier board 101, with the front of the first chip 21 facing the first carrier board 101.

[0053] For example, the first chip 21 has opposing front and back sides, and the front side of the first chip 21 may have bumps. In other embodiments, the front side of the first chip 21 may have chip pads. The first chip 21 may include a substrate located on the back side of the first chip 21, and the substrate material may include, but is not limited to, silicon.

[0054] In the step of mounting the first chip 21 and the first heat sink 31 onto the first carrier board 101, at least one first interconnect 41 may also be mounted onto the first carrier board 101. Exemplarily, the first interconnect 41 is located on the side of the first chip 21 away from the first heat sink 31 or on the side of the first heat sink 31 away from the first chip 21. In this embodiment, as... Figure 8 As shown, two first interconnects 41 are disposed on both sides of the first chip 21. One first interconnect 41 is located on the side of the first chip 21 away from the first heat sink 31, and the other first interconnect 41 is located on the side of the first heat sink 31 away from the first chip 21.

[0055] like Figure 8 As shown, a first adhesive layer 102 may be disposed on the first carrier board 101, and the first chip 21, the first heat sink 31, and the first interconnect 41 are attached to the first carrier board 101 through the first adhesive layer 102. For example, the first adhesive layer 102 is a debonded adhesive layer.

[0056] It needs to be explained that, Figure 8 Only one first chip 21 is shown mounted on the first carrier board 101. In fact, multiple first chips 21 can be mounted on the first carrier board 101 at the same time, and corresponding first heat sinks 31 and first interconnects 41 can be mounted on the side of the first chip 21.

[0057] like Figure 10 As shown, a first molding compound 103 is formed on the first substrate 101, and the first molding compound 103 at least covers the sidewalls of the first chip 21 and the sidewalls of the first heat sink 31. In this embodiment, the first molding compound 103 also covers the first interconnect 41.

[0058] Specifically, the method for forming the first molding compound 103 on the first carrier plate 101 includes: as follows Figure 9 As shown, a first original molding compound 103a is formed on the first carrier board 101, covering the first chip 21, the first heat sink 31, and the first interconnect 41; as Figure 10As shown, a portion of the thickness of the first original molding layer 103a is removed by grinding and / or etching processes, exposing the end faces of the first heat sink 31 and the first interconnect 41 away from the first carrier 101 and exposing the back side of the first chip 21.

[0059] In this embodiment, the heights of the first interconnect 41 and the first heat sink 31 can be equal, allowing the end faces of both the first interconnect 41 and the first heat sink 31 to be exposed simultaneously during the removal of a portion of the thickness of the first original molding compound 103a. If the heights of the first interconnect 41 and the first heat sink 31 are unequal, grinding can continue until the end face of both is exposed after grinding to expose the end face of one of them. It should be noted that in the first molding compound 103, i.e., after grinding of the first original molding compound 103a, the heights of the first interconnect 41 and the first heat sink 31 (where...) are... Figure 10 The dimensions (perpendicular to the horizontal direction) can be the same, which facilitates the subsequent stacking of chips and the lead-out of the first interconnect 41 and the first heat sink 31. In some other embodiments, the heights of the first heat sink 31 and the first interconnect 41 can be different.

[0060] The thickness of the first chip 21 is (for) Figure 10 The thickness of the first chip 21 (perpendicular to the horizontal direction) is less than or equal to the height of the first interconnect 41 and the first heat sink 31. When the thickness of the first chip 21 is equal to the height of the first heat sink 31, grinding exposes the end faces of the first interconnect 41 and the first heat sink 31, allowing the back side of the first chip 21 to be exposed from the surface of the first molding layer 103, which simplifies the process. When the thickness of the first chip 21 is less than the height of the first heat sink 31, after grinding exposes the end faces of the first interconnect 41 and the first heat sink 31, the first molding layer 103 still covers the first chip 21. If the back side of the first chip 21 cannot be ground, it can be exposed by laser drilling. If the back side of the first chip 21 can be ground, grinding can continue to remove part of the height of the first interconnect 41 and the first heat sink 31 to expose the back side of the first chip 21, ensuring that the subsequent encapsulated second heat sink can effectively dissipate heat from the substrate of the first chip 21.

[0061] like Figure 11 As shown, a metal interconnect layer is formed on the first molding layer 103. The metal interconnect layer includes a first metal pad 104a and a second metal pad 104b. The first metal pad 104a covers the first chip 21 and the first heat sink 31, and the second metal pad 104b is electrically connected to the conductive structure of the first interconnect 41.

[0062] Specifically, such as Figure 11As shown, the first metal pad 104a is in direct contact with the back surface of the first chip 21 and the end face of the first heat sink 31. Each first interconnect 41 has a corresponding second metal pad 104b. For example, each conductive post of each first interconnect 41 has a corresponding second metal pad 104b at its end. The first metal pad 104a and the second metal pad 104b can be made of the same material, for example, both of which are copper.

[0063] It should be noted that the first metal pad 104a covers the first chip 21 and the first heat sink 31, which ensures that the stacked chip and heat sink have a large heat dissipation area, which helps to improve the heat dissipation effect of the packaging structure; the back side of the first chip 21 can contact the first metal pad 104a, which helps to improve the heat dissipation effect of the first chip 21.

[0064] like Figure 12 As shown, a second chip 22 and a second heat sink 32 are mounted on the first molding layer 103. The front of the second chip 22 faces away from the first chip 21. The second chip 22 and the first heat sink 31 overlap at least partially.

[0065] In the step of mounting the second chip 22 and the second heat sink 32 on the first molding compound 103, a second interconnect 42 may also be mounted on the first molding compound 103.

[0066] Specifically, the second chip 22 and the second heat sink 32 can be mounted on the first metal pad 104a. The back of the second chip 22 and the metal thermally conductive structure of the second heat sink 32 can be in direct contact with the first metal pad 104a. The conductive structure of the second interconnect 42 is soldered to the second metal pad 104b. The first interconnect 41 is electrically connected to the second interconnect 42 through the second metal pad 104b.

[0067] The second chip 22 has a front side and a back side. The front side of the second chip 22 may have bumps or pads, and the back side of the second chip 22 is attached to the first metal pad 104a. The second chip 22 includes a substrate located on one side of the back side of the second chip 22.

[0068] It should be noted that when the substrates of the first chip 21 and the second chip 22 do not require insulation, such as Figure 12 As shown, the back of the second chip 22 can be directly attached to the first metal pad 104a, and the back of the first chip 21 can also contact the first metal pad 104a.

[0069] Figures 13 to 18 This is a schematic diagram of another part of the processing method of a fan-out chip stacked package structure provided in another embodiment of the present invention.

[0070] When the substrates of the first chip 21 and the second chip 22 have insulation requirements, for example, when the first chip 21 and the second chip 22 need to be insulated from other circuits, then as follows: Figure 13 As shown, the back of the second chip 22 can be glued and fixed to the first metal pad 104a with insulating thermally conductive adhesive 50. The back of the first chip 21 can also be provided with insulating thermally conductive adhesive 50, and the back of the first chip 21 can contact the first metal pad 104a through the insulating thermally conductive adhesive 50.

[0071] In some other embodiments, when the substrate of one of the first chip 21 and the second chip 22 has an insulation requirement, an insulating thermally conductive adhesive 50 can be provided on the back side of the chip with the insulation requirement, and the back side of the other chip can directly contact the first metal pad 104a.

[0072] The following description continues to illustrate the processing method of the fan-out type chip stacked package structure, taking the example that the back of both the first chip 21 and the second chip 22 are provided with insulating thermally conductive adhesive 50.

[0073] like Figure 15 As shown, a second molding layer 105 is formed on the first molding layer 103. The second molding layer 105 at least covers the sidewalls of the second chip 22, the sidewalls of the second heat sink 32, and the sidewalls of the second interconnect 42.

[0074] Specifically, the method for forming the second molding layer 105 on the first molding layer 103 includes: as follows Figure 14 As shown, a second original molding layer 105a is formed on the first molding layer 103, and the second original molding layer 105a covers the second interconnect 42, the second chip 22, and the second heat sink 32; as Figure 15 As shown, a portion of the thickness of the second original molding layer 105a is removed by grinding and / or etching processes, exposing at least the end face of the second interconnect 42 and the end face of the second heat sink 32, so as to expose the conductive structure of the second interconnect 42 and the metal thermally conductive structure of the second heat sink 32.

[0075] In the second molding layer 105, the height of the second interconnect 42 and the height of the second heat sink 32 can be the same, and the thickness of the second chip 22 can be less than the height of the second heat sink 32, but is not limited thereto.

[0076] In this embodiment, in order to bring out the second chip 22, refer to Figure 15 As shown, a plurality of laser holes 105b are formed in the second molding layer 105, and the laser holes 105b expose the bumps or pads of the second chip 22.

[0077] like Figure 16As shown, a first redistribution layer 106 is formed on the second molding layer 105. The first redistribution layer 106 is electrically connected to the front side of the second chip 22 and in contact with the metal thermally conductive structure of the second heat sink 32. The first redistribution layer 106 is also electrically connected to the conductive structure of the second interconnect 42.

[0078] refer to Figure 15 and Figure 16 As shown, the first redistribution layer 106 can fill the laser aperture 105b to electrically connect with the bumps or pads on the front side of the second chip 22.

[0079] It should be noted that, Figure 16 The first redistribution layer 106 includes only one metal trace layer. In practical applications, depending on performance requirements, the first redistribution layer 106 may include multiple interconnected metal trace layers.

[0080] like Figure 17 As shown, a top pad layer is formed on the first redistribution layer 106. The top pad layer includes a plurality of top pads 107, which are electrically connected to corresponding pads or metal traces in the first redistribution layer 106.

[0081] For example, the materials of the top pad 107 and the first redistribution layer 106 include, but are not limited to, copper.

[0082] like Figure 17 As shown, a first resin film 108 is disposed on the second molding layer 105. The first resin film 108 fills the metal traces between the first redistribution layer 106 and between the top pads 107. The first resin film 108 can also cover the top pad layer. Then, grinding is performed to remove part of the thickness of the first resin film 108, exposing the top surface of the top pads 107.

[0083] like Figure 18 As shown, the first carrier board 101 and the first adhesive layer 102 are removed, exposing part of the front side of the first chip 21 and the end face of the first interconnect 41 and the first heat sink 31 located on one side of the front side of the first chip 21.

[0084] In order to prevent the first molding layer 103 and the second molding layer 105 from warping, a second carrier 109 can be attached to the front side of the second chip 22 before the first carrier 101 is removed. The second carrier 109 can be bonded to the top pad layer through the second adhesive layer 110.

[0085] like Figure 19 As shown, a second redistribution layer 111 is formed on the surface of the first molding layer 103 away from the second molding layer 105. The second redistribution layer 111 is electrically connected to the front side of the first chip 21 and in contact with the metal thermally conductive structure of the first heat sink 31. The second redistribution layer 111 is also electrically connected to the conductive structure of the first interconnect 41.

[0086] Specifically, one end of the conductive structure of the first interconnect 41 is electrically connected to one end of the conductive structure of the second interconnect 42, the other end of the conductive structure of the first interconnect 41 is electrically connected to the second redistribution layer 111, and the other end of the conductive structure of the second interconnect 42 is electrically connected to the first redistribution layer 106, so that the first redistribution layer 106 and the second redistribution layer 111 are interconnected through the stacked first interconnect 41 and second interconnect 42.

[0087] It should be noted that, Figure 19 The second redistribution layer 111 includes only one metal trace layer. In practical applications, the second redistribution layer 111 may include multiple interconnected metal trace layers depending on performance requirements.

[0088] like Figure 19 As shown, a bottom pad layer is formed on the second redistribution layer 111. The bottom pad layer includes a plurality of bottom pads 112, which are electrically connected to corresponding pads or traces in the second redistribution layer 111.

[0089] For example, the materials of the bottom pad 112 and the second redistribution layer 111 include, but are not limited to, copper.

[0090] like Figure 19 As shown, a second resin film 113 is disposed on the first molding layer 103. The second resin film 113 fills the traces between the second redistribution layer 111 and between the bottom pads 112. The second resin film 113 can also cover the bottom pad layer. Then, grinding is performed to remove part of the thickness of the second resin film 113, exposing the top surface of the bottom pads 112.

[0091] It should be noted that in this application, the first heat sink 31 is electrically insulated from the second chip 22, and the second heat sink 32 is electrically insulated from the first chip 21, that is, the first heat sink 31 and the second heat sink 32 do not participate in electrical connection.

[0092] In one embodiment of this application, reference is made to... Figure 19As shown, the first redistribution layer 106 includes a first heat dissipation pad 106a, and the second redistribution layer 111 includes a second heat dissipation pad 111a. The first heat dissipation pad 106a is not connected to other metal traces of the first redistribution layer 106, and the second heat dissipation pad 111a is not connected to other metal traces of the second redistribution layer 111. The metal thermally conductive structure 301 of the first heat sink 31 is in contact with the second heat dissipation pad 111a, and the metal thermally conductive structure of the second heat sink 32 is in contact with the first heat dissipation pad 106a. By setting independent heat dissipation pads in the redistribution layer, it can be ensured that the first heat sink 31 and the second heat sink 32 do not participate in the electrical connection within the package structure, and the connection between the heat dissipation structures can also be ensured, thereby effectively dissipating heat from the chip.

[0093] Figure 20 This is a schematic diagram showing the connection between the heat-conducting structure of the first heat sink and the metal traces of the second redistribution layer in one embodiment of the present invention. Some embodiments of this application, such as... Figure 20 As shown, the first redistribution layer 106 includes a first heat dissipation pad 106a, the metal thermally conductive structure of the second heat sink 32 is in contact with the first heat dissipation pad 106a, and the metal thermally conductive structure of the first heat sink 31 is connected to the metal trace of an independent network in the second redistribution layer 111; or, in some embodiments of this application, the second redistribution layer 111 may include a second heat dissipation pad 111a, the metal thermally conductive structure of the first heat sink 31 is in contact with the second heat dissipation pad 111a, and the metal thermally conductive structure of the second heat sink 32 is connected to the metal trace of an independent network in the first redistribution layer 106. In this way, although the first heat sink 31 and the second heat sink 32 are in electrical contact with one of the two redistribution layers, neither the first heat sink 31 nor the second heat sink 32 is connected to any other metal trace of the other of the two redistribution layers, thus not affecting the electrical connection between the first redistribution layer 106 and the second redistribution layer 111, and also saving the wiring space of one redistribution layer.

[0094] Figure 21 This is a schematic diagram showing that, in one embodiment of the present invention, the metal thermally conductive structures of both the first and second heat sinks are connected to the metal traces of the redistribution layer. In some embodiments of this application, such as... Figure 21 As shown, the end face of the first heat sink 31 near the second chip 22 is provided with insulating thermally conductive adhesive 50, and the end face of the second heat sink 32 near the first chip 21 is provided with insulating thermally conductive adhesive 50. The metal thermally conductive structure of the first heat sink 31 is connected to the metal trace of an independent network in the second redistribution layer 111, and the metal thermally conductive structure of the second heat sink 32 is connected to the metal trace of an independent network in the first redistribution layer 106. In this way, neither the first heat sink 31 nor the second heat sink 32 participates in electrical connection, and the wiring space of the two redistribution layers can be saved.

[0095] Figures 22 to 23 This is a schematic diagram illustrating the process of encapsulating a passive component and a third heat sink on a redistribution layer in one embodiment of the present invention. Figure 24 This is a schematic diagram of a fan-out chip stacking package structure provided in another embodiment of the present invention.

[0096] In some embodiments of this application, after the second redistribution layer 111 is formed, such as Figure 22 As shown, a third heat sink 33 and a passive component 114 are mounted on the second redistribution layer 111. The third heat sink 33 includes a metal thermally conductive structure and a plastic encapsulation material for the metal thermally conductive structure. The third heat sink 33 overlaps with both the first chip 21 and the first heat sink 31. The passive component 114 is electrically connected to the second redistribution layer 111. An insulating thermally conductive adhesive 50 is provided between the third heat sink 33 and the second redistribution layer 111 to prevent the third heat sink 33 from participating in the electrical connection and to avoid the influence of the heat sink on the electrical connection relationship of the package structure.

[0097] For example, passive components 114 include, but are not limited to, capacitors, resistors, or inductors. The number of passive components 114 mounted on the second redistribution layer 111 can be one or more.

[0098] like Figure 23 As shown, a third molding layer 115 is formed on the second redistribution layer 111. The third molding layer 115 at least covers the sidewalls of the passive component 114 and the sidewalls of the third heat sink 33 and at least exposes the metal thermally conductive structure of the third heat sink 33.

[0099] Specifically, a third original molding compound 115a is formed on the second redistribution layer 111, covering the third heat sink 33 and the passive component 114; part of the thickness of the third original molding compound 115a is removed by processes such as grinding, exposing the end face of the third heat sink 33 away from the first molding compound 103 to expose the metal thermally conductive structure of the third heat sink 33, thus forming the third molding compound 115.

[0100] like Figure 24 As shown, a heat dissipation pad 116 is formed on the third molding layer 115, and the heat dissipation pad 116 is in contact with the metal thermally conductive structure of the third heat sink 33.

[0101] It should be noted that the passive component 114 and the third heat sink 33 are disposed on the second redistribution layer 111. This allows the passive component 114 and the third heat sink 33 to be directly encapsulated after the second redistribution layer 111 is formed, without the need to remove the second carrier board 109. In other embodiments, the passive component 114 and the third heat sink 33 can also be disposed on the first redistribution layer 106. In this case, the second carrier board 109 needs to be removed to expose the first redistribution layer 106 (specifically, to expose the top pad 107).

[0102] This application also provides a fan-out chip stacking package structure, which can be manufactured using the above-described processing method for fan-out chip stacking packages, but is not limited thereto.

[0103] refer to Figure 19 As shown, the fan-out chip stacked package structure includes a first chip 21, a first heat sink 31, a first molding compound 103, a second chip 22, a second heat sink 32, a second molding compound 105, a first redistribution layer 106, and a second redistribution layer 111. The first heat sink 31 is located on the side of the first chip 21; the first molding compound 103 at least covers the sidewalls of the first chip 21 and the sidewalls of the first heat sink 31; the second chip 22 and the second heat sink 32 are stacked on the back side of the first chip 21, with the front of the second chip 22 facing away from the first chip 21. The second chip 22 and the first heat sink 31 at least partially overlap, and the first chip 21 and the second heat sink 32 at least partially overlap. Both the first heat sink 31 and the second heat sink 32 include a metal thermal conductive structure 301 and a molded metal thermal conductive structure 301. The molding compound 302; the second molding compound 105 is connected to the first molding compound 103 and at least covers the sidewalls of the second chip 22 and the sidewalls of the second heat sink 32; the first redistribution layer 106 is located on one side of the front of the second chip 22 and is electrically connected to the front of the second chip 22, and the first redistribution layer 106 is in contact with the metal thermally conductive structure of the second heat sink 32; the second redistribution layer 111 is located on one side of the front of the first chip 21 and is electrically connected to the front of the first chip 21, and the second redistribution layer 111 is in contact with the metal thermally conductive structure of the first heat sink 31.

[0104] Specifically, the first chip 21 has a front side and a back side. In this embodiment, the front side of the first chip 21 may have bumps or chip pads. The first chip 21 may include a substrate located on the back side of the first chip 21, and the substrate material includes, but is not limited to, silicon.

[0105] The second chip 22 has a front side and a back side, and the front side of the second chip 22 may have bumps or pads. The second chip 22 includes a substrate located on the back side of the second chip 22.

[0106] For example, the metal thermally conductive structure 301 in the first heat sink 31 and the second heat sink 32 can be a solid thermally conductive pillar, which provides good thermal conductivity and simplifies the manufacturing process. The material of the thermally conductive pillar includes, but is not limited to, copper. In other embodiments, the metal thermally conductive structure 301 may also include interconnected metal layers. The molding compound 302 can be an epoxy molding compound (EMC).

[0107] like Figure 19As shown, the fan-out chip stacked package structure may further include a first interconnect 41 and a second interconnect 42. The first interconnect 41 is located in the first molding compound 103, and the second interconnect 42 is located in the second molding compound 105 and corresponds to the position of the first interconnect 41. Both the first interconnect 41 and the second interconnect 42 include a conductive structure 401 and an insulating material 402 that isolates the conductive structure. One end of the conductive structure of the first interconnect 41 is electrically connected to one end of the conductive structure of the second interconnect 42, and the other end of the conductive structure of the first interconnect 41 is electrically connected to the second redistribution layer 111. The other end of the conductive structure of the second interconnect 42 is electrically connected to the first redistribution layer 106. In other words, the first redistribution layer 106 and the second redistribution layer 111 are interconnected through the stacked first interconnect 41 and the second interconnect 42.

[0108] In this embodiment, a metal connection layer is provided between the first molding layer 103 and the second molding layer 105. The metal connection layer includes a first metal pad 104a and a second metal pad 104b. The first chip 21 and the first heat sink 31 are located on one side surface of the first metal pad 104a, and the second chip 22 and the second heat sink 32 are located on the other side surface of the first metal pad 104a. The second metal pad 104b is located between the conductive structures of the first interconnect 41 and the second interconnect 42 to electrically connect the first interconnect 41 and the second interconnect 42.

[0109] In detail, the surface area of ​​one side of the first metal pad 104a is greater than the sum of the back surface area of ​​the first chip 21 and the end surface area of ​​the first heat sink 31, and is also greater than the sum of the back surface area of ​​the second chip 22 and the end surface area of ​​the second heat sink 32.

[0110] It should be noted that when the substrates of the first chip 21 and the second chip 22 do not require insulation, such as Figure 12 As shown, the back of the second chip 22 and the end face of the second heat sink 32 can be directly attached to the first metal pad 104a. The back of the first chip 21 and the end face of the first heat sink 31 can also contact the first metal pad 104a, so the heat dissipation effect of the double-layer chip is better.

[0111] When the substrates of the first chip 21 and the second chip 22 have insulation requirements, that is, when the first chip 21 and the second chip 22 need to be insulated from other circuits, then as follows: Figure 19 As shown, the back of the second chip 22 can be glued and fixed to the first metal pad 104a by insulating thermally conductive adhesive 50. The back of the first chip 21 can also be provided with insulating thermally conductive adhesive 50, and the back of the first chip 21 contacts the first metal pad 50 through the insulating thermally conductive adhesive 50.

[0112] In some other embodiments, when the substrate of one of the first chip 21 and the second chip 22 has an insulation requirement, an insulating thermally conductive adhesive 50 can be provided on the back side of the chip with the insulation requirement, and the back side of the other chip can directly contact the first metal pad 104a.

[0113] In this embodiment, the heights of the first interconnect 41 and the first heat sink 31 can be equal, and the heights of the second interconnect 42 and the second heat sink 32 can be equal, which facilitates the outlining of the interconnects and heat sinks. In other embodiments, the heights of the first heat sink 31 and the first interconnect 41 can be different, and / or, the heights of the second interconnect 42 and the second heat sink 32 can be different.

[0114] In this application, the first heat sink 31 is electrically insulated from the second chip 22, and the second heat sink 32 is electrically insulated from the first chip 21. The first heat sink 31 and the second heat sink 32 do not participate in electrical connection.

[0115] Specifically, in one embodiment of this application, reference is made to... Figure 19 As shown, the first redistribution layer 106 includes a first heat dissipation pad 106a, and the second redistribution layer 111 includes a second heat dissipation pad 111a. The first heat dissipation pad 106a is not connected to other metal traces of the first redistribution layer 106, and the second heat dissipation pad 111a is not connected to other metal traces of the second redistribution layer 111. The metal thermally conductive structure 301 of the first heat sink 31 is in contact with the second heat dissipation pad 111a, and the metal thermally conductive structure of the second heat sink 32 is in contact with the first heat dissipation pad 106a. By setting independent heat dissipation pads in the redistribution layer, it can be ensured that the first heat sink 31 and the second heat sink 32 do not participate in the electrical connection within the package structure, and the connection between the heat dissipation structures can also be ensured, thereby effectively dissipating heat from the chip.

[0116] In some embodiments of this application, such as Figure 20As shown, the first redistribution layer 106 includes a first heat dissipation pad 106a, the metal thermally conductive structure of the second heat sink 32 is in contact with the first heat dissipation pad 106a, and the metal thermally conductive structure of the first heat sink 31 is connected to the metal trace of an independent network in the second redistribution layer 111; or, in some embodiments of this application, the second redistribution layer 111 may include a second heat dissipation pad 111a, the metal thermally conductive structure of the first heat sink 31 is in contact with the second heat dissipation pad 111a, and the metal thermally conductive structure of the second heat sink 32 is connected to the metal trace of an independent network in the first redistribution layer 106. In this way, although the first heat sink 31 and the second heat sink 32 are in electrical contact with one of the two redistribution layers, neither the first heat sink 31 nor the second heat sink 32 is connected to any other metal trace of the other of the two redistribution layers, thus not affecting the electrical connection between the first redistribution layer 106 and the second redistribution layer 111, and also saving the wiring space of one redistribution layer.

[0117] In some embodiments of this application, such as Figure 21 As shown, the end face of the first heat sink 31 near the second chip 22 is provided with insulating thermally conductive adhesive 50, and the end face of the second heat sink 32 near the first chip 21 is provided with insulating thermally conductive adhesive 50. The first heat sink 31 and the second heat sink 32 are in contact with the first metal pad 104a through the insulating thermally conductive adhesive 50. The metal thermally conductive structure of the first heat sink 31 is connected to the metal trace of an independent network in the second redistribution layer 111, and the metal thermally conductive structure of the second heat sink 32 is connected to the metal trace of an independent network in the first redistribution layer 106. In this way, neither the first heat sink 31 nor the second heat sink 32 participates in electrical connection, and the wiring space of the two redistribution layers can be saved.

[0118] In some embodiments of this application, such as Figure 24 As shown, the fan-out chip stacked package structure may further include a passive component 114, a third heat sink 33, a third molding compound 115, and a thermal pad 116. The third heat sink 33 includes a metal thermally conductive structure and a molding compound material for the metal thermally conductive structure. The passive component 114 and the third heat sink 33 are located on the second redistribution layer 111. The third heat sink 111 overlaps with both the first chip 21 and the first heat sink 31 to dissipate heat from the chip and the heat sink. An insulating thermally conductive adhesive 50 is provided between the third heat sink 33 and the second redistribution layer 111 to prevent the third heat sink 33 from participating in the electrical connection of the package structure. The passive component 114 is electrically connected to the second redistribution layer 111. The third molding compound 115 encapsulates the passive component 114 and the third heat sink 33. The thermal pad 116 is located on the third molding compound 115 and is in contact with the metal thermally conductive structure of the third heat sink 33. The number of passive components may be one or more.

[0119] In the fan-out type chip stacked packaging structure and its processing method provided by the present invention, the second chip 22 and the second heat sink 32 are stacked on one side of the back of the first chip 21. The second chip 22 and the first heat sink 31 at least partially overlap, and the first chip 21 and the second heat sink 32 at least partially overlap. Both the first heat sink 31 and the second heat sink 32 include a metal thermally conductive structure and a molding compound that isolates the metal thermally conductive structure. The metal thermally conductive structure of the first heat sink 31 is in contact with the second redistribution layer 111, and the metal thermally conductive structure of the second heat sink 32 is in contact with the first redistribution layer 106. Thus, the first heat sink 31 and the second heat sink 32... As a double-sided heat sink, heat sink 32 can increase the overall thermal capacity of the package structure and reduce the thermal resistance of the package structure, thereby effectively dissipating the heat of the first chip 21 and the second chip 22. In particular, it can effectively dissipate the heat in the substrate located on the back side of the chip, reducing heat accumulation in the chip and preventing heat buildup. This solves the heat dissipation problem when the chip power is too high, which helps to improve chip life and package structure reliability. In addition, the first heat sink 31 and the second heat sink 32 can be prepared before the package structure is processed and can be installed together with the chip, which helps to improve packaging efficiency.

[0120] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A fan-out type chip stacked package structure, characterized in that, include: First chip; The first heat sink is located on the side of the first chip; The first molding compound layer covers at least the sidewalls of the first chip and the sidewalls of the first heat sink. The second chip and the second heat sink are stacked on one side of the back of the first chip, the front of the second chip faces away from the first chip, the second chip and the first heat sink overlap at least partially, and the first chip and the second heat sink both include a metal thermally conductive structure and a molding compound that encapsulates the metal thermally conductive structure. The second molding layer is connected to the first molding layer and at least covers the sidewalls of the second chip and the sidewalls of the second heat sink; The first redistribution layer is located on one side of the front of the second chip and is electrically connected to the front of the second chip. The first redistribution layer is in contact with the metal thermally conductive structure of the second heat sink. as well as The second redistribution layer is located on one side of the front of the first chip and is electrically connected to the front of the first chip. The second redistribution layer is in contact with the metal thermally conductive structure of the first heat sink.

2. The fan-out chip stacking package structure as described in claim 1, characterized in that, Also includes: The first interconnect is located in the first molding layer; as well as The second interconnect is located in the second molding layer and corresponds to the position of the first interconnect. The first interconnect and the second interconnect both include a conductive structure and an insulating material that isolates the conductive structure. One end of the conductive structure of the first interconnect is electrically connected to one end of the conductive structure of the second interconnect, the other end of the conductive structure of the first interconnect is electrically connected to the second redistribution layer, and the other end of the conductive structure of the second interconnect is electrically connected to the first redistribution layer.

3. The fan-out chip stacking package structure as described in claim 2, characterized in that, A metal interconnect layer is provided between the first molding layer and the second molding layer. The metal interconnect layer includes a first metal pad and a second metal pad. The first chip and the first heat sink are located on one side surface of the first metal pad, and the second chip and the second heat sink are located on the other side surface of the first metal pad. The second metal pad is located between the conductive structures of the first interconnect and the second interconnect.

4. The fan-out chip stacking package structure as described in claim 3, characterized in that, The first metal pad is in direct contact with the back of the first chip and the metal thermally conductive structure of the first heat sink, and the back of the second chip and the metal thermally conductive structure of the second heat sink are in direct contact with the first metal pad.

5. The fan-out chip stacking package structure as described in claim 3, characterized in that, An insulating thermally conductive adhesive is disposed between the back of the first chip and the first metal pad, and / or, an insulating thermally conductive adhesive is disposed between the back of the second chip and the first metal pad.

6. The fan-out chip stacking package structure as described in claim 1, characterized in that, The first heat sink is electrically insulated from the second chip, and the second heat sink is electrically insulated from the first chip.

7. The fan-out chip stacked package structure as described in claim 1, characterized in that, The first redistribution layer includes a first thermal pad, and the second redistribution layer includes a second thermal pad. The thermally conductive metal structure of the first heat sink is in contact with the second thermal pad, and the thermally conductive metal structure of the second heat sink is in contact with the first thermal pad; or, the first redistribution layer includes a first thermal pad, and the thermally conductive metal structure of the second heat sink is in contact with the first thermal pad, and the thermally conductive metal structure of the first heat sink is connected to a metal trace of an independent network in the second redistribution layer; or, the second redistribution layer includes a second thermal pad, and the thermally conductive metal structure of the first heat sink is in contact with the second thermal pad, and the thermally conductive metal structure of the second heat sink is connected to a metal trace of an independent network in the first redistribution layer.

8. The fan-out chip stacked package structure as described in claim 1, characterized in that, The first heat sink has an insulating thermally conductive adhesive on its end face near the second chip, and the second heat sink has an insulating thermally conductive adhesive on its end face near the first chip. The metal thermally conductive structure of the first heat sink is connected to the metal trace of an independent network in the second redistribution layer, and the metal thermally conductive structure of the second heat sink is connected to the metal trace of an independent network in the first redistribution layer.

9. The fan-out chip stacking package structure as described in claim 1, characterized in that, It also includes a passive component, a third heat sink, a third molding compound, and a heat dissipation pad. The third heat sink includes a metal thermally conductive structure and a molding compound that encapsulates the metal thermally conductive structure. The passive component and the third heat sink are located on the second redistribution layer. The third heat sink overlaps with both the first chip and the first heat sink. An insulating thermally conductive adhesive is provided between the third heat sink and the second redistribution layer. The passive component is electrically connected to the second redistribution layer. The third molding compound encapsulates the passive component and the third heat sink. The heat dissipation pad is located on the third molding compound and is in contact with the metal thermally conductive structure of the third heat sink.

10. A method for fabricating a fan-out type chip stacked package structure, characterized in that, include: A first heat sink and a second heat sink are provided, both of which include a metal thermally conductive structure and a molding material for encapsulating the metal thermally conductive structure. The first chip and the first heat sink are mounted on the first carrier board, with the front of the first chip facing the first carrier board; A first molding compound is formed on the first substrate, the first molding compound at least covering the sidewall of the first chip and the sidewall of the first heat sink; A second chip and a second heat sink are mounted on the first molding layer, with the front side of the second chip facing away from the first chip, and the second chip and the first heat sink at least partially overlapping, and the second heat sink at least partially overlapping the first chip; A second molding layer is formed on the first molding layer, the second molding layer at least covering the sidewall of the second chip and the sidewall of the second heat sink; A first redistribution layer is formed on the second molding layer. The first redistribution layer is electrically connected to the front side of the second chip and is in contact with the metal thermally conductive structure of the second heat sink. as well as Remove the first carrier plate; A second redistribution layer is formed on the surface of the first molding layer away from the second molding layer. The second redistribution layer is electrically connected to the front side of the first chip and in contact with the metal thermally conductive structure of the first heat sink.

11. The processing method of the fan-out chip stacked package structure as described in claim 10, characterized in that, The step of mounting the first chip and the first heat sink onto the first carrier includes mounting at least one first interconnect onto the first carrier. The step of mounting the second chip and the second heat sink on the first molding layer includes mounting at least one second interconnect on the first interconnect; The first interconnect and the second interconnect both include a conductive structure and an insulating material that isolates the conductive structure. One end of the conductive structure of the first interconnect is electrically connected to one end of the conductive structure of the second interconnect, the other end of the conductive structure of the first interconnect is electrically connected to the second redistribution layer, and the other end of the conductive structure of the second interconnect is electrically connected to the first redistribution layer.

12. The processing method of the fan-out type chip stacked package structure as described in claim 11, characterized in that, After forming the first molding compound on the first substrate and before mounting the second chip and the second heat sink on the first molding compound, a metal interconnect layer is formed on the first molding compound. The metal interconnect layer includes a first metal pad and a second metal pad. The first metal pad covers the first chip and the first heat sink, and the second metal pad is electrically connected to the conductive structure of the first interconnect. In the step of mounting the second chip and the second heat sink on the first molding layer, the second chip and the second heat sink are mounted on the first metal pad, and the conductive structure of the second interconnect is soldered to the second metal pad.

13. The processing method of the fan-out type chip stacked package structure as described in claim 10, characterized in that, The metal thermally conductive structure is a thermally conductive pillar; in a heat sink, both ends of the thermally conductive pillar are exposed from the encapsulation material.

14. The processing method of the fan-out chip stacked package structure as described in claim 10, characterized in that, In the step of mounting the second chip and the second heat sink on the first molding layer, the back of the second chip is fixed by adhesive bonding with insulating thermally conductive adhesive; and / or, in the step of attaching the first chip and the first heat sink to the first carrier board, the back of the first chip has insulating thermally conductive adhesive.

15. The processing method of the fan-out chip stacked package structure as described in claim 10, characterized in that, Also includes: After forming a second redistribution layer on the surface of the first molding layer away from the second molding layer, a third heat sink and a passive component are mounted on the second redistribution layer. The third heat sink includes a metal thermally conductive structure and a molding material for molding the metal thermally conductive structure. The third heat sink overlaps with both the first chip and the first heat sink. An insulating thermally conductive adhesive is provided between the third heat sink and the second redistribution layer. The passive component is electrically connected to the second redistribution layer. A third molding layer is formed on the second redistribution layer, the third molding layer at least covering the sidewall of the passive component and the sidewall of the third heat sink and at least exposing the metal thermally conductive structure of the third heat sink; as well as A heat dissipation pad is formed on the third molding layer, and the heat dissipation pad is in contact with the metal thermally conductive structure of the third heat sink.

Images