Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device capable of effectively utilizing a region formed on a semiconductor element and a manufacturing method thereof. According to one embodiment, the semiconductor device includes at least one semiconductor chip, and the semiconductor chip includes a first chip, a second chip, and a third chip. The second chip is joined to the first chip on a first region of an upper surface of the first chip in an electrically connected manner, and has an area smaller than that of the first chip. The third chip is joined to the first chip on a second region of the upper surface of the first chip in an electrically connected manner, has an area smaller than that of the first chip, and has an electrical function different from that of the second chip.

Description

Technical Field

[0001] This embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In a semiconductor device manufactured by bonding two wafers together, regions are formed on the bonded semiconductor elements when the dimensions (i.e. areas) of the semiconductor elements on each wafer are different. Summary of the Invention

[0003] A semiconductor device and a method thereof are provided that can effectively utilize the region formed on a semiconductor element.

[0004] According to one embodiment, a semiconductor device includes at least one semiconductor chip, which has a first chip, a second chip, and a third chip. The second chip is electrically connected to the first chip and is bonded to the first chip in a first region on the upper surface of the first chip, having an area smaller than that of the first chip. The third chip is electrically connected to the first chip and is bonded to the first chip in a second region on the upper surface of the first chip, having an area smaller than that of the first chip, and having an electrical function different from that of the second chip. Attached Figure Description

[0005] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment. Figure 2 This is a cross-sectional view showing an example of the configuration of a semiconductor chip in the semiconductor device of the first embodiment. Figure 3A This is a cross-sectional view showing an example of the configuration of the periphery of the metal pads in the semiconductor device of the first embodiment. Figure 3B This is a cross-sectional view showing the power supply path for supplying power to a functional chip in a semiconductor device according to the first embodiment. Figure 4 This is a cross-sectional view showing an example of the configuration of the memory cell array and transistors in the semiconductor device of the first embodiment. Figure 5 This is a cross-sectional view showing an example of the configuration of the columnar portion in the semiconductor device of the first embodiment. Figure 6A This is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 6B It is a continuation Figure 6A A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6C It is a continuation Figure 6BA cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6D It is a continuation Figure 6C A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6E It is a continuation Figure 6D A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6F It is a continuation Figure 6E A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6G It is a continuation Figure 6F A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6H It is a continuation Figure 6G A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6I It is a continuation Figure 6H A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6J It is a continuation Figure 6I A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6K It is a continuation Figure 6J A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6L It is a continuation Figure 6K A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 6M It is a continuation Figure 6L A cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 7 This is a diagram showing an example of the dimensions of the array chip and the functional chip in the semiconductor device of the first embodiment. Figure 8 This is a diagram showing the dimensions of the array chip and the functional chip in a semiconductor device of a first variation of the first embodiment. Figure 9 This is a diagram showing the dimensions of the array chip and the functional chip in a semiconductor device of a second variation of the first embodiment. Figure 10 This is a diagram showing the dimensions of the array chip and the functional chip in the semiconductor device of the third variation of the first embodiment. Figure 11 This is a diagram showing the dimensions of the array chip and the functional chip in the semiconductor device of the fourth variation of the first embodiment. Figure 12This is a diagram showing the dimensions of the array chip and the functional chip in the semiconductor device of the fifth variation of the first embodiment. Figure 13 This is a cross-sectional view of a semiconductor device showing a sixth variation of the first embodiment. Figure 14 This is a cross-sectional view of a semiconductor device showing a seventh variation of the first embodiment. Figure 15 This is a cross-sectional view of a semiconductor device showing an eighth variation of the first embodiment. Figure 16 This is a side view of a semiconductor device showing a ninth variation of the first embodiment. Figure 17 This is a side view of a semiconductor device showing a tenth variation of the first embodiment. Figure 18 This is a side view showing an example of the configuration of the semiconductor device according to the second embodiment. Figure 19A This is a side view of a semiconductor device illustrating a first variation of the second embodiment. Figure 19B This is a side view of another example of a semiconductor device illustrating a first variation of the second embodiment. Figure 20 This is a side view of a semiconductor device illustrating a second variation of the second embodiment. Figure 21 This is a cross-sectional view showing an example of the configuration of a semiconductor chip in a comparative example semiconductor device. Detailed Implementation

[0006] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0007] This embodiment does not limit the invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as the actual figures. In the specification and drawings, the same reference numerals are used for elements that are the same as those described with respect to the drawings, and detailed descriptions are omitted where appropriate.

[0008] (First Implementation) Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the first embodiment. Figure 1 The X and Y directions, which are parallel to and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the wiring substrate 10, are shown. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not align with the direction of gravity.

[0009] Semiconductor device 1 includes a wiring substrate 10, semiconductor chips 20, 30-33, adhesive layers 40-43, resin layer 80, bonding wires 90, and sealing resin 91. The wiring substrate 10 is an example of a substrate, a second substrate, or a third substrate. The semiconductor chip 30 is an example of a first semiconductor chip or a third semiconductor chip. The semiconductor chip 31 is an example of a second semiconductor chip or a fourth semiconductor chip. The bonding wires 90 are examples of leads, second leads, or third leads. Semiconductor device 1 is, for example, a package for NAND flash memory.

[0010] The wiring substrate 10 is, for example, a printed circuit board or interposer comprising a wiring layer 11 and an insulating layer 15. The wiring layer 11 is, for example, made of a low-resistance metal such as copper (Cu), nickel (Ni), or alloys thereof. The insulating layer 15 is, for example, made of an insulating material such as glass epoxy resin. Figure 1 In the example shown, wiring layers 11 are provided only on the surface and back side of insulating layer 15. However, wiring substrate 10 may also have a multilayer wiring structure consisting of multiple wiring layers 11 and multiple insulating layers 15 stacked together. Wiring substrate 10 may also have through electrodes (pillar electrodes) that extend through its surface and back side, for example, like an interposer.

[0011] On the wiring layer 11 on the surface side of the insulating layer 15, a solder resist layer 14 is provided, which constitutes the surface (surface F1) of the wiring substrate 10. The solder resist layer 14 is an insulating layer used to protect the wiring layer 11 from the metal material (not shown) that connects the semiconductor chip 20 to the wiring layer 11 and to suppress short circuit defects.

[0012] On the wiring layer 11 on the back side of the insulating layer 15, a solder mask layer 14 constituting the back side of the wiring substrate 10 is provided. Metal bumps 13 are provided on the wiring layer 11 exposed from the solder mask layer 14. The metal bumps 13 are provided for electrically connecting other components (not shown) to the wiring substrate 10.

[0013] Semiconductor chip 20 is, for example, a controller chip that controls a memory chip. Semiconductor elements (not shown) are disposed on the side of semiconductor chip 20 facing the wiring substrate 10. These semiconductor elements may, for example, be CMOS (Complementary Metal Oxide Semiconductor) circuits constituting the controller. Electrode posts (not shown) electrically connected to the semiconductor elements are disposed on the back side (lower surface) of semiconductor chip 20. These electrode posts may be made of low-resistance metal materials such as copper, nickel, or alloys thereof.

[0014] A metal material is disposed around the electrode posts that serve as connecting bumps. The electrode posts are electrically connected to the wiring layer 11 exposed at the opening of the solder mask layer 14 via the metal material. The metal material is, for example, a low-resistance metal such as solder, silver, or copper. Thus, the metal material electrically connects the electrode posts of the semiconductor chip 20 to the wiring layer 11 of the wiring substrate 10.

[0015] A resin layer 80 is provided in the area surrounding the metal material and in the area between the semiconductor chip 20 and the wiring substrate 10. The resin layer 80 is formed, for example, by curing an underfill resin, and covers and protects the area around the semiconductor chip 20.

[0016] Semiconductor chip 30 is, for example, a memory chip containing NAND flash memory. Semiconductor chip 30 has semiconductor elements (not shown) on its surface (upper surface). The semiconductor elements can be a memory cell array and its peripheral circuitry (CMOS circuitry). The memory cell array can be a three-dimensional memory cell array composed of multiple memory cells arranged in three dimensions. Semiconductor chip 30 is bonded (i.e., disposed) on semiconductor chip 20 via adhesive layer 40. Additionally, semiconductor chip 31 is bonded to semiconductor chip 30 via adhesive layer 41. Semiconductor chip 32 is bonded to semiconductor chip 31 via adhesive layer 42. Semiconductor chip 33 is bonded to semiconductor chip 32 via adhesive layer 43. Semiconductor chips 31-33, for example, are memory chips containing NAND flash memory, similar to semiconductor chip 30. Semiconductor chips 30-33 can be the same type of memory chip. In the figure, in addition to semiconductor chip 20, which serves as a controller chip, four semiconductor chips 30-33, which serve as memory chips, are stacked. However, the number of layers in a semiconductor chip can be 3 or less, or 5 or more. As described later, as semiconductor elements, semiconductor chips 30-33 also have a functional chip CH3 (see reference). Figure 2 The functional chip CH3 is a different chip from the array chip CH2. Furthermore, the term "functional chip CH3" refers to semiconductor chips other than memory types such as NAND and DRAM (Dynamic Random Access Memory). Additionally, the term "functional chip CH3" refers to a chip that can add functions (such as high-speed operation, high voltage withstand, and power supply stabilization) to semiconductor memory devices compared to those that only have CMOS circuitry and the array chip CH2. The functional chip CH3 can also be called a chip component, an additional chip component, or an additional chip.

[0017] Bonding wire 90 connects to any pad on the wiring substrate 10 and the semiconductor chips 30-33. That is, bonding wire 90 connects the wiring substrate 10 to the pads on the semiconductor chips 30-33. For connection using bonding wire 90, the semiconductor chips 30-33 are stacked with a offset corresponding to the amount of pads. Furthermore, since semiconductor chip 20 is flip-chip connected via electrode posts, it is not wire-bonded. However, semiconductor chip 20 may also be wire-bonded in addition to connection using electrode posts.

[0018] Furthermore, the sealing resin 91 seals the semiconductor chips 20, 30-33, the adhesive layers 40-43, the spacers 50, the bonding wires 90, etc. Thus, the semiconductor device 1 constructs a semiconductor package by mounting multiple semiconductor chips 20, 30-33 on the wiring substrate 10.

[0019] Next, the details of semiconductor chips 30 to 33 will be explained.

[0020] Figure 2 This is a cross-sectional view showing an example of the configuration of semiconductor chips 30 and 31 in the semiconductor device 1 of the first embodiment. Additionally, Figure 2 Two semiconductor chips 30 and 31 are shown. Semiconductor chip 31 will be described below, but semiconductor chips 30, 32, and 33 also have the same configuration as semiconductor chip 31. Figure 2 In the example shown, semiconductor chips 30 and 31 are omitted in order to provide a detailed explanation. Figure 1 The illustration shows the semiconductor chip 20.

[0021] Semiconductor chip 31 includes a circuit chip CH1, an array chip CH2, and a functional chip CH3. Circuit chip CH1 is an example of a first chip. Array chip CH2 is an example of a second chip. Alternatively, a DRAM chip, SRAM (Static Random Access Memory) chip, or the like can be used instead of array chip CH2 as the second chip. Functional chip CH3 is an example of a third chip.

[0022] Circuit chip CH1 functions as a control circuit (i.e., a logic circuit) that controls the operation of array chip CH2. Circuit chip CH1 can also function as a control circuit that controls the operation of functional chip CH3.

[0023] The circuit chip CH1 has a semiconductor substrate 111, an interlayer insulating film 112, a transistor (i.e., a semiconductor element) 113, and a metal pad BP1. The metal pad BP1 is an example of a lower pad.

[0024] A semiconductor substrate 111 is disposed on the lower surface side of the circuit chip CH1. The semiconductor substrate 111 is, for example, a silicon (Si) substrate.

[0025] An interlayer insulating film 112 is disposed on a semiconductor substrate 111. The interlayer insulating film 112 is, for example, a silicon oxide film, or a laminate containing a silicon oxide film and other insulating films.

[0026] Multiple transistors 113 are disposed above the semiconductor substrate 111. The transistors 113 constitute peripheral circuitry (CMOS circuitry) as control circuitry for the memory cell array 123 of the array chip CH2. This control circuitry is electrically connected to the metal pad BP1. The transistors 113 can also also constitute peripheral circuitry as control circuitry for a functional chip CH3.

[0027] Metal pads BP1 are disposed on the bonding surface (i.e., the mating surface) S, which is bonded to the array chip CH2 and the functional chip CH3. The bonding surface S is also the upper surface of the circuit chip CH1, the lower surface of the array chip CH2, and the lower surface of the functional chip CH3. The metal pad BP1 located under the array chip CH2 is bonded to the metal pad BP2 of the array chip CH2. The metal pad BP1 located under the functional chip CH3 is bonded to the metal pad BP3 of the functional chip CH3. Metal pad BP2 is an example of an upper pad. Metal pads BP1, BP2, and BP3 are, for example, Cu layers.

[0028] The array chip CH2 is electrically connected to the circuit chip CH1 by bonding (i.e., adhering) it to the circuit chip CH1 in a first region R1 on the upper surface of the circuit chip CH1. The area of ​​the array chip CH2 is smaller than the area of ​​the circuit chip CH1. Furthermore, the areas of the circuit chip CH1 and the array chip CH2 are measured from the Z-direction.

[0029] The array chip CH2 has a semiconductor substrate 121, an interlayer insulating film 122, a memory cell array (i.e., semiconductor element) 123, a contact plug C1, a metal pad BP2, and a metal pad WP. The metal pad WP is an example of a pad, a second pad, a third pad, or a fourth pad.

[0030] A semiconductor substrate 121 is disposed on the upper surface side of the array chip CH2. The semiconductor substrate 121 is, for example, a silicon (Si) substrate.

[0031] An interlayer insulating film 122 is disposed below the semiconductor substrate 121. The interlayer insulating film 122 is, for example, a silicon oxide film, or a laminated film comprising a silicon oxide film and other insulating films.

[0032] The memory cell array 123 is disposed below the semiconductor substrate 121. The memory cell array 123 is, for example, a non-volatile memory. The memory cell array 123 has a stepped structure. The memory cell array 123 is electrically connected to the metal pad BP2.

[0033] Contact plug C1 electrically connects the conductive layer (word line WL) of memory cell array 123 to metal pad BP2.

[0034] Metal pad BP2 is disposed on the bonding surface S that bonds to the circuit chip CH1. Metal pad BP2 bonds to metal pad BP1 of the circuit chip CH1. Multiple metal pads BP2 may be, for example, Cu layers.

[0035] Metal pads WP are disposed on the upper surface of the array chip CH2. Metal pads WP function as external connection pads (bonding pads) for semiconductor chips 30-33. That is, metal pads WP are connected to bonding lines 90. Therefore, bonding lines 90 electrically connect metal pads WP to the wiring substrate 10. Metal pads WP may contain conductive metals such as nickel (Ni).

[0036] The functional chip CH3 is electrically connected to the circuit chip CH1 by bonding (i.e., attaching) it to a second region R2 on the upper surface of the circuit chip CH1, which is different from the first region R1. As described above, the functional chip CH3, like the array chip CH2, has a metal pad BP3. Furthermore, the functional chip CH3 is bonded (i.e., electrically connected) to the metal pad BP1 of the circuit chip CH1 via the metal pad BP3. The area of ​​the functional chip CH3 is smaller than the area of ​​the circuit chip CH1. Additionally, the area of ​​the functional chip CH3 is the area observed from the Z-direction.

[0037] By placing a functional chip CH3 on a second region R2, which is different from the first region R1 where the array chip CH2 is located, it is possible to fill the step difference caused by the area difference (i.e., the size difference) between the circuit chip CH1 and the array chip CH2. More specifically, in Figure 2In the example shown, the upper surface of the functional chip CH3 is approximately parallel to the upper surface of the array chip CH2. In other words, the thickness of the functional chip CH3 (i.e., the dimension in the Z direction) is equal to the thickness of the array chip CH2. By making the thickness of the functional chip CH3 equal to the thickness of the array chip CH2, the step difference caused by the area difference between the circuit chip CH1 and the array chip CH2 can be filled in a way that makes it approximately flat. The functional chip CH3 of the semiconductor chip 30 supports the upper semiconductor chip 31 of the semiconductor chip 30. By having the upper semiconductor chip 31 supported by the lower functional chip CH3, risks during assembly, such as chip tilting, can be suppressed. That is, the area of ​​the upper surface of the lower semiconductor chips 30-32 can be increased, thereby enabling proper stacking (chip bonding) of the semiconductor chips 30-33.

[0038] In addition, Figure 2 In the example shown, a component 115 is disposed between the array chip CH2 and the functional chip CH3. Component 115 may contain, for example, a resin such as epoxy resin. When component 115 is a resin, it may contain filler. The resin of component 115 may also be a different material from the sealing resin 91. In this case, for example, the filler size differs between component 115 and the sealing resin 91. Alternatively, the resin of component 115 may be the same material as the sealing resin 91. In this case, for example, the filler size is the same between component 115 and the sealing resin 91. Component 115 is not limited to resin; for example, it may be an insulating film such as SiO2.

[0039] The functional chip CH3 not only functions as a spacer filling the step difference caused by the area difference between the circuit chip CH1 and the array chip CH2, but also functions as one of the semiconductor elements constituting the semiconductor device 1 (i.e., semiconductor chips 30-33), performing an electrical function within the semiconductor device 1. In other words, the functional chip CH3 is not a spacer without electrical function like resin, but rather a spacer with electrical function. In this specification, the "electrical function" of a chip refers to the function of transmitting, receiving, or simultaneously transmitting and receiving at least one of power (i.e., at least one of current and voltage), control signals, and data with other chips.

[0040] The area of ​​the functional chip CH3 is different from that of the array chip CH2. By making the area of ​​the functional chip CH3 different from that of the array chip CH2, the limitation on the area of ​​the functional chip CH3 can be alleviated. In addition, the area of ​​the functional chip CH3 can be selected according to the area difference between the circuit chip CH1 and the array chip CH2 and the application of the functional chip CH3.

[0041] The functional chip CH3 can be a boost circuit. When the functional chip CH3 is a boost circuit, it can supply a large current to the semiconductor device 1, supply multiple voltages, and improve power conversion efficiency.

[0042] The functional chip CH3 can also be a passive component such as a capacitor. When the functional chip CH3 is a passive component, it can stabilize the power supply of the semiconductor device 1.

[0043] The functional chip CH3 can also be a heater. When the functional chip CH3 is a heater, it can heat the array chip CH2 for regeneration.

[0044] The functional chip CH3 can also be a Peltier element. When the functional chip CH3 is a Peltier element, it regenerates and cools the array chip CH2.

[0045] The functional chip CH3 can also be RAM such as SRAM and DRAM. When the functional chip CH3 is RAM, it enables the semiconductor device 1 to operate at high speed.

[0046] The functional chip CH3 can also be a controller for the array chip CH2. By configuring the controller adjacent to the array chip CH2, the transmission path between the controller and the array chip CH2 can be shortened. In addition, the semiconductor device 1 can be miniaturized.

[0047] The CH3 chip with functional characteristics can also be made of heterogeneous materials other than silicon (such as GaN, SiC, etc.). This improves the voltage withstand capability of the CH3 chip with functional characteristics, enabling its use in high-voltage power supplies.

[0048] The CH3 functional chip is not limited to having a single electrical function; it can also be constructed by combining components with multiple electrical functions.

[0049] Figure 3A This is a cross-sectional view showing an example of the configuration of the periphery of the metal pad WP in the semiconductor device 1 of the first embodiment. Figure 3A yes Figure 2 An enlarged view of the dashed box D shown.

[0050] Alternatively, it can be like Figure 3A As shown, component 115 is disposed on the right side of array chip CH2.

[0051] A recess 1211 is provided on the semiconductor substrate 121. The recess 1211 is provided in such a way that it extends from the upper surface to the lower surface of the semiconductor substrate 121.

[0052] The array chip CH2 also has an insulating film 124.

[0053] The insulating film 124 is a protective film (passivation film), for example, containing polyimide. The insulating film 124 is disposed on the side surface of the recess 1211 and the upper surface of the semiconductor substrate 121. Figure 3A In the example shown, the insulating film 124 is not disposed on the component 115. This is because, in order to prevent the insulating film 124 from remaining in the dicing area when monolithically forming semiconductor chips 30-33, a portion of the insulating film 124 is removed. However, as... Figure 6M As shown, the insulating film 124 can also be provided on the member 115, or it can be provided in a way that covers a part of the member 115.

[0054] A metal pad WP is disposed above the semiconductor substrate 121. More specifically, the metal pad WP is disposed on the insulating film 124. The metal pad WP is disposed such that it extends laterally from the bottom surface of the recess 1211 to the top surface of the recess 1211. That is, the metal pad WP is integrally formed with the wiring extending from the bottom surface of the recess 1211 to the top surface of the semiconductor substrate 121. Therefore, the metal pad WP extends through the semiconductor substrate 121.

[0055] The metal pad WP also has metal components 131 and 132.

[0056] Metal component 131, for example, contains nickel (Ni).

[0057] Metal component 132 is provided to cover metal component 131. Metal component 132 may contain, for example, gold (Au).

[0058] The array chip CH2 also has a contact plug C2.

[0059] The contact plug (pillar electrode) C2 is disposed in such a manner that it penetrates the interlayer insulating film 122 and extends from the bottom surface of the recess 1211 (the lower surface of the metal pad WP) to the metal pad BP2. Therefore, the contact plug C2 electrically connects the metal pad WP to the circuit chip CH1. The contact plug C2 may contain, for example, a conductive metal such as tungsten (W).

[0060] Figure 3B This is a cross-sectional view showing the power supply path P in the semiconductor device 1 of the first embodiment, which supplies power to the functional chip CH3. Power is supplied via a bonding wire 90, one end of which is connected to a metal pad WP (see reference). Figure 2 The wiring substrate 10, connected to the other end of the bonding line 90, supplies power (not shown) to the array chip CH2, which has metal pads WP. Additionally, as... Figure 3BAs shown, a power supply path P is formed between the metal pad WP and the functional chip CH3, supplying power from the power source to the functional chip CH3. The power supply path P passes through the contact plug C2 included in the circuit chip CH1. Therefore, even if the metal pad WP is not provided on the functional chip CH3, power can be supplied to the functional chip CH3 via the circuit chip CH1.

[0061] Next, the configuration of the memory cell array 123 and the transistor 113 will be described.

[0062] Figure 4 This is a cross-sectional view showing an example of the configuration of the memory cell array 123 and transistor 113 in the first embodiment.

[0063] The array chip CH2 has multiple word lines WL and source lines SL as electrode layers within the memory cell array 123. Figure 4 The stepped structure 201 of the memory cell array 123 is shown. Each word line WL is electrically connected to the word wiring layer 202 via a contact plug C1. Each columnar portion CL passing through multiple word lines WL is electrically connected to the bit line BL via a through-hole plug 203, and is also electrically connected to the source line SL. The source line SL comprises a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metal layer.

[0064] The circuit chip CH1 includes multiple transistors 113. Each transistor 113 includes a gate electrode 301 disposed on a semiconductor substrate 111 separated by a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the semiconductor substrate 111. Additionally, the circuit chip CH1 includes multiple contact plugs 302, a wiring layer 303, and a wiring layer 304. The multiple contact plugs 302 are disposed on the gate electrode 301, source diffusion layer, or drain diffusion layer of the transistor 113. The wiring layer 303 is disposed on the contact plugs 302 and includes multiple wirings. The wiring layer 304 is disposed on the wiring layer 303 and includes multiple wirings.

[0065] The circuit chip CH1 also includes a wiring layer 305, multiple via plugs 306, and multiple metal pads BP1. The wiring layer 305 is disposed on the wiring layer 304 and includes multiple wirings. The multiple via plugs 306 are disposed on the wiring layer 305, and the multiple metal pads BP1 are disposed on the via plugs 306. The metal pads BP1 are, for example, a Cu (copper) layer or an Al (aluminum) layer.

[0066] The array chip CH2 includes multiple metal pads BP2 disposed on metal pads BP1, and multiple via plugs 307 disposed on the metal pads BP2. Additionally, the array chip CH2 includes a wiring layer 308 disposed on the via plugs 307 and comprising multiple wirings. The metal pads BP2 are, for example, Cu layers or Al layers.

[0067] Figure 5 This is a cross-sectional view showing an example of the structure of the columnar portion CL in the first embodiment.

[0068] like Figure 5 As shown, the memory cell array 123 includes an interlayer insulating film 122 (see reference). Figure 4 Multiple word lines WL and multiple insulating layers 401 are alternately stacked on the surface. The word lines WL are, for example, W (tungsten) layers. The insulating layers 401 are, for example, silicon oxide films.

[0069] The columnar portion CL sequentially comprises a barrier insulating film 402, a charge storage layer 403, a tunnel insulating film 404, a channel semiconductor layer 405, and a core insulating film 406. The charge storage layer 403 is, for example, a silicon nitride film, formed on the side of the word line WL and the insulating layer 401, separated by the barrier insulating film 402. The charge storage layer 403 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 405 is, for example, a polysilicon layer, formed on the side of the charge storage layer 403, separated by the tunnel insulating film 404. The barrier insulating film 402, the tunnel insulating film 404, and the core insulating film 406 are, for example, silicon oxide films or metal insulating films.

[0070] Next, the manufacturing method of semiconductor device 1 will be described.

[0071] Figures 6A to 6M This is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0072] First, such as Figure 6A As shown, an array wafer W2 is prepared. The preparation of the array wafer W2 includes the steps of forming a memory cell array 123 on a semiconductor substrate 121 and coating a protective film 125 on an interlayer insulating film 122. The protective film 125 is, for example, an alkali-soluble film. The step of coating the protective film 125 may also be omitted.

[0073] After preparing the array wafer W2, as follows Figure 6B As shown, edge trimming is performed on array wafer W2. After edge trimming, a protective tape BT is attached to array wafer W2. The protective tape BT is used in the back-side grinding of array wafer W2. After attaching the protective tape BT, back-side grinding of array wafer W2 is performed. By performing back-side grinding, semiconductor substrate 121 is thinned.

[0074] After backside grinding, as Figure 6CAs shown, a dicing tape DT1 is attached to the array wafer W2. After attaching the dicing tape DT1, the protective tape BT is peeled off. After peeling off the protective tape BT, the peeled surface of the protective film 125 is cleaned. After cleaning the peeled surface of the protective film 125, the array wafer W2 is diced. By dicing, the array wafer W2 is monolithically divided into multiple array chips CH2. The dicing process can also be omitted after cleaning the peeled surface of the protective film 125. It is sufficient to perform the dicing process before bonding the multiple array chips CH2 and the multiple functional chips CH3 onto the circuit wafer W1 described later.

[0075] After cutting, such as Figure 6D As shown, multiple monolithically formed array chips CH2 are transferred onto the dicing tape DT2. The transfer process onto the dicing tape DT2 can also be omitted. After transferring the multiple array chips CH2 onto the dicing tape DT2, the protective film 125 is removed. The removal of the protective film 125 can also be omitted. After removing the protective film 125, a bonding pretreatment is performed. The bonding pretreatment is a pretreatment used to bond the array chips CH2 onto the circuit wafer W1. The bonding pretreatment includes, for example, N2 plasma treatment and water washing.

[0076] For the functional chip CH3, for example, it also undergoes the same process as the array chip CH2. Figures 6A to 6D This process prepares the wafer (i.e., semiconductor substrate 121) for bonding the monolithized functional chip CH3 onto the circuit wafer W1. Specifically, first, a wafer with the functional chip CH3 formed on it (i.e., semiconductor substrate 121) is prepared before monolithization. Next, edge trimming, attachment of the protective tape BT, and back-side grinding are performed sequentially. Then, the functional chip CH3 is monolithized by sequentially attaching the dicing tape DT1, peeling off the protective tape BT, cleaning the peeled surface of the protective film 125, and dicing. Then, transfer to the dicing tape DT2, removal of the protective film 125, and bonding pretreatment are performed sequentially. The transfer to the dicing tape DT2 and the removal of the protective film 125 can be omitted. The manufacturing method of the functional chip CH3 is not limited to the above methods.

[0077] In addition, such as Figure 6E As shown, a circuit wafer W1 is prepared. The preparation of the circuit wafer W1 includes the process of forming transistors 113 on a semiconductor substrate 111.

[0078] After preparing the circuit wafer W1, as follows Figure 6FAs shown, a protective film 114 is applied. The process of applying the protective film 114 can also be omitted. After applying the protective film 114, transistors 113 on the semiconductor substrate 111 are monolithically formed using laser grooving. The process of monolithizing transistors 113 can also be omitted. For example, monolithization can be performed simultaneously when a circuit wafer W1, which is bonded with multiple array chips CH2 and multiple functional chips CH3 (described later), is monolithically formed into multiple circuit chips CH1. The laser grooving is performed according to the dimensions of the circuit chip CH1. Monolithization of transistors 113 can also be performed by other methods such as blade cutting or stealth cutting using lasers.

[0079] After monolithizing transistor 113, as follows: Figure 6G As shown, the protective film 114 is removed. After removing the protective film 114, a bonding pretreatment is performed on the circuit wafer W1. After the bonding pretreatment of the circuit wafer W1, multiple array chips CH2 and multiple functional chips CH3 are bonded on the circuit wafer W1. When bonding the array chips CH2 and functional chips CH3 on the circuit wafer W1, the circuit wafer W1, the array chips CH2, and the functional chips CH3 are annealed. By bonding the array chips CH2 and functional chips CH3 on the circuit wafer W1, as shown... Figure 3A and Figure 4 As shown, metal pads BP1 and BP2 are bonded to each other. The array chip CH2 is bonded to the circuit wafer W1 in a manner that electrically connects the circuit wafer W1 (i.e., circuit chip CH1) to the array chip CH2 by bonding the metal pads BP1 and BP2 together. Conversely, the functional chip CH3 is bonded to the circuit wafer W1 in a manner that electrically connects the circuit wafer W1 to the functional chip CH3. Annealing can be performed in a mixed gas (e.g., a reducing gas mixture of hydrogen and nitrogen).

[0080] After bonding the array chip CH2 and the functional chip CH3 onto the circuit wafer W1, as follows Figure 6H As shown, a component 115 is formed on the circuit wafer W1, the array chip CH2, and the functional chip CH3. The component 115 is, for example, a resin such as epoxy resin. The component 115 may also be a material other than resin such as SiO2. After forming the component 115, the bevel of the component 115 is ground.

[0081] After bevel grinding of component 115, as Figure 6IAs shown, component 115 undergoes back-side grinding. After back-side grinding, component 115 is degassed and annealed (i.e., degassing). Through back-side grinding and degassing annealing, the height of the upper surface of component 115 becomes approximately the same as the height of the upper surface of the semiconductor substrate 121 containing array chip CH2 and functional chip CH3. Furthermore, back-side grinding is performed, for example, by CMP (Chemical Mechanical Polishing).

[0082] exist Figures 6J to 6M In the figure, the cross-sectional view shown by reference numeral B is an enlarged view of the dashed frame Dj to Dm on the cross-sectional view shown by reference numeral A. The figure shown by reference numeral A is merely an auxiliary figure used to show the range of the dashed frame Dj to Dm (i.e., the range of the enlarged view of reference numeral B), and is shown with the same appearance regardless of the progress of the process.

[0083] After the back side of component 115 is ground and degassed and annealed, as follows Figure 6J As shown, a recess 1211 is formed on the semiconductor substrate 121. That is, a recess 1211 extending from the upper surface to the lower surface of the semiconductor substrate 121 is formed on the semiconductor substrate 121 disposed on the upper surface side of the array chip CH2. By forming the recess 1211, the upper end of the contact plug C2 is exposed. The recess 1211 is formed, for example, by photolithography and RIE (Reactive Ion Etching).

[0084] After forming the recess 1211, as Figure 6K As shown, an insulating film 124 is formed. The insulating film 124 is formed, for example, on the side of the recess 1211 and on the semiconductor substrate 121. The insulating film 124 is formed, for example, by photolithography and curing. The insulating film 124 has an opening at the recess 1211.

[0085] After forming the insulating film 124, a seed layer (not shown) is formed. The seed layer may contain, for example, titanium (Ti). The seed layer is formed, for example, by sputtering or the like, on the entire surface of the substrate layer (i.e., the upper end of the insulating film 124 and the contact plug C2). After forming the seed layer, as... Figure 6L As shown, a photolithography method is used to pattern the resist 116 such that an opening 116a is formed at the location where the metal pad WP is formed. After patterning the resist 116, metal components 131 and 132 are formed within the opening 116a by a plating method. By forming a seed layer and metal components 131 and 132, the metal pad WP is formed on the upper surface of the array chip CH2. More specifically, the metal pad WP is integrally formed with the wiring extending from the bottom surface of the recess 1211 to the top of the semiconductor substrate 121, and is disposed on the top of the semiconductor substrate 121.

[0086] After forming the metal pad WP, ​​as Figure 6M As shown, resist 116 is stripped. After stripping resist 116, the seed layer (not shown) is removed except for the seed layer under the metal pad WP. After removing the seed layer, a UBM (Under Bump Metal) plating layer (not shown) is formed. The UBM plating layer is formed, for example, by wet electroplating. After forming the UBM plating layer, dicing is performed. By dicing, the circuit wafer W1 is monolithically divided into multiple circuit chips CH1 (i.e., semiconductor chips 30-33). In addition, Figure 6M The simplified diagram shows two circuit chips CH1 after being monolithically divided by cutting. Additionally, in... Figure 6M In the example shown, an insulating film 124 is present on component 115 at the right end of array chip CH2. However, it is also possible to... Figure 3A As shown, the insulating film 124 is removed from the component 115 before cutting.

[0087] After the semiconductor chips 30-33 are monolithically processed, they are mounted on top of the wiring substrate 10 for packaging and assembly. Through this packaging and assembly process, the semiconductor chips 30-33 are completed. Figure 1 and Figure 2 Semiconductor device 1 is shown.

[0088] Alternatively, the electrical characteristics of the semiconductor chips 30-33 can be measured by connecting wiring on the metal pad WP before the circuit wafer W1 is monolithically converted into semiconductor chips 30-33. By measuring the electrical characteristics of the semiconductor chips 30-33, selection of the semiconductor chips 30-33 can be performed. Therefore, the metal pad WP can be used as a probe terminal before the circuit wafer W1 is monolithically converted into semiconductor chips 30-33.

[0089] Figure 7 This is a diagram showing an example of the dimensions of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 of the first embodiment. Figure 7 In the figures, reference numeral A is a top view of the array chip CH2 and the functional chip CH3 attached to the circuit chip CH1. Reference numeral B is a front view of the array chip CH2 and the functional chip CH3 attached to the circuit chip CH1. Reference numeral C is a side view of the array chip CH2 and the functional chip CH3 attached to the circuit chip CH1.

[0090] exist Figure 7 In the example shown, the circuit chip CH1, the array chip CH2, and the functional chip CH3 have a rectangular shape when viewed from the Z direction (i.e., viewed from above). Figure 7As shown, the area of ​​array chip CH2 is smaller than the area of ​​circuit chip CH1. More specifically, in... Figure 7 In the example shown, the Y-direction dimension of array chip CH2 is equal to the Y-direction dimension of circuit chip CH1. Figure 7 In the example shown, the Y direction is orthogonal to the direction in which the array chip CH2 and the functional chip CH3 are adjacent (i.e., the X direction) and the thickness direction of the circuit chip CH1 (i.e., the Z direction). Furthermore, the dimension of the array chip CH2 in the X direction is smaller than the dimension of the circuit chip CH1 in the X direction.

[0091] like Figure 7 As shown, the area of ​​the functional chip CH3 is also smaller than the area of ​​the circuit chip CH1. More specifically, in... Figure 7 In the example shown, the Y-direction dimension of the functional chip CH3 is equal to the Y-direction dimension of the circuit chip CH1. Furthermore, the X-direction dimension of the functional chip CH3 is smaller than the X-direction dimension of the circuit chip CH1. Figure 7 In the example shown, the area of ​​array chip CH2 is smaller than the area of ​​functional chip CH3. The relationship between the areas of array chip CH2 and functional chip CH3 can also be explained by… Figure 7 The situation is the opposite. The array chip CH2 and the functional chip CH3 are bonded to different regions R1 and R2 on the upper surface of the circuit chip CH1.

[0092] according to Figure 7 In the example shown, the Y-direction dimension of array chip CH2 is equal to the Y-direction dimension of functional chip CH3. By making the Y-direction dimension of array chip CH2 equal to the Y-direction dimension of functional chip CH3, for example, when using passive components as functional chip CH3 to improve the power supply characteristics of array chip CH2, the power supply characteristics of each bit line BL of array chip CH2 can be uniformly improved.

[0093] In addition, according to Figure 7 In the example shown, the Y-direction dimensions of array chip CH2 and functional chip CH3 are equal to the Y-direction dimension of circuit chip CH1, and the combined X-direction dimensions of array chip CH2 and functional chip CH3 are slightly smaller than the X-direction dimension of circuit chip CH1. In other words, the combined area of ​​array chip CH2 and functional chip CH3 is slightly smaller than the area of ​​the upper surface of circuit chip CH1. Therefore, almost the entire upper surface area of ​​circuit chip CH1 can be filled using array chip CH2 and functional chip CH3. Furthermore, in Figure 7In the example shown, the dimension of array chip CH2 in the X direction is smaller than the dimension of functional chip CH3 in the X direction. The relationship between the dimensions of array chip CH2 and functional chip CH3 in the X direction can also be described as follows: Figure 7 The situation is the opposite.

[0094] according to Figure 7 In the example shown, since almost the entire area of ​​the upper surface of the circuit chip CH1 can be filled using the array chip CH2 and the functional chip CH3, the amount of resin (i.e., component 115) used to fill the space on the upper surface of the circuit chip CH1 can be minimized. Because the amount of resin used, which has a large difference in coefficient of linear expansion relative to the circuit chip CH1, can be reduced, warping of the semiconductor chips 30-33 can be suppressed. Furthermore, the formation of component 115 can be omitted to reduce the manufacturing process. By reducing the manufacturing process, manufacturing time and material usage can be shortened. As a result, the manufacturing cost of the semiconductor device 1 can be expected to be reduced.

[0095] As described above, according to the first embodiment, the semiconductor device 1 includes at least one semiconductor chip 30-33 having a circuit chip CH1, an array chip CH2, and a functional chip CH3. The array chip CH2 is electrically connected to the circuit chip CH1 in a first region R1 on the upper surface of the circuit chip CH1. The functional chip CH3 is electrically connected to the circuit chip CH1 in a second region R2 on the upper surface of the circuit chip CH1. The array chip CH2 and the functional chip CH3 have areas smaller than the area of ​​the circuit chip CH1.

[0096] Therefore, even if a difference arises between the element area of ​​the array chip CH2 and the element area of ​​the circuit chip CH1 due to the miniaturization of the memory cell array 123, the area on the circuit chip CH1 (i.e., the space area on the second region R2) caused by the difference can be filled using the functional chip CH3. By filling the area on the circuit chip CH1 with the functional chip CH3, risks during assembly, such as chip tilting, can be suppressed. That is, by eliminating the step difference between the circuit chip CH1 and the array chip CH2, the assembly of the semiconductor device 1 based on the stacking (i.e., chip bonding) of semiconductor chips 30 to 33 can be performed easily and appropriately.

[0097] Figure 21 This is a cross-sectional view showing an example of the configuration of semiconductor chips 30 and 31 in the comparative example semiconductor device 1. Figure 21 In the example shown, a resin spacer SP is disposed in a region on the circuit chip CH1. According to... Figure 21The example shown can eliminate the step difference between circuit chip CH1 and array chip CH2. However, since the resin spacer SP is not electrically functional, the area on circuit chip CH1 cannot be used electrically efficiently.

[0098] In contrast, according to the first embodiment, instead of using resin spacers SP or dummy chips, a functional chip CH3 is used to fill the area on the circuit chip CH1, thereby enabling the electrical efficient utilization of the area on the circuit chip CH1. In other words, the area on the circuit chip CH1 can be utilized to improve the electrical performance of the semiconductor device 1. Furthermore, the difference between the coefficient of linear expansion of the functional chip CH3 and the coefficient of linear expansion of the circuit chip CH1 is smaller than the difference between the coefficient of linear expansion of the resin spacer SP and the coefficient of linear expansion of the circuit chip CH1. Therefore, compared to the case where resin spacers SP are used, the warpage of the semiconductor chips 30-33 caused by the difference in coefficients of linear expansion can be reduced.

[0099] In the first embodiment, several variations can be applied.

[0100] (First variation) First, a first variation of the first embodiment, in which the dimension of the functional chip CH3 in the Y direction is smaller than the dimension of the array chip CH2 in the Y direction, will be described, focusing on the differences from the embodiment described above. Figure 8 This is a diagram showing the dimensions of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 of the first variant of the first embodiment.

[0101] exist Figure 7 The example illustrates that the Y-direction dimension of the functional chip CH3 is equal to the Y-direction dimension of the array chip CH2. In contrast, in... Figure 8 In the example shown, the Y-direction dimension of the functional chip CH3 is smaller than the Y-direction dimension of the array chip CH2. More specifically, the -Y-direction end of the functional chip CH3 is located further in the Y-direction than the -Y-direction end of the circuit chip CH1. Furthermore, the Y-direction end of the functional chip CH3 is located further in the -Y-direction than the Y-direction end of the circuit chip CH1. More specifically, the functional chip CH3 is located in the center of the second region R2 in the Y-direction.

[0102] according to Figure 8 In the example shown, since the functional chip CH3 can be formed in a size that allows it to meet the required performance, the manufacturing cost of the functional chip CH3 can be reduced.

[0103] (Second variation) Next, focusing on the differences from the above-described embodiments, a second variation of the first embodiment, in which multiple functional chips CH3A and CH3B of different sizes are provided along the Y direction, will be described. Figure 9 This is a diagram showing the dimensions of the array chip CH2 and the functional chips CH3A and CH3B in the semiconductor device 1 of the second modification of the first embodiment. Figure 9 In the example shown, two functional chips CH3A and CH3B of different sizes are arranged at intervals along the Y direction in the second region R2. The area of ​​functional chip CH3A is smaller than that of functional chip CH3B. That is, the Y-direction dimension of functional chip CH3A is smaller than that of functional chip CH3B. Furthermore, the X-direction dimension of functional chip CH3A is equal to that of functional chip CH3B. The function of functional chip CH3A may differ from that of functional chip CH3B. For example, functional chip CH3A could be a boost circuit, while functional chip CH3B could be a capacitor storing the voltage boosted by the boost circuit.

[0104] according to Figure 9 The example shown can improve the design freedom of semiconductor device 1 by alleviating the constraints on the area, number and function of functional chips CH3A and CH3B.

[0105] (Third variation) Next, focusing on the differences from the above-described embodiments, a third variation of the first embodiment, which includes multiple functional chips CH3 with dimensions in the Y direction equal to those in the Y direction of the array chip CH2, will be described. Figure 10 This is a diagram showing the dimensions of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 of the third modification of the first embodiment. Figure 7 The example described is a functional chip CH3 with a Y-direction dimension equal to that of array chip CH2. In contrast, in... Figure 10 In the example shown, in the second region R2, two functional chips CH3, whose dimensions in the Y direction are equal to those of the array chip CH2, are arranged adjacent to each other in the X direction. The areas of the two functional chips CH3 are equal.

[0106] according to Figure 10 The example shown is similar to Figure 7 Similarly, the power supply characteristics can be uniformly improved for each bit line BL of the array chip CH2. In addition, since the array chip CH2 and the functional chip CH3 can fill almost the entire area of ​​the upper surface of the circuit chip CH1, the warping of the semiconductor chips 30-33 can be suppressed.

[0107] (Fourth variation) Next, focusing on the differences from the above-described embodiments, a fourth variation of the first embodiment in which a plurality of functional chips CH3 of equal size are provided along the Y direction will be described. Figure 11 This is a diagram showing the dimensions of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 of the fourth modification of the first embodiment. Figure 11 In the example shown, multiple functional chips CH3 of equal size are arranged adjacent to each other in the Y direction on the second region R2. The functions of the multiple functional chips CH3 can be the same or different from each other.

[0108] according to Figure 11 In the example shown, for instance, when multiple heaters are used to heat an array chip CH2 as multiple functional chips CH3, it is possible to control whether or not regeneration of the array chip CH2 occurs based on the on / off state of the corresponding heater for each of the multiple plane PLNs (not shown) of the array chip CH2. The multiple plane PLNs are memory regions that can be controlled independently of each other.

[0109] (Fifth variation) Next, a fifth variation of the first embodiment with a different size of the functional chip CH3 will be described, focusing on the differences from the above embodiment. Figure 12 This is a diagram showing the dimensions of the array chip CH2 and the functional chip CH3 in the semiconductor device 1 of the fifth modification of the first embodiment. Figure 11 The example illustrates a configuration on a second region R2 of multiple functional chips CH3 of equal size arranged adjacent to each other in the Y direction. In contrast, in... Figure 12 In the example shown, multiple functional chips CH3 of different sizes (e.g., thicknesses) are arranged adjacent to each other in the Y direction on the second region R2.

[0110] according to Figure 12 The example shown can increase the design freedom of semiconductor device 1 by easing the constraints on the thickness of the functional chip CH3.

[0111] (Sixth variation) Next, a sixth variation of the first embodiment in which the metal pad WP is electrically connected to the circuit chip CH1 via the through-array chip CH2 will be described, focusing on the differences from the above embodiment. Figure 13 This is a cross-sectional view of a semiconductor device 1, which is a sixth variation of the first embodiment.

[0112] exist Figure 6JThe example described illustrates forming a recess 1211 on a semiconductor substrate 121 until the upper end of the contact plug C2 formed on the lower layer of the semiconductor substrate 121 is exposed, and forming a metal pad WP above the recess 1211. In contrast, in... Figure 13 In the example shown, a path 133 is provided under the metal pad WP to electrically connect the metal pad WP to the circuit chip CH1.

[0113] according to Figure 13 In the example shown, after the via H of the through array chip CH2 is formed in one step, the via 133 filling the via H and the metal pad WP at the upper end of the via 133 can be formed (i.e., rewiring). Therefore, since the processing of the recess 1211 is not required, manufacturing time can be reduced.

[0114] (Seventh variation) Next, a seventh variation of the first embodiment that does not form a metal pad WP will be described, focusing on the differences from the above embodiment. Figure 14 This is a cross-sectional view showing the semiconductor device 1 of the seventh modification of the first embodiment. Figure 14 In the example shown, a conductive columnar portion 134 is provided that passes through the member 115 (i.e., resin, SiO2, etc.). The columnar portion 134 is formed as a protrusion of the bonding line 90, for example, before the member 115 is formed. Alternatively, the columnar portion 134 is formed as a filling hole after the hole of the member 115 is formed.

[0115] according to Figure 14 In the example shown, manufacturing time can be reduced because the formation of metal pads WP can be omitted (i.e., rewiring). Furthermore, since it is not necessary to form vias H through the array chip CH2 (i.e., it is not necessary to provide space in the array chip CH2 for forming vias H), the chip size of the array chip CH2 can be reduced. Because the chip size of the array chip CH2 can be reduced, the number of chips obtained from the wafer can be increased. Because the number of chips obtained from the wafer can be increased, costs can be reduced. Moreover, since the distance between the columnar portion 134 formed by the component 115 (i.e., resin, SiO2, etc.) and the array chip CH2 can be controlled, direct damage to the array chip CH2 during wire bonding can be avoided. Therefore, chip cracks on the array chip CH2 during wire bonding can be suppressed.

[0116] (Eighth variation) Next, an eighth variation of the first embodiment in which a metal pad WP is formed on the circuit chip CH1 will be described, focusing on the differences from the embodiment described above. Figure 15 This is a cross-sectional view showing the semiconductor device 1 of the eighth modification of the first embodiment. Figure 15In the example shown, the metal pad WP is placed on the circuit chip CH1. Additionally, in Figure 15 In the example shown, component 115 (i.e., resin SiO2, etc.) is not provided on the circuit chip CH1.

[0117] according to Figure 15 In the example shown, since metal pads WP can be formed directly on the circuit chip CH1, manufacturing time can be reduced. Furthermore, since component 115 is not formed, manufacturing time can be further reduced, and costs can be lowered. Additionally, with... Figure 13 Compared to the example shown, the chip size of array chip CH2 can be reduced, thus reducing costs.

[0118] (Ninth variation) Figure 16 This is a side view showing the semiconductor device 1 of the ninth modification of the first embodiment. Additionally, in Figure 16 and the following Figures 17 to 20 In the middle, the following was omitted. Figure 1 The illustration shows the semiconductor chip 20. (See diagram below.) Figure 16 As shown, the number of semiconductor chip layers 30-37 can also be increased compared to the above embodiment. According to Figure 16 The example shown can improve the storage capacity and design freedom of semiconductor device 1.

[0119] (Tenth variation) Figure 17 This is a side view of the semiconductor device 1, showing a tenth variation of the first embodiment. (See attached image.) Figure 17 As shown, the number of semiconductor chips 30-37 can also be increased in the X direction compared to the above embodiment. According to Figure 17 The example shown can improve the storage capacity and design freedom of semiconductor device 1.

[0120] (Second Implementation) Next, the second embodiment, which uses a functional chip as a photoelectric conversion element, will be described, focusing on the differences from the embodiment described above. Figure 18 This is a side view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. In the second embodiment, semiconductor chip 30 (i.e., the third semiconductor chip), semiconductor chip 31 (i.e., the fourth semiconductor chip), and semiconductor chips 32 and 33 are equipped with a functional chip CH31 composed of photoelectric conversion elements.

[0121] like Figure 18 As shown, semiconductor chips 30-33 also include fiber optic terminals 5a positioned at a different location than the metal pad WP (i.e., the second pad). Figure 18In the example shown, the fiber optic terminal 5a is disposed on the side opposite to the side facing the array chip CH2 of the functional chip CH31.

[0122] In the semiconductor device 1 of the second embodiment, data is transmitted and received from the functional chip CH31 via the optical fiber 5 connected to the optical fiber terminal 5a. In addition, in the semiconductor device 1, power is supplied to the semiconductor chips 30-33 via the bonding wire 90 (i.e., the second lead) that connects the wiring substrate 10 (i.e., the second substrate) to the metal pads WP of the semiconductor chips 30-33.

[0123] According to the second embodiment, by including a functional chip CH31 composed of photoelectric conversion elements, high-speed data transmission can be performed on the functional chip CH31. As a result, the processing speed of the semiconductor device 1 can be improved.

[0124] (First variation) Figure 19A This is a side view of a semiconductor device 1 illustrating a first variation of the second embodiment. Figure 19A In the example shown, the semiconductor chips 30-32 (i.e., the fifth semiconductor chip) stacked on the wiring substrate 10 (i.e., the third substrate) include a functional chip CH3 without photoelectric conversion elements. The specific example of the functional chip CH3 without photoelectric conversion elements is as described in the first embodiment. On the other hand, the uppermost semiconductor chip 33 disposed on the semiconductor chip 32 includes a functional chip CH31 composed of photoelectric conversion elements. Furthermore, in... Figure 19A In the example shown, the thickness of the functional chip CH31 is greater than that of the array chip CH2. The wiring substrate 10, the pads WP (i.e., the fourth pads) of semiconductor chips 30-32, and the pads WP (i.e., the third pads) of semiconductor chip 33 are connected by bonding wires 90 (i.e., the third leads).

[0125] according to Figure 19A In the example shown, by placing the photoelectric conversion element CH31 on the top layer, even when the thickness of the photoelectric conversion element CH31 cannot be made the same as the thickness of the array chip CH2, assembly difficulties caused by the tilting of the semiconductor chips 30-33 can be avoided. Simultaneously, the number of chip layers can be increased, and the processing speed can be improved. Furthermore, by placing the photoelectric conversion element CH31 on the top layer, the position of the fiber optic terminal 5a can be freely configured. For example, it can replace... Figure 19A In this way, fiber optic terminals 5a are arranged on the side of the photoelectric conversion element CH31, and as... Figure 19B As shown, an optical fiber terminal 5a is disposed on the upper surface of the photoelectric conversion element CH31.

[0126] (Second variation) Figure 20 This is a side view of a semiconductor device 1 illustrating a second variation of the second embodiment. (See attached image.) Figure 20 As shown, the number of layers of semiconductor chips 33 and 37, which have a functional chip CH31 composed of photoelectric conversion elements, and semiconductor chips 30-32 and 34-36, which have a functional chip CH3 without photoelectric conversion elements, can be increased. Figure 20 In the example shown, a semiconductor chip 33 having a functional chip CH31 composed of photoelectric conversion elements is disposed between semiconductor chips 34 and 35 having functional chips CH3 that do not have photoelectric conversion elements. According to Figure 20 The example shown can increase the design freedom of semiconductor device 1.

[0127] (Other implementation methods) In the above embodiment, the array chip CH2 of semiconductor chips 30-33 includes a three-dimensional memory cell array formed by three-dimensionally arranging multiple memory cells. Alternatively, the array chip CH2 may also be a two-dimensional memory cell array, an image sensor, or the like. Furthermore, it may not be a NAND flash memory, but rather other memory elements such as DRAM or SRAM. The array chip CH2 may also be a CMOS circuit element, etc.

[0128] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention as described in the claims. [Explanation of reference numerals in the attached figures]

[0129] 1. Semiconductor device; 5. Optical fiber; 5a. Optical fiber terminal; 10. Wiring substrate; 30-33. Semiconductor chips; 90. Bonding wire; CH1. Circuit chip; CH2. Array chip; CH3. Functional chip; WP. Metal pad; R1. First region; R2. Second region

Claims

1. A semiconductor device comprising at least one semiconductor chip, The semiconductor chip has: First chip; A second chip, electrically connected to the first chip, is bonded to the first chip in a first region on the upper surface of the first chip, and has an area smaller than that of the first chip; and The third chip is electrically connected to the first chip in a second region on the upper surface of the first chip, has a smaller area than the first chip, and has an electrical function different from that of the second chip.

2. The semiconductor device according to claim 1, wherein, The combined area of ​​the second chip and the third chip is less than the area of ​​the upper surface of the first chip.

3. The semiconductor device according to claim 1, wherein, The area of ​​the second chip is different from that of the third chip.

4. The semiconductor device according to claim 1, wherein, The thickness of the second chip is different from that of the third chip.

5. The semiconductor device according to claim 1, wherein, The first chip has CMOS circuitry. The second chip has non-volatile memory.

6. The semiconductor device according to claim 1, wherein, The semiconductor chip has pads.

7. The semiconductor device according to claim 6, wherein, It also has a substrate. The semiconductor chip has at least a first semiconductor chip disposed on the substrate and a second semiconductor chip disposed on the first semiconductor chip.

8. The semiconductor device according to claim 7, wherein, It also includes leads that connect the substrate, the pads of the first semiconductor chip, and the pads of the second semiconductor chip.

9. The semiconductor device according to claim 5, wherein, The third chip has a photoelectric conversion element.

10. The semiconductor device according to claim 9, wherein, The semiconductor chip also has: The second pad; and The fiber optic connector is positioned at a location different from that of the second pad.

11. The semiconductor device according to claim 10, wherein, It also has a second substrate. The semiconductor chip has at least a third semiconductor chip disposed on the second substrate and a fourth semiconductor chip disposed on the third semiconductor chip.

12. The semiconductor device according to claim 11, wherein, It also includes a second lead that connects the second substrate, the second pad of the third semiconductor chip, and the second pad of the fourth semiconductor chip.

13. The semiconductor device according to claim 12, wherein, Data is transmitted and received through the optical fiber connected to the optical fiber connection terminal, and power is supplied to the third semiconductor chip and the fourth semiconductor chip through the second lead.

14. The semiconductor device according to claim 9, wherein, The semiconductor chip has a third pad. The semiconductor device also includes: Third substrate; A fifth semiconductor chip, disposed on or under the third substrate, has a fourth pad and a functional chip, wherein the functional chip does not have the photoelectric conversion element; as well as The third lead connects the third substrate, the third pad, and the fourth pad.

15. The semiconductor device according to any one of claims 1 to 14, wherein, The first chip has a lower pad disposed on the upper surface of the first chip. The second chip has an upper pad disposed on the lower surface of the second chip in a manner that engages with the lower pad.

16. A method for manufacturing a semiconductor device, comprising the following processes: On a first region of the upper surface of a wafer before it is monolithically formed into a first chip, a second chip is bonded in a manner electrically connected to the first chip. The second chip has an area smaller than that of the first chip. On a second region of the upper surface of the wafer, a third chip is joined in a manner electrically connected to the first chip. The third chip has a smaller area than the first chip and has an electrical function different from that of the second chip.

Images