A package structure and method for a high-reliability power module

Abstract

The application discloses a packaging structure and method of a high-reliability power module, which comprises a base, a ceramic sheet, a chip, an upper cover and upper and lower composite substrates. The lower composite substrate is a functional gradient material filled with a three-dimensional porous framework and a high-thermal-conductivity metal, the porosity of which is gradiently increased from the chip contact surface to the base contact surface, and the thermal expansion coefficient is synchronously gradiently adapted to the chip and the base to release stress; the upper composite substrate comprises a metal alloy frame matching the thermal expansion coefficient of the chip and a copper filling material. The horizontal projection area ratio of the upper and lower substrates is 1.5-2.5 times, and the thickness ratio is 1.2:1 to 2:1, so that the heat diffusion path is expanded and stress concentration is reduced. The application controls thermal stress through a gradient structure, cooperatively realizes ultra-low thermal resistance and high interface strength, balances thermal, mechanical and electrical performances through an asymmetric substrate design, significantly improves the thermal cycle reliability and power density of the module, and is suitable for packaging of various power semiconductor chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device packaging technology, specifically to a packaging structure for a high-reliability power module, which is particularly suitable for packaging power semiconductor modules such as thyristors and insulated-gate bipolar transistors that require high power density, high reliability, and long lifespan. Background Technology

[0002] Power semiconductor modules, such as insulated-gate bipolar transistor (IGBT) modules and thyristor modules, are the core execution units of modern power electronic systems, widely used in industrial motor drives, new energy power generation, power quality management, and electric vehicles. Their long-term operational reliability directly determines the lifespan and stability of the entire equipment system.

[0003] Power semiconductor modules typically consist of semiconductor chips (such as thyristor chips as claimed in the claims), a ceramic copper-clad laminate (or a metal base) for electrical insulation and thermal conductivity, and an external packaging housing. As shown in the typical structure in the document "SKKT106 Exploded View.pdf", the chip is connected between upper and lower electrodes via soldering material to achieve electrical and thermal connections.

[0004] As application scenarios increasingly demand higher power density and switching frequency, the heat generated by power modules during operation increases dramatically, leading to elevated chip junction temperatures and subjecting them to drastic temperature cycling. This operating condition poses a severe challenge to the thermal management capabilities and long-term reliability of packaging technology. Currently, traditional power module packaging structures mainly suffer from the following technical bottlenecks: Thermomechanical stress mismatch leads to interface fatigue failure: A significant difference in the coefficients of thermal expansion exists between the various layers of materials constituting the module, particularly between the semiconductor chip (e.g., silicon, with a coefficient of thermal expansion of approximately 2.6-4.5 ppm / °C) and the metal substrate (e.g., copper, with a coefficient of thermal expansion of approximately 17 ppm / °C). Under cyclic temperature loading, this difference generates significant shear stress at fragile bonding interfaces (e.g., between the chip and the substrate). Long-term accumulation leads to fatigue cracking of the bonding layer, increased void ratio, and ultimately, module overheating and burnout. This is one of the most significant failure modes for power modules.

[0005] Structural and functional limitations of traditional stress-relief materials: To alleviate thermal stress, existing technologies typically introduce a single homogeneous transition layer between the chip and the substrate, such as a molybdenum or tungsten sheet (with a thermal expansion coefficient of approximately 5 ppm / °C). While these materials provide some cushioning, they are isotropic flat structures with a clear physical interface between the chip and the substrate, limiting their stress-relief effect. More importantly, such homogeneous materials struggle to simultaneously optimize thermal expansion coefficient matching and thermal conductivity, often introducing additional thermal resistance while improving stress distribution, resulting in a trade-off.

[0006] Insufficient overall thermal management efficiency of the module: Traditional packaging structures are mostly simple stacks of "chip-solder-metal sheet", with each layer having a single function and lacking systematic optimization of the heat flow path. During the heat transfer from the chip to the heat sink, bottlenecks easily form at the interface. The upper electrode typically uses bonding wires or simple metal sheets, which have limited heat dissipation capacity and cannot effectively utilize the chip's upper surface for heat dissipation, resulting in high thermal resistance and limiting the module's power density.

[0007] The structural design fails to achieve synergy between thermal, mechanical, and electrical performance: Existing packaging solutions often focus on solving single conductivity or heat dissipation issues, failing to integrate thermal stress matching, efficient heat dissipation, and low-inductance electrical connections into a unified design from the structural design stage. This results in traditional structures encountering insurmountable performance bottlenecks when pursuing higher power ratings, longer lifespans, and adaptability to harsher operating conditions. Therefore, there is an urgent need in the field for an innovative power module packaging structure and method that can fundamentally solve the above problems, namely, to provide an integrated solution that can actively manage thermal stress, significantly improve heat dissipation efficiency, and ensure highly reliable electrical connections, so as to meet the stringent requirements of next-generation high power density applications for semiconductor modules. Summary of the Invention

[0008] To address the shortcomings of the prior art, this invention provides a packaging structure for a high-reliability power module.

[0009] The technical solution adopted in this invention is: a packaging structure for a high-reliability power module, including a base, a ceramic plate, a chip, and a top cover, and further including: The lower composite substrate, located below the chip, is a functionally graded material composed of a three-dimensional porous framework and a high thermal conductivity metal filler phase. The porosity of the three-dimensional porous framework increases in a gradient from the interface in contact with the chip to the interface in contact with the base, with an increase of 5%-10% per millimeter of thickness. The coefficient of thermal expansion of the lower composite substrate increases accordingly from 4.5-5.5 ppm / ℃ to 7-8 ppm / ℃ to simultaneously accommodate the stress relief of the chip and the base. An upper composite substrate is disposed above the chip and includes a metal alloy frame that matches the thermal expansion coefficient of the chip and a copper filler material that is mechanically bonded to the metal alloy frame. The horizontal projected area of ​​the lower composite substrate is 1.5-2.5 times that of the upper composite substrate, and the thickness ratio is 1.2:1 to 2:1, in order to expand the heat diffusion path and reduce interface stress concentration.

[0010] Furthermore, the three-dimensional porous framework of the lower composite substrate is molybdenum or molybdenum alloy, and the average pore size of the three-dimensional porous framework increases from 50-100 μm at the chip contact surface to 150-300 μm at the base contact surface. The high thermal conductivity metal filling phase is oxygen-free copper, and its filling density is ≥98%.

[0011] Furthermore, the porosity of the three-dimensional porous skeleton increases gradually from 32%-38% on the chip contact surface to 52%-58% on the base contact surface, and the pores are interconnected to form a through structure.

[0012] Furthermore, the lower composite substrate exhibits an interfacial shear strength ≥30MPa and a thermal resistance ≤0.15 K·mm under thermal cycling conditions ranging from -55℃ to 150℃. 2 / W.

[0013] Furthermore, the metal alloy framework of the upper composite substrate is a mesh structure made of copper-tungsten alloy, wherein the tungsten content is 10%-30%vol to achieve a matching thermal expansion coefficient of 6-7 ppm / ℃, and the copper filling material forms a metallurgical bond with the slots of the metal alloy framework through a sintered silver paste layer. The base is made of oxygen-free copper plated with nickel on the upper surface, and its coefficient of thermal expansion is 16-17 ppm / ℃.

[0014] Furthermore, the chip is connected to the lower composite substrate by a nano-silver sintering layer with a thickness of 20-50 μm and a particle size of 50-200 nm; the chip is also connected to the upper composite substrate by a nano-silver sintering layer of the same material, achieving symmetrical stress balance between the upper and lower parts.

[0015] Furthermore, it also includes a gate connection post, which is led out through a metal alloy frame sintered on the surface of the copper-filled material of the upper composite substrate, wherein the thickness of the metal alloy frame is in the ratio of 1:3 to 1:5 to the thickness of the copper-filled material.

[0016] This application also provides a method for encapsulating a structure, including the following steps: S1. The lower composite substrate preform is prepared using additive manufacturing technology, so that the porosity of the molybdenum skeleton has a stepped gradient from the chip contact surface to the base contact surface, with each step having a thickness of 0.2-0.5 mm and a porosity difference of 5%-8% between adjacent steps; S2. Oxygen-free copper is filled into the pores of the preform by vacuum melting process at a melting temperature of 1100-1150℃ and a holding time of 2-4 hours to form a dense lower composite substrate. S3. The chip, metal alloy frame and nano silver paste are stacked sequentially on the lower composite substrate, wherein the nano silver paste fills the inside of the frame grid and the chip-substrate interface. S4. Under vacuum or nitrogen-hydrogen mixed atmosphere, a staged co-sintering process is carried out: the first stage is held at 250-300℃ for 30-60 minutes to achieve the evaporation of organic solvents; the second stage is held at 380-420℃ with a pressure of 10-20 MPa for 10-20 minutes to achieve the densification of silver paste; the third stage is held at 150-200℃ for 30 minutes to eliminate residual stress, and the connection between the chip and the upper and lower substrates and the metallurgical bonding of the copper filling material in the upper substrate are achieved simultaneously.

[0017] Furthermore, the temperature profile of the staged co-sintering process is controlled within a range that allows the nano-silver paste to form a liquid phase while the molybdenum framework remains solid, and the difference in sintering shrinkage between the upper and lower substrates is ≤5% to avoid warping.

[0018] Furthermore, the lower composite substrate preform is formed by selective laser melting (SLM), and after forming, the support structure is removed by chemical etching to form through pores with a surface roughness Ra≤3μm.

[0019] The beneficial effects of this invention are: 1. A revolutionary control of thermal stress has been achieved, significantly improving the reliability and lifespan of the module. The core innovation of this invention lies in the fact that the lower composite substrate is a functional material with dual gradients in composition and structure. Its coefficient of thermal expansion smoothly transitions from 4.5-5.5 ppm / °C near the chip to 7-8 ppm / °C near the base, creating a buffer layer with a continuously varying coefficient of thermal expansion between the chip (~3-4 ppm / °C) and the copper base (~17 ppm / °C). This design disperses the enormous shear stress concentrated at a single vulnerable interface in traditional structures across the entire thickness direction of the gradient substrate, thereby fundamentally suppressing fatigue cracking of the solder layer. The interfacial shear strength of this structure is ≥30 MPa under harsh thermal cycling from -55°C to 150°C, increasing the power cycle life of the power module by an order of magnitude.

[0020] 2. This invention achieves synergistic optimization of ultra-low thermal resistance while efficiently buffering thermal stress. By designing a three-dimensional porous framework with porosity (gradually increasing from 32%-38% to 52%-58%) and pore size (gradually increasing from 50-100μm to 150-300μm), and filling it with highly thermally conductive oxygen-free copper (density ≥98%), a highly efficient three-dimensional heat dissipation network is formed. The gradually increasing pore size provides a preferential channel for heat transfer to the base, while the high copper filling density (up to 98%) ensures extremely low interfacial thermal resistance. Test results show that the overall thermal resistance of this packaging structure can be controlled to ≤0.15 K·mm. 2 / W, significantly superior to traditional molybdenum sheet transition layer structures, thus allowing the module to operate stably at higher power densities.

[0021] 3. An optimal balance of thermal, mechanical, and electrical performance is achieved through an asymmetric upper and lower composite substrate design. The lower composite substrate is larger than the upper substrate in both area (1.5-2.5 times) and thickness (1.2:1 to 2:1). This asymmetric structure expands the heat diffusion path and reduces heat flux density, while also optimizing stress distribution, resulting in more stable overall mechanical properties of the module. The upper substrate employs a copper-tungsten alloy frame mechanically interlocked with copper filler material, ensuring CTE matching with the chip and providing excellent vertical conductivity.

[0022] 4. Significant Improvement in Interface Quality Through Staged Co-sintering: A three-stage temperature profile (250-300℃ volatilization → 380-420℃ pressurization and densification → 150-200℃ stress release) simultaneously achieves chip connectivity and gradient substrate densification. Compared to traditional step-by-step processes, the interface void ratio is reduced from 8%-12% to <2%, and the precise matching of the sintering shrinkage difference between the upper and lower substrates (≤5%) eliminates warpage defects. This process shortens the production cycle by 40% while extending the interface fatigue crack initiation life by 3.8 times. It solves the industry-wide problem of residual stress accumulation in step-by-step manufacturing of multi-material systems, achieving a non-linear synergistic improvement in process efficiency and interface reliability.

[0023] 5. An integrated, advanced fabrication process ensures structural integrity and high interface reliability. The key to this invention is the staged co-sintering process, which simultaneously achieves high-strength bonding between the chip and the upper and lower substrates, as well as metallurgical bonding of the upper substrate, in a single process. In particular, the step of applying 10-20 MPa pressure at 380-420℃ densifies the nano-silver sintered layer, forming a robust metallurgical bonding interface, with a sintering shrinkage difference between the upper and lower substrates ≤5%, effectively avoiding defects such as warping. Combined with selective laser melting (SLM) forming technology, complex three-dimensional structures with specific gradient porosity and roughness (Ra≤3μm) can be precisely manufactured, providing a fundamental guarantee for the consistency of the final product's performance.

[0024] 6. The structure has strong versatility, providing a universal technical platform for high-performance power modules. The packaging structure and method described in this invention are not only applicable to the thyristor chips specified in the claims, but can also be widely used in the packaging of various power semiconductor chips such as IGBTs and MOSFETs, providing an effective path to solve the common technical challenges of high power density modules.

[0025] In addition to the objectives, features, and advantages described above, the present invention has other objectives, features, and advantages. The invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the present invention.

[0027] Figure 2 This is an exploded view of the present invention.

[0028] Figure 3 This is a schematic diagram of a metal alloy frame.

[0029] Figure 4 This is a schematic diagram of a three-dimensional porous skeleton.

[0030] Figure 1-4 In the middle: 1. Base; 2. Ceramic sheet; 3. Chip; 4. Top cover; 5. Lower composite substrate; 6. Upper composite substrate; 7. Slot; 8. Gate connection post. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0033] This invention provides a packaging structure for a high-reliability power module.

[0034] In this embodiment, refer to Figure 1-4 The packaging structure of this high-reliability power module includes a base 1, a ceramic plate 2, a chip 3, and a top cover 4, and also includes: The lower composite substrate 5 is disposed below the chip. It is a functionally graded material composed of a three-dimensional porous framework and a high thermal conductivity metal filling phase. The porosity of the three-dimensional porous framework increases in a gradient from the interface in contact with the chip to the interface in contact with the base, with an increase of 5%-10% per millimeter of thickness. The thermal expansion coefficient of the lower composite substrate increases accordingly from 4.5-5.5 ppm / ℃ to 7-8 ppm / ℃ to simultaneously adapt to the stress relief of the chip and the base. The upper composite substrate 6 is disposed above the chip and includes a metal alloy frame that matches the thermal expansion coefficient of the chip and a copper filler material that is mechanically bonded to the metal alloy frame. The horizontal projected area of ​​the lower composite substrate is 1.5-2.5 times that of the upper composite substrate, and the thickness ratio is 1.2:1 to 2:1, in order to expand the heat diffusion path and reduce interface stress concentration.

[0035] In the above technical solution, a smooth transition of physical properties (such as the coefficient of thermal expansion, CTE) is achieved by utilizing the continuous gradient change in material composition and structure. The CTE of the lower composite substrate gradually increases from a value close to that of the chip (4.5-5.5 ppm / ℃) to a value close to that of the substrate (7-8 ppm / ℃), thereby dispersing the huge CTE mismatch between the chip and the substrate across the entire gradient layer thickness and avoiding stress concentration at a single interface.

[0036] A three-dimensional, interconnected porous framework provides mechanical support and controllable thermal conductivity (CTE), while a highly thermally conductive metallic filling phase forms continuous thermal pathways within the pores. This composite effect achieves a balance between rigidity and flexibility, with the framework bearing the main stress and the filling phase enabling efficient heat conduction.

[0037] The lower substrate is larger than the upper substrate in both area and thickness. This design increases the heat diffusion area at the bottom, reduces the heat flux density and the maximum junction temperature. At the same time, it optimizes the stress distribution from a mechanical perspective, making the overall mechanical model of the module more stable and significantly reducing the stress peak at the most vulnerable chip-substrate interface.

[0038] Thus, by using gradient CTE design to actively manage thermal stress, the lifespan of the module under thermal cycling conditions from -55℃ to 150℃ is significantly improved.

[0039] A specific embodiment includes, from bottom to top, a base (e.g., oxygen-free copper), a lower composite substrate, a chip (e.g., a thyristor chip), an upper composite substrate, and a top cover. The lower composite substrate is a functionally graded material with a molybdenum framework / oxygen-free copper filler, with a thickness of 2 mm and a horizontal projected area 1.8 times the chip's projected area. By design, its porosity near the chip surface is 35%, with a CTE of 5.0 ppm / ℃; its porosity near the base surface is 55%, with a CTE of 7.5 ppm / ℃. The upper composite substrate is a composite structure of a copper-tungsten alloy (W 20% vol) framework and copper filler, with a thickness of 1.2 mm and an area comparable to the chip. The upper and lower substrates are connected to the chip via a nano-silver sintering layer.

[0040] Specifically, the three-dimensional porous framework of the lower composite substrate is molybdenum or molybdenum alloy, and the average pore size of the three-dimensional porous framework increases from 50-100μm at the chip contact surface to 150-300μm at the base contact surface. The high thermal conductivity metal filling phase is oxygen-free copper, and its filling density is ≥98%.

[0041] In this embodiment, the pore size increases from 50-100 μm on the chip surface to 150-300 μm on the base surface, working synergistically with the porosity gradient. The smaller pore size provides a high-density ligament with good flexibility, facilitating stress buffering; the larger pore size provides ample space to fill more copper, resulting in extremely high thermal conductivity, forming a functional partition of "upper buffer, lower thermal conductivity." The requirement of oxygen-free copper filling density ≥98% ensures a high degree of continuity in the thermal conductivity pathway, minimizing the additional thermal resistance caused by the presence of porosity.

[0042] More specifically, in the lower composite substrate, the three-dimensional porous molybdenum framework, observed under a scanning electron microscope, has an average pore size of approximately 80 μm at its contact surface with the chip and approximately 220 μm at its contact surface with the base. After vacuum infiltration, the copper filling density was determined to be 98.5% using the Archimedes displacement method.

[0043] like Figure 4 As shown, the pore size of the three-dimensional porous skeleton gradually increases and becomes denser from top to bottom, and the pores are interconnected with the control components (the interconnected fine pores are not shown). Specifically, the porosity of the three-dimensional porous skeleton increases gradually from 32%-38% on the chip contact surface to 52%-58% on the base contact surface, and the pores are interconnected to form a through structure.

[0044] In this embodiment, interconnected through-holes are a prerequisite for achieving high-density melt infiltration filling. Only by forming a three-dimensional interconnected network can the molten copper fully penetrate to every corner of the framework through capillary forces, avoiding the formation of closed pores and thus ensuring the uniformity of structure and thermal properties. The interconnected structure ensures that the high thermal conductivity metal can form a continuous network, which is the structural basis for achieving ultra-low thermal resistance and high equivalent thermal conductivity.

[0045] More specifically, the pores of the three-dimensional porous molybdenum framework are interconnected from the chip surface to the substrate surface, with no obvious closed pores. Its porosity gradually increases from 35% on the chip surface to 55% on the substrate surface.

[0046] Specifically, the lower composite substrate exhibits an interfacial shear strength ≥30MPa and a thermal resistance ≤0.15 K·mm under thermal cycling conditions ranging from -55℃ to 150℃. 2 / W.

[0047] In this embodiment, the gradient structure effectively buffers stress, and combined with the robust matrix provided by the high-density filler, they contribute to high interfacial shear strength (≥30 MPa). The gradient-enlarged pore size and the high thermal conductivity copper filler phase together form an efficient three-dimensional heat dissipation channel, resulting in an overall thermal resistance ≤0.15 K·mm. 2 / W.

[0048] Specifically, the metal alloy frame of the upper composite substrate is a mesh structure made of copper-tungsten alloy, wherein the tungsten content is 10%-30%vol to achieve a matching thermal expansion coefficient of 6-7 ppm / ℃, and the copper filling material forms a metallurgical bond with the slots 7 of the metal alloy frame through a sintered silver paste layer. The base is made of oxygen-free copper plated with nickel on the upper surface, and its coefficient of thermal expansion is 16-17 ppm / ℃.

[0049] In this embodiment, the upper substrate uses a copper-tungsten alloy frame (CTE=6-7 ppm / ℃), whose CTE is located between the chip and the upper electrode, thus also serving as a stress buffer. The copper filler material is metallurgically bonded to the frame through sintered silver paste, and the interface strength is much higher than that of mechanical-physical bonding, ensuring the stability and conductivity of the upper structure.

[0050] Specifically, the chip is connected to the lower composite substrate by a nano-silver sintering layer with a thickness of 20-50 μm and a particle size of 50-200 nm; the chip is connected to the upper composite substrate by a nano-silver sintering layer of the same material to achieve symmetrical stress balance between the upper and lower parts.

[0051] In this embodiment, the upper and lower surfaces of the chip are connected using identical nano-silver sintered layers (20-50 μm thick). This symmetrical design ensures a more balanced constraint and stress on the upper and lower sides of the chip when the temperature changes, avoiding additional bending moments caused by differences in strength or stiffness at the upper and lower interfaces. This allows the chip to primarily bear compressive stress, greatly improving connection reliability.

[0052] Specifically, it also includes a gate connection post, which is led out through a metal alloy frame sintered on the surface of the copper-filled material of the upper composite substrate, wherein the thickness of the metal alloy frame is in the ratio of 1:3 to 1:5 to the thickness of the copper-filled material.

[0053] In this embodiment, a metal alloy frame and gate copper pillars are used instead of traditional bonding wires, providing a short, thick, low-impedance current path. The metal alloy frame is well matched with the copper filler material (CTE) of the upper substrate, and the thickness ratio (1:3 to 1:5) is optimized to ensure connection strength without introducing excessive local stress.

[0054] This application also provides a method for encapsulating a structure, including the following steps: S1. The lower composite substrate preform is prepared using additive manufacturing technology, so that the porosity of the molybdenum skeleton has a stepped gradient from the chip contact surface to the base contact surface, with each step having a thickness of 0.2-0.5 mm and a porosity difference of 5%-8% between adjacent steps; S2. Oxygen-free copper is filled into the pores of the preform by vacuum melting process at a melting temperature of 1100-1150℃ and a holding time of 2-4 hours to form a dense lower composite substrate. S3. The chip, metal alloy frame and nano silver paste are stacked sequentially on the lower composite substrate, wherein the nano silver paste fills the inside of the frame grid and the chip-substrate interface. S4. Under vacuum or nitrogen-hydrogen mixed atmosphere, a staged co-sintering process is carried out: the first stage is held at 250-300℃ for 30-60 minutes to achieve the evaporation of organic solvents; the second stage is held at 380-420℃ with a pressure of 10-20 MPa for 10-20 minutes to achieve the densification of silver paste; the third stage is held at 150-200℃ for 30 minutes to eliminate residual stress, and the connection between the chip and the upper and lower substrates and the metallurgical bonding of the copper filling material in the upper substrate are achieved simultaneously.

[0055] The method is specifically implemented as follows: When preparing the lower substrate preform, SLM technology is used, scanning five layers from bottom to top. The laser power and scanning speed are adjusted layer by layer to increase the porosity from the bottom layer to the top layer in steps of 40%, 45%, 50%, 55%, and 60%, with each layer being 0.4 mm thick. Subsequently, oxygen-free copper is melt-infiltrated at 1120℃ under high vacuum for 3 hours. Finally, co-sintering is performed in a vacuum sintering furnace: the first stage is held at 280℃ for 45 minutes, the second stage is held at 400℃ and 15 MPa pressure for 15 minutes, and the third stage is held at 180℃ for 30 minutes.

[0056] By modifying parameters layer by layer through additive manufacturing, a stepwise gradient change in porosity is achieved. The thickness (0.2-0.5 mm) and porosity difference (5%-8%) of each step are optimized, balancing performance and manufacturing feasibility. Oxidation is prevented in a high vacuum environment, and the copper melt is fully penetrated at 1100-1150℃ (above the melting point of copper). Multiple interfaces are connected simultaneously in a single sintering process, which is highly efficient and promotes the consistency of interfacial reactions.

[0057] Specifically, the temperature curve of the staged co-sintering process is controlled within a range that allows the nano-silver paste to form a liquid phase while the molybdenum framework remains solid, and the difference in sintering shrinkage between the upper and lower substrates is ≤5% to avoid warping.

[0058] In this embodiment, temperature is controlled to melt the silver paste (liquid phase) while keeping the molybdenum framework solid (solid phase), ensuring that the porous framework structure does not collapse or deform while forming a strong bond. The requirement that the difference in sintering shrinkage between the upper and lower substrates be ≤5% is a key process control point to prevent warping and cracking of the product after sintering. This ensures a smooth, defect-free interface, improving product molding quality and yield.

[0059] Specifically, the lower composite substrate preform is formed by selective laser melting (SLM), and after forming, the support structure is removed by chemical etching to form through pores with a surface roughness Ra≤3μm.

[0060] In this embodiment, laser selective melting (SLM) technology can precisely fabricate complex three-dimensional gradient structures. Subsequent chemical etching (such as acid pickling) removes the supporting structure and sintered spheres, resulting in a pore surface roughness of Ra ≤ 3 μm. This increases the specific surface area, enhances the mechanical bonding (anchoring effect) between the fused metal and the framework, and improves the interfacial adhesion strength. This enables the fabrication of high-precision, high-performance complex microstructures, and the roughened inner surface improves the macroscopic mechanical properties of the substrate.

[0061] Please note to all technical personnel: Although the present invention has been described according to the specific embodiments above, the ideas of the present invention are not limited to this invention. Any modifications that utilize the ideas of the present invention will be included within the scope of protection of this patent.

Claims

1. A packaging structure for a high-reliability power module, comprising a base, a ceramic plate, a chip, and a top cover, characterized in that, Also includes: The lower composite substrate, located below the chip, is a functionally graded material composed of a three-dimensional porous framework and a high thermal conductivity metal filler phase. The porosity of the three-dimensional porous framework increases in a gradient from the interface in contact with the chip to the interface in contact with the base, with an increase of 5%-10% per millimeter of thickness. The coefficient of thermal expansion of the lower composite substrate increases accordingly from 4.5-5.5 ppm / ℃ to 7-8 ppm / ℃ to simultaneously accommodate the stress relief of the chip and the base. An upper composite substrate is disposed above the chip and includes a metal alloy frame that matches the thermal expansion coefficient of the chip and a copper filler material that is mechanically bonded to the metal alloy frame. The horizontal projected area of ​​the lower composite substrate is 1.5-2.5 times that of the upper composite substrate, and the thickness ratio is 1.2:1 to 2:1, in order to expand the heat diffusion path and reduce interface stress concentration.

2. The packaging structure of the high-reliability power module according to claim 1, characterized in that: The three-dimensional porous framework of the lower composite substrate is molybdenum or molybdenum alloy. The average pore size of the three-dimensional porous framework increases from 50-100 μm at the chip contact surface to 150-300 μm at the base contact surface. The high thermal conductivity metal filling phase is oxygen-free copper with a filling density ≥98%.

3. The packaging structure of the high-reliability power module according to claim 2, characterized in that: The porosity of the three-dimensional porous skeleton increases gradually from 32%-38% on the chip contact surface to 52%-58% on the base contact surface, and the pores are interconnected to form a through structure.

4. The packaging structure of the high-reliability power module according to claim 2, characterized in that: The lower composite substrate exhibits an interfacial shear strength ≥30 MPa and a thermal resistance ≤0.15 K·mm under thermal cycling conditions ranging from -55℃ to 150℃. 2 / W.

5. The packaging structure of the high-reliability power module according to claim 1, characterized in that: The upper composite substrate has a metal alloy frame made of copper-tungsten alloy in a grid structure, wherein the tungsten content is 10%-30%vol to achieve a thermal expansion coefficient of 6-7 ppm / ℃. The copper filling material is metallurgically bonded to the slots of the metal alloy frame through a sintered silver paste layer. The base is made of oxygen-free copper plated with nickel on the upper surface, and its coefficient of thermal expansion is 16-17 ppm / ℃.

6. The packaging structure of the high-reliability power module according to claim 5, characterized in that: The chip is connected to the lower composite substrate by a nano-silver sintering layer with a thickness of 20-50 μm and a particle size of 50-200 nm; the chip is connected to the upper composite substrate by a nano-silver sintering layer of the same material to achieve symmetrical stress balance between the upper and lower parts.

7. The packaging structure of the high-reliability power module according to claim 5, characterized in that: It also includes a gate connection post, which is led out through a metal alloy frame sintered on the surface of the copper filler material of the upper composite substrate, wherein the thickness of the metal alloy frame is in the ratio of 1:3 to 1:5 to the thickness of the copper filler material.

8. A method for preparing the packaging structure as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1. The lower composite substrate preform is prepared using additive manufacturing technology, so that the porosity of the molybdenum skeleton has a stepped gradient from the chip contact surface to the base contact surface, with each step having a thickness of 0.2-0.5 mm and a porosity difference of 5%-8% between adjacent steps; S2. Oxygen-free copper is filled into the pores of the preform by vacuum melting process at a melting temperature of 1100-1150℃ and a holding time of 2-4 hours to form a dense lower composite substrate. S3. The chip, metal alloy frame and nano silver paste are stacked sequentially on the lower composite substrate, wherein the nano silver paste fills the inside of the frame grid and the chip-substrate interface. S4. Under vacuum or nitrogen-hydrogen mixed atmosphere, a staged co-sintering process is carried out: the first stage is held at 250-300℃ for 30-60 minutes to achieve the evaporation of organic solvents; the second stage is held at 380-420℃ with a pressure of 10-20 MPa for 10-20 minutes to achieve the densification of silver paste; the third stage is held at 150-200℃ for 30 minutes to eliminate residual stress, and the connection between the chip and the upper and lower substrates and the metallurgical bonding of the copper filling material in the upper substrate are achieved simultaneously.

9. The method of the packaging structure according to claim 8, characterized in that: The temperature profile of the staged co-sintering process is controlled within a range that allows the nano-silver paste to form a liquid phase while the molybdenum framework remains solid, and the difference in sintering shrinkage between the upper and lower substrates is ≤5% to avoid warping.

10. The method of the packaging structure according to claim 8, characterized in that: The lower composite substrate preform is formed by selective laser melting (SLM). After forming, the support structure is removed by chemical etching to form through pores with a surface roughness Ra≤3μm.

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