Semiconductor element and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device mainly comprises the following steps: firstly, bonding a first wafer to a carrier; secondly, performing a first grinding manufacturing process on the back surface of the first wafer; thirdly, performing a first trimming manufacturing process on the sidewall of the first wafer; fourthly, forming a first protective layer on the sidewall of the first wafer; fifthly, forming a first contact pad on the back surface of the first wafer; sixthly, bonding a second wafer to the first wafer; seventhly, performing a second grinding manufacturing process on the back surface of the second wafer; eighthly, performing a second trimming manufacturing process on the sidewall of the second wafer; ninthly, forming a second protective layer on the sidewall of the first wafer and the sidewall of the second wafer; and tenthly, forming a second contact pad on the back surface of the second wafer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for forming a protective layer on the sidewall of a wafer. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages utilizing smaller areas compared to previous packages. Some smaller types of semiconductor component packages include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated chips (3DIC), wafer-level packages (WLP), and package-on-package (PoP) devices, among others.

[0003] 3D integrated chips offer increased integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced length of interconnects between stacked chips. However, many challenges remain to be addressed for 3D integrated chip technology. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly involves first bonding a first wafer to a carrier, then performing a first grinding process on the back side of the first wafer, performing a first trimming process on the sidewalls of the first wafer to form a first protective layer on the sidewalls of the first wafer, forming a first contact pad on the back side of the first wafer, bonding a second wafer to the first wafer, performing a second grinding process on the back side of the second wafer, performing a second trimming process on the sidewalls of the second wafer to form a second protective layer on both the sidewalls of the first and second wafers, and finally forming a second contact pad on the back side of the second wafer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a second wafer bonded to a first wafer and a protective layer disposed on the sidewalls of the first wafer and the second wafer, wherein the thickness of the protective layer on the sidewall of the second wafer is less than the thickness of the protective layer on the sidewall of the first wafer. Attached Figure Description

[0006] Figures 1 to 13 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0007] Symbol Explanation

[0008] 12: First Wafer

[0009] 14: Carrier

[0010] 16: Base

[0011] 18: Intermetallic dielectric layer

[0012] 20: Metal interconnects

[0013] 22: Silicon Through-Hole

[0014] 24: Protective layer

[0015] 26: Contact pad

[0016] 28: Dielectric layer

[0017] 30: Metal interconnects

[0018] 32: Second wafer

[0019] 34: Protective layer

[0020] 42: Third wafer

[0021] 44: Protective layer

[0022] 52: Fourth wafer

[0023] 62: Fifth Wafer Detailed Implementation

[0024] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0025] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0026] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0027] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0028] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0029] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0030] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0031] Please refer to Figures 1 to 13 , Figures 1 to 13 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a first wafer 12 made of semiconductor material is first provided, wherein the first wafer 12 includes a substrate 16 made of semiconductor material, and the substrate 16 may be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a substrate made of silicon-on-insulator (SOI). These material choices are all within the scope of this invention. In this embodiment, the first wafer 12 and subsequent wafers stacked thereon preferably include dynamic random-access memory (DRAM), but it is not excluded that they can be used in subsequent fabrication processes to fabricate various components such as medium-voltage components, high-voltage components, pixel circuits, low-voltage components of low-voltage drive circuits, and / or graphics processing units (GPUs).

[0032] Then, a front-end of line (FEOL) fabrication process and a back-end of line (BEOL) fabrication process are performed on the first wafer 12. In this embodiment, the front-end of line fabrication process may include fabricating, for example, metal oxide semiconductor (MOS) transistors, oxide field-effect semiconductor transistors (OS FETs), fin structure transistors (FinFETs), or other active (active) devices and / or passive (passive) devices on the first wafer 12, depending on the fabrication process or product selection. The back-end of line fabrication process may form metal interconnect structures such as inter-metal dielectric layers 18 and metal interconnects 20 on these active and / or passive devices. Taking the fabrication of a metal-oxide-semiconductor transistor as an example, the front-end fabrication process may include forming a gate structure on a substrate, spacers (not shown) on the sidewalls of the gate structure, and source / drain regions on both sides of the spacers within the substrate. The gate structure may contain polysilicon or metal materials, the spacers may contain dielectric materials such as silicon oxide or silicon nitride, and the source / drain regions may contain different dopants depending on the conductivity type of the transistor being fabricated, such as P-type dopants or N-type dopants.

[0033] Next, an interlayer dielectric layer can be formed on the substrate and cover metal-oxide-semiconductor transistors or other active components. Then, contact plugs and subsequent metal interconnect fabrication processes are performed to form multiple contact plugs within the interlayer dielectric layer to connect the source / drain regions and the gate structure. An interlayer dielectric layer 18 is disposed on the interlayer dielectric layer, and metal interconnects 20 are disposed within the interlayer dielectric layer and connect to the contact plugs. The topmost metal interconnect 20 on the front side of the first wafer 12 can also serve as a contact point for a direct bond interconnect (DBI), which can be docked with a DBI on another wafer in subsequent fabrication processes. In this embodiment, the interlayer dielectric layer and the interlayer dielectric layer 18 may contain oxides, such as, but not limited to, tetraethyl orthosilicate (TES). The contact plugs, metal interconnects 20, or direct bond interconnects may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited to these. In addition, the substrate 16 of the first wafer 12 is preferably provided with through-silicon vias (TSVs) 22 to connect the active components and / or passive components on the substrate 16.

[0034] The first wafer 12 is then flipped and bonded to a carrier 14, wherein the first wafer 12 and the carrier 14 are connected by an oxide bond. Like the first wafer 12, the carrier 14 in this embodiment also includes a silicon wafer or a substrate 16 made of semiconductor material, and the substrate 16 may be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a silicon-on-insulator (SOI) substrate. However, it is not limited to this; according to other embodiments of the present invention, the carrier 14 may also include materials such as silicon, silicon carbide, or glass. Unlike the first wafer 12, which has active and / or passive components fabricated by front-end or back-end processes, the carrier 14 is preferably a blank wafer and does not have any active and / or passive components fabricated by front-end or back-end processes on it.

[0035] Subsequently, as Figure 2 As shown, a grinding process is performed on the back side of the first wafer 12 to remove part of the substrate 16 of the first wafer 12, thereby reducing its thickness.

[0036] Then as Figure 3 As shown, a trimming process is performed on the sidewalls of the first wafer 12 to make the sidewalls of the substrate 16 of the first wafer 12 flush with the sidewalls of the intermetallic dielectric layer 18 and even part of the sidewalls of the carrier 14.

[0037] Then as Figure 4 As shown, a protective layer 24 is formed on the sidewalls of the first wafer 12 and a portion of the sidewalls of the carrier 14. In this embodiment, the protective layer 24 preferably comprises a dielectric material, such as, but not limited to, silicon nitride, silicon oxide, or combinations thereof.

[0038] Subsequently, as Figure 5As shown, a second grinding process is performed to remove a portion of the substrate 16 on the back side of the first wafer 12 and expose the silicon vias 22, before forming contact pads 26 on the back side of the first wafer 12. According to one embodiment of the present invention, the contact pads 26 can be fabricated by first forming one or more dielectric layers 28 on the substrate 16 on the back side of the first wafer 12, and then forming metal interconnects 30 within the dielectric layer 28 using a single-damascene or double-damascene method. The metal interconnects 30 can serve as contacts for the contact pads 26 in a hybrid bonding process or as points for direct bond interconnects (DBIs), which can then be mated with direct bond interconnects on another wafer in subsequent fabrication processes. In this embodiment, the dielectric layer 28 may contain oxides, such as, but not limited to, tetraethyl orthosilicate (TES), while the contact pads 26 or direct bond interconnects may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto.

[0039] like Figure 6 As shown, a second wafer 32 is then provided, which includes a substrate 16 made of semiconductor material. The substrate 16 can be a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a substrate made of silicon-on-insulator (SOI). Like the first wafer 12, the second wafer 32 also includes silicon through-holes 22, interlayer dielectric layers, intermetallic dielectric layers 18, and metal interconnects 20, which are fabricated by front-end (FEOL) and back-end (BEOL) processes. The uppermost metal interconnect 20 can also serve as a contact pad for a hybrid bonding process or a contact point for a direct bonding interconnect (DBI).

[0040] Next, a hybrid bonding process is performed to dock the first wafer 12 and the second wafer 32 to form a stacked structure. During the bonding process, the second wafer 32 can be flipped so that the front side of the second wafer 32 or the side exposing the metal interconnects 20 faces the front side of the first wafer 12 or the side exposing the metal interconnects 30. Then, the metal interconnects 20 and 30 of the two wafers or the direct bonding interconnects are directly bonded by means such as heating, so that the metal interconnects 20 of the second wafer 32 and the intermetallic dielectric layer 18 directly contact the metal interconnects 30 and the intermetallic dielectric layer 18 of the first wafer 12. It should be noted that although the sidewalls of the intermetallic dielectric layer 18 of the second wafer 32 are approximately flush with the sidewalls of the protective layer 24 of the first wafer 12, this is not the limitation. According to other embodiments of the present invention, the sidewalls of the intermetallic dielectric layer 18 of the second wafer 32 may not be flush with the sidewalls of the protective layer 24 of the first wafer 12. For example, the width of the intermetallic dielectric layer 18 of the second wafer 32 may be greater than the sum of the widths of the intermetallic dielectric layer 18 and the protective layer 24 of the first wafer 12. This variation is also within the scope of the present invention.

[0041] Subsequently, as Figure 7 As shown, a grinding process is performed on the back side of the second wafer 32 to remove part of the substrate 16 of the second wafer 32, thereby reducing its thickness.

[0042] Then as Figure 8 As shown, a trimming process is performed on the sidewall of the second wafer to make the sidewall of the substrate 16 of the second wafer 32 flush with the sidewall of the substrate 16 of the first wafer 12.

[0043] Then as Figure 9 As shown, another protective layer (not shown) is formed on the sidewalls of the first wafer 12 and the second wafer 32, wherein the protective layer is as follows: Figure 4 It may generally contain dielectric materials, such as, but not limited to, silicon nitride, silicon oxide, or combinations thereof. It is worth noting that, since the protective layer formed in this stage preferably contains the same material as the aforementioned protective layer 24, after the protective layer is formed on the sidewalls of the first wafer 12 and the second wafer 32 in this stage, the two protective layers are preferably combined to form a new protective layer 34, and the thickness of the protective layer 34 on the sidewall of the second wafer 32 is preferably less than the thickness of the protective layer 34 on the sidewall of the first wafer 12. In other words, since... Figure 4 A protective layer 24 has been formed on the sidewall of the first wafer 12. Therefore, after the protective layer 34 is formed in this stage, the sidewall of the second wafer 32 only contains the thickness of a single protective layer, while the sidewall of the first wafer 12 contains the thickness of a double protective layer.

[0044] According to one embodiment of the present invention, the thickness of the protective layer formed in this stage is approximately equal to Figure 4The thickness of the protective layer 24 formed is such that the thickness of the protective layer 34 on the sidewall of the first wafer 12 after the formation of the protective layer 34 in this stage is about twice the thickness of the protective layer 34 on the sidewall of the second wafer 32, but it is not limited to this.

[0045] Then as Figure 10 As shown, another grinding process can be performed to remove a portion of the substrate 16 on the back side of the second wafer 32 and expose the silicon via 22, and then a contact pad 26 can be formed on the back side of the second wafer 32. As... Figure 5 In this embodiment, the contact pad 26 can be fabricated by first forming one or more dielectric layers 28 on the substrate 16 on the back side of the second wafer 32, and then forming metal interconnects 30 within the dielectric layer 28 using a single damascene or double damascene method. The metal interconnects 30 can serve as contacts for hybrid bonding contact pads 26 or direct bonding interconnects (DBI), which can be mated with direct bonding interconnects on another wafer in subsequent fabrication processes. In this embodiment, the dielectric layer 28 may contain oxides such as, but not limited to, tetraethyl orthosilicate (TES), while the contact pads 26 or direct bonding interconnects may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto.

[0046] Subsequently, as Figure 11 As shown, you can compare it again. Figure 6 The fabrication process first involves bonding a third wafer 42 to the back side of the second wafer 32. Similar to the first wafer 12 and the second wafer 32 mentioned above, the third wafer 42 also includes silicon through-hole vias 22, interlayer dielectric layers, intermetallic dielectric layers 18, and metal interconnects 20, which are fabricated using front-end (FEOL) and back-end (BEOL) processes. The metal interconnects 20 can also serve as contact pads for hybrid bonding processes or as contacts for direct bonding interconnects (DBI).

[0047] Then it can be compared. Figures 7 to 10 The fabrication process involves a grinding process on the back side of the third wafer 42 to remove part of the substrate 16, reducing its thickness. A trimming process is then performed on the sidewalls of the third wafer 42 to align the sidewalls of the substrate 16 with the sidewalls of the first wafer 12 and the second wafer 32. Finally, another protective layer is formed on the sidewalls of the first wafer 12, the second wafer 32, and the third wafer 42. Similar to the aforementioned protective layer, the protective layer formed in this stage is as follows: Figure 4 and Figure 9 It may contain dielectric materials such as, but not limited to, silicon nitride, silicon oxide, or combinations thereof.

[0048] Since the protective layer formed in this stage preferably contains the same material as the aforementioned protective layers, after the protective layer is formed on the sidewalls of the first wafer 12, the second wafer 32, and the third wafer 42, the three protective layers preferably combine to form a new protective layer 44. Simultaneously, the thickness of the protective layer 44 on the sidewall of the third wafer 42 is preferably less than the thickness of the protective layer 44 on the sidewall of the second wafer 32, and the thickness of the protective layer 44 on the sidewall of the second wafer 32 is also less than the thickness of the protective layer 44 on the sidewall of the first wafer 12. In other words, because... Figure 9 A protective layer 34 has been formed on the sidewalls of the first wafer 12 and the second wafer 32. Therefore, after the protective layer 44 is formed in this stage, the sidewall of the third wafer 42 only contains the thickness of a single protective layer, the second wafer 32 contains the thickness of a double protective layer, and the sidewall of the first wafer 12 contains the thickness of a triple protective layer.

[0049] According to one embodiment of the present invention, the thickness of the protective layer formed in this stage is approximately equal to Figure 4 The thickness of the protective layer 24 formed is such that, after the protective layer 44 is formed in this stage, the thickness of the protective layer 44 on the sidewall of the first wafer 12 is about three times the thickness of the protective layer 44 on the sidewall of the third wafer 42, while the thickness of the protective layer 44 on the sidewall of the second wafer 32 is about twice the thickness of the protective layer 44 on the sidewall of the third wafer 42. Or, from a cross-sectional view, the protective layer 44 is better formed into a stepped portion on the three wafer sidewalls, wherein the width of the protective layer 44 near the bottom is greater than the width of the protective layer 44 near the top.

[0050] Then as Figure 12 As shown, compare again Figure 6 The fabrication process first involves bonding a fourth wafer 52 to the back side of the third wafer 42. Similar to the first wafer 12, the second wafer 32, and the third wafer 42 mentioned above, the fourth wafer 52 also includes silicon through-hole vias 22, interlayer dielectric layers, intermetallic dielectric layers 18, and metal interconnects 20, which are fabricated using front-end (FEOL) and back-end (BEOL) processes. The metal interconnects 20 can also serve as contact pads for hybrid bonding processes or as contacts for direct bonding interconnects (DBI).

[0051] like Figure 13As shown, a grinding and / or etching process can then be performed to remove the carrier 14, and a fifth wafer 62 is then bonded to the front side of the first wafer 12. Like the first wafer 12 and the second wafer 32 described above, the fifth wafer 62 also includes silicon through-hole vias 22, interlayer dielectric layers, inter-metal dielectric layers 18, and metal interconnects 20, etc., fabricated using front-end (FEOL) and back-end (BEOL) processes. The metal interconnects 20 can also serve as contact pads in a hybrid bonding process or as contacts in a direct bonding interconnect (DBI) process, and the first wafer 12 and the fifth wafer 62 can be interconnected using a hybrid bonding method. According to a preferred embodiment of the present invention, the fifth wafer is preferably a logic chip, and the aforementioned stacked structure of the first wafer 12 to the fourth wafer 52 from bottom to top together constitutes a dynamic random-access memory (DRAM) stacked structure. This completes the fabrication of a semiconductor device according to the present invention.

[0052] In summary, this invention primarily discloses a wafer-to-wafer stacking technology for high bandwidth memory (HBM). The process involves first bonding a first wafer 12 to a temporary carrier 14, then performing a first grinding process on the back side of the first wafer, followed by a first trimming process on the sidewalls of the first wafer to form a first protective layer 24 on the sidewalls and a first contact pad on the back side of the first wafer. Next, a second wafer 32 is bonded to the first wafer. Then, a second grinding process is performed on the back side of the second wafer, followed by a second trimming process on the sidewalls of the second wafer to form a second protective layer 34 on both the sidewalls of the first and second wafers. Finally, a second contact pad is formed on the back side of the second wafer. The wafer bonding, grinding, and trimming processes can then be repeated to form a structure composed of multiple stacked wafers. Finally, the carrier is removed, and a logic wafer is bonded to the first wafer. Since a protective layer is easily formed on the sidewall of the wafer after each new wafer is bonded, the width of the protective layer on the sidewall of the lower wafer (such as the first wafer) is preferably greater than the width of the protective layer on the sidewall of the upper wafer (such as the second or third wafer).

[0053] According to one embodiment of the invention, the protective layer on the sidewalls of each wafer can provide additional protection during subsequent packaging, and the bonding methods between wafers and between stacked structures can include, but are not limited to, various bonding methods such as hybrid bonding processes, microbump bonding processes, or gold bump processes. This invention allows multiple wafers to be stacked before chip probe testing (CP test) and repair steps are performed via through-silicon vias (TSVs), redistribution layers (RDLs), contact pads, and bumps on the stacked structure. This reduces manufacturing cycle time and cost compared to the prior art's method of performing probe testing before stacking wafers.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The first wafer is bonded to the carrier; The first grinding process is performed on the back side of the first wafer. The first trimming process is performed on the sidewall of the first wafer. A first protective layer is formed on the sidewall of the first wafer; as well as A first contact pad is formed on the back side of the first wafer.

2. The method of claim 1, wherein the first wafer comprises a plurality of first through-silicon vias, the method comprising: The plurality of first silicon vias are exposed after the first protective layer is formed.

3. The method of claim 2, further comprising exposing the plurality of first silicon vias prior to forming the first contact pad.

4. The method of claim 2, further comprising: The second wafer is bonded to the first wafer; A second grinding process is performed on the back side of the second wafer. A second trimming process is applied to the sidewall of the second wafer. A second protective layer is formed on the sidewall of the first wafer and the sidewall of the second wafer; as well as A second contact pad is formed on the back side of the second wafer.

5. The method of claim 4, wherein the second wafer comprises a plurality of second through-silicon vias, the method comprising: The plurality of second silicon vias are exposed after the second protective layer is formed.

6. The method of claim 4, further comprising exposing the plurality of second silicon vias prior to forming the second contact pad.

7. The method of claim 4, wherein the first wafer sidewall is flush with the second wafer sidewall.

8. The method of claim 1, wherein the carrier comprises a silicon wafer.

9. A semiconductor element, characterized in that, Include: The second wafer is bonded to the first wafer; and A protective layer is disposed on the first wafer sidewall and the second wafer sidewall, wherein the thickness of the protective layer on the second wafer sidewall is less than the thickness of the protective layer on the first wafer sidewall.

10. The semiconductor element of claim 9, further comprising: The third wafer is bonded to the second wafer; and The protective layer is disposed on the first wafer sidewall, the second wafer sidewall, and the third wafer sidewall, wherein the thickness of the protective layer on the third wafer sidewall is less than the thickness of the protective layer on the second wafer sidewall.

11. The semiconductor device of claim 10, wherein the second wafer sidewall is flush with the third wafer sidewall.

12. The semiconductor device of claim 9, wherein the first wafer sidewall is flush with the second wafer sidewall.

Images