Bonding method of semiconductor device
By combining low-melting-point pads with dielectric layers and using low-temperature annealing processes, the problem of not being able to simultaneously achieve low-temperature bonding, conductive interconnection, and insulating isolation in existing technologies has been solved, enabling the development of high-density three-dimensional integration technology and improving product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-16
AI Technical Summary
Existing bonding processes cannot simultaneously meet the multiple requirements of low-temperature bonding, conductive interconnection, and insulation isolation, thus limiting the development of high-density three-dimensional integration technology.
By using a combination of low-melting-point pads and dielectric layers, the pads are melted into a liquid state through a low-temperature annealing process to fill the vias and bond them, achieving conductive interconnection and insulating isolation at low temperatures.
It effectively avoids thermal damage caused by high-temperature bonding, while taking into account low-temperature bonding, conductive interconnection and insulation isolation, thus improving the development of high-density three-dimensional integration technology and product yield.
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Figure CN122228015A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a bonding method for semiconductor devices. Background Technology
[0002] With the development of semiconductor manufacturing processes, high-density 3D integrated advanced packaging technology continues Moore's Law and has become a core direction for improving chip performance. In 3D integrated advanced packaging technology, bonding technology, as a key process for achieving chip interconnection, directly determines the reliability and integration density of the integration.
[0003] Existing bonding processes are either limited to a single material system or rely on high-temperature processes, which cannot simultaneously meet the multiple requirements of low-temperature low-damage, conductive interconnection and insulating isolation, thus restricting the development of high-density three-dimensional integration technology. Summary of the Invention
[0004] This application provides a bonding method for semiconductor devices that can meet multiple requirements such as low-temperature bonding, conductive interconnection, and insulation isolation, thereby improving product yield.
[0005] According to some embodiments of this application, this application provides a bonding method for semiconductor devices, including:
[0006] A first substrate is provided, on which a first low-melting-point pad is formed; a second substrate is provided, on which a dielectric layer is formed, a first via is formed in the dielectric layer, and a second low-melting-point pad is formed in a portion of the first via, the second low-melting-point pad being formed on the second substrate; the first substrate and the second substrate are aligned so that the first low-melting-point pad is inserted into the first via and abuts against the second low-melting-point pad; an annealing process is performed to melt the first low-melting-point pad and the second low-melting-point pad into a liquid state and fuse them to fill the first via and to bond the first substrate to the dielectric layer.
[0007] Furthermore, the melting points of the first low-melting-point pad and the second low-melting-point pad are between 150°C and 300°C.
[0008] Furthermore, both the first low-melting-point pad and the second low-melting-point pad are made of conductive metals or alloys with melting points between 150°C and 300°C.
[0009] Furthermore, the materials of the first low-melting-point pad and the second low-melting-point pad are both alloys composed of a single metal or multiple metals selected from indium, tin, and bismuth.
[0010] Furthermore, the dielectric layer is made of a polymer composed of one or more of polyimide, benzocyclobutene, and polybenzoxazole.
[0011] Furthermore, after the first low-melting-point pad and the second low-melting-point pad melt into a liquid state, they exhibit one of the following states within the first through-hole: partial overflow, complete filling with no overflow, or incomplete filling.
[0012] Furthermore, the top width of the first through hole is greater than or equal to the bottom width.
[0013] Furthermore, the top surface of the second low-melting-point pad abuts against the top surface of the first low-melting-point pad, and the size of the top surface of the second low-melting-point pad is less than or equal to the size of the top surface of the first low-melting-point pad; and / or, the height of the second low-melting-point pad is greater than or equal to the distance from the top surface of the first low-melting-point pad to the top of the first via.
[0014] Furthermore, the height of the second low-melting-point pad is 1 / 5 to 1 / 2 of the thickness of the dielectric layer.
[0015] Further, before aligning the first substrate and the second substrate, the method includes: activating the surfaces of the first low-melting-point pad, the second low-melting-point pad, and the dielectric layer using at least one of plasma and acid solution; and / or, after aligning the first substrate and the second substrate and before performing the annealing process, the method further includes: placing the first substrate and the second substrate into a bonding apparatus for pre-bonding.
[0016] The technical solution provided in this application has at least the following advantages:
[0017] This application provides a bonding method for semiconductor devices. A first low-melting-point pad is formed on a first substrate, and a dielectric layer is formed on a second substrate, with a first via formed in the dielectric layer. A second low-melting-point pad is formed in a portion of the first via. The first and second substrates are aligned so that the first low-melting-point pad is inserted into the first via and contacts the second low-melting-point pad. Then, an annealing process is performed to melt the first and second low-melting-point pads into a liquid state and fuse them to fill the first via and bond the first substrate to the dielectric layer. In this way, the first and second low-melting-point pads are heated and melted into a liquid state and fused to fill the first via, and the first substrate and dielectric layer are bonded. This effectively avoids thermal damage caused by high-temperature bonding, effectively meets the multiple requirements of low-temperature bonding, conductive interconnection, and insulation isolation, promotes the development of high-density three-dimensional integration technology, and is beneficial to product yield. Attached Figure Description
[0018] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic flowchart of the bonding method for the semiconductor device provided in this embodiment;
[0020] Figures 2A to 2C This is a cross-sectional schematic diagram of step S10 in the bonding method of the semiconductor device provided in this embodiment;
[0021] Figures 3A to 3E This is a cross-sectional schematic diagram of step S20 in the bonding method of the semiconductor device provided in this embodiment;
[0022] Figure 4 This is a cross-sectional schematic diagram of step S30 in the bonding method of the semiconductor device provided in this embodiment;
[0023] Figure 5 This is a cross-sectional schematic diagram of step S40 in the bonding method of the semiconductor device provided in this embodiment.
[0024] Explanation of icon numbers:
[0025] 100 - First substrate, 110 - First mask layer, 111 - Second via, 120 - First metal material layer, 121 - First low melting point pad, 200 - Second substrate, 210 - Dielectric layer, 211 - First via, 220 - Second mask layer, 230 - Second metal material layer, 231 - Second low melting point pad. Detailed Implementation
[0026] Research has found that existing bonding processes typically involve simultaneous metal-to-metal and dielectric-to-dielectric bonding at high or medium temperatures. To ensure bond strength, a high-temperature environment (typically above 550°C) or a medium-temperature environment (typically between 300°C and 550°C) is required. However, high or medium temperatures can cause thermal damage to some sensitive materials, and the resulting interconnect structures can exhibit concentrated thermal stress, affecting product packaging yield. Low-temperature bonding processes (typically below 300°C) are usually limited to single materials, such as pure metal low-temperature bonding or pure polymer bonding. However, pure metal low-temperature bonding lacks sufficient insulation performance, and pure polymer bonding cannot meet the requirements for conductive interconnects, making it difficult to adapt to integrated "conductive-insulating" scenarios.
[0027] Based on this, this application provides a bonding method for a semiconductor device, comprising: providing a first substrate on which a first low-melting-point pad is formed; providing a second substrate on which a dielectric layer is formed, a first via is formed on the dielectric layer, and a second low-melting-point pad is formed in a portion of the first via, the second low-melting-point pad being formed on the second substrate; then, aligning the first substrate and the second substrate to insert the first low-melting-point pad into the first via and abut against the second low-melting-point pad; then, performing an annealing process to melt the first low-melting-point pad and the second low-melting-point pad into a liquid state and fuse them to fill the first via, and bonding the first substrate to the dielectric layer. In this way, the first low-melting-point pad and the second low-melting-point pad are heated and melted into a liquid state and then fused to fill the first via, and the first substrate and the dielectric layer are bonded, effectively avoiding thermal damage caused by high-temperature bonding, and effectively balancing the multiple requirements of low-temperature bonding, conductive interconnection, and insulating isolation, thus improving the development of high-density three-dimensional integration technology and benefiting product yield.
[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0029] Figure 1 This is a schematic flowchart illustrating the bonding method for the semiconductor device provided in this embodiment. (Reference) Figure 1 The bonding method for semiconductor devices provided in this application includes:
[0030] S10: Provide a first substrate, on which a first low-melting-point pad is formed;
[0031] S20: A second substrate is provided, on which a dielectric layer is formed, a first through-hole is formed in the dielectric layer, and a second low-melting-point pad is formed in a portion of the first through-hole. The second low-melting-point pad is formed on the second substrate.
[0032] S30: Align the first substrate with the second substrate to insert the first low-melting-point pad into the first through-hole and abut against the second low-melting-point pad;
[0033] S40: Perform an annealing process to melt the first low-melting-point pad and the second low-melting-point pad into a liquid state and fuse them together to fill the first through-hole and to bond the first substrate to the dielectric layer.
[0034] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.
[0035] First, step S10 is performed, providing a first substrate 100, on which a first low-melting-point pad 121 is formed. Then, step S20 is performed, providing a second substrate 200, on which a dielectric layer 210 is formed, a first via 211 is formed in the dielectric layer 210, and a second low-melting-point pad 231 is formed in a portion of the first via 211.
[0036] In practice, steps S10 and S20 can be executed simultaneously, or steps S10 can be executed first and then steps S20, or steps S20 can be executed first and then steps S10.
[0037] In one embodiment, such as Figures 2A to 2C As shown, the steps for forming the first low-melting-point pad 121 include:
[0038] like Figure 2A As shown, a first substrate 100 is provided. The material of the first substrate 100 can be, but is not limited to, silicon (Si), gallium nitride (GaN), and glass. In this embodiment, the melting point of the first low-melting-point pad is between 150°C and 300°C. Preferably, the material of the first low-melting-point pad 121 can be a conductive metal or alloy with a melting point between 150°C and 300°C. Optionally, low-temperature melting-point metal materials between 150°C and 300°C include indium (In) (melting point 156.6°C), tin (Sn) (melting point 231.9°C), lithium (Li) (melting point 180.5°C), and bismuth (Bi) (melting point 271.4°C). Preferably, the material of the first low-melting-point pad 121 is a single metal or an alloy composed of multiple metals selected from indium (In), tin (Sn), and bismuth (Bi).
[0039] Then, a first mask layer 110 is formed on the first substrate 100, and at least one second via 111 is formed in the first mask layer 110, the second via 111 exposing a portion of the surface of the first substrate 100. The material of the first mask layer 110 may be, but is not limited to, photoresist, silicon dioxide, and silicon nitride. If the first mask layer 110 is made of photoresist, a photolithography process can be performed to pattern the first mask layer 110. If the first mask layer 110 is made of silicon dioxide or silicon nitride, a photolithography and etching process is required to pattern the first mask layer 110.
[0040] like Figure 2B As shown, a first metal material layer 120 is formed on the first mask layer 110, and the first metal material layer 120 fills the second through-hole 111. In this embodiment, the first metal material layer 120 can be formed by a lift-off process or a bump plating process.
[0041] like Figure 2C As shown, the first mask layer 110 is removed, and the remaining first metal material layer 120 forms the first low-melting-point pad 121. When the material of the first mask layer 110 is photoresist, the first mask layer 110 is removed by an ashing process; when the first mask layer 110 is silicon dioxide or silicon nitride, the first mask layer 110 is removed by etching.
[0042] For example, the size of the first substrate 100 can be from 300 micrometers to 500 micrometers. The diameter of the second via 111 can be from 0.5 micrometers to 5 micrometers. Correspondingly, the height of the first low-melting-point pad 121 can be from 0.5 micrometers to 5 micrometers. The bottom diameter of the first low-melting-point pad 121 can be from 5 micrometers to 20 micrometers. At least two first low-melting-point pads 121 are formed on the first substrate 100, and the spacing between the first low-melting-point pads 121 can be from 10 micrometers to 40 micrometers.
[0043] In one embodiment, such as Figures 3A to 3E As shown, the steps for forming the second low-melting-point pad 231 include:
[0044] Specifically, such as Figure 3A As shown, a second substrate 200 is provided, which may be made of the same material as the first substrate 100. The material of the second substrate 200 may be, but is not limited to, silicon (Si), gallium nitride (GaN), or glass.
[0045] In this embodiment, the second low-melting-point pad 231 is made of the same material as the first low-melting-point pad 121. The melting point of the second low-melting-point pad 231 is between 150°C and 300°C. The material of the second low-melting-point pad 231 can be a conductive metal or alloy with a melting point between 150°C and 300°C. Preferably, the material of the second low-melting-point pad 231 is a single metal or an alloy composed of multiple metals selected from indium (In), tin (Sn), and bismuth (Bi).
[0046] Then, a dielectric layer 210 is formed on the second substrate 200. In this embodiment, the dielectric layer 210 can be spin-coated or spray-coated on the second substrate 200, and then cured. The dielectric layer 210 in this embodiment can be a polymer composed of one or more of polyimide, benzocyclobutene, and polybenzoxazole. The cured dielectric layer 210 has the functions of high temperature resistance and isolation. Compared with dielectric layers made of other materials, such as silicon dioxide or silicon nitride, this embodiment uses a polymer composed of one or more of polyimide, benzocyclobutene, and polybenzoxazole, which can achieve low-temperature curing, and the spin-coating process is more compatible with subsequent packaging. The low modulus and high flexibility can effectively release thermal stress and avoid cracking and delamination. The low dielectric constant and low loss match the requirements of high-frequency and high-speed interconnection. The coefficient of thermal expansion can be controlled, the interface adhesion is high, and some types have low moisture absorption. It can also realize multi-functional integration of dielectric, bonding, passivation, etc., and the thin and thick film preparation is flexible and the mass production cost is lower.
[0047] Next, as Figure 3A As shown, photolithography and etching processes are performed to form a first via 211 in the dielectric layer 210. Specifically, the process includes the following steps: First, a negative photoresist layer is coated on the dielectric layer 210; then, patterning exposure is performed on the negative photoresist layer, using an exposure dose of 50-400 mJ / cm²; then, the exposed negative photoresist layer is developed using a developer; next, using the negative photoresist layer as a mask, an etching process is performed to form the first via 211 in the dielectric layer 210. Further, after the development process and before the etching process, a soft baking process can be performed to remove any remaining developer. The preferred soft baking process parameters are 2 to 10 minutes and 80 to 120°C. Furthermore, after the etching process, the second substrate 200 is subjected to a hard baking process to completely solidify the dielectric layer 210, thereby improving the mechanical properties of the dielectric layer 210. The hard baking process parameters are preferably 30 minutes to 120 minutes and 80°C to 200°C.
[0048] In one embodiment, the top width of the first via 211 is greater than or equal to the bottom width. For example, the top width of the first via 211 is equal to the bottom width, and the cross-section of the first via 211 is an inverted trapezoid. During the etching process, the dielectric layer 210 is etched at an angle (e.g., within 45°). In another embodiment, the top width of the first via 211 is equal to the bottom width, and the cross-section of the first via 211 is rectangular. Preferably, the top width of the first via 211 is greater than the bottom width, which is beneficial to improving the fault tolerance of the alignment between the first low-melting-point pad and the second low-melting-point pad, and thus improving product yield. If the top width of the first via 211 is less than the bottom width, the fault tolerance of the alignment between the first low-melting-point pad and the second low-melting-point pad will decrease.
[0049] In one embodiment, the thickness of the dielectric layer 210 can be from 5 micrometers to 20 micrometers. A first via 211 on the dielectric layer 210 exposes the second substrate 200, and the depth of the first via 211 can be infinitely close to the thickness of the dielectric layer 210. For example, the depth of the first via 211 can be from 5 micrometers to 20 micrometers.
[0050] In this embodiment, the height of the second low-melting-point pad 231 occupies a portion of the thickness of the dielectric layer. For example, the height of the second low-melting-point pad 231 occupies 1 / 5 to 1 / 2 of the thickness of the dielectric layer 210.
[0051] In this embodiment, a lift-off process is used to form the second metal material layer 230. Specifically, as follows... Figure 3B As shown, a second mask layer 220 is formed on the dielectric layer 210, covering the dielectric layer 210 and filling the first via 211. The second mask layer 220 is, for example, PI (polyimide). Next, as... Figure 3C As shown, a photolithography process is performed to form a second mask layer opening in the second mask layer 220. This second mask layer opening is above and communicates with the first via 211, exposing a portion of the sidewalls of the dielectric layer 210 below the first via 211. That is, the second mask layer 220 covers a portion of the surface of the dielectric layer 210 above the first via 211. Taking an example where the first via 211 is an inverted trapezoid and the second mask layer opening is rectangular, the width of the second mask layer opening is greater than the bottom width of the first via 211 and less than the top width of the first via 211. Figure 3DAs shown, a second metal material layer 230 is formed, covering the top of the second mask layer 220 and the dielectric layer 210 exposed in the first via 211. Next, the second mask layer 220 is removed, and the second metal material layer 230 on top of the second mask layer 220 is also removed, leaving the second metal material layer 230 within the first via 211 to form the second low-melting-point pad 231. Since the temperature requirements for removing the dielectric layer 210 are different from those for removing the second mask layer 220, removing the second mask layer 220 does not affect the dielectric layer 210.
[0052] In practice, other processes can also be used to form the second low-melting-point pad 231, such as bump plating, PVD, or electron beam evaporation.
[0053] Next, proceed to step S30, as follows: Figure 4 As shown, the first substrate 100 and the second substrate 200 are aligned so that the first low melting point pad 121 is inserted into the first through hole 211 and abuts against the second low melting point pad 231.
[0054] Prior to step S30, the process further includes activating the surfaces of the first low-melting-point pad 121, the second low-melting-point pad 231, and the dielectric layer 210 using at least one of plasma and an acid solution. Specifically, when plasma is used to activate the surfaces of the first low-melting-point pad 121, the second low-melting-point pad 231, and the dielectric layer 210, the process parameters include: a plasma processing power of 50W to 150W and a processing time of 5 seconds to 120 seconds.
[0055] In one embodiment, an acid solution is used to activate the surfaces of the first low-melting-point pad 121, the second low-melting-point pad 231, and the dielectric layer 210. The acid solution, for example, is a citric acid solution, and the process parameters for the citric acid solution include: a concentration range of 1 wt% to 10 wt%, a processing temperature of 25°C to 40°C, and a processing time of 30 to 60 seconds. After the surface activation treatment is completed, the surface is rinsed with deionized water and dried using nitrogen gas.
[0056] In step S30, any high-precision alignment bonding equipment, including wafer bonding machine, flip bonding machine, hybrid bonding machine, chip bonding machine and hot press bonding machine, can be used to align the first substrate 100 and the second substrate 200, and insert the first low melting point pad 121 into the first through hole 211 and abut against the second low melting point pad 231.
[0057] In this embodiment, the top surface of the second low-melting-point pad 231 abuts against the top surface of the first low-melting-point pad 121, and the size of the top surface of the second low-melting-point pad 231 is less than or equal to the size of the top surface of the first low-melting-point pad 121. In this embodiment, the height of the second low-melting-point pad 231 is greater than or equal to the distance from the top surface of the first low-melting-point pad 121 to the top of the first through-hole 211. If the height of the second low-melting-point pad 231 is less than the distance from the top surface of the first low-melting-point pad 121 to the top of the first through-hole 211, when the first low-melting-point pad 121 and the second low-melting-point pad 231 melt into a liquid state, a large gap will remain in the first through-hole 211, which may prevent conductive interconnection.
[0058] Preferably, the cross-section of the first through-hole 211 is an inverted trapezoid, the top surface dimension of the second low-melting-point pad 231 is smaller than the top surface dimension of the first low-melting-point pad 121, and the height of the second low-melting-point pad 231 is greater than the distance from the top surface of the first low-melting-point pad 121 to the top of the first through-hole 211. In another embodiment, the cross-section of the first through-hole 211 is rectangular, the top surface dimension of the second low-melting-point pad 231 is smaller than the top surface dimension of the first low-melting-point pad 121, and the height of the second low-melting-point pad 231 is greater than the distance from the top surface of the first low-melting-point pad 121 to the top of the first through-hole 211. In yet another embodiment, the cross-section of the first through-hole 211 is rectangular, the top surface dimension of the second low-melting-point pad 231 is equal to the top surface dimension of the first low-melting-point pad 121, and the height of the second low-melting-point pad 231 is equal to the distance from the top surface of the first low-melting-point pad 121 to the top of the first through-hole 211.
[0059] When the size of the top surface of the second low-melting-point pad 231 is smaller than the size of the top surface of the first low-melting-point pad 121, the first substrate 100 and the second substrate 200 are aligned, and when the first low-melting-point pad 121 abuts against the second low-melting-point pad 231, a gap is left between the first substrate 100 and the dielectric layer 210.
[0060] Next, step S30 further includes: after aligning the first substrate 100 and the second substrate 200, and before performing the annealing process, it further includes: placing the first substrate 100 and the second substrate 200 into a bonding apparatus for pre-bonding.
[0061] In one embodiment, the pre-bonding process parameters include: a temperature of 80°C to 150°C, a pressure of 0.5 MPa to 5 MPa, and continuous temperature and pressure maintenance for 5 to 30 minutes.
[0062] Next, step S40 is executed to perform the annealing process, such as... Figure 5As shown, the first low-melting-point pad 121 and the second low-melting-point pad 231 are melted into a liquid state and then fused together to fill the first through-hole 211 and to bond the first substrate 100 to the dielectric layer 210. In this embodiment, after the first low-melting-point pad 121 and the second low-melting-point pad 231 are melted into a liquid state, preferably, the first low-melting-point pad 121 and the second low-melting-point pad 231 completely fill the first through-hole 211 without overflowing. However, it is understood that after the first low-melting-point pad 121 and the second low-melting-point pad 231 are melted into a liquid state, there may be partial overflow, or the first through-hole 211 may not be completely filled, both of which are within the protection scope of this application. One end of the interconnect structure A formed after melting is connected to the first substrate 100, and the other end is connected to the second substrate 200, thereby ensuring conductive interconnection, and adjacent interconnect structures A are separated by the dielectric layer 210 to meet the requirements of insulation isolation.
[0063] The annealing process parameters include annealing at a temperature range of 100°C to 200°C for 30 to 120 minutes. During the annealing process, the first low-melting-point pad 121 and the second low-melting-point pad 231 melt and fuse together in the first through-hole 211 to form an integrated interconnect structure A of the first low-melting-point pad and the second low-melting-point pad.
[0064] In summary, the semiconductor device bonding method provided in this application includes providing a first substrate on which a first low-melting-point pad is formed; providing a second substrate on which a dielectric layer is formed, a first via is formed in the dielectric layer, and a second low-melting-point pad is formed in a portion of the first via; aligning the first substrate and the second substrate to insert the first low-melting-point pad into the first via and abut against the second low-melting-point pad; performing an annealing process to melt the first low-melting-point pad and the second low-melting-point pad into a liquid state and fuse them to fill the first via; and bonding the first substrate to the dielectric layer. Thus, the first low-melting-point pad and the second low-melting-point pad are heated and melted into a liquid state and then fused to fill the first via, and the first substrate and the dielectric layer are bonded. This effectively avoids thermal damage caused by high-temperature bonding and effectively addresses the multiple requirements of low-temperature bonding, conductive interconnection, and insulating isolation, improving the development of high-density three-dimensional integration technology and benefiting product yield.
[0065] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A bonding method for a semiconductor device, characterized in that, include: A first substrate is provided, on which a first low-melting-point pad is formed; A second substrate is provided, on which a dielectric layer is formed, a first via is formed in the dielectric layer, and a second low-melting-point pad is formed in a portion of the first via. Align the first substrate with the second substrate to insert the first low-melting-point pad into the first through-hole and abut against the second low-melting-point pad; An annealing process is performed to melt the first low-melting-point pad and the second low-melting-point pad into a liquid state and then fuse them to fill the first via, and to bond the first substrate to the dielectric layer.
2. The bonding method for semiconductor devices according to claim 1, characterized in that, The melting points of both the first low-melting-point pad and the second low-melting-point pad are between 150°C and 300°C.
3. The bonding method for semiconductor devices according to claim 2, characterized in that, The materials of the first low-melting-point pad and the second low-melting-point pad are both conductive metals or alloys with melting points between 150°C and 300°C.
4. The bonding method for semiconductor devices according to claim 3, characterized in that, The materials of the first low-melting-point pad and the second low-melting-point pad are both alloys composed of a single metal or multiple metals selected from indium, tin, and bismuth.
5. The bonding method for semiconductor devices according to claim 1, characterized in that, The dielectric layer is made of a polymer composed of one or more of polyimide, benzocyclobutene, and polybenzoxazole.
6. The bonding method for semiconductor devices according to claim 1, characterized in that, The first low-melting-point pad and the second low-melting-point pad are completely filled after melting into a liquid state.
7. The bonding method for semiconductor devices according to claim 1, characterized in that, The top width of the first through hole is greater than or equal to the bottom width.
8. The bonding method for a semiconductor device according to claim 1, characterized in that, The top surface of the second low-melting-point pad abuts against the top surface of the first low-melting-point pad, and the size of the top surface of the second low-melting-point pad is less than or equal to the size of the top surface of the first low-melting-point pad; and / or, the height of the second low-melting-point pad is greater than or equal to the distance from the top surface of the first low-melting-point pad to the top of the first via.
9. The bonding method for a semiconductor device according to claim 1, characterized in that, The height of the second low-melting-point pad is 1 / 5 to 1 / 2 of the thickness of the dielectric layer.
10. The bonding method for a semiconductor device according to claim 1, characterized in that, Before aligning the first substrate and the second substrate, the method includes: activating the surfaces of the first low-melting-point pad, the second low-melting-point pad, and the dielectric layer using at least one of plasma and acid solution; and / or, after aligning the first substrate and the second substrate and before performing the annealing process, the method further includes: placing the first substrate and the second substrate into a bonding apparatus for pre-bonding.