On-chip interconnect network structure based on multi-die three-dimensional stacking

Abstract

Embodiments of the present disclosure disclose a multi-wafer three-dimensional stacked on-chip interconnection network structure. A specific implementation of the structure includes a power supply layer, a switching layer, a first active interconnection layer, a second active interconnection layer, and a core particle layer; the power supply layer is based on 3D stacked chip reconstruction to provide distributed power supply; the first active interconnection layer and the second active interconnection layer use programmable switching interconnection core particles to form an active network through rewiring layer reconstruction and conduct dynamic routing and topology reconstruction; the power supply layer, the switching layer, the first active interconnection layer, and the second active interconnection layer are integrated by wafer-to-wafer bonding, and the core particle layer is attached by chip-to-wafer. The implementation expands the interconnection network in the vertical direction through multi-layer wafer stacking, avoiding the limitation of single-layer area.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of advanced packaging and system integration technology for integrated circuits, and more specifically to on-chip interconnect network structures based on multi-wafer three-dimensional stacking. Background Technology

[0002] Common implementations of on-chip system interconnect structures include adapter board structures, multilayer RDL reconstruction structures based on PI adhesive (polyimide), packaging substrate structures, and dedicated interconnect base die structures.

[0003] Among these, the adapter board structure relies on its high-density wiring to achieve physical connections between chips, but the interconnect logic is entirely determined by the chip itself. The adapter board only provides static routing, and chips typically communicate with each other through point-to-point interconnects (such as SerDes), lacking global network flexibility. This structure is suitable for small-scale integration, but interconnects become a bottleneck as the number of chips increases. The multilayer RDL reconfiguration structure based on PI adhesive achieves an active interconnect network through reconfiguration technology, and the interconnect chips are programmable. However, limited by the power supply requirements of the Top layer, DTC (Deep Trench Capacitor) chips must be placed directly below the logic chips, resulting in a reduced layout density of interconnect chips. While the interconnect network offers some flexibility, its scale is limited, and long-distance interconnect delays are high. The packaging substrate structure can achieve wafer-level interconnects, but the substrate is passive, resulting in poor interconnect flexibility and reliance on the interconnect capabilities of the Top layer chips. Although the interconnect range is wider than the adapter board, dynamic reconfiguration is not possible, and signal transmission delay increases significantly with distance. In the dedicated interconnect Base Die structure, the Base Die serves as an interconnect base, providing programmable interfaces and vertical interconnects. However, due to the limitations of the photomask area, when the computed chip area approaches the photomask limit, the interconnect expansion capability of the Base Die is insufficient, and the interconnect layer is only one layer, which cannot solve the problem of long-distance delay between large-scale chips.

[0004] All of the above structures are based on single-layer interconnects or limited stacking, resulting in small interconnect network size, low flexibility, and high latency for long-distance communication. The interconnect core relies on the chip or passive substrate, making it impossible to independently achieve efficient and scalable on-chip networks. Summary of the Invention

[0005] The summary portion of this disclosure is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description portion. This summary portion is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0006] Some embodiments of this disclosure propose an on-chip interconnect network structure based on multi-wafer three-dimensional stacking to solve the technical problems mentioned in the background section above.

[0007] In a first aspect, some embodiments of this disclosure provide an on-chip interconnect network structure based on multi-wafer 3D stacking. The structure includes: a power supply layer, a transition layer, a first active interconnect layer, a second active interconnect layer, and a chip layer. The power supply layer is reconstructed based on 3D stacked power supply chips to provide distributed power supply. The first and second active interconnect layers adopt programmable switching interconnect chips, and form an active network through rewiring layer reconstruction, and perform dynamic routing and topology reconstruction. The power supply layer, transition layer, first active interconnect layer, and second active interconnect layer are integrated by wafer-to-wafer bonding, and the chip layer is mounted on the wafer through chip-to-wafer bonding.

[0008] Optionally, the above power supply layer is based on a multi-layer redistribution layer wafer-level reconstruction process, using 3D stacked power supply chips, with through-silicon vias and pads fabricated on the back side, forming a power supply network after reconstruction, which can provide power to a single chip or multiple chips in a coordinated manner.

[0009] Optionally, the aforementioned transition layer is fabricated using silicon transition board technology and includes: high-density deep trench capacitors and through-silicon vias. Multi-layer wiring is achieved through damascene technology, serving as a signal transition and power transmission intermediary. The silicon transition board is a high-density electronic interconnection intermediary. By fabricating high-density wiring layers and vertical through-silicon vias inside the silicon transition board, ultra-high bandwidth and efficient connection between multiple chips mounted on top of the silicon transition board are achieved.

[0010] Optionally, the first active interconnect layer and the second active interconnect layer adopt a multi-layer rewiring layer reconstruction process and use programmable switching interconnect chips. The bumps of the first active interconnect layer chip are arranged upwards, and the bumps of the second active interconnect layer chip are arranged downwards to form a complementary interconnect network. The programmable switching interconnect chip is a dedicated chip based on a coarse-grained reconfigurable architecture or an embedded field-programmable gate array, which allows dynamic data routing and function reconfiguration to be implemented at the chip level. The hardware connection method can be changed by programming to adapt to different computing tasks.

[0011] Optionally, the power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer are stacked by wafer-to-wafer bonding, and the chip layer completes system integration by chip-to-wafer mounting.

[0012] Secondly, some embodiments of this disclosure provide a fabrication process for an on-chip interconnect network structure based on multi-wafer three-dimensional stacking. This fabrication process includes: fabricating a power supply layer, a transition layer, a first active interconnect layer, and a second active interconnect layer on each target wafer; sequentially stacking the power supply layer, transition layer, first active interconnect layer, and second active interconnect layer in three dimensions via wafer-to-wafer bonding, wherein the bonding interface includes high-density copper-copper hybrid bonding to achieve low-resistance, high-bandwidth vertical interconnection; and bonding multiple functional chips to the second active interconnect layer via a chip-to-wafer mounting process on top of the stacked four-layer structure, thereby completing the integration of the entire on-chip interconnect network structure.

[0013] The various embodiments disclosed above have the following beneficial effects: Through the on-chip interconnect network structure based on multi-wafer three-dimensional stacking of some embodiments of this disclosure, the interconnect network expands vertically through multi-layer wafer stacking, avoiding the area limitation of a single layer. For example, the first active interconnect layer and the second active interconnect layer handle local and global interconnects respectively, increasing interconnect resources and supporting more chip integration. Existing base dies are limited by photomasks, while this patent, through multi-layer stacking, effectively doubles the interconnect area, allowing the system scale to exceed photomask limits. Enhanced flexibility: The active interconnect layer uses programmable switching chips, allowing software-defined network topologies (such as Mesh, Torus, etc.) to adapt to different application requirements. Compared with fixed interconnect adapter boards, this patent can dynamically reconfigure paths, achieving load balancing and fault tolerance. High performance and low latency: Multi-layer stacking shortens the interconnect path. For example, long-distance communication can be achieved through vertical TSVs and short-distance horizontal interconnects, reducing latency by more than 30% compared to a single long path. Through high-speed switching of the active layer, the number of signal relays is reduced, optimizing latency. High power supply efficiency: An independent power supply layer provides distributed power supply, reducing voltage drop while avoiding occupying interconnect layer area. In existing technologies, DTC dies encroach on interconnect space. This patent separates the power supply layer from the interconnect layer, increasing interconnect density. Reliability is improved: mature W2W bonding and D2W mounting processes enhance mechanical strength and thermal management through a stacked structure. Three-dimensional stacking allows for heat dissipation, and improved heat dissipation through TSVs results in system reliability superior to 2.5D integration. Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and elements are not necessarily drawn to scale.

[0015] Figure 1 This is a schematic diagram of a multi-wafer three-dimensional stacked on-chip interconnect network structure disclosed herein;

[0016] Figure 2 This is a flowchart of some embodiments of the fabrication process of a multi-wafer three-dimensional stacked on-chip interconnect network structure according to the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0018] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0019] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0022] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] Figure 1 A schematic diagram of an on-chip interconnect network structure based on multi-wafer three-dimensional stacking according to the present disclosure is shown. The on-chip interconnect network structure based on multi-wafer three-dimensional stacking includes: a power supply layer 101, a transition layer 102, a first active interconnect layer 103, a second active interconnect layer 104, and a core layer 105.

[0024] In some embodiments, the power supply layer is reconstructed based on 3D stacked power supply chips to provide distributed power supply. The aforementioned power supply layer is based on a multi-layer (RDL) redistribution layer wafer-level reconstruction process, using 3D stacked power supply chips (high input voltage / low current, low output voltage / high current), with through silicon vias (TSVs) and pads fabricated on the back side, forming a power supply network after reconstruction, which can provide power supply in single-chip or multi-chip collaboratively.

[0025] The power supply layer provides efficient and stable distributed power for the entire on-chip system, converting the high voltage / low current input from the outside into the low voltage / high current required by the chip.

[0026] The power supply layer is fabricated using a multi-layer RDL wafer-level reconfiguration process. Multiple pre-tested, qualified 3D stacked power supply chips are embedded within an organic dielectric (such as polyimide, PI) to form a reconfigured wafer. These power supply chips employ a three-dimensional stacked design, integrating power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and control circuitry to achieve high conversion efficiency. On the back side of the reconfigured wafer, through-silicon vias and pads are fabricated using semiconductor processes for power and signal connections to the underlying packaging substrate. This power supply layer can operate monolithically or in combination, providing a unified power supply network for the upper-layer system.

[0027] Multilayer RDL wafer-level reconfiguration is an advanced packaging technology that achieves high-density, high-performance interconnects between chips by rearranging circuitry on the wafer. Essentially, it involves creating additional metal wiring layers and insulating layers on top of the original I / O pads of the chip or wafer, redistributing electrical signals to locations more conducive to package connections. In the multilayer stacked architecture of on-chip systems, it is responsible for horizontal signal transmission and power distribution between different chips.

[0028] Optionally, the aforementioned interposer layer is fabricated using silicon interposer technology and includes high-density deep trench capacitors (DTCs) and through-silicon vias (TSVs). Multi-layer wiring is achieved through a damascus process, serving as a signal switching and power transmission intermediary. The silicon interposer is a high-density electronic interconnect intermediary. By fabricating high-density wiring layers and vertical TSVs within the silicon interposer, ultra-high bandwidth and efficient connections are achieved between multiple chips mounted on top of the silicon interposer. The silicon interposer enables heterogeneous integration, allowing chips (i.e., "dies") from different process nodes, with different functions, and even from different suppliers to be integrated onto the same silicon interposer and work together.

[0029] The aforementioned transition layer serves as an intermediate hub for signal switching and power transmission, providing high-density vertical interconnects and decoupling capacitors. This transition layer is manufactured using a silicon interconnect process. The silicon interconnect utilizes a damascus process to achieve multi-layer copper wiring, providing high-density horizontal interconnects. The interconnect integrates high-density deep trench capacitors to provide instantaneous current to the upper-layer chips and stabilize the power supply voltage. TSVs running through the interconnect enable vertical power and signal transmission between the power supply layer and the upper active interconnect layer.

[0030] In some embodiments, the first active interconnect layer and the second active interconnect layer employ programmable switching interconnect chips, reconfigured through a rewiring layer to form an active network, and perform dynamic routing and topology reconfiguration. The first active interconnect layer and the second active interconnect layer constitute the "intelligent" interconnect backbone of the system-on-a-chip, responsible for receiving, routing, and forwarding data packets, realizing a dynamic and reconfigurable network topology.

[0031] The aforementioned first and second active interconnect layers employ a multi-layer RDL redistribution layer reconstruction process and utilize programmable switching interconnect chips. The first active interconnect layer chips have their bumps facing upwards, while the second active interconnect layer chips have their bumps facing downwards, forming a complementary interconnect network. These programmable switching interconnect chips are dedicated chips based on a coarse-grained reconfigurable architecture (CGRA) or an embedded field-programmable gate array (eFPGA), allowing for dynamic data routing and functional reconfiguration at the chip level. Hardware connectivity can be programmed to adapt to different computing tasks. Within the chip system, the programmable switching interconnect chip is responsible for efficiently managing and scheduling data flow between individual chips. Ensuring efficient and reliable operation of the programmable switching interconnect chip involves key technologies such as advanced packaging and high-density interconnects, flexible data routing and network topology, reliability and testability design, and power and consumption management.

[0032] The first and second active interconnect layers embed multiple programmable switching interconnect chips into the dielectric layer and perform high-density routing via RDL to form a continuous active network. The programmable switching interconnect chips are dedicated chips based on coarse-grained reconfigurable architectures or embedded field-programmable gate arrays, and their routing logic can be configured via software.

[0033] The first active interconnect layer uses a "bump-up" configuration, with its active surface connected to the upper second active interconnect layer via micro-bumps. The second active interconnect layer uses a "bump-down" configuration, with its active surface connected to the lower first active interconnect layer via micro-bumps. This complementary configuration allows the two active interconnect layers to communicate directly via the shortest vertical interconnect (such as hybrid bonding), forming a high-bandwidth, low-latency three-dimensional switching network. The first layer can primarily handle data exchange within a local area, while the second layer can handle global data exchange, thereby achieving task offloading and optimization.

[0034] In some embodiments, wafer-to-wafer bonding is used to integrate the power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer, and chip-to-wafer mounting is used to attach the chip layer.

[0035] The aforementioned power supply layer, the aforementioned transition layer, the first active interconnect layer, and the second active interconnect layer are stacked by wafer-to-wafer W2W bonding, and the chip layer completes system integration by chip-to-wafer D2W mounting.

[0036] The chip layer integrates various functional chips, such as CPU, GPU, memory, and I / O controllers, which are the entities that perform computing tasks. These functional chips are integrated onto the upper surface of the active interconnect layer 2 using a chip-to-wafer mounting process. Specific steps include: thermoforming electrical connections using thermal bonding, underfilling to enhance mechanical reliability, molding to protect the chip and provide mechanical support, and finally, grinding to thin the chip and control overall thickness and improve heat dissipation.

[0037] Figure 2 A flowchart 200 illustrates a fabrication process for an on-chip interconnect network structure based on multi-wafer 3D stacking according to the present disclosure. The fabrication process for this on-chip interconnect network structure based on multi-wafer 3D stacking includes the following steps:

[0038] Step 201: Construct a power supply layer, a transition layer, a first active interconnect layer, and a second active interconnect layer on each target wafer.

[0039] In some embodiments, the execution entity of the fabrication process based on the on-chip interconnect network structure of multi-wafer three-dimensional stacking (e.g., the control terminal of the fabrication process) can fabricate a power supply layer, a transition layer, a first active interconnect layer and a second active interconnect layer on each target wafer respectively.

[0040] Step 202: The power supply layer, the transition layer, the first active interconnect layer and the second active interconnect layer are stacked in three dimensions in sequence by wafer-to-wafer bonding.

[0041] In some embodiments, the aforementioned execution entity can perform wafer-to-wafer bonding to sequentially stack the power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer in three dimensions. The bonding interface includes high-density copper-copper hybrid bonding to achieve low-resistance, high-bandwidth vertical interconnects.

[0042] Step 203: On the stacked four-layer structure, multiple functional chips are bonded to the second active interconnect layer through chip-to-wafer mounting process to complete the integration of the entire on-chip interconnect network structure.

[0043] In some embodiments, the aforementioned execution entity can bond multiple functional chips to the second active interconnect layer on top of the stacked four-layer structure using a chip-to-wafer mounting process, thereby completing the integration of the entire on-chip interconnect network structure.

[0044] The embodiments disclosed above have the following beneficial effects: Multilayer wafer 3D stacked architecture: In particular, the layered design and sequential stacking structure of the power supply layer, transition layer, and dual active interconnect layers are the core for achieving scalability and low latency. Programmable configuration of active interconnect layers: Programmable switched interconnect dies are used in the first and second active interconnect layers, and active networks are formed through RDL reconstruction to achieve flexible interconnection. 3D stacked power supply chip reconstruction of the power supply layer: The specific design of the power supply chip (high voltage input / low voltage output) and the back-side TSV process, combined with reconstruction technology, provide efficient distributed power supply. Manufacturing process integration method: Including specific process steps (such as bonding, underfill, molding, and thinning) for W2W bonding of each functional layer and D2W mounting of die layers, ensuring stack reliability and interconnect density.

[0045] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0046] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. A multi-wafer three-dimensional stacked on-chip interconnect network structure, characterized in that, include: Power supply layer, transition layer, first active interconnect layer, second active interconnect layer and core layer; The power supply layer is reconstructed based on 3D stacked power supply chips to provide distributed power supply; The first and second active interconnect layers use programmable switching interconnect chips, which are reconfigured through the rewire layer to form an active network and perform dynamic routing and topology reconfiguration. The power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer are integrated by wafer-to-wafer bonding, and the chip layer is mounted on the wafer by chip bonding.

2. The on-chip interconnect network structure based on multi-wafer three-dimensional stacking according to claim 1, characterized in that, The power supply layer is based on a multi-layer redistribution layer wafer-level reconstruction process, using 3D stacked power supply chips, with through-silicon vias and pads fabricated on the back side. After reconstruction, a power supply network is formed, which can provide power to a single chip or multiple chips in a coordinated manner.

3. The on-chip interconnect network structure based on multi-wafer three-dimensional stacking according to claim 2, characterized in that, The interconnect layer is fabricated using silicon interconnect board technology and includes high-density deep trench capacitors and through-silicon vias. Multi-layer wiring is achieved through damascene technology, serving as a signal interconnection and power transmission intermediary. The silicon interconnect board is a high-density electronic interconnection intermediary. By fabricating high-density wiring layers and vertical through-silicon vias inside the silicon interconnect board, ultra-high bandwidth and efficient connection between multiple chips mounted on top of the silicon interconnect board are achieved.

4. The on-chip interconnect network structure based on multi-wafer three-dimensional stacking according to claim 3, characterized in that, The first active interconnect layer and the second active interconnect layer adopt a multi-layer rewiring layer reconstruction process and use programmable switching interconnect chips. The bumps of the first active interconnect layer chip are arranged upwards, and the bumps of the second active interconnect layer chip are arranged downwards to form a complementary interconnect network. The programmable switching interconnect chip is a dedicated chip based on a coarse-grained reconfigurable architecture or an embedded field-programmable gate array, which allows dynamic data routing and function reconfiguration to be implemented at the chip level. The hardware connection method can be changed by programming to adapt to different computing tasks.

5. The on-chip interconnect network structure based on multi-wafer three-dimensional stacking according to claim 1, characterized in that, The power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer are stacked by wafer-to-wafer bonding, and the chip layer completes system integration by chip mounting on the wafer.

6. A fabrication process for a multi-wafer three-dimensional stacked on-chip interconnect network structure, characterized in that, include: The power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer are fabricated and reconstructed on each target wafer respectively; By using wafer-to-wafer bonding, the power supply layer, the transition layer, the first active interconnect layer, and the second active interconnect layer are stacked in three dimensions in sequence. The bonding interface includes high-density copper-copper hybrid bonding to achieve low-resistance, high-bandwidth vertical interconnect. On top of the stacked four-layer structure, multiple functional chips are bonded to the second active interconnect layer through chip-to-wafer mounting technology, thus completing the integration of the entire on-chip interconnect network structure.

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