Array substrate and display device

Abstract

An array substrate includes: a first substrate; a first conductive layer located on the first substrate, the first conductive layer including a plurality of data lines; a buffer layer located on the side of the first conductive layer away from the first substrate; a semiconductor material layer located on the side of the buffer layer away from the first substrate, wherein the semiconductor material layer includes an active layer of a transistor; a gate insulating layer located on the side of the semiconductor material layer away from the first substrate; and a second conductive layer located on the side of the gate insulating layer away from the first substrate, wherein the second conductive layer includes at least a portion of a source of a transistor, at least a portion of a drain of a transistor, and at least a portion of a gate of a transistor.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate, a display device, and a method for manufacturing the array substrate. Background Technology

[0002] In the rapidly evolving field of thin-film transistor (TFT) technology, advancements in materials science and manufacturing processes are crucial for improving device performance and functionality. TFTs are integrated components in a wide range of applications, including displays, sensors, and integrated circuits. Innovative approaches to film composition and mask utilization are constantly being developed to maximize efficiency, improve electrical properties, and reduce manufacturing complexity. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate, comprising: a first substrate; a first conductive layer located on the first substrate, wherein the first conductive layer includes a plurality of data lines; a buffer layer located on the side of the first conductive layer away from the first substrate; a semiconductor material layer located on the side of the buffer layer away from the first substrate, wherein the semiconductor material layer includes an active layer of a transistor; a gate insulating layer located on the side of the semiconductor material layer away from the first substrate; and a second conductive layer located on the side of the gate insulating layer away from the first substrate, wherein the second conductive layer includes at least a portion of the source of the transistor, at least a portion of the drain of the transistor, and at least a portion of the gate of the transistor.

[0004] Optionally, the source extends through the gate insulation layer and the buffer layer to be electrically connected to a corresponding data line among the plurality of data lines.

[0005] Optionally, the array substrate further includes a third conductive layer located on the side of the buffer layer away from the first substrate; wherein the third conductive layer includes a relay electrode; the source electrode extends through the gate insulating layer and the buffer layer via a via to be connected to the relay electrode; and the relay electrode is connected to a corresponding data line among the plurality of data lines.

[0006] Optionally, the relay electrode is located on the side of the corresponding data line away from the first substrate and on the side of the source electrode close to the first substrate; and the relay electrode comprises the same material as at least one of the gate electrode or the drain electrode.

[0007] Optionally, the source includes a first end that contacts the active layer and a second end that does not contact the active layer; and the side of the second end closest to the first substrate contacts the gate insulating layer.

[0008] Optionally, the array substrate further includes: a first passivation layer located on the side of the second conductive layer away from the first substrate; and a planarization layer located on the side of the first passivation layer away from the first substrate; wherein the first passivation layer comprises a plurality of sublayers with different compositions.

[0009] Optionally, the stress of the first passivation layer is in the range of -4000 Pa to -1000 Pa.

[0010] Optionally, the first passivation layer includes a first sublayer located on the side of the second conductive layer away from the first substrate, and a second sublayer located on the side of the first sublayer away from the first substrate; and one of the first sublayer and the second sublayer includes silicon oxide, while the other includes silicon nitride.

[0011] Optionally, the second sublayer comprises 0.3% to 2.0% w / w of silicon-hydrogen.

[0012] Optionally, the second sublayer comprises 8% to 15% w / w silicon-hydrogen.

[0013] Optionally, the second sublayer comprises 1% to 10% w / w silicon-hydrogen.

[0014] Optionally, the thickness of the first sublayer is in the range of 100 nm to 300 nm; and the thickness of the second sublayer is in the range of 150 nm to 500 nm.

[0015] Optionally, the first passivation layer further includes a third sublayer located on the side of the second sublayer away from the first substrate; and the third sublayer includes silicon nitride.

[0016] Optionally, the second sublayer comprises 0.3% to 2.0% w / w of silicon-hydrogen; and the third sublayer comprises 8% to 15% w / w of silicon-hydrogen.

[0017] Optionally, the ratio of the thickness of the second sublayer to the thickness of the third sublayer is in the range of 1:4 to 1:1; the thickness of the first sublayer is in the range of 100nm to 300nm; and the total thickness of the second sublayer and the third sublayer is in the range of 150nm to 500nm.

[0018] Optionally, the array substrate further includes a fourth conductive layer located on the side of the gate insulating layer away from the first substrate and on the side of the second conductive layer close to the first substrate; wherein at least one of the gate or the drain includes a sublayer located on the fourth conductive layer and a sublayer located on the second conductive layer.

[0019] Optionally, the array substrate further includes a fifth conductive layer located on the side of the second conductive layer away from the first substrate; wherein at least one of the gate, the source, or the drain includes a sublayer located in the second conductive layer and a sublayer located in the fifth conductive layer.

[0020] Optionally, the gate is spaced apart from the drain by a first minimum distance and from the source by a second minimum distance; and the first minimum distance is at least 4 μm larger than the second minimum distance.

[0021] Optionally, the array substrate further includes: a first electrode layer located on the side of the planarization layer away from the first substrate; a second passivation layer located on the side of the first electrode layer away from the first substrate; a second electrode layer located on the side of the second passivation layer away from the first substrate; and a plurality of touch signal lines, a plurality of touch leads, and a plurality of connection electrodes; wherein a corresponding connection electrode among the plurality of connection electrodes connects the touch signal lines among the plurality of touch signal lines to the touch leads among the plurality of touch leads; the first electrode layer includes a first electrode and the plurality of touch leads; the second electrode layer includes a second electrode and the plurality of connection electrodes; and the second electrode is electrically connected to the drain of the transistor.

[0022] Optionally, the array substrate further includes vias through which the corresponding connection electrodes are connected to the touch signal line and the touch lead; wherein a portion of the touch lead is inserted into the via; the orthographic projection of the touch lead on the first substrate partially overlaps with the orthographic projection of the corresponding connection electrode on the first substrate; and the corresponding connection electrode connects the touch signal line to the touch lead, wherein the touch signal line and the touch lead are located on two different layers.

[0023] Optionally, the array substrate further includes: a third passivation layer located on the side of the second electrode layer away from the first substrate; and a touch electrode layer located on the side of the third passivation layer away from the first substrate; wherein the plurality of touch signal lines are located on the touch electrode layer; the touch signal lines extend through vias penetrating the third passivation layer to connect to the corresponding connection electrode; and the corresponding connection electrode extends through vias penetrating the second passivation layer to connect to the touch lead.

[0024] On the other hand, this disclosure provides a display device including an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 A scanning electron microscope image of an array substrate with the inorganic layer separated from the gate is shown.

[0027] Figure 2 A scanning electron microscope image of an array substrate in which the inorganic layer and the gate have not separated is shown.

[0028] Figure 3 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 4 Scanning electron microscope images of array substrates according to some embodiments of the present disclosure are shown.

[0030] Figure 5 The correlation between the gate voltage and drive current of transistors in the relevant array substrate is shown.

[0031] Figure 6 The correlation between the gate voltage and drive current of transistors in an array substrate according to some embodiments of the present disclosure is shown.

[0032] Figure 7 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0033] Figure 8 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 9 This is a schematic diagram illustrating the structure of a portion of the display area of ​​an array substrate according to some embodiments of the present disclosure.

[0035] Figure 10 This is a schematic diagram illustrating the structure of a portion of the peripheral region of an array substrate according to some embodiments of the present disclosure.

[0036] Figure 11 It is along Figure 10 Cross-sectional view of line A-A' in the middle.

[0037] Figure 12 The correlation between the gate voltage and drive current of a second transistor in the peripheral region of an array substrate according to some embodiments of the present disclosure is shown.

[0038] Figure 13 The correlation between the gate voltage and drive current of a second transistor in the peripheral region of an array substrate according to some embodiments of the present disclosure is shown.

[0039] Figure 14 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 15 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 16 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 17 Depicting Figure 14 and Figure 15 A schematic diagram of the via SV described in the diagram.

[0043] Figure 18 yes Figure 14 and Figure 15 An enlarged view of the via SV described in the image.

[0044] Figure 19 The connection between the corresponding connecting electrode and the touch lead located in the first electrode layer is shown.

[0045] Figure 20 The connection between the corresponding connection electrode and the touch signal line located in the second conductive layer is shown. Detailed Implementation

[0046] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0047] In related display panels, issues of device whitening and conductive properties exist in the double-layer copper process used to form the gate. The inventors of this disclosure have discovered that the root cause is the separation of the inorganic layer from the gate metal material, allowing moisture penetration, which leads to conductive properties. The inventors of this disclosure have also discovered that this problem is caused by stress mismatch between the inorganic layer and the gate.

[0048] Figure 1 A scanning electron microscope image of an array substrate with the inorganic layer separated from the gate is shown. Figure 2 A scanning electron microscope image of an array substrate in which the inorganic layer and the gate have not separated is shown. (Refer to...) Figure 1 The array substrate includes a gate G, a silicon oxide (SiO) layer on the gate G, and a silicon nitride (SiN) layer on the side of the SiO layer away from the gate G. The separation of the SiO layer from the gate G is achieved through… Figure 1 The Chinese character is represented as Sep. Figure 2The diagram shows an array substrate where the silicon oxide layer (SiO) and the gate electrode (G) are not separated.

[0049] Therefore, this disclosure particularly provides an array substrate and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes: a first substrate; a first conductive layer located on the first substrate, wherein the first conductive layer includes a plurality of data lines; a buffer layer located on a side of the first conductive layer away from the first substrate; a semiconductor material layer located on a side of the buffer layer away from the first substrate, wherein the semiconductor material layer includes an active layer of a transistor; a gate insulating layer located on a side of the semiconductor material layer away from the first substrate; and a second conductive layer located on a side of the gate insulating layer away from the first substrate, wherein the second conductive layer includes at least a portion of the source of a transistor, at least a portion of the drain of a transistor, and at least a portion of the gate of a transistor.

[0050] Figure 3 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3 In some embodiments, the array substrate includes a first substrate BS1, a first conductive layer SL1 on the first substrate BS1, a buffer layer BUF on the side of the first conductive layer SL1 away from the first substrate BS1, a third conductive layer REL on the side of the buffer layer BUF away from the first substrate BS1, a semiconductor material layer SML on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI on the side of the semiconductor material layer SML away from the first substrate BS1, a fourth conductive layer CT1 on the side of the gate insulating layer GI away from the first substrate BS1, a second conductive layer SL2 on the side of the fourth conductive layer CT1 away from the first substrate BS1, and a third conductive layer REL on the side of the second conductive layer SL2 away from the first substrate BS1. The first passivation layer PVX1 is located on the side of the first substrate BS1 away from the first substrate BS1, the planarization layer PLN is located on the side of the first passivation layer PVX1 away from the first substrate BS1, the first electrode layer E1L is located on the side of the planarization layer PLN away from the first substrate BS1, the second passivation layer PVX2 is located on the side of the first electrode layer E1L away from the first substrate BS1, the second electrode layer E2L is located on the side of the second passivation layer PVX2 away from the first substrate BS1, the spacer layer PS is located on the side of the second electrode layer E2L away from the first substrate BS1, the color filter CF is located on the side of the spacer layer PS away from the first substrate BS1, and the second substrate BS2 is located on the side of the color filter CF away from the first substrate BS1.

[0051] In some embodiments, the first conductive layer SL1 includes a plurality of data lines DL, and a corresponding data line of the plurality of data lines DL is connected to the source S of the transistor TFT in the array substrate. In some embodiments, the first conductive layer SL1 also includes a light-shielding element LS. The orthographic projection of the light-shielding element LS on the first substrate BS1 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the active layer ACT of the transistor TFT on the first substrate BS1.

[0052] In some embodiments, the third conductive layer REL includes a relay electrode RE. In some embodiments, the relay electrode RE connects a corresponding data line to the source S of the transistor TFT. In one example, the relay electrode RE comprises molybdenum-niobium. In another example, the relay electrode RE comprises a molybdenum alloy.

[0053] In some embodiments, the source S of the transistor TFT extends through a via to connect to the relay electrode RE, the via extending through the buffer layer BUF. In one example, the source S of the transistor TFT is located in the second conductive layer SL2. In one example, the source S of the transistor TFT comprises copper.

[0054] In some embodiments, the source S includes a first end TM1 that contacts the active layer ACT and a second end TM2 that does not contact the active layer ACT2. Optionally, the orthographic projection of the first end TM1 on the first substrate BS1 at least partially overlaps with the orthographic projection of the active layer ACT on the first substrate BS1. Optionally, the orthographic projection of the first end TM1 on the first substrate BS1 does not overlap with the orthographic projection of the gate insulating layer GI on the first substrate BS1. Optionally, the orthographic projection of the second end TM2 on the first substrate BS1 at least partially overlaps with the orthographic projection of the gate insulating layer GI on the first substrate BS1. Optionally, the orthographic projection of the second end TM2 on the first substrate BS1 does not overlap with the orthographic projection of the active layer ACT on the first substrate BS1. In some embodiments, the side of the second end TM2 closest to the first substrate BS1 contacts the gate insulating layer GI.

[0055] In some embodiments, the drain D of the transistor TFT includes a first sublayer located in the fourth conductive layer CT1 and a second sublayer located in the second conductive layer SL2. In one example, the first sublayer of the drain D of the transistor TFT located in the fourth conductive layer CT1 includes molybdenum-niobium. In another example, the first sublayer of the drain D of the transistor TFT located in the fourth conductive layer CT1 includes a molybdenum alloy. In yet another example, the second sublayer of the drain D of the transistor TFT located in the second conductive layer SL2 includes copper.

[0056] In some embodiments, the gate G of the transistor TFT includes a first sub-layer located in the fourth conductive layer CT1 and a second sub-layer located in the second conductive layer SL2. In one example, the first sub-layer of the gate G of the transistor TFT located in the fourth conductive layer CT1 comprises molybdenum-niobium. In another example, the first sub-layer of the gate G of the transistor TFT located in the fourth conductive layer CT1 comprises a molybdenum alloy. In yet another example, the second sub-layer of the gate G of the transistor TFT located in the second conductive layer SL2 comprises copper.

[0057] In some embodiments, the first passivation layer PVX1 includes a plurality of sublayers. Optionally, the first passivation layer PVX1 includes a first sublayer PVX1-1 located on the side of the second conductive layer SL2 away from the first substrate BS1, a second sublayer PVX1-2 located on the side of the first sublayer PVX1-1 away from the first substrate BS1, and a third sublayer PVX1-3 located on the side of the second sublayer PVX1-2 away from the first substrate BS1.

[0058] In some embodiments, the first sublayer PVX1-1 of the first passivation layer PVX1 comprises silicon oxide; the second sublayer PVX1-2 of the first passivation layer PVX1 comprises silicon nitride; and the third sublayer PVX1-3 of the first passivation layer PVX1 comprises silicon nitride. In some embodiments, the stress of the first passivation layer PVX1 having the first sublayer PVX1-1, the second sublayer PVX1-2, and the third sublayer PVX1-3 is in the range of -4000 Pa to -1000 Pa, for example, -4000 Pa to -3500 Pa, -3500 Pa to -3000 Pa, -3000 Pa to -2500 Pa, -2500 Pa to -2000 Pa, -2000 Pa to -1500 Pa, or -1500 Pa to -1000 Pa.

[0059] In an alternative embodiment, the first sublayer PVX1-1 of the first passivation layer PVX1 comprises silicon nitride; the second sublayer PVX1-2 of the first passivation layer PVX1 comprises silicon oxide; and the third sublayer PVX1-3 of the first passivation layer PVX1 comprises silicon nitride.

[0060] In some embodiments, the second sublayer PVX1-2 of the first passivation layer PVX1 comprises 0.3% to 2.0% (e.g., 0.3% to 0.5%, 0.5% to 0.7%, 0.7% to 0.9%, 0.9% to 1.1%, 1.1% to 1.3%, 1.3% to 1.5%, 1.5% to 1.7%, 1.7% to 1.9%, or 1.9% to 2.0%) w / w silicon-hydrogen (Si-H). In one example, the stress of silicon nitride with 1.0% w / w silicon-hydrogen is -1060. As used herein, the term “w / w” refers to weight / weight. For example, if the second sublayer PVX1-2 with a total mass of 100 grams contains 0.3 grams of silicon-hydrogen and 99.7 grams of silicon nitride, then the second sublayer PVX1-2 comprises 0.3% w / w silicon-hydrogen.

[0061] In some embodiments, the second sublayer PVX1-2 of the first passivation layer PVX1 comprises 1% to 10% silicon-hydrogen.

[0062] In some embodiments, the third sublayer PVX1-3 of the first passivation layer PVX1 comprises 8% to 15% (e.g., 8% to 9%, 9% to 10%, 10% to 11%, 11% to 12%, 12% to 13%, 13% to 14%, or 14% to 15%) w / w silicon-hydrogen. In one example, the silicon nitride with 9.7% w / w silicon-hydrogen has a stress of 89.3.

[0063] In some embodiments, the ratio of the thickness of the second sublayer PVX1-2 to the thickness of the third sublayer PVX1-3 is in the range of 1:4 to 1:1, for example, 1:4 to 1:3, 1:3 to 2:5, 2:5 to 1:2, 1:2 to 3:5, 3:5 to 2:3, 2:3 to 3:4, or 3:4 to 1:1.

[0064] In some embodiments, the total thickness of the second sublayer PVX1-2 and the third sublayer PVX1-3 of the first passivation layer PVX1 is in the range of 150 nm to 500 nm.

[0065] In some embodiments, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is in the range of 100 nm to 300 nm.

[0066] In a specific example, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is 200 nm, the thickness of the second sublayer PVX1-2 is 100 nm, and the thickness of the third sublayer PVX1-3 is 100 nm.

[0067] The inventors of this disclosure have discovered that the array substrate according to this disclosure has an improved on-state current I. onAnd reduced stress ensures that the first passivation layer PVX1 covers the gate G, thereby avoiding the problem of film separation. Figure 4 Scanning electron microscope images of array substrates according to some embodiments of the present disclosure are shown. Figure 4 As shown, in the array substrate of this disclosure, no film separation occurs between the first passivation layer and the gate G.

[0068] Figure 5 The correlation between gate voltage and drive current of transistors in a correlated array substrate where film separation occurs is shown. Figure 6 The correlation between the gate voltage and drive current of transistors in an array substrate according to some embodiments of the present disclosure is illustrated. (Refer to...) Figure 5 In transistors with separated film layers, the device characteristics are anomalous. (Refer to...) Figure 6 In the transistors in the array substrate according to some embodiments of this disclosure, the transistors exhibit normal device characteristics. Figure 5 and Figure 6 In the diagram, A represents the curve when the leakage voltage is 0.1V, B represents the curve when the leakage voltage is 5.1V, C represents the curve when the leakage voltage is 10.1V, and D represents the curve when the leakage voltage is 15.1V.

[0069] Various suitable implementations can be practiced in this disclosure. In one example, a single layer of molybdenum or copper, or a bilayer structure of molybdenum-niobium / copper, molybdenum alloy / copper, or titanium / copper, or a trilayer structure of molybdenum-niobium / copper / molybdenum alloy, or molybdenum alloy / copper / molybdenum alloy, is deposited on a first substrate and patterned to form a first conductive layer. The first conductive layer is formed to a thickness of […]. to Within the range.

[0070] A single layer of silicon oxide, or a bilayer structure of silicon nitride / silicon dioxide, or a trilayer structure of silicon nitride / silicon oxynitride / silicon oxide, is deposited on the first conductive layer to form a buffer layer. The buffer layer is formed to a thickness of [insert thickness here]. to Within a certain range. Silicon nitride can be a single layer or stacked into layers with a thickness ranging from... to Two or three layers. The thickness of silicon oxynitride is... to Within the range. Silica is located on the top layer, in contact with the subsequent layers, with a thickness of [missing information]. to

[0071] Subsequently, a monolayer of metal oxide is deposited on the buffer layer to form a semiconductor material layer. This monolayer metal oxide is a high-mobility oxide material doped with indium zinc oxide (IZO), or a material doped with rare earth elements such as praseodymium (Pr), such as indium gallium zinc oxide (IGZO) or aluminum-indium tin zinc oxide (Al-ITZO). The semiconductor material layer is formed to a thickness of [missing information]. to Within the range.

[0072] Subsequently, a single layer of silicon oxide, a two-layer structure of silicon nitride / silicon dioxide, or a three-layer structure of silicon nitride / silicon oxynitride / silicon oxide is deposited on the semiconductor material layer to form a gate insulating layer. The gate insulating layer is formed to a thickness of [insert thickness here]. to Within a certain range. Silicon oxide can be a single layer or stacked into two or three layers. The thickness of silicon oxynitride is within... to Within the range. Silica is located on the top layer, in contact with the subsequent active layer, with a thickness of [missing information]. to

[0073] Subsequently, a single layer of molybdenum or copper metal, or a bilayer structure of molybdenum-niobium / copper or molybdenum titanium disilicide / copper, or a trilayer structure of molybdenum-niobium / copper / molybdenum titanium disilicide or molybdenum titanium disilicide / copper / molybdenum titanium disilicide, is deposited on the gate insulating layer to form the gate. The gate is formed to a thickness of [insert thickness here]. arrive Within the range.

[0074] Subsequently, silicon oxide is deposited to form a first sublayer of the first passivation layer, low-hydrogen silicon nitride is deposited to form a second sublayer of the first passivation layer, and low-stress silicon nitride is deposited to form a third sublayer of the first passivation layer. The first passivation layer is formed with a total thickness of [missing information]. to Within a certain range. For example, the thickness of the first sublayer of the first passivation layer is in the range of 100 nm to 300 nm, and the combined thickness of the second and third sublayers is in the range of 150 nm to 500 nm. The ratio of the thickness of the second sublayer to the thickness of the third sublayer can be 1:1, 1:2, 1:3, 1:4, 2:3, 2:5, 3:4, or 3:5. The silicon-hydrogen content in the second sublayer is in the range of 0.3% to 2.0%, and the silicon-hydrogen content in the third sublayer is in the range of 8% to 15%.

[0075] Positive photoresist is deposited to form a planarization layer. The first electrode layer is formed on the planarization layer.

[0076] Subsequently, dense low-hydrogen silicon nitride is deposited to form a second passivation layer to block water vapor and hydrogen.

[0077] Subsequently, a second electrode layer is formed on the second passivation layer.

[0078] Figure 7 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 7 In some embodiments, the array substrate includes a first substrate BS1, a first conductive layer SL1 on the first substrate BS1, a buffer layer BUF on the side of the first conductive layer SL1 away from the first substrate BS1, a semiconductor material layer SML on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI on the side of the semiconductor material layer SML away from the first substrate BS1, a second conductive layer SL2 on the side of the gate insulating layer GI away from the first substrate BS1, a first passivation layer PVX1 on the side of the second conductive layer SL2 away from the first substrate BS1, and a first passivation layer PVX1 on the side of the first passivation layer PVX1. 1. A planarization layer PLN on the side away from the first substrate BS1, a first electrode layer E1L on the side of the planarization layer PLN away from the first substrate BS1, a second passivation layer PVX2 on the side of the first electrode layer E1L away from the first substrate BS1, a second electrode layer E2L on the side of the second passivation layer PVX2 away from the first substrate BS1, a spacer layer PS on the side of the second electrode layer E2L away from the first substrate BS1, a color filter CF on the side of the spacer layer PS away from the first substrate BS1, and a second substrate BS2 on the side of the color filter CF away from the first substrate BS1.

[0079] In some embodiments, the first conductive layer SL1 includes a plurality of data lines DL, and a corresponding data line of the plurality of data lines DL is connected to the source S of the transistor TFT in the array substrate. In some embodiments, the first conductive layer SL1 also includes a light-shielding element LS. The orthographic projection of the light-shielding element LS on the first substrate BS1 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the active layer ACT of the transistor TFT on the first substrate BS1.

[0080] In some embodiments, the source S of the transistor TFT extends through a via to connect to a corresponding data line, the via extending through the buffer layer BUF. In one example, the source S of the transistor TFT is located in the second conductive layer SL2. In one example, the source S of the transistor TFT comprises copper.

[0081] In some embodiments, the drain D of the transistor TFT is located in the second conductive layer SL2. In one example, the drain D of the transistor TFT located in the second conductive layer SL2 comprises copper.

[0082] In some embodiments, the gate G of the transistor TFT is located in the second conductive layer SL2. In one example, the gate G of the transistor TFT located in the second conductive layer SL2 comprises copper.

[0083] In some embodiments, the first passivation layer PVX1 includes a plurality of sublayers. Optionally, the first passivation layer PVX1 includes a first sublayer PVX1-1 located on the side of the second conductive layer SL2 away from the first substrate BS1, and a second sublayer PVX1-2 located on the side of the first sublayer PVX1-1 away from the first substrate BS1.

[0084] In some embodiments, the first sublayer PVX1-1 of the first passivation layer PVX1 comprises silicon oxide; the second sublayer PVX1-2 of the first passivation layer PVX1 comprises silicon nitride. In some embodiments, the stress of the first passivation layer PVX1 having the first sublayer PVX1-1 and the second sublayer PVX1-2 is in the range of -4000 Pa to -1000 Pa, for example, -4000 Pa to -3500 Pa, -3500 Pa to -3000 Pa, -3000 Pa to -2500 Pa, -2500 Pa to -2000 Pa, -2000 Pa to -1500 Pa, or -1500 Pa to -1000 Pa.

[0085] In some embodiments, the second sublayer PVX1-2 of the first passivation layer PVX1 comprises 0.3% to 2.0% (e.g., 0.3% to 0.5%, 0.5% to 0.7%, 0.7% to 0.9%, 0.9% to 1.1%, 1.1% to 1.3%, 1.3% to 1.5%, 1.5% to 1.7%, 1.7% to 1.9%, or 1.9% to 2.0%) w / w silicon-hydrogen. In one example, the silicon nitride with 1.0% w / w silicon-hydrogen has a stress of -1060. In an alternative embodiment, the second sublayer PVX1-2 of the first passivation layer PVX1 comprises 8% to 15% (e.g., 8% to 9%, 9% to 10%, 10% to 11%, 11% to 12%, 12% to 13%, 13% to 14%, or 14% to 15%) w / w silicon-hydrogen. In one example, the silicon nitride with 9.7% w / w silicon-hydrogen has a stress of 89.3.

[0086] In some embodiments, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is in the range of 100 nm to 300 nm. In some embodiments, the thickness of the second sublayer PVX1-2 of the first passivation layer PVX1 is in the range of 150 nm to 500 nm.

[0087] In a specific example, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is 200 nm, and the thickness of the second sublayer PVX1-2 is 300 nm.

[0088] Figure 8 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 8 In some embodiments, the array substrate includes a first substrate BS1, a first conductive layer SL1 on the first substrate BS1, a buffer layer BUF on the side of the first conductive layer SL1 away from the first substrate BS1, a third conductive layer REL on the side of the buffer layer BUF away from the first substrate BS1, a semiconductor material layer SML on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI on the side of the semiconductor material layer SML away from the first substrate BS1, a fourth conductive layer CT1 on the side of the gate insulating layer GI away from the first substrate BS1, a second conductive layer SL2 on the side of the fourth conductive layer CT1 away from the first substrate BS1, and a fifth conductive layer on the side of the second conductive layer SL2 away from the first substrate BS1. The fifth conductive layer CT2, the first passivation layer PVX1 located on the side of the fifth conductive layer CT2 away from the first substrate BS1, the planarization layer PLN located on the side of the first passivation layer PVX1 away from the first substrate BS1, the first electrode layer E1L located on the side of the planarization layer PLN away from the first substrate BS1, the second passivation layer PVX2 located on the side of the first electrode layer E1L away from the first substrate BS1, the second electrode layer E2L located on the side of the second passivation layer PVX2 away from the first substrate BS1, the spacer layer PS located on the side of the second electrode layer E2L away from the first substrate BS1, the color filter CF located on the side of the spacer layer PS away from the first substrate BS1, and the second substrate BS2 located on the side of the color filter CF away from the first substrate BS1.

[0089] In some embodiments, the first conductive layer SL1 includes a plurality of data lines DL, and a corresponding data line of the plurality of data lines DL is connected to the source S of the transistor TFT in the array substrate. In some embodiments, the first conductive layer SL1 also includes a light-shielding element LS. The orthographic projection of the light-shielding element LS on the first substrate BS1 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the active layer ACT of the transistor TFT on the first substrate BS1.

[0090] In some embodiments, the third conductive layer REL includes a relay electrode RE. In some embodiments, the relay electrode RE connects a corresponding data line to the source S of the transistor TFT. In one example, the relay electrode RE comprises molybdenum-niobium. In another example, the relay electrode RE comprises a molybdenum alloy.

[0091] In some embodiments, the source S of the transistor TFT extends through a via to connect to the relay electrode RE, the via extending through the buffer layer BUF. In one example, the source S of the transistor TFT includes a first sublayer located in the second conductive layer SL2 and a second sublayer located in the fifth conductive layer CT2. In one example, the first sublayer of the source S of the transistor TFT located in the second conductive layer SL2 includes copper. In one example, the second sublayer of the source S of the transistor TFT located in the fifth conductive layer CT2 includes molybdenum-niobium. In another example, the second sublayer of the source S of the transistor TFT located in the fifth conductive layer CT2 includes a molybdenum alloy.

[0092] In some embodiments, the drain D of the transistor TFT includes a first sub-layer located in the fourth conductive layer CT1, a second sub-layer located in the second conductive layer SL2, and a third sub-layer located in the fifth conductive layer CT2. In one example, the first sub-layer of the drain D of the transistor TFT located in the fourth conductive layer CT1 comprises molybdenum-niobium. In another example, the first sub-layer of the drain D of the transistor TFT located in the fourth conductive layer CT1 comprises a molybdenum alloy. In another example, the second sub-layer of the drain D of the transistor TFT located in the second conductive layer SL2 comprises copper. In one example, the third sub-layer of the drain D of the transistor TFT located in the fifth conductive layer CT2 comprises molybdenum-niobium. In another example, the third sub-layer of the drain D of the transistor TFT located in the fifth conductive layer CT2 comprises a molybdenum alloy.

[0093] In some embodiments, the gate G of the transistor TFT includes a first sub-layer located in the fourth conductive layer CT1, a second sub-layer located in the second conductive layer SL2, and a third sub-layer located in the fifth conductive layer CT2. In one example, the first sub-layer of the gate G of the transistor TFT located in the fourth conductive layer CT1 comprises molybdenum-niobium. In another example, the first sub-layer of the gate G of the transistor TFT located in the fourth conductive layer CT1 comprises a molybdenum alloy. In another example, the second sub-layer of the gate G of the transistor TFT located in the second conductive layer SL2 comprises copper. In one example, the third sub-layer of the gate G of the transistor TFT located in the fifth conductive layer CT2 comprises molybdenum-niobium. In another example, the third sub-layer of the gate G of the transistor TFT located in the fifth conductive layer CT2 comprises a molybdenum alloy.

[0094] In some embodiments, the first passivation layer PVX1 includes a plurality of sublayers. Optionally, the first passivation layer PVX1 includes a first sublayer PVX1-1 located on the side of the second conductive layer SL2 away from the first substrate BS1, a second sublayer PVX1-2 located on the side of the first sublayer PVX1-1 away from the first substrate BS1, and a third sublayer PVX1-3 located on the side of the second sublayer PVX1-2 away from the first substrate BS1.

[0095] In some embodiments, the first sublayer PVX1-1 of the first passivation layer PVX1 comprises silicon oxide; the second sublayer PVX1-2 of the first passivation layer PVX1 comprises silicon nitride; and the third sublayer PVX1-3 of the first passivation layer PVX1 comprises silicon nitride. In some embodiments, the stress of the first passivation layer PVX1 having the first sublayer PVX1-1, the second sublayer PVX1-2, and the third sublayer PVX1-3 is in the range of -4000 Pa to -1000 Pa, for example, -4000 Pa to -3500 Pa, -3500 Pa to -3000 Pa, -3000 Pa to -2500 Pa, -2500 Pa to -2000 Pa, -2000 Pa to -1500 Pa, or -1500 Pa to -1000 Pa.

[0096] In some embodiments, the second sublayer PVX1-2 of the first passivation layer PVX1 comprises 0.3% to 2.0% (e.g., 0.3% to 0.5%, 0.5% to 0.7%, 0.7% to 0.9%, 0.9% to 1.1%, 1.1% to 1.3%, 1.3% to 1.5%, 1.5% to 1.7%, 1.7% to 1.9%, or 1.9% to 2.0%) w / w silicon-hydrogen. In one example, the silicon nitride with 1.0% w / w silicon-hydrogen has a stress of -1060.

[0097] In some embodiments, the third sublayer PVX1-3 of the first passivation layer PVX1 comprises 8% to 15% (e.g., 8% to 9%, 9% to 10%, 10% to 11%, 11% to 12%, 12% to 13%, 13% to 14%, or 14% to 15%) w / w silicon-hydrogen. In one example, the silicon nitride with 9.7% w / w silicon-hydrogen has a stress of 89.3.

[0098] In some embodiments, the ratio of the thickness of the second sublayer PVX1-2 to the thickness of the third sublayer PVX1-3 is in the range of 1:4 to 1:1, for example, 1:4 to 1:3, 1:3 to 2:5, 2:5 to 1:2, 1:2 to 3:5, 3:5 to 2:3, 2:3 to 3:4, or 3:4 to 1:1.

[0099] In some embodiments, the total thickness of the second sublayer PVX1-2 and the third sublayer PVX1-3 of the first passivation layer PVX1 is in the range of 150 nm to 500 nm.

[0100] In some embodiments, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is in the range of 100 nm to 300 nm.

[0101] In a specific example, the thickness of the first sublayer PVX1-1 of the first passivation layer PVX1 is 200 nm, the thickness of the second sublayer PVX1-2 is 100 nm, and the thickness of the third sublayer PVX1-3 is 100 nm.

[0102] The inventors of this disclosure have discovered that by setting the gate G in a third sublayer located in the fifth conductive layer CT2, the adhesion between the first passivation layer PVX1 and the gate G can be significantly improved, thereby reducing problems related to film separation. Compared to copper, molybdenum-niobium or molybdenum alloys exhibit better adhesion to the first passivation layer PVX1. The inventors of this disclosure have also discovered that the array substrate according to this disclosure has an improved on-state current I. on The reduced stress ensures that the first passivation layer PVX1 covers the gate G, thus avoiding the problem of film separation.

[0103] The inventors of this disclosure have also discovered that negative bias temperature instability stress cannot be effectively improved in relevant array substrates. Even increasing the light-shielding area cannot meet the application requirements of automotive products. To solve this problem, the inventors of this disclosure have discovered a novel array substrate that enhances the performance and reliability of devices used in automotive applications.

[0104] Figure 9 This is a schematic diagram illustrating the structure of a portion of the display area of ​​an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 9 In the display area, the array substrate includes a first substrate BS1, a first conductive layer SL1 on the first substrate BS1, a buffer layer BUF on the side of the first conductive layer SL1 away from the first substrate BS1, a semiconductor material layer SML on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI on the side of the semiconductor material layer SML away from the first substrate BS1, a second conductive layer SL2 on the side of the gate insulating layer GI away from the first substrate BS1, a first passivation layer PVX1 on the side of the second conductive layer SL2 away from the first substrate BS1, a planarization layer PLN on the side of the first passivation layer PVX1 away from the first substrate BS1, a first electrode layer E1L on the side of the planarization layer PLN away from the first substrate BS1, a second passivation layer PVX2 on the side of the first electrode layer E1L away from the first substrate BS1, and a second electrode layer E2L on the side of the second passivation layer PVX2 away from the first substrate BS1.

[0105] As used herein, the term "display area" refers to the area of ​​the array substrate in a display panel that actually displays the image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to the pixel electrode in a liquid crystal display or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to the black matrix in a liquid crystal display or the area corresponding to the pixel defining layer in an organic light-emitting diode display panel. Optionally, an inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, an inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels.

[0106] In some embodiments, the first conductive layer SL1 includes a plurality of data lines DL in the display area, and a corresponding data line of the plurality of data lines DL is connected to the source S of the first transistor TFT1 located in the display area of ​​the array substrate. In some embodiments, the first conductive layer SL1 further includes a light-shielding element LS. The orthographic projection of the light-shielding element LS on the first substrate BS1 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the active layer ACT of the first transistor TFT1 on the first substrate BS1.

[0107] In some embodiments, the gate G of the first transistor TFT1 located in the display area is spaced apart from the drain D of the first transistor TFT1 by a first minimum distance md1, and from the source D of the first transistor TFT1 by a second minimum distance md2. In some embodiments, the first minimum distance md1 is greater than the second minimum distance md2. Optionally, the first minimum distance md1 is at least 4 μm larger than the second minimum distance md2, for example, at least 5 μm, at least 6 μm, at least 7 μm, at least 8 μm, at least 9 μm, at least 10 μm, at least 11 μm, or at least 12 μm.

[0108] In some embodiments, the first minimum distance md1 is in the range of 5 μm to 12 μm, for example, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, or 11 μm to 12 μm.

[0109] In some embodiments, the second minimum distance md2 is in the range of 3 μm to 7 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, or 6 μm to 7 μm.

[0110] The inventors of this disclosure have discovered that the first transistor TFT1 in the array substrate exhibits bulk accumulation; the electron accumulation layer extends to the entire depth of the active layer. The first transistor TFT in the array substrate of this disclosure exhibits good negative bias light stress stability due to the high gate drive, resulting in a near-zero on-state voltage, regardless of the defect state density changes caused by negative bias light stress. This structure leads to excellent light / bias stress stability of the array substrate, which is particularly significant for large-area display panels.

[0111] By making the first minimum distance md1 greater than the second minimum distance md2, although the electric field in the drain offset region decreases, resulting in a decrease in the electron concentration in the drain offset region, it is surprisingly observed that the electrical performance of the active layer remains essentially unchanged due to the presence of the bottom gate (light-shielding element).

[0112] Figure 10 This is a schematic diagram illustrating the structure of a portion of the peripheral region of an array substrate according to some embodiments of the present disclosure. Figure 11 It is along Figure 10 The cross-sectional view of line A-A' in the diagram is shown in the image. Figure 10 and Figure 11 In the surrounding area, the array substrate includes a first substrate BS1, a first conductive layer SL1 located on the first substrate BS1, a buffer layer BUF located on the side of the first conductive layer SL1 away from the first substrate BS1, a semiconductor material layer SML located on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the first substrate BS1, and a second conductive layer SL2 located on the side of the gate insulating layer GI away from the first substrate BS1.

[0113] As used herein, the term "peripheral area" refers to the area of ​​the array substrate in a display panel where various circuits and wires are arranged to transmit signals to the display substrate. To increase the transparency of the display device, opaque or light-blocking components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0114] In some embodiments, the first conductive layer SL1 includes a light-shielding element LS in its peripheral region. The orthographic projection of the light-shielding element LS in the peripheral region onto the first substrate BS1 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the active layer ACT of the second transistor TFT2 in the peripheral region onto the first substrate BS1.

[0115] In some embodiments, the gate G of the second transistor TFT2 located in the display area is spaced apart from the drain D of the first transistor TFT1 by a third minimum distance md3, and spaced apart from the source D of the second transistor TFT2 by a fourth minimum distance md4. In some embodiments, the third minimum distance md3 is greater than the fourth minimum distance md4. Optionally, the third minimum distance md3 is at least 4 μm larger than the fourth minimum distance md4, for example, at least 5 μm, at least 6 μm, at least 7 μm, at least 8 μm, at least 9 μm, at least 10 μm, at least 11 μm, or at least 12 μm.

[0116] In some embodiments, the third minimum distance md3 is in the range of 5 μm to 15 μm, for example, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, 9 μm to 10 μm, 10 μm to 11 μm, 11 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14 μm, or 14 μm to 15 μm.

[0117] In some embodiments, the fourth minimum distance md4 is in the range of 3 μm to 7 μm, for example, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, or 6 μm to 7 μm.

[0118] The second transistor TFT2 located in the peripheral region (e.g., a transistor in a scanning circuit) operates in a positive bias environment. The inventors of this disclosure have discovered that the second transistor TFT2 located in the peripheral region of the array substrate of this disclosure maintains positive bias temperature stress stability under positive bias conditions, which is critical for its reliable operation in applications exposed to such environments.

[0119] In some embodiments, the array substrate includes a first via v1 and a second via v2 extending through the gate insulating layer GI, respectively. In some embodiments, the first via v1 exposes a portion of the source S, and the second via v2 exposes a portion of the drain D.

[0120] In some embodiments, the orthographic projection of the first via v1 on the first substrate BS1 is spaced apart by a first distance d1 from the orthographic projection of the channel of the active layer ACT of the second transistor TFT2 on the first substrate BS1. In some embodiments, the orthographic projection of the first via v1 on the first substrate BS1 is spaced apart by a second distance d2 from the orthographic projection of the light-shielding member LS on the first substrate BS1, and the orthographic projection of the light-shielding member LS on the first substrate BS1 is spaced apart by a third distance d3 from the orthographic projection of the channel of the active layer ACT of the second transistor TFT2 on the first substrate BS1. Optionally, the first distance d1 is equal to the sum of the second distance d2 and the third distance d3.

[0121] In some embodiments, the first distance d1 is greater than or equal to 2 μm. Optionally, the second distance d2 is greater than or equal to 1 μm, and the third distance is greater than or equal to 1 μm. The inventors of this disclosure have discovered that when the first distance d1 is greater than or equal to 2 μm, there is no source-gate short circuit on the array substrate.

[0122] Table 1 shows the correlation between a second distance d2 in a second transistor located in the peripheral region of an array substrate and negative bias temperature instability stress (NBTIS) in some embodiments of the present disclosure.

[0123]

[0124] As shown in Table 1, the minimum (e.g., 0) NBTIS can be obtained when the second distance d2 is 10 μm.

[0125] Figure 12 The correlation between the gate voltage and drive current of a second transistor in the peripheral region of an array substrate according to some embodiments of the present disclosure is shown. Figure 12 The second transistor corresponds to a second distance d2 of 10 μm. Figure 12 The results of negative bias temperature stress (NBTS) testing on the second transistor are shown in the absence of light. The curves from right to left represent the transistor characteristics in the dark state, 100 seconds after the NBTS test, 500 seconds after the NBTS test, 1000 seconds after the NBTS test, 1800 seconds after the NBTS test, and 3600 seconds after the NBTS test. The curve corresponding to the dark state represents the baseline performance of the transistor without any applied stress. The characteristics corresponding to the dark state are stable and used as a reference point.

[0126] Figure 13 The correlation between the gate voltage and drive current of a second transistor in the peripheral region of an array substrate according to some embodiments of the present disclosure is shown. Figure 13 The second transistor corresponds to a second distance d2 of 10 μm. Figure 13 The results of a negative bias temperature instability stress (NBTIS) test on a second transistor under 6000 nit illumination are shown. The curves from right to left represent the transistor characteristics in the dark state, 100 seconds after the NBTIS test, 500 seconds after the NBTIS test, 1000 seconds after the NBTIS test, 1800 seconds after the NBTIS test, and 3600 seconds after the NBTIS test. The curve corresponding to the dark state represents the baseline performance of the transistor without any applied stress. The characteristics corresponding to the dark state are stable and used as a reference point.

[0127] Figure 14This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 15 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 16 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figures 14 to 16 In some embodiments, the array substrate includes a first substrate BS1, a first conductive layer SL1 on the first substrate BS1, a buffer layer BUF on the side of the first conductive layer SL1 away from the first substrate BS1, a third conductive layer REL on the side of the buffer layer BUF away from the first substrate BS1, a semiconductor material layer SML on the side of the buffer layer BUF away from the first substrate BS1, a gate insulating layer GI on the side of the semiconductor material layer SML away from the first substrate BS1, and a fourth conductive layer CT1 on the side of the gate insulating layer GI away from the first substrate BS1. The fourth conductive layer CT1 has a second conductive layer SL2 on the side away from the first substrate BS1, a first passivation layer PVX1 on the side of the second conductive layer SL2 away from the first substrate BS1, a planarization layer PLN on the side of the first passivation layer PVX1 away from the first substrate BS1, a first electrode layer E1L on the side of the planarization layer PLN away from the first substrate BS1, a second passivation layer PVX2 on the side of the first electrode layer E1L away from the first substrate BS1, and a second electrode layer E2L on the side of the second passivation layer PVX2 away from the first substrate BS1.

[0128] Reference Figures 14 to 16 In some embodiments, the array substrate further includes a plurality of touch signal lines TSL, a plurality of touch leads TLL, and a plurality of connection electrodes CE. In some embodiments, each connection electrode in the plurality of connection electrodes CE connects the touch signal lines in the plurality of touch signal lines TSL to the touch leads in the plurality of touch leads TLL.

[0129] In some embodiments, each connecting electrode is located in the second electrode layer E2L, for example, each connecting electrode is located in the same layer as the second electrode E2.

[0130] In some embodiments, the touch lead is located in the first electrode layer E1L, for example, the touch lead and the first electrode E1 are located in the same layer.

[0131] Reference Figure 14 and Figure 15In some embodiments, the array substrate further includes vias SV through which respective connection electrodes are connected to touch signal lines and touch wires. In some embodiments, a portion of the touch lead is inserted into the via SV. In some embodiments, the orthographic projection of the touch lead on the first substrate BS1 partially overlaps with the orthographic projection of the corresponding connection electrode on the first substrate BS1. The touch lead and the touch signal line are located in two different layers, and the corresponding connection electrode connects the touch signal line to the touch lead.

[0132] In some embodiments, refer to Figure 14 The touch signal line is located in the second conductive layer SL2, the touch lead is located in the first electrode layer E1L, and each connecting electrode is located in the second electrode layer E2L.

[0133] In some embodiments, refer to Figure 15 The array substrate further includes a third signal line layer SL3, which is located on the side of at least one sublayer (e.g., the first sublayer PVX1-1) of the first passivation layer PVX1 away from the second conductive layer SL2. In some embodiments, touch signal lines are located in the third signal line layer SL3, touch leads are located in the first electrode layer E1L, and each connecting electrode is located in the second electrode layer E2L.

[0134] In some embodiments, the third signal line layer SL3 further includes an intermediate electrode IE. In some embodiments, the second electrode E2 is connected to the intermediate electrode IE, and the intermediate electrode IE is connected to the drain D of the transistor TFT.

[0135] Reference Figure 16 In some embodiments, the array substrate further includes a third passivation layer PVX3 located on the side of the second electrode layer E2L away from the first substrate BS1, and a touch electrode layer TEL located on the side of the third passivation layer PVX3 away from the first substrate BS1. In some embodiments, touch signal lines are located on the touch electrode layer TEL, touch leads are located on the first electrode layer E1L, and each connection electrode is located on the second electrode layer E2L. In some embodiments, the touch signal lines extend through vias penetrating the third passivation layer PVX3 to connect to the corresponding connection electrodes, and the corresponding connection electrodes extend through vias penetrating the second passivation layer PVX2 to connect to the touch leads.

[0136] The inventors of this disclosure discovered that by setting Figure 14 The touch structure depicted herein can be fabricated on an array substrate without an additional mask. By modifying the mask used for the first electrode layer E1L, the electrodes in the first electrode layer E1L can be used as hard masks, and interleaved vias can be formed. The array substrate of this disclosure achieves the maximum possible aperture ratio.

[0137] The inventors of this disclosure discovered that by setting Figure 15 The touch structure depicted in the image can incorporate two additional masks.

[0138] The inventors of this disclosure discovered that by setting Figure 16 The touch structure described herein can minimize the process risks of manufacturing array substrates, thereby reducing the risks associated with process variations.

[0139] Figure 17 Depicting Figure 14 and Figure 15 A schematic diagram of the via SV described in the diagram. Figure 18 yes Figure 14 and Figure 15 An enlarged view of the via SV described in [reference]. Figure 17 and Figure 18 A portion of the touch lead is inserted into the via SV.

[0140] Figure 19 The connection between the corresponding connecting electrode and the touch lead located in the first electrode layer is shown. Figure 20 The connection between the corresponding connection electrode and the touch signal line located in the second conductive layer is shown.

[0141] Various suitable implementations can be practiced in this disclosure. In one example, a single layer of molybdenum or copper, or a bilayer structure of molybdenum-niobium / copper, molybdenum alloy / copper, or titanium / copper, or a trilayer structure of molybdenum-niobium / copper / molybdenum alloy, or molybdenum alloy / copper / molybdenum alloy, is deposited on a first substrate and patterned to form a first conductive layer. The first conductive layer is formed to have a thickness of 1000 nm. Within the range.

[0142] A single layer of silicon oxide, or a silicon nitride / silicon dioxide bilayer structure, or a silicon nitride / silicon oxynitride / silicon oxide trilayer structure, is deposited on the first conductive layer to form a buffer layer. The buffer layer is formed to have a thickness of 1000 to [missing value]. Within a certain range. Silicon nitride can be a single layer or stacked into layers with a thickness ranging from 3000 to... Two or three layers. The thickness of silicon oxynitride is 1000 to... Within the range. Silica is located on the top layer, in contact with the subsequent layers, with a thickness of 300 to...

[0143] Subsequently, a monolayer of metal oxide is deposited on the buffer layer to form a semiconductor material layer. This monolayer metal oxide is a high-mobility oxide material doped with indium zinc oxide (IZO), or a material doped with rare earth elements such as praseodymium (Pr), such as indium gallium zinc oxide (IGZO) or aluminum-indium tin zinc oxide (Al-ITZO). The semiconductor material layer is formed with a thickness of 300 nm. Within the range.

[0144] Subsequently, a single-layer silicon oxide structure, a double-layer silicon nitride / silicon dioxide structure, or a triple-layer silicon nitride / silicon oxynitride / silicon oxide structure is deposited on the semiconductor material layer to form a gate insulating layer. The gate insulating layer is formed to a thickness of [insert thickness here]. to Within a certain range. Silicon oxide can be a single layer or stacked into two or three layers. The thickness of silicon oxynitride is within... to Within the range. Silica is located on the top layer, in contact with the subsequent active layer, with a thickness of [missing information]. to

[0145] Subsequently, a single layer of molybdenum or copper metal, or a bilayer structure of molybdenum-niobium / copper or molybdenum titanium disilicide / copper, or a trilayer structure of molybdenum-niobium / copper / molybdenum titanium disilicide or molybdenum titanium disilicide / copper / molybdenum titanium disilicide, is deposited on the gate insulating layer to form the gate and multiple touch signal lines. The gate and multiple touch signal lines are formed with a thickness of 1000 μm and... Within the range.

[0146] Subsequently, silicon oxide is deposited to form a first sublayer of the first passivation layer, low-hydrogen silicon nitride is deposited to form a second sublayer of the first passivation layer, and low-stress silicon nitride is deposited to form a third sublayer of the first passivation layer. The first passivation layer is formed with a total thickness of 1000 to [missing value]. Within a certain range. For example, the thickness of the first sublayer of the first passivation layer is in the range of 100 to 300 nm, and the combined thickness of the second and third sublayers is in the range of 150 to 500 nm. The ratio of the thickness of the second sublayer to the thickness of the third sublayer can be 1:1, 1:2, 1:3, 1:4, 2:3, 2:5, 3:4, or 3:5. The silicon-hydrogen content in the second sublayer is in the range of 0.3% to 2.0%, and the silicon-hydrogen content in the third sublayer is in the range of 8% to 15%.

[0147] A positive photoresist is deposited to form a planarization layer. A first electrode layer is formed on the planarization layer. The first electrode layer includes a plurality of touch leads. The touch leads are connected to touch signal lines via corresponding connection electrodes subsequently formed.

[0148] Subsequently, dense low-hydrogen silicon nitride is deposited to form a second passivation layer to block water vapor and hydrogen.

[0149] Subsequently, a second electrode layer is formed on the second passivation layer. The second electrode layer includes a plurality of connection electrodes. Each connection electrode is connected to a touch lead located on the first electrode layer and to a touch signal line located on the second conductive layer.

[0150] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is a liquid crystal display device.

[0151] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a first conductive layer on a first substrate, wherein the first conductive layer includes a plurality of data lines; forming a buffer layer on a side of the first conductive layer away from the first substrate; forming a semiconductor material layer on the side of the buffer layer away from the first substrate, wherein the semiconductor material layer includes an active layer of a transistor; forming a gate insulating layer on the side of the semiconductor material layer away from the first substrate; and forming a second conductive layer on the side of the gate insulating layer away from the first substrate, wherein the second conductive layer includes at least a portion of a source of a transistor, at least a portion of a drain of a transistor, and at least a portion of a gate of a transistor.

[0152] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: First substrate; A first conductive layer is located on the first substrate, wherein the first conductive layer includes a plurality of data lines; A buffer layer is located on the side of the first conductive layer away from the first substrate. A semiconductor material layer is located on the side of the buffer layer away from the first substrate, wherein the semiconductor material layer includes an active layer of a transistor; A gate insulating layer located on the side of the semiconductor material layer away from the first substrate; and A second conductive layer is located on the side of the gate insulating layer away from the first substrate, wherein the second conductive layer includes at least a portion of the source of the transistor, at least a portion of the drain of the transistor, and at least a portion of the gate of the transistor.

2. The array substrate according to claim 1, wherein, The source extends through the gate insulation layer and the buffer layer to be electrically connected to a corresponding data line among the plurality of data lines.

3. The array substrate according to claim 1 further includes a third conductive layer located on the side of the buffer layer away from the first substrate. in, The third conductive layer includes a relay electrode; The source electrode extends through the gate insulating layer and the buffer layer via a via to connect to the relay electrode; and The relay electrode is connected to the corresponding data line among the plurality of data lines.

4. The array substrate according to claim 3, wherein, The relay electrode is located on the side of the corresponding data line away from the first substrate, and on the side of the source electrode closer to the first substrate; and The relay electrode comprises the same material as at least one of the gate or the drain.

5. The array substrate according to claim 3, wherein, The source electrode includes a first end that contacts the active layer and a second end that does not contact the active layer; and The side of the second end closest to the first substrate is in contact with the gate insulating layer.

6. The array substrate according to any one of claims 1 to 5, further comprising: A first passivation layer is located on the side of the second conductive layer away from the first substrate. as well as A planarization layer is located on the side of the first passivation layer away from the first substrate. The first passivation layer comprises multiple sublayers with different compositions.

7. The array substrate according to claim 6, wherein, The stress of the first passivation layer is in the range of -4000Pa to -1000Pa.

8. The array substrate according to claim 6, wherein, The first passivation layer includes a first sub-layer located on the side of the second conductive layer away from the first substrate, and a second sub-layer located on the side of the first sub-layer away from the first substrate; and One of the first sublayer and the second sublayer comprises silicon oxide, and the other comprises silicon nitride.

9. The array substrate according to claim 8, wherein, The second sublayer comprises 0.3% to 2.0% w / w of silicon-hydrogen.

10. The array substrate according to claim 8, wherein, The second sublayer comprises 8% to 15% w / w silicon-hydrogen.

11. The array substrate according to claim 8, wherein, The second sublayer comprises 1% to 10% w / w silicon-hydrogen.

12. The array substrate according to claim 8, wherein, The thickness of the first sublayer is in the range of 100 nm to 300 nm; and The thickness of the second sublayer is in the range of 150 nm to 500 nm.

13. The array substrate according to claim 8, wherein, The first passivation layer further includes a third sublayer located on the side of the second sublayer away from the first substrate; and The third sublayer comprises silicon nitride.

14. The array substrate according to claim 13, wherein, The second sublayer comprises 0.3% to 2.0% w / w silicon-hydrogen; and The third sublayer comprises 8% to 15% w / w silicon-hydrogen.

15. The array substrate according to claim 13, wherein, The ratio of the thickness of the second sublayer to the thickness of the third sublayer is in the range of 1:4 to 1:1; The thickness of the first sublayer is in the range of 100 nm to 300 nm; and The total thickness of the second sublayer and the third sublayer is in the range of 150 nm to 500 nm.

16. The array substrate according to any one of claims 1 to 3, further comprising a fourth conductive layer located on the side of the gate insulating layer away from the first substrate and on the side of the second conductive layer close to the first substrate; in, At least one of the gate or the drain includes a sublayer located in the fourth conductive layer and a sublayer located in the second conductive layer.

17. The array substrate according to claim 16, further comprising a fifth conductive layer located on the side of the second conductive layer away from the first substrate; in, At least one of the gate, the source, or the drain includes a sublayer located in the second conductive layer and a sublayer located in the fifth conductive layer.

18. The array substrate according to any one of claims 1 to 17, wherein, The gate is spaced apart from the drain by a first minimum distance and from the source by a second minimum distance; and The first minimum distance is at least 4 μm greater than the second minimum distance.

19. The array substrate according to any one of claims 1 to 18, further comprising: The first electrode layer is located on the side of the planarization layer away from the first substrate. The second passivation layer is located on the side of the first electrode layer away from the first substrate. The second electrode layer is located on the side of the second passivation layer away from the first substrate. as well as Multiple touch signal lines, multiple touch leads, and multiple connection electrodes; The corresponding connection electrode among the plurality of connection electrodes connects the touch signal line among the plurality of touch signal lines to the touch lead among the plurality of touch lead; The first electrode layer includes a first electrode and the plurality of touch leads; The second electrode layer includes a second electrode and the plurality of connecting electrodes; and The second electrode is electrically connected to the drain of the transistor.

20. The array substrate according to claim 19, further comprising vias, wherein the corresponding connection electrodes are connected to the touch signal line and the touch lead through the vias; in, A portion of the touch lead is inserted into the via; The orthographic projection of the touch lead on the first substrate partially overlaps with the orthographic projection of the corresponding connecting electrode on the first substrate. as well as The corresponding connection electrode connects the touch signal line to the touch lead, and the touch signal line and the touch lead are located on two different layers.

21. The array substrate according to claim 19, further comprising: A third passivation layer is located on the side of the second electrode layer away from the first substrate. as well as A touch electrode layer is located on the side of the third passivation layer away from the first substrate. The plurality of touch signal lines are located in the touch electrode layer; The touch signal line extends through a via penetrating the third passivation layer to connect to the corresponding connection electrode; and The corresponding connection electrode extends through a via penetrating the second passivation layer to connect to the touch lead.

22. A display device comprising an array substrate according to any one of claims 1 to 21 and one or more integrated circuits connected to the array substrate.

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