Cycling processing of silicon nanostructures

Abstract

Methods for processing a silicon nanostructure erected from a support structure are provided. The silicon nanostructure has a major surface bounded by a tilted surface relative to the major surface. The method includes subjecting the silicon nanostructure to a first cyclic process. Each cycle of the first cyclic process includes oxidizing the major surface and the tilted surface, thereby forming a silicon oxide layer on the major surface and the tilted surface; applying a first etching process configured to anisotropically etch the silicon oxide layer from the major surface while leaving the silicon oxide layer on the tilted surface, thereby exposing silicon of the silicon nanostructure; and applying a second etching process configured to selectively etch the exposed silicon of the silicon nanostructure using the silicon oxide layer of the tilted surface as a masking layer. Selective etching of the major surface relative to the tilted surface is thereby achieved, such that a recess is formed in the silicon nanostructure having its opening at the major surface of the silicon nanostructure.

Description

Technical Field

[0001] This invention relates to the formation of nanostructures. More specifically, it relates to the splitting of nanostructures arranged on a support structure. Background Technology

[0002] Interest in fabricating devices with dimensions smaller than 100 nm (such as advanced semiconductor devices) is growing. Today, the lateral dimensions of advanced semiconductor devices (i.e., electronic components such as transistors) have reached or even fallen below 20 nm. However, it is difficult to fabricate structures with lateral dimensions smaller than 20 nm using existing processes. For example, the spatial resolution of ultraviolet lithography (UVL), commonly used in industry to fabricate semiconductor devices, is limited. Therefore, alternative methods are needed to overcome these challenges and allow the fabrication of nanostructures with lateral dimensions smaller than 20 nm.

[0003] Therefore, many technologies are under development to allow the fabrication of nanostructures with lateral dimensions below 20 nm. Some examples are extreme ultraviolet lithography, self-aligned multipatterning, electron beam direct writing, nanoimprint lithography, and directional self-assembly.

[0004] Currently, extreme ultraviolet (EUV) lithography is the most advanced direct patterning method in high-volume manufacturing. However, EUV lithography is affected by very thin resist layers, and achieving the desired line edge roughness (LER) and linewidth roughness (LEW) is often difficult with this patterning technique. Self-aligned patterning is a complementary patterning technique widely used when optical lithography cannot provide the required resolution. This self-aligned patterning also has some technical limitations and involves multiple processing steps, driving associated patterning costs. Typically, its yield and throughput are limited.

[0005] In view of the above, there is room for improvement in the fabrication of nanostructures, especially nanostructures with lateral dimensions of less than 20 nm. Summary of the Invention

[0006] The present invention is set forth in the appended claims.

[0007] A method is provided for fabricating a silicon nanostructure having a main surface defined by a tilted surface relative to the main surface. This fabrication results in the splitting of the silicon nanostructure. The silicon nanostructure is a 3D structure erected from a planar support structure. The portion of the silicon nanostructure erected from the support structure has a main surface and a tilted surface. The main surface is generally parallel to the planar support structure. The tilted surface extends downward from the main surface to the top surface of the support structure. The method includes subjecting the silicon nanostructure to a first cyclic process. Each cycle of the first cyclic process includes: oxidizing the main surface and the tilted surface to form a silicon oxide layer on the main surface and the tilted surface; applying a first etching process configured to anisotropically etch the silicon oxide layer from the main surface while retaining the silicon oxide layer on the tilted surface, thereby exposing the silicon of the silicon nanostructure; and applying a second etching process configured to selectively etch the exposed silicon of the silicon nanostructure using the silicon oxide layer of the tilted surface as a mask layer. This achieves selective etching of the main surface relative to the tilted surface, such that a recess is formed in the silicon nanostructure having its opening at the main surface of the silicon nanostructure.

[0008] The proposed method for splitting silicon nanostructures integrates multiple separate processes used in existing technologies into a single process as distinct process steps. This provides improved process control, reduces operating expenses (OPEX) and capital expenditures (Capex), and increases throughput. Specifically, increased process control is provided by utilizing cyclic processing, where different processing effects dominate in different steps. Furthermore, process control and multi-step integration are achieved by introducing a first etching process and a second etching process within each cycle of the cyclic processing. In the first and second etching processes, surface modification and etching are performed in different ways; that is, with different process selectivity. Therefore, by utilizing cyclic processing, where different processes dominate in different steps of each cycle in the cyclic process, control is achieved, enabling the formation of recesses in the silicon nanostructures undergoing the cyclic process. Compared to conventional processing of nanostructures, the number of processing steps can be reduced through the proposed cyclic processing. This contributes to increased throughput and makes production more economical. The proposed process helps push the resolution limit because the number of defects in the produced nanostructures can be reduced. The proposed processing method can even repair some defects introduced into the structure. All of this relies on changes to existing equipment and processes, saving the industry time and resources. It should also be noted that the proposed method for splitting silicon nanostructures is performed without using patterned hard masks.

[0009] The supporting structure can be used as a stop layer.

[0010] A silicon oxide layer is formed on the main surface and the inclined surface, which allows oxidation to be performed so that all surfaces of the silicon nanostructure erected from the support structure include the silicon oxide layer.

[0011] Oxidation can be performed using plasma.

[0012] The plasma in the oxidation process can be configured such that the ions impacting the silicon nanostructure have a kinetic energy of less than 1 eV, preferably less than 0.1 eV. This low ion energy results in a uniform oxide layer with the same thickness on the horizontal, inclined, and vertical surfaces relative to the principal plane of the sample surface—an isotropic oxidation process. Then, by applying an anisotropic etching process to this oxide layer, the oxide layer can be selectively etched away from the horizontal surface while retaining the oxide layer on the inclined and vertical surfaces.

[0013] The first etching process and the second etching process can be different etching processes.

[0014] According to one embodiment, a first etching process can be performed by reactive ion etching using ions with a first kinetic energy when impacting a silicon nanostructure. The ions in the reactive ion etching of the first etching process can be formed from ionized SF6 gas contained in a gas mixture supplied to the processing chamber volume. A second etching process can be performed by reactive ion etching using ions with a second kinetic energy when impacting a silicon nanostructure. The ions in the reactive ion etching of the second etching process can be formed from ionized SF6 gas contained in a gas mixture supplied to the processing chamber volume. The second kinetic energy is lower than the first kinetic energy. Therefore, reactive ion etching can be used for both the first and second etching processes, with different kinetic energies for the two processes.

[0015] According to another embodiment, the first etching process can be performed by reactive ion etching, and the second etching process can be a second cyclic etching process, wherein each cycle includes: surface modification by introducing chemical species into the processing chamber volume surrounding the silicon nanostructure, and surface activation removal by inert gas ion bombardment. Therefore, a continuous etching process in the form of reactive ion etching can be used for the first etching process, and a cyclic etching process can be used for the second etching process. Reactive ion etching can be performed using ionized SF6 gas contained in the gas mixture supplied to the processing chamber volume. In the second cyclic etching process, the inert gas can be argon. The chemical species used in the surface modification of the second cyclic etching process can be halogens. The surface modification of the second cyclic etching process can be performed in a gas phase containing only neutral chemical species. More specifically, the surface modification of the second cyclic etching process can be performed by chlorination. Excess chemical species can be extracted from the processing chamber volume after the surface modification of the second cyclic etching process.

[0016] According to another embodiment, both the first and second etching processes can be cyclic etching processes that include both surface modification and surface activation. The first etching process can be a third cyclic etching process, wherein each cycle includes: surface modification by introducing chemical species into the processing chamber volume surrounding the silicon nanostructure, and surface activation removal by bombardment with inert gas ions having a third kinetic energy. The chemical species used in the surface modification of the third cyclic etching process can be halogens. The surface modification of the third cyclic etching process can be carried out in a gas phase containing only neutral chemical species. More specifically, the surface modification of the third cyclic etching process can be accomplished by chlorination. After the surface modification of the third cyclic etching process, excess chemical species can be extracted from the processing chamber volume. The second etching process can be a fourth cyclic etching process, wherein each cycle includes: surface modification by introducing chemical species into the processing chamber volume, and surface activation removal by bombardment with inert gas ions having a fourth kinetic energy. The fourth kinetic energy is lower than the third kinetic energy. Therefore, two different cyclic etching processes can be used for the first and second etching processes, with different kinetic energies for the two processes. The chemical species used in the surface modification of the fourth-cycle etching process can be halogens. Surface modification in the fourth-cycle etching process can be performed in a gas phase containing only neutral chemical species. More specifically, surface modification in the fourth-cycle etching process can be performed via chlorination adsorption. Excess chemical species can be removed from the processing chamber volume after surface modification in the fourth-cycle etching process.

[0017] In the third and fourth cycle etching processes, the inert gas can be argon. The fourth kinetic energy can be an average kinetic energy of 40 eV to 60 eV. The third kinetic energy can be a kinetic energy in the range of an average kinetic energy of 65 eV to 80 eV.

[0018] According to another embodiment, the first etching process can be performed by a fifth-cycle etching process including surface modification and surface activation, and the second etching process can be a reactive ion etching process. Reactive ion etching can be performed using ionized SF6 gas contained in a gas mixture supplied to the processing chamber volume. The fifth-cycle etching process includes: surface modification by introducing chemical species into the processing chamber volume encapsulating the silicon nanostructure, and surface activation removal by inert gas ion bombardment. The inert gas can be argon. The chemical species used in the surface modification of the fifth-cycle etching process can be halogens. The surface modification of the fifth-cycle etching process can be performed in a gas phase containing only neutral species. More specifically, the surface modification of the fifth-cycle etching process can be performed by chlorination adsorption. Excess chemical species can be extracted from the processing chamber volume after the surface modification of the fifth-cycle etching process.

[0019] At least a portion of each cycle in the first cycle process, preferably each cycle, may further include purging the processing chamber volume by flushing it with a gas mixture, preferably an oxygen-containing gas mixture, for processing silicon nanostructures. The flushing may be performed for 1 to 30 seconds at a process pressure of 0.01 mTorr to 100 mTorr, preferably 0.1 mTorr to 3 mTorr and an oxygen flow rate of 10 sccm to 200 sccm, preferably 30 sccm to 50 sccm.

[0020] Silicon nanostructures can be arranged on a support structure. The support structure can be silicon, silicon nitride, or silicon oxide.

[0021] The number of cycles in the first cycle can range from 5 to 200 cycles.

[0022] One or more of the cyclic processes discussed above can be implemented via pulses. Cyclic processes can overlap and / or merge, ultimately resulting in multiplexed and continuous processes, where the desired reactions and processes are controlled as needed. The process can include dynamic process parameter variations during the process, allowing etching parameters to change as needed during the process. According to some examples, a particular process may include starting with a continuous dry etching process and then ending in a cyclic manner to ensure a high-performance dry etching process. One aspect of this parameter variation is that it can be guided by real-time feedback from process monitoring, which can be performed in-situ or ex-situ using, for example, optical emission spectroscopy and / or residual gas analyzers. One or more of the cyclic processes discussed above can include atomic layer etching processes. In particular, one or more of the cyclic processes discussed above can be atomic layer etching processes.

[0023] A cyclic etching process refers to a process that involves a series of events or processes that repeat in a predictable pattern. It typically comprises a series of steps or stages that occur in a specific sequence and return to the starting point upon completion. A cycle can include various pulses or consist of pulses.

[0024] A pulse is a brief, sudden change in a physical quantity that usually returns to its original state.

[0025] Atomic layer etching (ALE) is an etching technique that uses sequential half-reactions to result in layer-by-layer material reduction. An ALE implementation comprises at least two sequential steps: surface modification (reaction A) and removal (reaction B). These reactions can be cyclical, and at least one step is at least partially self-limiting. The modification step forms a thin reactive surface layer of well-defined thickness, which is subsequently more easily removed than the unmodified material. This layer is characterized by changes in chemical composition and / or material structure. Removal methods include thermal desorption, particle bombardment, and chemical reactions. Here, the ALE process also includes quasi-atomic layer etching processes, which may include quasi-self-limiting and non-self-limiting reactions.

[0026] A self-limiting reaction is a reaction that slows down or stops over time or, equivalently, over a dose of species. Self-limiting reactions can include, but are not limited to, deposition, chemisorption, physisorption, transformation (e.g., oxidation, nitridation), and extraction. In the case of extraction, the raw material is a compound, where modification preferentially removes one element from the surface, while another element is removed in a subsequent removal step. Attached Figure Description

[0027] The above and other aspects will now be described in more detail with reference to the accompanying drawings. These drawings should not be considered limiting; rather, they are intended for interpretation and understanding.

[0028] As shown in the figures, the dimensions of layers and regions may be enlarged for illustrative purposes and are thus provided to illustrate the general structure. The same reference numerals always refer to the same elements.

[0029] Figure 1 The silicon nanostructures exposed to the processing disclosed herein are illustrated schematically.

[0030] Figure 2 This is a block diagram of a method for fabricating silicon nanostructures.

[0031] Figure 3 includes Figures 3A to 3G This schematically shows that in Figure 2 The result after the processing steps in the method. Detailed Implementation

[0032] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate the currently preferred embodiments of the invention. However, the invention may be implemented in many different forms.

[0033] This invention relates to a method for fabricating silicon nanostructures. In particular, it relates to the selective etching of the main surface of a silicon nanostructure relative to an inclined surface. Such fabrication results in the splitting of the silicon nanostructure. Therefore, this invention allows for the splitting of the spacing within an array of silicon nanostructures.

[0034] Combination Figure 1 An example of a silicon nanostructure 10 to be exposed to the processing of the present invention is schematically shown. The tilt angle α of the tilted surface 14 relative to the main surface 12 is 60° in this example. However, it should be appreciated that the processing of silicon nanostructures as discussed herein can be performed on silicon nanostructures with different geometries, as long as the silicon nanostructure exhibits a main surface limited by the tilted surface. The tilt angle α of the tilted surface 14 relative to the main surface 12 is greater than 10°, preferably greater than 20°. Figure 1 The diagram shows a tilt angle α of 60°. However, other tilt angles, such as 90°, can be used. Furthermore, the tilt angle α can vary for different tilted surfaces of the silicon nanostructure.

[0035] The silicon nanostructure 10 is typically made of crystalline silicon. However, the silicon nanostructure 10 can also be amorphous silicon or polycrystalline silicon. The silicon nanostructure 10 is disposed on a support structure 20. The support structure 20 is typically planar. The support structure 20 can be formed of silicon, silicon oxide, or silicon nitride. Other materials can also be used to form the support structure. The support structure 20 may include a stop layer. The stop layer can be formed of SiNx materials, such as Si3N4, silicon carbon nitride, SiCN, silicon germanium, SiGe, titanium nitride, TiN, and carbon hard masks. However, other types of materials suitable as stop layers can also be used.

[0036] The silicon nanostructure 10 is a 3D structure. The silicon nanostructure 10 stands upright from the planar support structure 20. The portion of the silicon nanostructure 10 that stands upright from the support structure 20 exhibits a main surface 12 and an inclined surface 14. The main surface 12 is generally parallel to the support structure 20. The inclined surface 14 extends downward from the main surface 12 to the top surface of the support structure 20.

[0037] exist Figure 1 The diagram shows a single silicon nanostructure; however, it should be understood that multiple silicon nanostructures can be simultaneously exposed to the processing of the present invention. Such multiple silicon nanostructures are preferably arranged on the same support structure 20. According to one example, such multiple silicon nanostructures are preferably arranged in an array with a known spacing. If so, spacing division has been performed after the silicon nanostructure array has been exposed to the method of the present invention.

[0038] Combination Figure 2 as well as Figures 3A to 3G The method for fabricating silicon nanostructures 10 will be discussed. The silicon nanostructure 10 has a main surface 12 defined by an inclined surface 14 relative to the main surface 12. Such silicon nanostructures 10, arranged on a support structure 20, are... Figure 3A As shown in the image.

[0039] The method includes subjecting a silicon nanostructure to a first cyclic process S204. The number of cycles in the first cyclic process S204 can vary depending on various factors, such as the thickness of the silicon nanostructure 10, the processing parameters of the process steps in the first cyclic process S204, and the type of process steps in the first cyclic process S204. Typically, the number of cycles in the first cyclic process S204 can vary from 5 cycles to 200 cycles.

[0040] Each cycle of the first cyclic process S204 includes oxidizing the main surface 12 and the inclined surface 14 of S210, thereby forming silicon oxide layers 18a and 18b on the main surface 12 and the inclined surface 14. The result of this first oxidation step of S210 is... Figure 3B As shown in the diagram. Each cycle of the first cycle process S204 further includes applying a first etching process S212, which is configured to anisotropically etch the silicon oxide layer 18a from the main surface 12 while at least partially retaining the silicon oxide layer 18b on the inclined surface 14, thereby exposing the silicon of the main surface 12 of the silicon nanostructure 10. The result after such a first etching process S212 is... Figure 3C As shown in the diagram, the silicon oxide layer 18a of the main surface 12 has been etched away. Each cycle of the first cycle process S204 further includes applying a second etching process S214, which is configured to selectively etch the exposed silicon of the main surface 12 of the silicon nanostructure 10 using the silicon oxide layer 18b of the tilted surface 14 as a mask layer. This achieves selective etching of the main surface 12 relative to the tilted surface 14. This forms a recess 16 in the silicon nanostructure 10. The recess 16 has its opening at the main surface 12 of the silicon nanostructure 10. Figure 3D The results are shown after the second etching process S214, which is the first such process. Figure 3D In this process, a recess 16 is formed at the main surface 12. Although the second etching process S214 is configured to selectively etch the exposed silicon of the main surface 12 of the silicon nanostructure 10 using the silicon oxide layer 18b of the tilted surface 14 as a mask layer, the silicon oxide layer 18b of the tilted surface 14 will also generally be affected by the second etching process S214 and will eventually be substantially etched away. This is Figure 3D The diagram shows that the silicon oxide layer 18b on the inclined surface 14 has disappeared. Once this has happened, or preferably shortly before, when the silicon oxide layer 18b on the inclined surface still uniformly covers the sidewall 14, but the oxide layer is already very thin and at risk of breaking during further processing, it is time to begin a new cycle of the first cycle process S204. Figures 3E to 3G The second cycle of the first cycle process S204 is shown. (As...) Figure 3EAs shown, new silicon oxide layers 18a and 18b are formed on the main surface 12 and inclined surface 14 of S210 by re-oxidizing them. Figure 3F The result is shown after another step of the first etching process S212. Here, it is shown that the silicon oxide layer 18a of the main surface 12 has been etched away again. Figure 3G The result is shown after another step of applying the second etching process S214. Here, the recess 16 is shown to be even deeper than before.

[0041] Therefore, the current processing of the silicon nanostructure 10 provides selective etching, resulting in the formation of a recess 16 in the silicon nanostructure 10. The recess 16 has its opening at the main surface 12 of the silicon nanostructure 10.

[0042] When the silicon nanostructure 10 is an elongated structure, the recess 16 can form a channel in the elongated silicon nanostructure. However, by continuing the first cycle process S204 with an additional cycle, the recess 16 can form a through-hole in the elongated silicon nanostructure 10, thereby dividing the elongated silicon nanostructure 10 into two.

[0043] After oxidation S210, preferably immediately following oxidation S210, the first etching process S212 is performed. After the first etching process S212, preferably immediately following the first etching process S212, the second etching process S214 is performed.

[0044] Oxidation S210 can be performed using plasma. The plasma can be provided in such a manner that the ions bombarding the silicon nanostructure 10 have an energy of less than 1 eV, preferably less than 0.1 eV. The plasma assisting the oxidation process can be generated in an oxygen-containing gas mixture. As an example, the plasma can be generated using 13.56 MHz or 2 MHz and a radio frequency power of 0.1 W to 3000 W, preferably 1000 W to 2000 W, inductively or transformerically coupled to a processing chamber in which the fabrication of the silicon nanostructure is performed. Oxidation can be carried out for 1 to 300 seconds, preferably 5 to 20 seconds, at a process pressure of 0.01 mTorr to 2000 mTorr, preferably 30 mTorr to 100 mTorr and an oxygen flow rate of 10 sccm to 200 sccm, preferably 30 sccm to 50 sccm, without any additional gas in the processing chamber volume.

[0045] Silicon oxide layers 18a and 18b are formed on the main surface 12 and the inclined surface 14, i.e., oxidation, and are carried out such that all surfaces of the silicon nanostructure 10 erected from the support structure 20 include silicon oxide layers.

[0046] The first cycle process S204 can be performed in any dedicated plasma etching system. Examples of equipment manufacturers include Lam Research, Applied Materials, Tokyo Electron (TEL), Oxford Instruments Plasma Technology (OIPT), and Plasma-Therm. Specifically, the process can be performed in the Plasmalab100 ICP-RIE system from OIPT, the Takachi ICP-RIE system from Plasma-Therm, or the 2300 Kiyo plasma etching system with a transformer-coupled plasma source from Lam Research.

[0047] At the start of the first cycle of process S204 (preferably each cycle), the processing chamber S208 is flushed with gas. The gas is preferably oxygen. This removes any gases and reaction byproducts that may have remained in the chamber from previous steps. This gas flushing of the S208 processing chamber prepares the chamber and the equipment within it for subsequent steps. Typical process parameters for gas flushing of S208 using oxygen are: an oxygen flow rate of 10 sccm to 200 sccm, preferably 30 sccm to 50 sccm, at a process pressure of 0.01 mTorr to 50 mTorr, preferably 0.1 mTorr to 3 mTorr, for a duration of 1 to 30 seconds. As will be readily understood, these process parameters depend on the volume of the processing chamber. Preferably, no plasma is applied to the processing chamber volume during the gas flushing of S208.

[0048] Furthermore, before starting the first cycle process S204, the silicon nanostructure 10 and the support structure 20, which may also have the silicon nanostructure 10 disposed thereon, can be pre-cleaned. Therefore, the method may include a pre-cleaning step S202. Such pre-cleaning S202 may include exposing the silicon nanostructure 10 (and possibly the support structure 20, on which the silicon nanostructure 10 is disposed) for plasma or chemical processing. This is to obtain silicon nanostructure 10 (and possibly the support structure 20, on which the silicon nanostructure 10 is disposed) free of contaminants and native oxides. For native oxide removal, buffer oxide etching (10:1) can be performed, for example, by immersing the substrate in buffered HF for 30 seconds, rinsing in deionized water for 30 seconds, and then dry-blowing with N2 for 15 seconds.

[0049] The first etching process S212 and the second etching process S214 will now be discussed in more detail. First, the first etching process S212 and the second etching process S214 are different etching processes. In this document, "different etching processes" means that at least one process parameter in the etching process is changed when transitioning from the first etching process S212 to the second etching process S214. It is important to note that the first etching process S212 is configured to anisotropically etch the silicon oxide layer 18a from the main surface 12 while retaining the silicon oxide layer 18b on the tilted surface 14, while the second etching process S214 is configured to selectively etch the exposed silicon of the silicon nanostructure 10 using the silicon oxide layer 18b of the tilted surface 14 as a mask layer. Several different scenarios of the first etching process S212 and the second etching process S214 will be discussed below.

[0050] According to the first example, reactive ion etching is used for both the first etching process S212 and the second etching process S214. However, the kinetic energy of the ions is different for the two processes, or the gas mixture is different for the two processes, or both are different. Reactive ion etching is a continuous etching mode. According to this first example, the first etching process S212 is performed using reactive ion etching with ions having a first kinetic energy when impacting the silicon nanostructure 10, and the second etching process S214 is performed using reactive ion etching with ions having a second kinetic energy when impacting the silicon nanostructure 10. The second kinetic energy is lower than the first kinetic energy. Preferably, the ions impacting the silicon nanostructure in the second etching process S214 have a kinetic energy of less than 1 eV, preferably less than 0.1 eV. This ensures that the oxide layer retained on the inclined and vertical surfaces is not significantly etched during the process and can serve as an effective etching mask for selectively etching the silicon exposed on the horizontal surface after selectively removing the oxide layer from the horizontal surface during the first etching process S212. The ion energy and directionality of the first etching process S212 must be significantly higher than those of the second etching process S214. This ensures the directionality of the etching process (anisotropic etching), and therefore ensures selective etching of the oxide layer from the horizontal surface. Simultaneously, the ion energy used in the first etching process should not be too high. This is to ensure that the oxide etch rate remains relatively low, so that the etching process can actually be stopped when the oxide layer is completely etched from the horizontal surface, while it still remains as a continuous film on both the inclined and vertical surfaces. Importantly, the second etching process S214 must be stopped before the silicon oxide layer 18b on the inclined surface 14 becomes discontinuous. Crucially, the ion energy must be kept well below the physical sputtering threshold. This is because physical sputtering is more efficient on the inclined surface and would hinder selective etching of the oxide layer from the horizontal surface. The exact value will depend on other process details, primarily the process gas mixture.

[0051] In the reactive ion etching process of the first etching step, ions can be formed from ionized SF6 gas contained in a gas mixture supplied to the processing chamber volume. The ionization of the gas can be accomplished using plasma, generated by applying a radio frequency power of 13.56 MHz and 0.1 W to 30 W, preferably 10 W to 20 W, to electrodes on which silicon nanostructures are placed. In the reactive ion etching process of the second etching step, ions can also be formed from ionized SF6 gas contained in a gas mixture supplied to the processing chamber volume. The ionization of the gas can be accomplished using plasma, generated by applying a radio frequency power of 13.56 MHz or 2 MHz and 0.1 W to 3000 W, preferably 1000 W to 2000 W, to the processing chamber where the silicon nanostructure fabrication is performed, with the radio frequency power inductively or transformerically coupled to the processing chamber. According to this first example, typical process parameters for the first etching process S212 are: a process pressure of 0.01 mTorr to 20 mTorr, preferably 0.01 mTorr to 5 mTorr, and an SF6 gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 50 sccm, for a duration of 0.1 seconds to 300 seconds, preferably 3 seconds to 30 seconds. According to this first example, typical process parameters for the second etching process S214 are: a process pressure of 0.01 mTorr to 100 mTorr, preferably 1 mTorr to 50 mTorr, and an SF6 gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 50 sccm, for a duration of 0.1 seconds to 300 seconds, preferably 3 seconds to 30 seconds. The exact process parameters will depend on the processing chamber design and the size and geometry of the sample being processed.

[0052] According to the second example, reactive ion etching is used to perform the first etching process S212, and a second cyclic etching process is used to perform the second etching process S214, wherein each cycle includes surface modification and surface activation. The reactive ion etching of the first etching process S212 can be performed using ionized SF6 gas contained in the gas mixture supplied to the processing chamber volume. After the reactive ion etching of the first etching process S212 is completed, the silicon oxide layers 18a and 18b of the silicon nanostructure 10 have been anisotropically etched, such that the silicon oxide layer 18a on the main surface 12 is etched away while the silicon oxide layer 18b on the tilted surface 14 is retained. The cycle of the second cyclic etching process includes a surface modification step and a surface activation step. Surface modification can be performed by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure. The chemical species can be halogens. Surface modification can be performed in a gas phase containing only neutral chemical species. More specifically, surface modification can be performed by the chemisorption of chlorine. Excess chemical species can be extracted from the processing chamber volume after surface modification. Surface activation can be performed by bombarding the silicon nanostructure 10 with inert gas ions. Argon ions are preferred. Typically, at least in the case of plasma-assisted surface modification, similar to the process previously reported by Samantha Tan et al. in “Highly Selective Directional Atomic Layer Etching of Silicon”, ECS Journal of Solid State Science and Technology, 4(6) N5010-N5012 (2015), the average kinetic energy of the argon ions bombarding the silicon nanostructure 10 is set to 40 eV to 60 eV. In this example of the second etching process S214, the number of cycles of the second cyclic etching process depends on the process selectivity of etching silicon compared to silicon oxide. Empirically, the process selectivity can be expected to be about 1:10 or better; therefore, the cyclic process of the second etching process S214 is typically set to run 10 to 30 cycles until the silicon oxide layer 18b on the inclined surface is eroded. The second etching process S214 is preferably stopped before the silicon oxide layer 18b on the inclined surface 14 becomes discontinuous. During the second etching process S214, silicon from the main surface 12 is etched away, while some oxides are left on the inclined surface 14.Typical process parameters for the second cyclic etching process of the second etching process S214 in this example are: 10 to 30 cycles at a process pressure of 0.01 mTorr to 100 mTorr, preferably 0.01 mTorr to 60 mTorr, a Cl2 gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 30 sccm, and an Ar gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 30 sccm, with each step in the cycle lasting 0.1 seconds to 300 seconds, preferably 0.5 seconds to 30 seconds. The process pressure for the chlorination step is preferably 30 mTorr to 60 mTorr. This chlorination step is typically performed without applying any radio frequency power to the electrode where the silicon nanostructure is located. The radio frequency power inductively coupled or transformer-coupled to the chamber is preferably in the range of 500 W to 1500 W, preferably in the range of 900 W to 1100 W. The process pressure for the activation step using Ar bombardment is preferably 1 mTorr to 5 mTorr. This activation step is typically performed with a very small radio frequency (RF) power applied to the electrode where the silicon nanostructure is located. This power is typically adjusted to have an average Ar ion energy between 40 eV and 60 eV, typically corresponding to an applied power of 0 W to 20 W. The RF power inductively or transformerically coupled to the chamber during this step is preferably 100 W to 500 W, more preferably 200 W to 200 W. The exact process parameters will depend on the design of the processing chamber and the size and geometry of the sample being processed.

[0053] According to the third example, both the first etching process S212 and the second etching process S214 are performed as cyclic etching processes that include both surface modification and surface activation. However, the kinetic energy of the ions used in the surface activation of the second etching process S214 is different from that used in the surface activation of the first etching process S212. In both the first etching process S212 and the second etching process S214, surface modification can be performed by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure. The chemical species can be halogens. Furthermore, surface modification can be performed in a gas phase containing only neutral chemical species. More specifically, surface modification can be performed by the chemisorption of chlorine. During surface modification, Cl2 preferably dissociates into atomic species. Transformer-coupled plasma or inductively coupled plasma can be used for surface modification, which does not require applying power to the treated silicon structure 10. Typically, surface modification using chlorine can be performed using a pressure of 60 mTorr, a source power of 900 W, and a duration of 2 seconds or preferably 0.5 seconds. Surface activation in both the first etching process S212 and the second etching process S214 is performed by bombarding the silicon nanostructure 10 with inert gas ions. Argon ions are preferred. Typically, the source power during surface activation is set to 300 W, the pressure to 5 mTorr, and the duration to 2.5 seconds. Using argon ions with different kinetic energies, good selectivity in etching silicon compared to silicon oxide can be achieved. Experimental results, such as those presented by Samantha Tan et al. in “Highly Selective Directional Atomic Layer Etching of Silicon”, ECS Journal of Solid State Science and Technology, 4(6) N5010-N5012 (2015), have shown that silicon can be selectively etched compared to silicon oxide using atomic layer etching as discussed above. Silicon can be selectively etched using an average kinetic energy of 40 eV to 60 eV with argon ions, compared to silicon oxide. Therefore, argon ions with an average kinetic energy of 40 eV to 60 eV are preferably used for surface modification in the second etching process S214. On the other hand, a relatively high average kinetic energy of argon ions is required for etching silicon oxide in the surface modification of the first etching process S212. An average kinetic energy of 65 eV to 80 eV of argon ions can be used for surface activation after the surface modification in the first etching process S212.Preferably, the average kinetic energy is maintained below 80 eV during surface activation in the first etching process S212 to avoid high-speed sputtering of the silicon oxide layer. In this way, controlled etching stop can be achieved when the oxide layer 18a is selectively removed from the horizontal surface on the main surface 12, and the oxide layer 18b is retained on the inclined and vertical surfaces. After surface modification by the cyclic etching process associated with the first etching process S212 and / or the second etching process S214, excessive chemical species can be extracted from the processing chamber volume.

[0054] According to the fourth example, the first etching process S212 can be performed by a cyclic etching process including surface modification and surface activation, while the second etching process S214 can be a reactive ion etching process. Reactive ion etching can be performed using ionized SF6 gas in a gas mixture supplied to the processing chamber volume. The parameters of this reactive ion etching process can be the same as those provided in the first etching process S212 in the previously described first example. Surface modification of the cyclic etching process of the first etching process S212 can be performed by introducing chemical species into the processing chamber volume encapsulating the silicon nanostructure. Surface modification can be performed in a gas phase containing only neutral species. More specifically, surface modification can be performed by chlorination. After surface modification of the cyclic etching process of the first etching process S212, excess chemical species can be extracted from the processing chamber volume. Surface activation of the cyclic etching process of the first etching process S212 can be achieved by inert gas ion bombardment. The inert gas can be argon. The process parameters of the cyclic process in this example can be the same as those of the cyclic etching process S214 in the previous example.

[0055] The fabrication of the silicon nanostructure 10 according to the present invention can be used to assist various photolithography and patterning techniques, including but not limited to deep ultraviolet lithography (DUV), extreme ultraviolet lithography (EUV), nanoimprint lithography (NIL), and self-aligned multiple patterning (SAMP). This fabrication assists these techniques by splitting the spacing of the structures fabricated using these techniques, thereby providing a means to fabricate or even scale down various nanoscale devices in a cost-effective manner. Thus, this process can be used to fabricate various nanoscale devices, which can also be produced using other photolithography and patterning techniques. According to a non-limiting example, this fabrication can be used to recess a FinFET gate channel. According to another non-limiting example, this fabrication can be used to form and / or modify transistor gate channels, such as GAAFET nanowire gate channels.

[0056] Those skilled in the art will recognize that the present invention is by no means limited to the content expressly described above. Rather, many modifications and variations are possible within the scope of the appended claims.

[0057] For example, surface modification and / or surface activation in any of the cycling processes discussed above may include self-limiting reactions that slow down or stop over time or, equivalently, with species dosage. Such self-limiting reactions include chemisorption, deposition, extraction, and / or transformation, such as oxidation or nitriding.

[0058] Methods for fabricating silicon nanostructures can also include an additional passivation step prior to the oxidation step. Such a passivation step prevents oxidation of the silicon surface while simultaneously allowing oxidation of other surfaces.

[0059] When executing methods for fabricating silicon nanostructures, process control information can be monitored, for example, through light emission and residual gas analysis. The process parameters of the method can then be adjusted based on this information.

[0060] The methods used to fabricate silicon nanostructures can be repeated until the fabrication has no further impact on the nanostructure. For example, a finned silicon nanostructure can split into two finned silicon nanostructures. The two newly formed finned silicon nanostructures are thinner than the initial finned silicon nanostructure.

[0061] In conjunction with the above discussion of removing excess chemical species from the processing chamber volume for various embodiments / examples, this can be performed by alternately evacuating the processing chamber to a low pressure and then rapidly purging the processing chamber with gas at a relatively high pressure. This alternation can be performed several times to help quickly remove remaining species from the processing chamber. Evacuation is preferably performed at a chamber pressure below 0.1 mTorr. Purging is preferably performed with an inert gas or a gas mixture containing an inert gas. Alternatively, purging may include hydrogen, which removes excess oxygen from the processing chamber. The chamber pressure during purging is preferably above 10 mTorr, more preferably above 50 mTorr. The optimal purging pressure depends on the evacuation capability of the specific etching system.

[0062] Oxidation S210 and the first etching process S212 can be separated from the steps for removing excess oxygen from the processing chamber volume. This can be performed by alternately evacuating the chamber to a low pressure and purging the processing chamber with a gas or gas mixture. This alternation can be performed several times to help rapidly remove any remaining species in the processing chamber. Evacuation is preferably performed to a chamber pressure below 0.1 mTorr. Purging is preferably performed with an inert gas or a gas mixture containing an inert gas. Alternatively, purging may include hydrogen, which removes excess oxygen from the processing chamber. The chamber pressure during gas purging is preferably above 10 mTorr, more preferably above 50 mTorr. The optimal purging pressure depends on the evacuation capability of the specific etching system.

[0063] It is also recognized that box structures can be formed by exposing silicon nanostructures, which are not elongated but have substantially square extensions exhibiting a substantially flat top surface limited by sloping surfaces. Furthermore, silicon nanostructures exhibiting circular, triangular, or any geometrically shaped top surface can be fabricated using the fabrication techniques disclosed herein.

[0064] Furthermore, different embodiments of the first and second etching processes have been disclosed and discussed above. However, the inventors also recognize that the method for splitting the 3D silicon nanostructure 10 erected from the planar support structure 20 can be performed using etching processes similar to the following: anisotropically etching the silicon oxide layer 18a from the main surface 12 while retaining the silicon oxide layer 18b on the inclined surface 14, thereby exposing the silicon of the silicon nanostructure 10; and selectively etching the exposed silicon of the silicon nanostructure 10 using the silicon oxide layer 18b of the inclined surface 14 as a mask layer. In this case, the etching rate of the silicon oxide needs to be sufficiently lower than the etching rate of the underlying silicon.

[0065] This can be accomplished, for example, by performing etching processes S212 and S214 using the same continuous reactive ion etching or the same cyclic etching process. However, the kinetic energy of the ions is selected such that the etching rate of silicon oxide is sufficient to effectively etch the oxide layer from the horizontal surface, but low enough to allow the oxide layer retained on the sidewalls to serve as an effective etching mask for the underlying silicon on the horizontal surface. In this case, the process parameters can remain the same or change little during both the etching of silicon oxide from the horizontal surface and the subsequent etching of the underlying silicon. Preferably, the ions impacting the surface have a kinetic energy greater than 0.1 eV, preferably greater than 1 eV, and less than 20 eV, preferably less than 10 eV. This ensures that the oxide layer retained on the inclined and vertical surfaces is not significantly etched during the process and can serve as an effective etching mask for selectively etching the silicon exposed on the horizontal surface after selectively removing the oxide layer from the horizontal surface. Importantly, the ion energy must be kept well below the physical sputtering threshold. This is because such physical sputtering is more efficient on inclined surfaces and would hinder selective etching of the oxide layer from the horizontal surface.

[0066] In continuous reactive ion etching (CRIE), ions can be formed from ionized SF6 gas contained in a gas mixture continuously supplied to the processing chamber volume. Gas ionization can be accomplished using plasma generated by applying a radio frequency power of 13.56 MHz and 0.1 W to 100 W, preferably 5 W to 30 W, to electrodes on which silicon nanostructures are placed. Typical process parameters for the etching process are: a process pressure of 0.01 mTorr to 20 mTorr, preferably 0.01 mTorr to 5 mTorr, and an SF6 gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 50 sccm, for a duration of 0.1 s to 300 s, preferably 3 s to 30 s. The exact process parameters will depend on the processing chamber design and the size and geometry of the sample being processed.

[0067] Alternatively, in continuous reactive ion etching (CRIE) processes, ions can be formed from ionized SF6 gas contained in a gas mixture continuously supplied to the processing chamber volume by applying an additional RF power of 13.56 MHz or 2 MHz and 0.1 W to 3000 W, preferably 1000 W to 2000 W, inductively or transformerically coupled to the processing chamber in which the fabrication of silicon nanostructures is performed. Typical process parameters in this case are: a process pressure of 0.01 mTorr to 20 mTorr, preferably 0.01 mTorr to 5 mTorr, and an SF6 gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 50 sccm, for a duration of 0.1 s to 200 s, preferably 3 s to 25 s. The exact process parameters will depend on the processing chamber design and the size and geometry of the sample being processed.

[0068] In a cyclic etching process that includes surface modification and surface activation, ions can be formed by ionized inert gas, preferably Ar. Surface modification can be accomplished by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure. The chemical species can be halogens. Alternatively, surface modification can be accomplished in a gas phase containing only neutral chemical species. More specifically, surface modification can be accomplished by the chemisorption of chlorine. During surface modification, Cl2 preferably dissociates into atomic species. Transformer-coupled plasma or inductively coupled plasma can be used for surface modification, which does not require applying power to the treated silicon structure 10. Typically, surface modification using chlorine can be performed at pressures of 5 mTorr to 100 mTorr, preferably 20 mTorr to 50 mTorr, with a source power of 500 W to 1000 W or zero, and the surface modification can be performed for a duration of 0.1 s to 100 s, preferably 1 s to 20 s. Surface activation can be performed using argon ions with an average kinetic energy in the range of above 0.1 eV, preferably above 1 eV, and below 100 eV, preferably below 50 eV. Within this energy window, good selectivity in etching silicon compared to silicon oxide can be achieved. The exact values ​​will depend on the details of the ion energy distribution, which in turn depends on the processing chamber design and power supply design. An example of process parameters for achieving this ion energy is the application of a radio frequency power of 13.56 MHz and 0.1 W to 100 W, preferably 5 W to 30 W, to an electrode on which the silicon nanostructure is placed. Typical process parameters for the etching process are: a process pressure of 0.01 mTorr to 20 mTorr, preferably 0.01 mTorr to 5 mTorr and an Ar gas flow rate of 1 sccm to 200 sccm, preferably 5 sccm to 50 sccm, for a duration of 0.1 s to 300 s, preferably 3 s to 30 s. Following surface modification in a cyclic etching process associated with a cyclic etching process, excess chemical species can be extracted or purged from the processing chamber volume. Typically, the processing chamber is purged by flowing an inert gas mixture, preferably Ar, at a flow rate of 10 to 100 sccm, preferably 40 to 60 sccm, while maintaining the processing chamber pressure in the range of 10 to 100 mTorr, preferably 25 to 50 mTorr. The extraction or purging step can be in the range of 0 to 100 s, preferably less than 10 s, to ensure a sufficiently short processing time. The exact process parameters will depend on the processing chamber design and the size and geometry of the samples being processed.

[0069] Furthermore, by studying the accompanying drawings, the disclosure, and the appended claims, a person skilled in the art can understand and implement variations when practicing the claimed invention.

Claims

1. A method for splitting a 3D silicon nanostructure (10) erected from a planar support structure (20), the portion of the silicon nanostructure (10) erected from the support structure (20) having a main surface (12), the main surface (12) being defined by an inclined surface (14) relative to the main surface (12), the inclined surface (14) extending from the main surface (12) to a top surface of the support structure (20), the method comprising: The silicon nanostructure (10) is subjected to a first cyclic process (S204), each cycle in the first cyclic process (S204) comprising: Oxidize (S210) the main surface (12) and the inclined surface (14) to form silicon oxide layers (18a, 18b) on the main surface (12) and the inclined surface (14). A first etching process (S212) is applied, configured to anisotropically etch the silicon oxide layer (18a) from the main surface (12) while retaining the silicon oxide layer (18b) on the inclined surface (14), thereby exposing the silicon of the silicon nanostructure (10); and A second etching process (S214) is applied, which is configured to selectively etch the exposed silicon of the silicon nanostructure (10) using the silicon oxide layer (18b) of the tilted surface (14) as a mask layer; This enables selective etching of the main surface (12) relative to the inclined surface (14), such that a recess (16) is formed in the silicon nanostructure (10), the recess (16) having its opening at the main surface (12) of the silicon nanostructure (10).

2. The method according to claim 1, wherein, The oxidation (S210) is performed using plasma.

3. The method according to claim 1 or 2, in, The first etching process (S212) is performed by reactive ion etching using ions with a first kinetic energy when impacting the silicon nanostructure (10), and The second etching process (S214) is performed by reactive ion etching using ions with a second kinetic energy when impacting the silicon nanostructure (10), wherein the second kinetic energy is lower than the first kinetic energy.

4. The method according to claim 1 or 2, in, The first etching process (S212) is performed by reactive ion etching; and Wherein, the second etching process (S214) is a second cyclic etching process, wherein each cycle includes: Surface modification was achieved by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure (10), and Surface activation removal is achieved by bombardment with inert gas ions.

5. The method according to claim 1 or 2, in, The first etching process (S212) is a third-cycle etching process, wherein each cycle includes: Surface modification was achieved by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure (10), and Surface activation removal is achieved through bombardment with inert gas ions possessing a third kinetic energy; and The second etching process (S214) is a fourth cyclic etching process, wherein each cycle includes: Surface modification was achieved by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure (10), and Surface activation removal is achieved by bombardment with inert gas ions having a fourth kinetic energy, wherein the fourth kinetic energy is lower than the third kinetic energy.

6. The method according to claim 5, wherein, For both the third and fourth etch cycles, the inert gas is argon, wherein the fourth kinetic energy is an average kinetic energy of 40 eV to 60 eV, and wherein the third kinetic energy is an average kinetic energy in the range of 65 eV to 80 eV.

7. The method according to claim 1 or 2, in, The first etching process is a fifth-cycle etching process, wherein each cycle includes: Surface modification was achieved by introducing chemical species into the processing chamber volume enclosing the silicon nanostructure (10), and Surface activation removal is achieved through inert gas ion bombardment; and The second etching process is performed by reactive ion etching.

8. The method according to any one of claims 1 to 7, wherein, At least a portion of each cycle of the first cycle process (S204), preferably each cycle, further includes purging the processing chamber volume by flushing (S208) the processing chamber volume used for processing the silicon nanostructure with a gas mixture, preferably an oxygen-containing gas mixture.

9. The method according to claim 8, wherein, The rinsing (S208) is performed for 1 to 30 seconds at a process pressure of 0.01 mTorr to 100 mTorr, preferably 0.1 mTorr to 3 mTorr and an oxygen flow rate of 10 sccm to 200 sccm, preferably 30 sccm to 50 sccm.

10. The method according to any one of claims 1 to 9, wherein, The silicon nanostructure (10) is arranged on the support structure (20), wherein the support structure is preferably formed of silicon, silicon nitride or silicon oxide.

11. The method according to any one of claims 3, 4 or 7, wherein, The reactive ion etching is performed using ionized SF6 gas.

12. The method according to any one of claims 4, 5 or 7, wherein, The surface modification is performed in a gas phase containing only neutral chemical species.

13. The method according to any one of claims 4, 5 or 7, wherein, The surface modification is accomplished through the chemisorption of chlorine.

14. The method according to claim 4, 5 or 7, wherein, The surface modification is followed by the extraction of excess chemical species from the processing chamber volume.

15. The method according to claim 2, wherein, The plasma in the oxidation (210) is configured such that the ions impacting the silicon nanostructure (10) have a kinetic energy of less than 1 eV, preferably less than 0.1 eV.

16. The method according to any one of claims 1 to 15, wherein, The silicon nanostructure (10) is made of crystalline silicon.

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