Continuous waveform data generation system, method, and base station based on heterogeneous computing platform

Abstract

The application belongs to the technical field of satellite navigation, and discloses a continuous waveform data generation system and method based on a heterogeneous computing platform and a base station. The system comprises a heterogeneous platform of an integrated processor system and programmable logic. A customized DMA controller is arranged in the programmable logic. The processor performs one-time configuration on the customized DMA controller in the programmable logic, including a start address, a length, a cycle flag, a frequency control word, a PRN sequence number and the like. The customized DMA controller automatically reads navigation messages from the system memory according to the configuration, and supplies data in a continuous stream to a downstream signal processing module to generate a navigation baseband signal without intervention of the processor again. The application realizes efficient and uninterrupted data transmission, solves the problem of carrier phase loss of lock caused by the transmission gap of the traditional DMA, and meets the real-time and continuity requirements of high-precision signal generation of satellite navigation.

Description

Technical Field

[0001] This invention belongs to the field of satellite navigation technology and relates to a continuous waveform data generation system, method and base station based on a heterogeneous computing platform, which is applicable to navigation signal transmission control in ground-based pseudo-satellite positioning systems. Background Technology

[0002] With the development of information technology, heterogeneous computing platforms, especially system-on-a-chip (SoC) that integrates a Processing System (PS) and Programmable Logic (PL) on a single chip, have become the preferred choice for high-performance embedded system design. The advantage of this architecture lies in its flexibility in running general-purpose operating systems (such as Linux) and complex algorithms on the PS, while leveraging the powerful capabilities of the PL (i.e., FPGA) for large-scale parallel computing and high-speed real-time processing. In many applications, the software on the PS is responsible for generating or managing application-layer data, such as navigation messages in pseudo-satellite navigation systems and data packets to be sent in communication systems, storing this data in large-capacity, high-bandwidth system memory (typically DDR SDRAM) connected to the PS. This data is then transmitted at high speed to the programmable logic (PL), where custom hardware logic performs real-time, high-throughput low-level processing, such as digital filtering, spread spectrum, modulation, and encoding.

[0003] Currently, the most common technology for data transfer between DDR memory on the PS side and hardware logic on the PL side is Direct Memory Access (DMA). DMA allows peripherals (i.e., logic in the PL) to directly exchange data with main memory without consuming core processing time of the processor (CPU). However, standard DMA controller IP cores provided by chip manufacturers (such as Xilinx AXI DMA IP) are designed for general-purpose, block-based transfers. This exposes serious performance bottlenecks and design flaws in specific applications that require generating continuous, seamless, and infinitely looping data streams. Specifically, standard DMA typically operates based on "descriptors." The PS-side driver needs to construct one or more descriptors in memory, each containing information such as source address, destination address, and data length. Then, the PS side starts the DMA controller, which transfers data blocks one by one according to the descriptor linked list. After completing the task specified by each descriptor, the DMA controller usually stops and generates an interrupt, notifying the PS side that it can prepare for the next task. However, in scenarios requiring continuous transfers, the following drawbacks exist: (1) Frequent processor intervention is required: The PS end must constantly process DMA controller completion interrupts and configure new descriptors or restart the DMA controller engine. This consumes valuable CPU cycles, preventing the CPU from focusing on performing higher-level, non-deterministic tasks, such as network time synchronization of pseudo-satellite base stations, interaction with external networks, or complex attitude calculations. (2) Inevitable transmission gaps: There is a time delay from the time the DMA controller completes a data block transfer to the time the PS end responds to the interrupt and then reconfigures and restarts the DMA controller. This delay is usually on the order of microseconds (μs) to milliseconds (ms), which directly results in the input data stream being discontinuous from the PL end, with "holes" or "gaps". (3) Serious impact on signal quality: For pseudo-satellite navigation signals or coherent communication signals, the phase continuity of the signal is crucial. The unavoidable transmission gaps mentioned in point (2) will directly disrupt the signal continuity, causing the user receiver (such as a GPS receiver) to be unable to correctly lock the carrier phase and pseudocode phase, causing the entire positioning system to fail.

[0004] Although some technicians have attempted to alleviate this problem by constructing a circular buffer using the block RAM (BRAM) within the PL (Programmable Logic Controller), the capacity of BRAM is very limited (typically in the KB to several MB range), making it unable to store long-cycle navigation message data, and its flexibility is far inferior to DDR memory with capacities in the GB range. Therefore, a continuous waveform data generation system and method based on a heterogeneous computing platform is needed to solve the aforementioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to propose a continuous waveform data generation system based on a heterogeneous computing platform. By embedding a custom DMA controller in the programmable logic, and performing a one-time initialization configuration, it facilitates seamless, continuous, and highly efficient data flow transmission from system memory to programmable logic without any further intervention from the processor system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A continuous waveform data generation system based on a heterogeneous computing platform, suitable for generating navigation baseband signals, includes a heterogeneous computing platform integrating a processor system and programmable logic; The processor system has system memory for storing one or more waveform data blocks to be generated; The programmable logic incorporates a custom DMA controller and a downstream signal processing module, namely the pseudo-satellite navigation signal baseband generation module, which is used to receive continuous data streams as navigation messages and generate navigation baseband signals. A custom DMA controller is used to receive configuration commands from the processor system and access system memory. The custom DMA controller includes a hardware state machine, a configuration register set, an address counter, and a data path module. The configuration register group is used to store configuration information, including: The source address register is used to store the physical starting address in system memory; The transfer length register is used to define the data block size; The control register, which includes a start bit, a cycle enable flag, a frequency control word, and a PRN sequence number, is used to start data transmission, control the cycle, and adjust signal parameters. And a status register, which includes a busy flag, an end address register, and an error flag, used to report the status; The hardware state machine is used to parse the configuration cycle enable flag to enable hardware autonomous cyclic reading of specified data blocks in system memory. It includes idle state, read configuration state, data transfer state and cycle check state. After completing the transmission of a data block, the hardware state machine enters a loop check state and, based on the loop enable flag in the control register, decides whether to return to the data transmission state or enter the idle state. The data input terminal of the downstream signal processing module is connected to the output terminal of the custom DMA controller.

[0007] In addition to the four states mentioned above, the hardware state machine also adds a clock synchronization check / error handling state, which is used to verify that the DDS clock is synchronized with the RF front end, and enters the error handling state when the error flag is triggered.

[0008] Based on the aforementioned continuous waveform data generation system based on a heterogeneous computing platform, this invention also proposes a continuous waveform data generation method based on the same system and a heterogeneous computing platform, which adopts the following technical solution: A method for generating continuous waveform data based on a heterogeneous computing platform includes the following steps: Step 1. The processor system performs a one-time configuration of the custom DMA controller via a configuration bus; The configuration information includes the physical start address of the data to be read in the system memory, a data block length value, a cycle enable flag indicating the working mode, a frequency control word, a PRN sequence number, and an end address; Step 2. After completing the configuration, the processor system writes a start command to the control register to activate data transmission; Step 3. After detecting the start command, the hardware state machine drives the data path module to automatically read a complete data block from the system memory according to the configured physical start address and data block length in the system memory; Step 4. After completing the read operation of a data block, the hardware state machine automatically checks the state of the cycle enable flag; If it is in the enabled state, the hardware state machine automatically resets the internal address counter to the physical starting address in the system memory and seamlessly changes the state to repeat step 3, forming a continuous loop of data read operations without the need for processor system intervention. If the state is disabled, the hardware state machine will transition to the stop state after completing the reading of the current data block and report the transmission completion to the processor system through the status register, without requiring further processing. Step 5. During continuous data reading, the customized DMA controller outputs the continuously read data to the downstream signal processing module deployed in the programmable logic in real time and without interruption through a streaming protocol interface; The downstream signal processing module receives a continuous data stream as a navigation message, generates a corresponding pseudo-random code based on the configured PRN sequence number, and performs spread spectrum modulation and BPSK carrier modulation on the navigation message and pseudo-random code to generate a navigation baseband signal.

[0009] Furthermore, based on the aforementioned continuous waveform data generation system based on a heterogeneous computing platform, this invention also proposes a pseudo-satellite positioning base station using this system to generate navigation baseband signals conforming to LOCATA or GNSS standards.

[0010] Compared with the prior art, the present invention has the following beneficial effects: As described above, this invention relates to a continuous waveform data generation system, method, and base station based on a heterogeneous computing platform. The system includes a heterogeneous computing platform integrating a processor system (PS) and programmable logic. A custom DMA controller is built into the programmable logic. The PS performs a one-time initialization configuration of the custom DMA controller. Upon detecting a start command, the hardware state machine within the custom DMA controller reads a complete data block from system memory (DDR SDRAM). After reading, the hardware state machine automatically checks the status of the cyclic read enable flag in the configuration register group. If the flag is enabled, the hardware state machine automatically resets the address counter inside the custom DMA controller to the physical starting address in system memory and seamlessly transitions its state to repeat the data transmission process. This forms a continuous cyclic data read operation without any further intervention from the processor system. Compared to standard DMA read methods, this invention achieves truly seamless data stream transmission. Through a hardware autonomous cyclic mechanism, it completely eliminates the transmission gaps between data blocks caused by processor software intervention, ensuring the phase continuity and time determinism of signal generation, and meeting the most stringent real-time system requirements. Secondly, this invention significantly liberates processor resources. The processor only needs to be configured once during system startup, and then it can be completely freed from data transfer tasks. This allows all computing power to be used to execute complex upper-level application software, control algorithms, or interactions with other peripherals, significantly improving the overall system performance and responsiveness. Furthermore, this invention improves data transmission efficiency, avoiding a series of time-consuming operations such as interrupt response, context switching, and software configuration, bringing the data bus utilization close to its theoretical limit and achieving higher data throughput. In addition, this invention enhances the system's flexibility and scalability. Since the data source is located in a large-capacity system memory, the system can flexibly generate very long or very complex waveforms and easily update waveform data without resynthesizing the FPGA logic. For example, this invention can be combined with the LOCATA pseudo-satellite positioning system to ensure strict continuity of the transmitted navigation signal in the time domain, thereby preventing the receiver from losing lock due to phase jumps and supporting centimeter-level high-precision positioning. The generated satellite navigation signal is transmitted in the L1 band through the AD9361 RF front-end. Testing has verified that the signal spectrum is stable and the code phase is accurate. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the continuous waveform data generation system based on a heterogeneous computing platform in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the programmable logic (PL) structure in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the DMA controller in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the state transition of the hardware state machine in Embodiment 1 of the present invention; Figure 5 The diagram shows the data path correctness verification results of the signal generated by the method of the present invention. It shows the signal waveform captured by the on-chip logic analyzer (ILA) in a single trigger. The horizontal axis is time [ns] and the vertical axis is the signal amplitude. Figure 6 The diagram shows the verification results of the data path correctness of the signal generated by the method of this invention. The diagram shows the overall signal waveform captured by the on-chip logic analyzer (ILA) after multiple triggers; the horizontal axis represents time [ns], and the vertical axis represents signal amplitude; labels 1 and 2 represent the transmitted modulated wave, and labels 3 and 4 represent the received modulated wave; Figure 7 The diagram shows the data path correctness verification results of the signal generated by the method of the present invention, which shows the signal waveform of the on-chip logic analyzer (ILA) cyclically transmitting and receiving; the horizontal axis is time [ns], and the vertical axis is the data value [0-15]. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 As shown in the figure, this embodiment describes a continuous waveform data generation system based on a heterogeneous computing platform, which is applied to the design of a pseudo-satellite positioning base station for the LOCATA system based on ZYNQ.

[0013] Specifically, the continuous waveform data generation system in this embodiment includes a heterogeneous computing platform integrating a processor system (PS) and a programmable logic system (PL), namely a system-on-a-chip (SoC).

[0014] The processor system PS is equipped with a hard-core ARM architecture processor. The processor system includes an ARM processor and a system memory DDR SDRAM that is connected to the processor at high speed.

[0015] The system memory DDR SDRAM is used to store one or more waveform data blocks to be generated.

[0016] In this embodiment, these waveform data blocks are pre-generated navigation messages.

[0017] In this embodiment, the programmable logic PL is an FPGA (Field Programmable Gate Array) logic array.

[0018] Design a custom DMA controller within the programmable logic (PL) to implement a hardware-autonomous, seamless cyclic read mechanism from large-capacity DDR memory, thereby generating a truly continuous data stream.

[0019] Conventional DMA is based on a descriptor linked list, requiring processor interrupt intervention after each block transfer, resulting in microsecond / millisecond gaps and CPU resource consumption. The key difference between this and conventional DMA controllers is that the customized DMA controller in this invention uses one-time configuration and a hardware state machine for autonomous looping, eliminating the need for further processor intervention and achieving seamless nanosecond-level data stream transmission. It is particularly suitable for the continuous generation of pseudo-satellite navigation signals (such as supporting C / A code at 10.23MHz and TDMA time hopping).

[0020] In addition, the PL also includes a downstream signal processing module and an RF interface connected to the downstream signal processing module. The downstream signal processing module is a pseudo-satellite navigation signal baseband generation module, which is used to generate navigation baseband signals.

[0021] The radio frequency interface is used to transmit signals (i.e., navigation baseband signals), such as... Figure 1 As shown.

[0022] Figure 2 This is a block diagram of the overall hardware implementation design of the continuous waveform data generation system of the present invention. Figure 2 The diagram illustrates the programmable logic (PL) portion of a heterogeneous computing platform (ZYNQ). The figure shows the custom DMA controller read / write modules (axi_dma_rd, axi_dma_wr), as well as the downstream signal generation module Gnss_gen and the modulation module BPSK.

[0023] The processor system PS connects to the downstream signal generation module Gnss_gen, the modulation module BPSK, and the core axi_dma_rd module in the PL via the AXI-Lite configuration bus for parameter configuration and control.

[0024] like Figure 3 As shown, the customized DMA controller in this embodiment includes a configuration register group, a data path module, an address counter, a hardware state machine, a first-in-first-out (FIFO) buffer, a configuration bus, and a streaming output interface.

[0025] During the configuration phase, the configuration bus transmits the processor system's configuration commands to the configuration register set.

[0026] During the data transmission phase, the hardware state machine drives the data path module to read data from the system memory DDR SDRAM. An address counter maintains the address, which is then buffered in a FIFO and output to the downstream signal processing module via a streaming interface.

[0027] The functions of each part in the custom DMA controller are as follows: The configuration register set is used to receive configuration commands from the processor system and to store configuration information. This configuration information is written to the configuration register set during the configuration phase and read by the hardware state machine during the data transmission phase.

[0028] The configuration information includes at least: the 64-bit physical start address of the data to be read in the system memory, the 32-bit data block length value, the cycle enable flag used to indicate the working mode, the frequency control word, the PRN sequence number, and the end address.

[0029] The frequency control word is used for DDS carrier generation, supporting the L1 band at 1575.42MHz; the PRN sequence number is used for pseudo-random code generation, supporting multiple CDMA / TDMA signals; the end address is used to define the cycle boundary, supporting the time hopping table mechanism.

[0030] The configuration register set is written during the configuration phase and read by the hardware state machine during the data transfer phase.

[0031] The configuration register set includes: A source address register is used to store the physical starting address (64 bits) in system memory; this physical starting address is written during the configuration phase and used to initialize the address counter during the data transfer phase. A transfer length register is used to define the data block size (32 bits) and control the amount of data read during the data transfer phase; A control register containing a start bit, a cycle enable flag, a frequency control word, and a PRN sequence number is used to start data transmission, control the cycle, and adjust signal parameters such as frequency, power, and pseudocode. It also includes a status register containing a busy flag, an end address register, and an error flag, used to report the status and support the TDMA time-hopping mechanism (refer to the time-hopping table, duty cycle 10%). The frequency control word (Freqword_tx, 32 bits) is used to control the DDS carrier frequency, supporting the L1 band at 1575.42MHz. The PRN sequence number is used for pseudo-random code C / A generation, supporting C / A code rate of 10.23MHz and multiple CDMA signals.

[0032] The end address register (32-bit) is used to define the end address of the read operation and supports continuous looping.

[0033] Error flags are used to report clock synchronization or transmission errors, such as clock synchronization failure.

[0034] The source address register is used to store the physical starting address in system memory; it is used to write configuration information during the configuration phase and to initialize the address counter to the physical starting address in system memory during the data transfer phase.

[0035] The transfer length register is used to define the data block size and control the amount of data read during the data transfer phase.

[0036] The control register is used to start the transmission and control the loop. In step 2 of the following embodiment 2, the start command is written, and in step 4 of the following embodiment 2, the loop enable flag status is checked.

[0037] The status register is used to report the status to the processor system. The status is updated after each data block transfer is completed. The reported status includes two states: completed or busy.

[0038] The data path module is used to read data from system memory and perform read operations during the data transmission phase.

[0039] The address counter is used to generate the read address. It is reset after each data block is read. Specifically, if the cycle enable flag is enabled, the hardware state machine resets the address counter to the physical starting address in system memory.

[0040] The address counter supports end address comparison. When the read address reaches the end address, it is reset in combination with the cycle enable flag and PRN number to adapt to the periodic playback requirements of pseudo-satellite navigation messages.

[0041] A hardware state machine is used to resolve a cyclic enable flag in the configuration register group and thereby enable hardware autonomous cyclic reading of specified data blocks in system memory, so that no repeated intervention from the processor system is required after startup.

[0042] A hardware state machine must contain at least the following five states: The states are: Idle (IDLE), Configuration Read (CONFIG_READ), Data Transfer (DATA_TRANSFER), Loop Check (CHECK_LOOP), and Clock Synchronization Check / Error Handling.

[0043] Synchronization check / error handling status is used to verify that the DDS clock is synchronized with the RF front end (AD9361) and enters error handling status when the error flag is triggered (reporting transmission interruption, supporting real-time spread spectrum modulation of pseudo-satellite signals).

[0044] If the error flag is triggered, the status register is reported and the transmission is reset, supporting real-time processing of pseudo-satellite navigation signals.

[0045] The FIFO buffer is located between the memory read path and the streaming output path, such as... Figure 3 As shown, the FIFO buffer is used to handle clock domain crossover and bus access latency on the data path, ensuring a smooth and stable output data stream.

[0046] like Figure 4 As shown, the control logic of the hardware state machine design is: After startup, it first enters the CONFIG_READ state from the IDLE state to read the configuration state; Then it enters the DATA_TRANSFER state and reads data blocks from system memory; After the data block is read, it enters the CHECK_LOOP state and checks the loop enable flag (the flag is set in a fixed position during the configuration phase and is used for subsequent loop checks). If enabled, the address counter is reset (back to the starting address) and the transfer is returned; otherwise, it stops. If a clock missynchronization or error is detected, the system enters error handling mode, reports the status register, and optionally restarts the configuration. After completing the transfer of a data block, the hardware state machine enters the CHECK_LOOP state and decides whether to return to the data transfer state or enter the idle state based on the loop enable flag.

[0047] The working principle of the customized DMA controller in this embodiment is as follows: Autonomous cyclic reading is achieved through a hardware state machine, without the need for processor intervention.

[0048] During the configuration phase, the hardware state machine enters the CONFIG_READ state to read the configuration register group; during the transfer phase, it enters the DATA_TRANSFER state to drive the data path channel and read data blocks from system memory.

[0049] After the data block is read, the hardware state machine enters the CHECK_LOOP state, checks the loop enable flag, and if the flag is enabled, resets the address counter and returns to the data transfer state; otherwise, it stops.

[0050] If the cycle enable flag is 1, it means the cycle is enabled; if the cycle enable flag is 0, it means the cycle is disabled.

[0051] First, the processor system PS performs a one-time initialization configuration of the custom DMA controller, which is a "fire-and-forget" configuration.

[0052] This design contrasts sharply with the repetitive configuration required by conventional DMA, ensuring an uninterrupted data flow.

[0053] The starting address of the data in system memory, the total length of the data block to be transferred in a loop, and the loop enable flag used to activate the loop mode are written to the configuration register group of the custom DMA controller via the configuration bus.

[0054] Secondly, after completing the configuration, the processor system (PS) sends a simple start command. From then on, control of data transmission is completely transferred to the hardware logic in the programmable logic (PL), without the need for secondary intervention from the processor system (PS).

[0055] Upon receiving the start command, the hardware state machine inside the custom DMA controller begins driving its data path to read data from system memory. Once it has precisely read a data block of a preset length, the hardware state machine does not stop or request an interrupt; instead, it immediately checks the previously configured cyclic enable flag.

[0056] If the flag is valid, the hardware state machine will automatically and instantaneously reset the internal address counter to the physical starting address in the initially configured system memory, and then seamlessly begin reading data for the next data cycle.

[0057] Because the "check-reset-restart" process performed by the hardware state machine is completed entirely by the hardware within nanoseconds (ns), it is transparent and uninterrupted to the external data stream.

[0058] The final customized DMA controller continuously provides a smooth, continuous data stream to the downstream signal processing module for real-time processing through its streaming output port. The streaming protocol interface is the AXI-Stream bus protocol interface.

[0059] The difference between this invention and a conventional DMA controller lies in the fact that conventional DMA relies on descriptor lists and interrupt mechanisms. After each transfer, the PS terminal needs to respond and reconfigure, causing delays and gaps. This invention only requires writing to the register group once during the configuration phase. The hardware state machine then autonomously handles the loop checks and resets, achieving nanosecond-level seamless transmission. It is particularly suitable for generating continuous waveforms such as the LOCTA pseudo-satellite signal (supporting TDMA time-hopping and BPSK modulation).

[0060] The downstream signal processing module performs real-time digital signal processing based on the received continuous data stream to generate the target waveform signal.

[0061] Specifically, in this embodiment, the downstream signal processing module is a pseudo-satellite navigation signal baseband generation module. The downstream signal processing module has a built-in BPSK modulator, which is used to perform binary phase shift keying modulation.

[0062] The difference between this invention and ordinary DMA controllers (such as the standard AXI DMA IP) is that this invention introduces a hardware autonomous loop mechanism and a one-time configuration strategy through a customized DMA controller, which completely eliminates the problems of frequent processor intervention and transmission gaps.

[0063] Traditional DMA relies on descriptor lists and interrupt mechanisms, resulting in high CPU overhead and latency. This invention's hardware state machine achieves nanosecond-level seamless reset and supports continuous waveform generation, significantly improving real-time performance and efficiency.

[0064] The pseudo-satellite navigation signal baseband generation module can receive the continuous data stream as navigation messages.

[0065] The baseband generation module generates a corresponding pseudo-random code based on the configured PRN sequence number, and performs spread spectrum modulation and BPSK carrier modulation on the navigation message and pseudo-random code to generate a navigation baseband signal that conforms to the LOCATA or GNSS standard.

[0066] The generated navigation baseband signal is transmitted through the radio frequency interface, such as... Figure 1 As shown.

[0067] The continuous waveform data generation system described in this invention enables efficient, continuous, and uninterrupted data stream transmission from large-capacity dynamic memory to the programmable logic area through a custom DMA controller deployed within the programmable logic.

[0068] Example 2 This embodiment 2 describes a method for generating continuous waveform data based on a heterogeneous computing platform. This method is implemented based on the continuous waveform data generation system based on a heterogeneous computing platform in embodiment 1.

[0069] A method for generating continuous waveform data based on a heterogeneous computing platform includes the following steps: Step 1. The processor system configures the custom DMA controller once via a configuration bus.

[0070] The configuration information includes the physical starting address of the data to be read in the 64-bit system memory, a 32-bit data block length value, and a cyclic enable flag to indicate the working mode.

[0071] In this embodiment, the configuration bus preferably uses the AXI-Lite protocol bus.

[0072] Step 2. After the processor system completes the configuration, it writes a start command to the control register to activate data transmission.

[0073] Step 3. After detecting the start command, the hardware state machine drives the data path module to automatically read a complete data block from the system memory according to the configured physical start address and data block length in the system memory.

[0074] Step 4. After completing the read operation of a data block, the hardware state machine automatically checks the state of the cycle enable flag.

[0075] If the loop enable flag is enabled, the hardware state machine automatically resets the internal address counter to the physical starting address in the system memory and seamlessly switches states to repeat step 3, forming a continuous loop of data read operations.

[0076] If the state is disabled, it means that cyclic reading is not required (e.g., in a single transmission scenario). In this case, the hardware state machine will transition to the stop state after completing the reading of the current data block and report the transmission completion to the processor system through the status register.

[0077] This invention enables continuous, cyclical data reading operations without any further intervention from the processor system.

[0078] Step 5. During continuous data reading, the customized DMA controller outputs the continuously read data to the downstream signal processing module deployed in the programmable logic in real time and without interruption through a streaming protocol interface.

[0079] Step 6. The downstream signal processing module processes the received data and transmits the processed target waveform signal through the RF front-end. Specifically, the downstream signal processing module receives a continuous data stream as a navigation message, generates a corresponding pseudo-random code based on the configured PRN sequence number, performs spread spectrum modulation and BPSK carrier modulation on the navigation message and pseudo-random code, generates a navigation baseband signal conforming to the LOCATA or GNSS standard, and transmits it through the RF front-end (such as AD9361).

[0080] The DMA controller does not receive all the data at once and then transmit it. Instead, it transmits the data to the downstream signal processing module through the streaming interface every time it reads a data unit (such as a byte or word), ensuring real-time continuous output.

[0081] In addition, to verify the effectiveness of the method of the present invention, the following specific experiments are also given.

[0082] First, the software on the PS side performs a one-time initialization configuration of the custom DMA controller.

[0083] Specifically, the software of the processor system PS first prepares the waveform data to be transmitted in a loop in the system memory DDR SDRAM, such as a complete navigation message data block.

[0084] Subsequently, the processor system PS performs a fire-and-forget configuration of the custom DMA controller (axi_dma_rd) via the AXI-Lite bus.

[0085] Configuration information is written to the configuration register set inside the custom DMA controller. The configuration information includes at least: the 64-bit physical start address of the data in system memory, the 32-bit length value of the data block, a cyclic enable flag for activating the cyclic mode (indicating the operating mode), and the frequency control word and PRN sequence number for pseudosatellite applications.

[0086] Secondly, after completing the configuration, a simple start command is sent to initiate the autonomous transmission of the hardware state machine.

[0087] Specifically, after the processor system (PS) completes its configuration, it writes a start command to a control register of the custom DMA controller (axi_dma_rd). From then on, control over data transfer is completely handed over to the hardware logic in the programmable logic (PL) for autonomous execution, and the processor system (PS) no longer needs to intervene.

[0088] The core of this invention lies in the internal design of the axi_dma_rd module, whose internal structure is as follows: Figure 3 As shown, its control core is a hardware state machine, and the workflow of this state machine is as follows: Figure 4 As shown, when the hardware state machine of axi_dma_rd detects the start command, it will transition from the idle state (IDLE) to the data transfer state (DATA_TRANSFER).

[0089] In this state, it drives its internal data path module according to the configuration register set (such as...). Figure 3 The starting address and length information stored in the memory are used to read a complete data block from the system memory through its AXI main interface.

[0090] The key seamless looping mechanism of the custom DMA controller in this embodiment is that after a data block is read, the hardware state machine does not stop or request an interrupt, but automatically enters a looping check state.

[0091] In cyclic check mode, the hardware state machine checks the cyclic enable flag in the configuration register set.

[0092] If the flag is enabled, the hardware state machine will instantly drive the address counter to reset to the initial physical starting address in the system memory, and seamlessly switch back to the data transfer state to immediately begin reading the next data block.

[0093] This "check-reset-reboot" process is entirely autonomously completed by the hardware at the nanosecond (ns) level, and is transparent and uninterrupted to the external data stream, thus ensuring the seamless continuity of the output data stream.

[0094] If the flag is disabled, it means that only a single transfer is required. After the hardware state machine finishes reading the current data block, it will transition to the idle state and report the transfer completion to the PS through the status register.

[0095] Ultimately, the custom DMA controller smooths the continuously read data through its internal FIFO buffer (used to handle clock domain crossover and bus delay) to form a smooth, continuous data stream, which is then continuously output to the downstream signal processing module through a streaming output interface (AXI-Stream bus protocol interface).

[0096] The downstream signal processing module Gnss_gen receives the continuous data stream (navigation message) and performs real-time spread spectrum processing on it with a locally generated pseudo-random code. The processed signal is then sent to a BPSK modulator for binary phase-shift keying modulation. The final target waveform signal is then transmitted through the radio frequency front-end (i.e., Figure 1 It is transmitted through the radio frequency interface in the middle.

[0097] Because there are no transmission gaps, the signal transmitted by the AD9361 is a perfectly continuous wave in the time domain, and the receiver can stably lock onto the signal. Figure 5 , Figure 6 and Figure 7 This is a verification result of the effectiveness of the continuous data path constructed by the present invention.

[0098] In this test, the continuous waveform data generation system was configured to cyclically transmit and receive a simple data sequence (0-15).

[0099] Waveforms captured by the on-chip logic analyzer ILA are shown below: Figure 5 shows the signal waveform captured by a single trigger, where the horizontal axis represents time [ns] and the vertical axis represents the signal amplitude. As can be seen from Figure 5, the waveform shows that the initial part of the data stream is continuous and without gaps.

[0100] Figure 6 shows the overall signal waveform captured by multiple triggers. The horizontal axis represents time [ns], and the vertical axis represents the signal amplitude. Labels 1 and 2 represent the transmitted modulated wave [continuous rising / falling edges], and labels 3 and 4 represent the received modulated wave [stable loop response].

[0101] Depend on Figure 6It can be seen that after adopting the method of the present invention, the signal is stably transmitted and received for a long time without any gaps caused by software intervention, thus proving the continuity of the transmitted modulated wave and the stable response of the received modulated wave.

[0102] Figure 7 The waveforms of the cyclically transmitted and received signals are shown, with the horizontal axis representing time [ns] and the vertical axis representing data values ​​[0-15]. (See attached image.) Figure 7 The accuracy of the data content was effectively verified, and the loop boundaries were seamlessly connected.

[0103] The test results demonstrate that the continuous data path constructed by this invention, driven by a custom DMA, is stable and reliable, which is a prerequisite for generating continuous waveforms. This invention cleverly solves the technical problem faced by heterogeneous computing platforms in generating continuous real-time signal streams by designing a custom DMA controller with hardware autonomous looping functionality within a programmable logic (PL). It has passed hardware testing and verification, thus possessing extremely high industrial practical value.

[0104] This invention, combined with the LOCATA pseudo-satellite positioning system, achieves efficient, continuous, and uninterrupted data stream transmission from system memory to programmable logic. It supports TDMA / CDMA signal formats, PRN code generation, and BPSK modulation, and can be applied to various modern electronic systems with extremely high requirements for real-time signal generation, continuity, and time accuracy, such as pseudo-satellite navigation base station design. It realizes efficient, continuous, and uninterrupted data stream transmission from large-capacity dynamic memory to programmable logic area.

[0105] The method of the present invention effectively solves the latency and system overhead problems caused by the need for frequent processor intervention of the standard direct memory access (DMA) controller when generating continuous high-speed data streams on a system-on-a-chip (SoC).

[0106] Example 3 This embodiment 3 describes a pseudo-satellite positioning base station, which uses the continuous waveform data generation system in embodiment 1 above to generate navigation baseband signals that conform to the LOCATA or GNSS standards.

[0107] Of course, the above description is only a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. It should be noted that any equivalent substitutions or obvious modifications made by those skilled in the art under the guidance of this specification fall within the scope of this specification and should be protected by the present invention.

Claims

1. A continuous waveform data generation system based on a heterogeneous computing platform, suitable for navigation baseband signal generation, comprising a heterogeneous computing platform integrating a processor system and programmable logic; characterized in that, The processor system has system memory for storing one or more waveform data blocks to be generated; The programmable logic incorporates a custom DMA controller and a downstream signal processing module, namely the pseudo-satellite navigation signal baseband generation module, which is used to receive continuous data streams as navigation messages and generate navigation baseband signals. A custom DMA controller is used to receive configuration commands from the processor system and access system memory. The custom DMA controller includes a hardware state machine, a configuration register set, an address counter, and a data path module. The configuration register group is used to store configuration information, including: The source address register is used to store the physical starting address in system memory; The transfer length register is used to define the data block size; The control register, which includes a start bit, a cycle enable flag, a frequency control word, and a PRN sequence number, is used to start data transmission, control the cycle, and adjust signal parameters. And a status register, which includes a busy flag, an end address register, and an error flag, used to report the status; The hardware state machine is used to parse the configuration cycle enable flag to enable hardware autonomous cyclic reading of specified data blocks in system memory. It includes idle state, read configuration state, data transfer state and cycle check state. After completing the transmission of a data block, the hardware state machine enters a loop check state and, based on the loop enable flag in the control register, decides whether to return to the data transmission state or enter the idle state. The data input terminal of the downstream signal processing module is connected to the output terminal of the custom DMA controller; The operation of the customized DMA controller is as follows: The custom DMA controller achieves autonomous cyclic reading through a hardware state machine, without the need for processor system intervention; During the configuration phase, the hardware state machine enters the read configuration state to read the configuration register group; during the data transmission phase, the hardware state machine enters the data transmission state and drives the data path module to read data blocks from system memory. After the data block is read, the hardware state machine checks the state of the cycle enable flag in the control register; if the cycle enable flag is enabled, the address counter is reset and the data transmission state is returned; otherwise, the process stops. The hardware state machine also includes a clock synchronization check / error handling state, which is used to verify that the DDS clock is synchronized with the RF front end, and enters the error handling state when the error flag is triggered. The customized DMA controller continuously reads data from the system memory and outputs it in real time and without interruption to the downstream signal processing module deployed in the programmable logic through a streaming protocol interface. The downstream signal processing module performs real-time digital signal processing on the received data to generate the target waveform signal; The streaming protocol interface is the AXI-Stream bus protocol interface; the processor system configures the custom DMA controller once through a configuration bus, which is the AXI-Lite protocol bus.

2. The continuous waveform data generation system based on a heterogeneous computing platform according to claim 1, characterized in that, The configuration information is written into the configuration register group during the configuration phase and read by the hardware state machine during the data transmission phase. The configuration information includes the physical start address of the data to be read in the system memory, the data block length value, the cyclic enable flag indicating the working mode, and the frequency control word, PRN sequence number, and end address for pseudo-satellite applications. The frequency control word is used for DDS carrier generation; the PRN sequence number is used to generate pseudo-random codes that distinguish different base stations; and the end address is used to define the loop boundary and support the TDMA time hopping table mechanism of the pseudo-satellite system.

3. The continuous waveform data generation system based on a heterogeneous computing platform according to claim 1, characterized in that, The address counter is used to maintain the read address; after each data block is read, if the loop enable flag is enabled, the address counter is reset to the physical starting address in the system memory. The address counter supports end address comparison. When the read address reaches the end address, it is reset in combination with the cycle enable flag to adapt to the periodic playback requirements of pseudo-satellite navigation messages. The data path module is used to read data from system memory and performs read operations during the data transmission phase.

4. The continuous waveform data generation system based on a heterogeneous computing platform according to claim 1, characterized in that, The custom DMA controller also includes a first-in-first-out (FIFO) buffer located between the memory read path and the streaming output path to handle clock domain crossover and bus access latency on the data path.

5. A continuous waveform data generation system based on a heterogeneous computing platform according to claim 1, characterized in that, The heterogeneous computing platform is a system-on-a-chip; the processor built into the processor system is an ARM architecture hard-core processor; the programmable logic is an FPGA logic array; and the system memory is DDR SDRAM.

6. The continuous waveform data generation system based on a heterogeneous computing platform according to claim 1, characterized in that, The downstream signal processing module receives a continuous data stream as a navigation message, generates a corresponding pseudo-random code according to the configured PRN sequence number, and performs spread spectrum modulation and BPSK carrier modulation on the navigation message and the pseudo-random code to generate a navigation baseband signal.

7. A method for generating continuous waveform data based on a heterogeneous computing platform, comprising the continuous waveform data generation system based on a heterogeneous computing platform as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Step 1. The processor system performs a one-time configuration of the custom DMA controller via a configuration bus; The configuration information includes the physical start address of the data to be read in the system memory, a data block length value, a cycle enable flag indicating the working mode, a frequency control word, a PRN sequence number, and an end address; Step 2. After completing the configuration, the processor system writes a start command to the control register to activate data transmission; Step 3. After detecting the start command, the hardware state machine drives the data path module to automatically read a complete data block from the system memory according to the configured physical start address and data block length in the system memory; Step 4. After completing the read operation of a data block, the hardware state machine automatically checks the state of the cycle enable flag; If it is in the enabled state, the hardware state machine automatically resets the internal address counter to the physical starting address in the system memory and seamlessly changes the state to repeat step 3, forming a continuous loop of data read operations without the need for processor system intervention. If the state is disabled, the hardware state machine will transition to the stop state after completing the reading of the current data block and report the transmission completion to the processor system through the status register, without requiring further processing. Step 5. During continuous data reading, the customized DMA controller outputs the continuously read data to the downstream signal processing module deployed in the programmable logic in real time and without interruption through a streaming protocol interface; The downstream signal processing module receives a continuous data stream as a navigation message, generates a corresponding pseudo-random code based on the configured PRN sequence number, and performs spread spectrum modulation and BPSK carrier modulation on the navigation message and pseudo-random code to generate a navigation baseband signal.

8. A pseudo-satellite positioning base station, characterized in that, The continuous waveform data generation system based on a heterogeneous computing platform as described in any one of claims 1 to 6 is used to generate navigation baseband signals that conform to the LOCATA or GNSS standards.

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