Graphical Reverse Analysis and Automatic Reconfiguration Method for PLC Logic in Old Machine Tools

Abstract

This application provides a graphical reverse analysis and automatic reconfiguration method for PLC logic in old machine tools, relating to the field of industrial control technology. The method includes the following steps: obtaining the ladder diagram program file of the original CNC system through a hardware interface; standardizing the format of the ladder diagram program file to generate a unified intermediate representation structure; parsing the connection relationships of each contact, coil, timer, and counter in the intermediate representation structure, constructing a directed hypergraph and labeling the type and timing attributes of each component node; identifying the timing logic chain in the intermediate representation structure and extracting timing constraints; automatically identifying and labeling the safety logic blocks in the directed hypergraph based on a preset safety logic pattern library using a graph pattern matching algorithm; and generating the reconfigured PLC program based on the labeled directed hypergraph and timing constraints, combined with the programming model of the target PLC system.

Description

Technical Field

[0001] This invention belongs to the field of industrial control technology, specifically relating to a graphical reverse analysis and automatic reconfiguration method for the PLC logic of old machine tools. Background Technology

[0002] After long-term service, old CNC machine tools generally suffer from hardware aging and discontinued spare parts, making it urgent to upgrade their control systems. In existing upgrade technologies, the migration of PLC logic mainly relies on manual methods: engineers read through the ladder diagram program of the original system line by line, understand its control logic based on experience, and then reprogram it on the new system.

[0003] However, non-standard programming structures are widespread in ladder logic programs—for example, using a "timer coil + self-holding circuit" to simulate timing functions, using long-chain intermediate relays to achieve implicit interlocking, and employing a dual-coil structure that drives the same output point from multiple locations. These non-standard structures are particularly common in older PLC programs, but the programming specifications and instruction sets of different PLC brands differ, making it difficult to accurately identify the true semantics of these non-standard structures during manual analysis. They are often misunderstood as ordinary logic, leading to functional errors or loss of safety logic in the refactored program.

[0004] Therefore, how to automatically identify and correctly parse the non-standard programming structure in the ladder diagram of old PLCs, and ensure that the reconstructed program is semantically equivalent to the original program, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the existing technology, a graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools is provided, including the following steps: The ladder diagram program file of the original CNC system is obtained through a hardware interface, and the ladder diagram program file is processed to standardize the format to generate a unified intermediate representation structure. The connection relationships of each contact, coil, timer, and counter in the intermediate representation structure are analyzed to construct a directed hypergraph G=(V, E); where V represents a component node and E represents a signal flow dependency edge; and the type and timing attributes of each component node are labeled. Identify the timing logic chain in the intermediate representation structure and extract the timing constraint relationship T={(v i , v j , type, delay)};where, v i and v j For component nodes, type indicates the constraint type, and delay indicates the delay time; Based on a pre-defined safety logic pattern library, a graph pattern matching algorithm is used to automatically identify and label safety logic blocks in a directed hypergraph G. Based on the labeled directed hypergraph G and timing constraint relationships T, combined with the programming model of the target PLC system, a reconstructed PLC program is generated.

[0006] According to the technical solution provided in this application, the construction of the directed hypergraph G=(V,E) includes the following steps: Traverse the intermediate representation structure, identify all coil elements that are repeatedly assigned values, and construct a double-coil collision set C = {c1, c2, …, c k}, where each double-coil collision set c i For the same physical output address, there is a set of all logical blocks that drive that physical output address; For each double-coil collision set c i By analyzing the path reachability in the directed hypergraph G, the collision set c of the two coils is determined. i The timing mutual exclusion relationships between the included drive branches: If path reachability analysis determines that each driving branch has interlocking constraints in its logical structure, then the conflict set c is... i It is labeled as a decoupled dual coil and a merged logic tree is generated to merge multiple drive branches into a single logic output; If path reachability analysis determines that there are no interlocking constraints in the logical structure of each driving branch, then the conflict set c is... i The double coil is marked as a risky type, triggering a user alert, and is also represented as the double coil collision set c in the directed hypergraph G. i A mutual exclusion protection logic block is inserted before the corresponding physical output address node. The mutual exclusion protection logic block is used to ensure that only one drive branch can be turned on at any given time.

[0007] According to the technical solution provided in this application, the construction of the directed hypergraph G=(V, E) includes the following steps: Analyze the long chain interlocking paths indirectly formed by multiple intermediate relays in the directed hypergraph G, and identify the implicit interlocking structures that meet the following conditions: there are at least two signal flow paths that are not directly related to each other, each path passes through at least two intermediate relay nodes and finally converges to the same coil node, and the interruption of any signal flow path causes the coil node to lose power. The implicit interlocking structure is extracted from the distributed node relationship to generate an explicit interlocking logic block, and a virtual interlocking node is added to the directed hypergraph G. The virtual interlocking node replaces the original multiple distributed interlocking paths, so that the implicit interlocking structure maintains topological integrity during the reconstruction process. Simultaneously, the original intermediate relay node information of each path in the explicit interlock logic block is recorded as a traceability annotation for the reconstructed program.

[0008] According to the technical solution provided in this application, the step of annotating the type and timing attributes of each component node includes the following steps: Identify the non-standard timer structure in the intermediate representation structure. The non-standard timer structure includes: a timer coil node, a relay node connected in parallel with the timer coil node to form a self-holding path, and an output node controlled by the normally open contact of the timer coil node. The timer coil node and the relay node form a closed loop, so that the timer coil node is continuously energized through the self-holding of the relay node after being turned on. The normally open contact of the timer coil node closes after a preset delay, triggering the output node. The intermediate representation structure is pattern matched using a preset topological feature template to identify non-standard timer structures that conform to the above structure, and the preset delay value of the timer coil node is extracted. The identified non-standard timer structures are labeled as semantic restoration timer types, the preset delay value is recorded in the timing attributes, and the relay nodes are marked as redundant nodes, which are omitted when generating the reconstructed PLC program.

[0009] According to the technical solution provided in this application, the annotation of the type and timing attributes of each component node V includes the following steps: Traverse all input nodes in the intermediate representation structure and filter out candidate signal nodes related to mechanical wear state based on the signal change characteristics of each input node; According to the preset wear signal identification rules, the candidate signal nodes are classified and determined to identify the wear signal type of each candidate signal node; The input nodes that are identified as wear signals are marked with wear association attributes in the directed hypergraph G, and the corresponding wear signal type identifier is recorded in the node attributes; Tracing downstream along the signal flow dependency edge E in the directed hypergraph G, identify the coil nodes controlled by each wear signal node, and establish the coupling association path between the wear signal node and the coil node; The coupling association path is recorded in key-value pair form to generate a coupling mapping table. The coupling mapping table is used to reserve a communication interface between the wear signal node and the external compensation module when generating the reconstructed PLC program.

[0010] According to the technical solution provided in this application, the step of classifying and determining the wear signal type of each candidate signal node according to a preset wear signal identification rule includes the following steps: Obtain the signal change records of each candidate signal node and extract the number of state flips for each candidate signal node per unit time. Candidate signal nodes whose state flip count exceeds a preset threshold are marked as nodes to be classified; For each node to be classified, perform at least one of the following classification decisions: If the node to be classified is a digital input node and its pulse width is less than the minimum action response time of the corresponding mechanical switch, then the node is determined to be a contact oxidation wear signal. If the output address corresponding to the node to be classified is an overload protection signal, and the trigger frequency of the node exceeds a preset frequency threshold, then the node is determined to be a gap overload type wear signal. If the node to be classified is a position feedback signal node, and there is a periodic fluctuation component in its pulse sequence, then the node is determined to be a lead screw wear signal. The determination result is recorded in the node attributes as the wear signal type identifier.

[0011] According to the technical solution provided in this application, after constructing the directed hypergraph G=(V, E), the following steps are also included: Iterate through all component nodes in the directed hypergraph, and for each component node v i Perform the following operations: With component node v i Starting from the signal flow dependent edge E, a depth-first search is performed. If no coil node is found, the element node v is marked. i There are no output nodes in the positive direction; With component node v i Starting from the endpoint, perform a depth-first search along the reverse direction of the signal flow dependent edge E. If no input node or constantly powered input node can be found, then mark the element node v. i For reverse no-input nodes; The element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction i It was determined to be an isolated node; Remove isolated nodes and their associated signal flow dependent edges E from the directed hypergraph G.

[0012] According to the technical solution provided in this application, the element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction will be... i After a node is determined to be isolated, before deleting the isolated node and its associated signal flow dependent edge E from the directed hypergraph G, the following steps are also included: For each component node v that simultaneously satisfies the conditions of no output node in the forward direction and no input node in the reverse direction i Execute path duplicate detection: With component node v i Starting from the signal flow dependent edge E, perform a depth-first search along the positive direction and record the sequence of all nodes traversed during the search process; If, during the search process, after passing through at least three different intermediate relay nodes, the search returns to the element node v... i Then determine v i It belongs to the ring self-locking node, and the ring self-locking node is excluded from the isolated node.

[0013] According to the technical solution provided in this application, the method for each dual-coil collision set c i By analyzing the path reachability in the directed hypergraph G, the collision set c of the two coils is determined. i The timing mutual exclusion relationships between the included drive branches include the following steps: For the two-coil collision set c i Each pair of drive branches, including a first branch and a second branch, performs the following operations: Obtain the output node of the last control element in the first branch, and obtain the output node of the last control element in the second branch; In a directed hypergraph G, starting from two output nodes respectively, a search is performed along the positive direction of the signal flow dependent edge E. If the two search paths eventually converge at the same interlocked relay node, and the state change of the interlocked relay node can cut off the conduction condition of one of the branches, then it is determined that the first branch and the second branch have interlocking constraints in their logical structure. If all drive branches have interlocking constraints between each other, then the dual-coil conflict set c is determined. i Each driving branch contained herein has interlocking constraints in its logical structure; otherwise, it is determined that there are no interlocking constraints.

[0014] According to the technical solution provided in this application, after excluding the ring-shaped self-locking node from the isolated node, the method further includes the following steps: The excluded ring-shaped self-locking nodes are marked as ring-shaped self-locking structures in the directed hypergraph G; Preserve the ring-locked node and all its associated signal flow dependent edges E; When generating the reconstructed PLC program, nodes marked as ring self-locking structures are converted into their equivalent oscillation circuits or interlocking holding circuits.

[0015] Compared with the prior art, the beneficial effects of this application are as follows: First, this application achieves automated semantic recognition of non-standard programming structures. Older PLC ladder diagrams widely contain non-standard structures such as "timer coil + self-holding circuit" simulating timing functions, dual-coil structures driving the same output point from multiple locations, and implicit interlocking implemented through long-chain intermediate relays. These structures are easily misinterpreted during manual analysis. This application constructs a directed hypergraph G=(V, E) to structure the ladder diagram into a graph model. Combined with preset topological feature templates for pattern matching, it automatically identifies the aforementioned non-standard structures and parses their true semantics, ensuring that the reconstructed PLC program is functionally strictly equivalent to the original program.

[0016] Second, it ensures the complete preservation of timing logic and security logic. Timing dependencies (such as sequential start-up and delay protection) and security logic (such as emergency stop chains and limit protection) are often scattered across multiple network segments in ladder diagrams, making it difficult to fully capture them manually. This application extracts timing constraints to explicitly represent timing semantics, and simultaneously uses a pre-defined security logic pattern library to automatically identify and label security logic blocks through graph pattern matching algorithms, ensuring that both timing relationships and security logic are completely preserved during the reconstruction process.

[0017] Third, it significantly improves the efficiency and reliability of the transformation. Traditional manual parsing and rewriting methods may take 2-4 weeks, and the results vary from person to person. This application compresses the PLC logic migration process to a few hours, and the parsing results are deterministic and repeatable. The reconstructed program is superior to the manual solution in terms of functional equivalence, timing correctness, and safety integrity.

[0018] In summary, this invention solves the technical problems of difficulty in identifying non-standard structures and easy loss of timing and safety logic in old machine tool PLC programs through graphical reverse analysis and automatic reconstruction, and realizes rapid and highly reliable upgrade and transformation of control systems. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating the steps of the graphical reverse analysis and automatic reconfiguration method for the PLC logic of old machine tools provided in this application. Detailed Implementation

[0020] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] As mentioned in the background section, this application proposes a graphical reverse analysis and automatic reconfiguration method for the PLC logic of outdated machine tools, such as... Figure 1 As shown, it includes the following steps: S1. Obtain the ladder diagram program file of the original CNC system through the hardware interface, perform format standardization processing on the ladder diagram program file, and generate a unified intermediate representation structure; S2. Analyze the connection relationships of each contact, coil, timer, and counter in the intermediate representation structure, and construct a directed hypergraph G=(V, E); where V represents a component node and E represents a signal flow dependency edge; and label the type and timing attributes of each component node; S3. Identify the timing logic chains in the intermediate representation structure and extract the timing constraint relationship T={(v i , v j ,type, delay)};where, v i and v j For component nodes, type indicates the constraint type, and delay indicates the delay time; S4. Based on the preset safety logic pattern library, the safety logic blocks in the directed hypergraph G are automatically identified and marked using the graph pattern matching algorithm; based on the marked directed hypergraph G and the timing constraint relationship T, combined with the programming model of the target PLC system, the reconstructed PLC program is generated.

[0023] Specifically, this embodiment uses a certain model of imported horizontal machining center as an example. The original CNC system of this machine tool is the FANUC 0i system, which has been in service for 12 years. Now it is necessary to upgrade the control system to a certain domestic open CNC system, while retaining the original mechanical structure.

[0024] First, step one is performed to obtain the original system's ladder diagram program file and perform standardization processing. Using the RS232 serial communication interface provided by the original CNC system, a read command is sent using dedicated communication software to export the ladder diagram program stored internally as a file. This file format is the FANUC system's proprietary MEM file format, containing ladder diagram segment information, component types, component addresses, and connection relationships. After obtaining this file, format standardization processing is performed, specifically including: parsing the binary structure of the MEM file, extracting the start address, segment length, and instruction sequence within each ladder diagram segment; and converting the opcodes and operands in the instruction sequence into a unified intermediate representation structure. This intermediate representation structure uses the Extensible Markup Language (XML) format. Each ladder diagram segment corresponds to a segment element, and each component within a segment corresponds to a component element. Component elements contain type attributes such as contact, coil, timer, counter, and address attributes. The connection relationships between components are described through connection elements, recording the connection direction between the source and target components. The purpose of standardization processing is to eliminate the differences in ladder diagram formats between different PLC brands, laying the foundation for subsequent unified parsing. In this step, semantic mapping is performed on FANUC system-specific instructions such as the timer instruction TMR and the counter instruction CNT, converting them into standard timer and counter elements in the intermediate representation structure.

[0025] Step two involves parsing the intermediate representation structure and constructing a directed hypergraph. All element elements in the intermediate representation structure are traversed, extracting the type and address information of each element. Simultaneously, signal flow dependencies between elements are established based on connection elements. The core of this step is constructing a directed hypergraph G=(V,E). Element nodes V include four types: contact nodes, coil nodes, timer nodes, and counter nodes. Each node contains the following attributes: element address, element type (e.g., normally open contact, normally closed contact, output coil, timer coil, counter coil), timing attributes, and timing attribute values ​​(e.g., timer preset value, counter preset value). Signal flow dependency edges E represent the relationship of signal flow from one element to another. When the output of element A serves as the input condition for element B, a directed edge is established from A to B. Taking a common start-stop circuit in ladder diagrams as an example, the normally open contact and self-holding contact of the start button are connected in parallel and then in series with the normally closed contact of the stop button, which then drives the output coil. When constructing the directed hypergraph, both the start button node and the self-holding contact node have directed edges pointing to the stop button node, and the stop button node points to the output coil node, forming a complete signal flow path. For timers and counters, in addition to establishing signal flow dependency edges, their preset delay values ​​or pre-designed values ​​are extracted as timing attributes of the nodes for annotation. For parallel and series branches in the ladder diagram, the multi-input single-output case is handled by introducing virtual convergence nodes, ensuring that the directed hypergraph can accurately describe the logical structure of the original ladder diagram.

[0026] Step 3: Identify the timing logic chain and extract timing constraints. After constructing the directed hypergraph, traverse and analyze the paths containing timer and counter nodes to identify the timing logic chain. A timing logic chain is a time-dependent logical sequence consisting of timers, counters, and their controlled contacts. For example, a typical delay-start circuit includes a timer coil. After being energized, the timer coil closes its normally open contact after a preset delay, driving the subsequent output coil. This step extracts the timing constraints T of this timing logic chain. The extraction process is as follows: Starting from the timer coil node, search forward along the signal flow dependency edge to find the normally open or normally closed contact node of the timer coil; analyze the contact type. If it is a normally open contact, the constraint type is delay-on; if it is a normally closed contact, the constraint type is delay-off; continue searching forward from the contact node to the target coil node it controls, and record the target coil node; use the preset delay value of the timer coil node as the delay parameter to form a timing constraint tuple. For complex timing chains formed by multiple timers cascaded together, multiple timing constraint tuples are extracted sequentially to form a set of timing constraints. This step, by explicitly defining timing dependencies, provides a basis for maintaining the original program's timing behavior during subsequent program refactoring.

[0027] Step 4: Identify and label safety logic blocks. This step, based on a pre-defined safety logic pattern library, automatically identifies safety logic blocks in the directed hypergraph G using a graph pattern matching algorithm. The safety logic pattern library pre-stores graph patterns for various common safety logics, including emergency stop logic patterns, limit protection logic patterns, servo enable logic patterns, and spindle brake logic patterns. Taking the emergency stop logic pattern as an example, its graph pattern characteristics are: an emergency stop button node is typically a normally closed contact, connected in series with multiple servo enable contacts, ultimately driving an emergency stop relay coil or directly controlling the enable signal of the servo drive. The graph pattern matching algorithm uses a subgraph isomorphic matching method, matching each pattern graph in the safety logic pattern library with the directed hypergraph G to find all subgraphs structurally isomorphic to the pattern graph. During the matching process, not only node type and edge direction matching are considered, but also node address range matching; for example, the address of the emergency stop button node usually belongs to a specific range of input addresses. For successfully matched subgraphs, all nodes and edges contained therein are labeled as safety logic blocks, and a safety identifier is added to the node attributes to record the safety logic type to which the node belongs. For example, a node identified as having emergency stop logic will have a flag added to its attributes indicating that the safety type is emergency stop. Once this flag is set, these safety logic blocks will be forcibly retained during subsequent program generation to prevent the loss of safety features due to refactoring.

[0028] Step 5: Generate the reconstructed PLC program. Based on the annotated directed hypergraph G and timing constraints T, combined with the programming model of the target PLC system, the reconstructed PLC program is automatically generated. The programming model of the target PLC system includes its supported programming language types such as ladder diagrams, structured text, instruction lists, component address mapping rules, and instruction sets. In this embodiment, the target system is a domestically developed open CNC system that supports ladder diagram programming. Its component address range is X input, Y output, M intermediate relay, T timer, and C counter. The generation process is as follows: Traverse the signal flow dependency edges E in the directed hypergraph G, and output the logical relationships of each component node according to the topological sorting order; for each coil node, convert all its input paths into drive segments in the ladder diagram; for the timing constraints T, convert them into timer instructions of the target system; for nodes marked as safety logic blocks, add comment markers during generation to ensure quick location during subsequent debugging. The generated reconstructed PLC program is saved as a file and can be directly imported into the target CNC system for compilation and execution.

[0029] This embodiment automatically converts the ladder diagram program of the original FANUC 0i system into the ladder diagram program of the target domestic system through the above steps. The whole process does not require manual line-by-line parsing and rewriting, and the transformation cycle is shortened from several weeks to several hours. The security logic is completely preserved, and the reconstructed program is functionally equivalent to the original program.

[0030] In a preferred embodiment, constructing the directed hypergraph G=(V,E) includes the following steps: Traverse the intermediate representation structure, identify all coil elements that are repeatedly assigned values, and construct a double-coil collision set C = {c1, c2, …, c k}, where each double-coil collision set c i For the same physical output address, there is a set of all logical blocks that drive that physical output address; For each double-coil collision set c i By analyzing the path reachability in the directed hypergraph G, the collision set c of the two coils is determined. i The timing mutual exclusion relationships between the included drive branches: If path reachability analysis determines that each driving branch has interlocking constraints in its logical structure, then the conflict set c is... i It is labeled as a decoupled dual coil and a merged logic tree is generated to merge multiple drive branches into a single logic output; If path reachability analysis determines that there are no interlocking constraints in the logical structure of each driving branch, then the conflict set c is... i The double coil is marked as a risky type, triggering a user alert, and is also represented as the double coil collision set c in the directed hypergraph G. iA mutual exclusion protection logic block is inserted before the corresponding physical output address node. The mutual exclusion protection logic block is used to ensure that only one drive branch can be turned on at any given time.

[0031] Specifically, this embodiment describes a specific implementation method for handling dual-coil conflicts. Dual-coil conflicts refer to the phenomenon where the same physical output address is driven by multiple logic blocks in a ladder diagram program. This is common in older PLC programs and is usually caused by multiple field modifications. Improper handling may result in uncertain output states in the reconstructed program.

[0032] During the construction of the directed hypergraph G, dual-coil collision detection is performed simultaneously. All coil elements in the intermediate representation structure are traversed, and a mapping table is built using the output address as the key. All logic blocks driving the same output address are collected into a set. Specifically, for each coil element, its address attribute is obtained. If the address already exists in the mapping table, the logic block to which the current coil element belongs is added to the corresponding set; otherwise, a new set is created, and the current logic block is added. After the traversal is complete, the dual-coil collision set C = {c1, c2, …, c} is obtained. k}, where each c i This corresponds to a physical output address that is driven in multiple locations, and contains the set of all logic blocks that drive that address. Each logic block refers to the complete signal flow path from the input signal to the coil element, including all contacts, intermediate relays, and timers along the path.

[0033] For each double-coil collision set c i By analyzing the path reachability in the directed hypergraph G, we can determine c. i The timing mutual exclusion relationships between the various driving branches included. Here is a summary of its core idea: for c i For each pair of drive branches, the output node of the last control element in each branch is obtained, i.e., the last contact or relay node before driving the coil. In the directed hypergraph G, a depth-first search is performed along the positive direction of the signal flow dependency edge E, starting from these two output nodes respectively, to determine whether the two search paths will intersect at the same interlocked relay node. An interlocked relay node is a relay node whose state change can cut off the conduction condition of one of the branches. For example, a normally closed contact is connected in series in the branch, and the branch is opened when the relay is energized. If two paths intersect at the same interlocked relay node, and the state change of the relay can cut off one of the branches, then it is determined that there is an interlock constraint between the two branches.

[0034] If path reachability analysis determines c i If each driving branch in the middle has interlocking constraints in its logical structure, then the conflict set c will be... iThis is labeled as a decoupling dual-coil. For example, an output coil is driven by both forward and reverse conditions, and there is an electrical interlock between forward and reverse rotation. That is, the normally closed contact of the forward relay is connected in series in the reverse branch, and the normally closed contact of the reverse relay is connected in series in the forward branch. In this case, the two branches are interlocked and can be safely decoupled. For decoupling dual-coil, a merging logic tree is generated to combine multiple driving branches into a single logic output. The method for generating the merging logic tree is as follows: taking the original output coil node as the root node, performing an OR operation on the logic expressions of all its input branches to merge them, while retaining the original interlocking relationships of each branch, forming a single composite logic expression, which is implemented using a single network segment in the refactoring program.

[0035] If path reachability analysis determines c i If the driving branches in the middle have no interlocking constraints in their logical structure, meaning that at least two branches may be conducting simultaneously, then the conflict set c is considered a conflict set. i This is labeled as a risky dual-coil. For example, two independent start signals drive the same output coil, and there is no interlocking relationship between them. If both signals are valid simultaneously, the output state will be determined by the scanning order, which introduces uncertainty. For risky dual-coil systems, a user warning is first triggered, listing the conflicting output addresses and conflicting branch information on the interface, prompting the user for confirmation. Simultaneously, the conflict set c of this dual-coil is represented in the directed hypergraph G. i A mutual exclusion protection logic block is inserted before the corresponding physical output address node. This mutual exclusion protection logic block adopts a priority interlock structure, specifically: defining the priority order of each drive branch, and adding a priority judgment logic before the output to ensure that only one branch can be conducted at any given time. The priority order can be specified by the user or default to the branch number order. After inserting the mutual exclusion protection logic block, the original dual-coil structure is converted into a single-coil structure with a clear priority, eliminating output uncertainty.

[0036] This embodiment uses the above method to automatically identify and handle dual-coil conflict problems in old PLC programs, safely merge decoupled dual coils, insert mutual exclusion protection for risky dual coils and prompt the user for confirmation, thus avoiding uncertainty in the output state of the program after reconstruction due to dual-coil conflict, and improving the reliability and maintainability of the program.

[0037] In a preferred embodiment, constructing the directed hypergraph G=(V, E) includes the following steps: Analyze the long chain interlocking paths indirectly formed by multiple intermediate relays in the directed hypergraph G, and identify the implicit interlocking structures that meet the following conditions: there are at least two signal flow paths that are not directly related to each other, each path passes through at least two intermediate relay nodes and finally converges to the same coil node, and the interruption of any signal flow path causes the coil node to lose power. The implicit interlocking structure is extracted from the distributed node relationship to generate an explicit interlocking logic block, and a virtual interlocking node is added to the directed hypergraph G. The virtual interlocking node replaces the original multiple distributed interlocking paths, so that the implicit interlocking structure maintains topological integrity during the reconstruction process. Simultaneously, the original intermediate relay node information of each path in the explicit interlock logic block is recorded as a traceability annotation for the reconstructed program.

[0038] Specifically, this embodiment describes a specific implementation method for identifying and handling implicit interlocking structures. Implicit interlocking refers to a long chain of interlocking paths indirectly formed by multiple intermediate relays. The interlocking relationship is not directly represented by two contacts connected in series, but rather indirectly achieved through the interlocking reactions of multiple intermediate relays. This structure is common in older PLC programs, especially in complex interlocking protection circuits. Due to programmer habits or limitations of early PLC instruction sets, interlocking relationships are often constructed using a step-by-step transmission method with multiple intermediate relays. During manual analysis, this type of implicit interlocking structure is easily overlooked, leading to the loss of interlocking protection after program reconstruction.

[0039] After constructing the directed hypergraph G, implicit interlocking structure identification is performed. The long chain of interlocking paths indirectly formed by multiple intermediate relays in the directed hypergraph G is analyzed to identify implicit interlocking structures that meet the following conditions: there are at least two independent signal flow paths, each path passing through at least two intermediate relay nodes, ultimately converging at the same coil node, and the interruption of any signal flow path causes the coil node to lose power. The identification process is as follows: traverse all coil nodes in the directed hypergraph G; for each coil node, perform a depth-first search along the reverse direction of the signal flow dependency edge E, recording all paths that can reach the coil node; for each path, extract the sequence of intermediate relay nodes traversed on the path; select coil nodes with more than or equal to two paths and each path containing at least two intermediate relay nodes as candidate targets; for each candidate target, check whether there is a direct intersection between its paths. If there is no direct intersection but each path can independently de-energize the coil, then an implicit interlocking structure exists.

[0040] For example, in the hydraulic system starting circuit of a machine tool, the hydraulic pump starts under three conditions: normal oil temperature, normal oil level, and normal filter. Each condition is transmitted via an independent intermediate relay signal. These three intermediate relays are connected in series to drive the hydraulic pump contactor coil. In the ladder diagram, these three intermediate relays may be distributed in different network segments, each receiving a sensor signal and outputting its own signal, which is then connected in series in one network segment to drive the hydraulic pump contactor. This structure indirectly implements the AND logic relationship between the three sensor signals through the three intermediate relays, and the loss of any sensor signal will cause the intermediate relay to de-energize, thereby de-energizing the hydraulic pump contactor coil. This is a typical implicit interlock structure.

[0041] After identifying the implicit interlock structure, it is extracted from the distributed node relationships to generate an explicit interlock logic block. The extraction process is as follows: collect all signal flow paths participating in the implicit interlock, extract the starting condition of each path (i.e., the input node or constantly energized node at the path's starting point), and the ending condition of the path (i.e., the coil node at the path's ending point). Combine these conditions to form an explicit logical expression. Taking the hydraulic system mentioned above as an example, the starting conditions for the three paths are extracted as normal oil temperature signal, normal oil level signal, and normal filter signal, and the ending condition for all three is the hydraulic pump contactor coil. The generated explicit interlock logic block is: Hydraulic pump contactor coil = normal oil temperature signal AND normal oil level signal AND normal filter signal. In the directed hypergraph G, a new virtual interlock node is added. This node represents the output of the explicit interlock logic block. This virtual interlock node replaces the original multiple distributed interlock paths, that is, the original long chain interlock paths are deleted, and the virtual interlock node is used as a new signal source, directly connected to the original coil node. In this way, the implicit interlocking structure is made explicit, simplifying the graph structure while maintaining the original interlocking function.

[0042] Simultaneously, the original intermediate relay node information for each path in the explicit interlock logic block is recorded as a traceability annotation for the reconstructed program. Specifically, the recorded information includes the address, type, and function of each intermediate relay node involved in the original interlock structure. This information is embedded as a comment in the generated reconstructed program, facilitating subsequent maintenance personnel's understanding of the origin and implementation of the interlock logic. For example, a comment can be added next to the generated reconstructed program network segment explaining: "This interlock logic is derived from the series circuit of three intermediate relays in the original program, corresponding to the normal oil temperature, normal oil level, and normal filter signals, respectively."

[0043] This embodiment uses the method described above to automatically identify and explicitly display implicit interlock structures in legacy PLC programs, avoiding parsing omissions caused by scattered interlock logic. The explicit interlock logic is clearer and easier to read in the reconstructed program, and retains the traceability information of the original intermediate relay nodes, facilitating maintenance and debugging.

[0044] In a preferred embodiment, labeling the type and timing attributes of each component node includes the following steps: Identify the non-standard timer structure in the intermediate representation structure. The non-standard timer structure includes: a timer coil node, a relay node connected in parallel with the timer coil node to form a self-holding path, and an output node controlled by the normally open contact of the timer coil node. The timer coil node and the relay node form a closed loop, so that the timer coil node is continuously energized through the self-holding of the relay node after being turned on. The normally open contact of the timer coil node closes after a preset delay, triggering the output node. The intermediate representation structure is pattern matched using a preset topological feature template to identify non-standard timer structures that conform to the above structure, and the preset delay value of the timer coil node is extracted. The identified non-standard timer structures are labeled as semantic restoration timer types, the preset delay value is recorded in the timing attributes, and the relay nodes are marked as redundant nodes, which are omitted when generating the reconstructed PLC program.

[0045] Specifically, this embodiment describes a detailed implementation method for identifying and restoring non-standard timer structures. Many non-standard timer structures exist in older PLC programs. This is due to limitations in the instruction sets of early PLC systems or programmer habits, especially in early models from brands like FANUC and Mitsubishi, where the number of standard timer instructions was limited. Field engineers often used timer coils with self-holding circuits to simulate timing functions. In a ladder diagram, this type of non-standard timer structure is represented by a timer coil connected in parallel with a relay node to form a self-holding circuit. After the timer coil is energized, it remains energized through the self-holding function of the relay node. The normally open contact of the timer coil closes after a preset delay, triggering subsequent output nodes. During manual analysis, this structure is easily misinterpreted as ordinary logic, leading to the reconstructed program losing its timing function or having timing sequence errors.

[0046] During the process of labeling the type and timing attributes of each component node, non-standard timer structure identification is performed simultaneously. The specific process is as follows: All timer coil nodes in the intermediate representation structure are traversed. For each timer coil node, the contact node it controls is searched forward along the signal flow dependency edge. During the search, if a parallel self-holding path is found for the timer coil node, and this self-holding path consists of the normally open contact of a relay node, and this relay node and the timer coil node are controlled by the same start condition, then it is initially determined to be a candidate non-standard timer structure. Further searching of the normally open contacts of the timer coil node reveals that if this normally open contact controls an output node after a preset delay, and this output node is not directly related to the relay node in the self-holding path, then the structure is confirmed to be a non-standard timer structure.

[0047] For example, in the ladder diagram of a certain FANUC system, there exists the following structure: a timer coil is connected in parallel with the normally open contact of an intermediate relay, and both are controlled by a start button; the normally open contact of the timer coil is connected in series in the drive circuit of the output coil. When the start button is closed, the timer coil is energized and begins timing, while the intermediate relay is simultaneously energized and self-holding, allowing the timer coil to continue timing even after the start button is released; after a preset delay time, the normally open contact of the timer coil closes, energizing the output coil. This is a typical non-standard timer structure, functionally equivalent to a delay-on timer.

[0048] After identifying a non-standard timer structure, pattern matching is performed using a preset topology feature template. The topology feature template predefines the graphical pattern characteristics of the non-standard timer structure: the timer coil node is connected in parallel with a relay node, and the normally open contact of the relay node forms a self-holding circuit; the normally open contact of the timer coil node controls the output node; there is no other intermediate control logic between the timer coil node and the relay node. The candidate structure is matched against the template. If a match is successful, the preset delay value of the timer coil node is extracted. This delay value is typically stored in the parameter attributes of the timer element; for example, in the FANUC system, the preset delay value of the timer coil is stored in the operand of the TMR instruction.

[0049] The identified non-standard timer structures are marked as semantically restored timer types, and the extracted preset delay value is recorded in the timing attributes. Simultaneously, relay nodes in the self-holding loop are marked as redundant nodes. The meaning of a redundant node is that in the non-standard timer structure, this relay node is only used to maintain the energized state of the timer coil. After conversion to a standard timer, its function is replaced by the self-holding mechanism of the standard timer, therefore it does not need to be retained in the refactoring program. When generating the refactored PLC program, the structures marked as semantically restored timer types are converted to standard timer instructions supported by the target PLC system. For example, in the target Siemens system, it is converted to the TON instruction; in the target Mitsubishi system, it is converted to the T instruction. During the conversion, the extracted preset delay value is used as the parameter of the timer instruction, the start condition of the timer coil in the original structure is used as the enable condition of the standard timer, and the output node controlled by the normally open contact of the timer coil in the original structure is used as the output of the standard timer. Relay nodes are omitted, and corresponding program code is no longer generated.

[0050] This embodiment uses the above method to automatically identify non-standard timer structures in old PLC programs and restore them to standard timer semantics, avoiding the loss of timing functions caused by misjudgment of non-standard structures. This makes the reconstructed program more standardized and readable, while reducing redundant logic and improving program running efficiency.

[0051] In a preferred embodiment, labeling the type and timing attributes of each component node V includes the following steps: Traverse all input nodes in the intermediate representation structure and filter out candidate signal nodes related to mechanical wear state based on the signal change characteristics of each input node; According to the preset wear signal identification rules, the candidate signal nodes are classified and determined to identify the wear signal type of each candidate signal node; The input nodes that are identified as wear signals are marked with wear association attributes in the directed hypergraph G, and the corresponding wear signal type identifier is recorded in the node attributes; Tracing downstream along the signal flow dependency edge E in the directed hypergraph G, identify the coil nodes controlled by each wear signal node, and establish the coupling association path between the wear signal node and the coil node; The coupling association path is recorded in key-value pair form to generate a coupling mapping table. The coupling mapping table is used to reserve a communication interface between the wear signal node and the external compensation module when generating the reconstructed PLC program.

[0052] Specifically, this embodiment describes a specific implementation method for wear signal identification and coupling mapping. After long-term operation, old machine tools exhibit varying degrees of wear on their mechanical components, leaving characteristic traces in the PLC's input signals. For example, limit switches may generate abnormal jitter pulses due to contact oxidation, lead screw wear can cause periodic fluctuations in the position feedback signal, and increased transmission backlash can frequently trigger overload protection signals. These wear-related signals are often ignored in traditional retrofitting processes, resulting in the reconstructed system being unable to perceive the mechanical state and unable to coordinate with subsequent backlash / deformation compensation modules for optimization. This embodiment identifies these wear signals and establishes coupling mapping to provide an information interface for the mechanical compensation module.

[0053] After constructing the directed hypergraph G and labeling the component node types and timing attributes, the wear signal identification step is executed. First, all input nodes in the intermediate representation structure are traversed, and the signal change record for each input node is extracted. The signal change record is obtained from the original CNC system's operating log or historical data collected on-site, containing information on the state changes of each input node over time. If historical data is unavailable, signal change data can be collected over a period of time through online monitoring during the trial operation phase before modification. In this embodiment, a 24-hour no-load test is performed on the target machine tool, collecting the state changes of all input nodes and recording the timestamp of each state reversal.

[0054] Based on the signal change characteristics of each input node, candidate signal nodes related to mechanical wear are selected. The selection criterion is the signal change frequency: under normal machine tool operation, mechanical wear will cause abnormally frequent triggering of related signals. The number of state transitions for each input node per unit time is calculated, and nodes with a state transition count exceeding a preset threshold are marked as candidate signal nodes. In this embodiment, the preset threshold is 10 times per minute, that is, nodes that trigger more than once every 6 seconds on average are considered candidates. For limit switch type nodes, under normal operating conditions, they only trigger once at the end of the stroke. If frequent transitions of dozens of times per minute occur, it indicates that the contacts are oxidized or mechanically loose.

[0055] Based on preset wear signal identification rules, candidate signal nodes are classified and their wear signal types are determined. The specific classification method is described later; the judgment logic is outlined here. For digital input nodes, their pulse width is analyzed. If the pulse width is less than the minimum action response time of the corresponding mechanical switch, it is determined to be a contact oxidation type wear signal. For overload protection signal nodes, their trigger frequency is statistically analyzed. If the trigger frequency exceeds a preset frequency threshold, it is determined to be a gap overload type wear signal. For position feedback signal nodes, their pulse sequence is subjected to spectral analysis. If periodic fluctuation components are present, it is determined to be a leadscrew wear type wear signal.

[0056] Input nodes identified as wear signals are labeled with wear association attributes in the directed hypergraph G, and the corresponding wear signal type identifier is recorded in the node attributes. The wear association attribute is a Boolean flag; a true value indicates that the node is a wear signal node. The wear signal type identifier is an enumeration type, with values ​​of contact oxidation type, gap overload type, or leadscrew wear type. For example, for a limit switch node identified as having contact oxidation, a record with a true wear association and a wear type of contact oxidation is added to its node attributes.

[0057] After the wear signal is labeled, the tracedown proceeds downstream along the signal flow dependency edge E in the directed hypergraph G to identify the coil nodes controlled by each wear signal node. The tracing method is as follows: starting from the wear signal node, a depth-first search is performed along the positive direction of the signal flow dependency edge E, recording all coil nodes encountered during the search. These coil nodes are the actuators controlled by the wear signal. For example, if the jitter pulse signal of a limit switch, after passing through the intermediate relay logic, ultimately controls the feed enable coil of the machine tool, then this feed enable coil is recorded as a coil node controlled by the wear signal.

[0058] Establish the coupling path between wear signal nodes and coil nodes, recording the signal transmission path between the wear signal node and the coil node it controls, including all intermediate relay nodes and logical operations along the path. Record the coupling path in key-value pair format to generate a coupling mapping table. Each entry in the coupling mapping table contains the following fields: wear signal node address, wear signal type identifier, list of controlled coil node addresses, and the logical dependency type between each coil node and the wear signal node. Logical dependency types include direct control, AND logic combination, and OR logic combination, etc.

[0059] The generated coupling mapping table is used to reserve communication interfaces between wear signal nodes and external compensation modules when generating the reconstructed PLC program. Specifically, in the reconstructed PLC program, a corresponding state variable is created for each wear signal node. This state variable not only reflects the current signal value but also carries a wear type identifier. This state variable is made available to external compensation modules through preset communication protocols such as Modbus TCP and OPC UA. External compensation modules, such as clearance deformation compensators, can read this wear status information and dynamically adjust compensation parameters according to the wear type. For example, when a limit switch shows contact oxidation wear, the compensator can add software filtering to the limit switch signal to avoid false triggering due to jitter; when a lead screw wear signal is read, the compensator can dynamically adjust the backlash compensation amount.

[0060] This embodiment uses the above method to automatically identify wear-related signals in old PLC programs, establish a coupling mapping between wear signals and actuators, provide an information interface for external compensation modules, realize the linkage optimization of control logic and mechanical state, and improve the adaptability and accuracy maintenance capability of the upgraded system.

[0061] In a preferred embodiment, the step of classifying and determining the wear signal type of each candidate signal node according to a preset wear signal identification rule includes the following steps: Obtain the signal change records of each candidate signal node and extract the number of state flips for each candidate signal node per unit time. Candidate signal nodes whose state flip count exceeds a preset threshold are marked as nodes to be classified; For each node to be classified, perform at least one of the following classification decisions: If the node to be classified is a digital input node and its pulse width is less than the minimum action response time of the corresponding mechanical switch, then the node is determined to be a contact oxidation wear signal. If the output address corresponding to the node to be classified is an overload protection signal, and the trigger frequency of the node exceeds a preset frequency threshold, then the node is determined to be a gap overload type wear signal. If the node to be classified is a position feedback signal node, and there is a periodic fluctuation component in its pulse sequence, then the node is determined to be a lead screw wear signal. The determination result is recorded in the node attributes as the wear signal type identifier.

[0062] Specifically, this embodiment describes a specific implementation method for classifying and determining wear signals. After screening candidate signal nodes, the signal change records of each candidate signal node are first obtained. The signal change record is an ordered sequence containing timestamps and state values. For example, for a switch input node, the time and state value of each state change from 0 to 1 or from 1 to 0 are recorded. The number of state transitions for each candidate signal node per unit time is extracted from the signal change record. The number of state transitions is defined as the number of times the signal state changes per unit time, with each rising edge and falling edge counted as one transition. In this embodiment, the number of transitions is counted per minute. For nodes that are continuously collected for 24 hours, the average number of transitions per minute is calculated.

[0063] Candidate signal nodes whose state toggling count exceeds a preset threshold are marked as nodes to be classified. The preset threshold setting needs to consider the characteristics of different signal types. In this embodiment, the threshold for switch input nodes is 5 times per minute, the threshold for overload protection signals is 3 times per hour, and the threshold for position feedback signals is a fluctuation amplitude per revolution exceeding a preset value, rather than simply the number of toggling counts. Only when the number of toggling counts exceeds the threshold will the node proceed to the next classification step; otherwise, it is considered a normal signal and no wear marking is performed.

[0064] For each node to be classified, perform the corresponding classification decision based on its node type. The classification decision includes the following three cases: The first scenario involves a digital input node. Digital input nodes typically connect to components such as limit switches, travel switches, and buttons. When such nodes exhibit abnormally frequent switching, it's necessary to determine if it's a contact oxidation-related wear signal. Contact oxidation increases contact resistance, leading to intermittent contact under mechanical vibration, manifesting as short-duration pulses. The specific determination method is as follows: obtain the pulse sequence of the node, extract the width of each pulse (i.e., the high-level duration), and compare the pulse width with the minimum action response time of the corresponding mechanical switch. The minimum action response time of a mechanical switch refers to the shortest time required for the switch contacts to move from actuation to stable closure, typically ranging from 10 to 50 milliseconds, with the specific value determined based on the switch model. If the pulse width is less than this minimum action response time, the pulse is determined to be abnormal jitter caused by oxidized contacts, and the node is identified as a contact oxidation-related wear signal.

[0065] In the second scenario, the output address corresponding to the node to be classified is an overload protection signal. Overload protection signals typically originate from fault outputs of thermal relays, motor protectors, or frequency converters. Increased transmission clearance intensifies mechanical impact, easily leading to momentary motor overload, manifested as frequent triggering of the overload protection signal. The determination method is as follows: Statistically count the triggering frequency of the node, i.e., the number of times the signal changes from a normal state to an overload state per unit time; compare the triggering frequency with a preset frequency threshold. In this embodiment, the preset frequency threshold is twice per hour. If the triggering frequency exceeds this threshold, the node is determined to be a clearance overload type wear signal. A clearance overload type wear signal indicates an abnormal clearance in the transmission chain, requiring close attention from the subsequent compensation module.

[0066] The third scenario involves a position feedback signal node. Position feedback signal nodes are typically connected to the pulse output of an encoder, linear encoder, or inductive synchronizer. Screw wear causes periodic changes in the transmission error of the screw pair, which manifests as periodic fluctuations in the pulse sequence in the position feedback signal. The determination method is as follows: acquire the pulse sequence of the node over a certain period, perform a Discrete Fourier Transform on the pulse sequence, and analyze its spectral characteristics; detect whether there is a periodic fluctuation component corresponding to the screw rotation period. Specifically, the screw rotation period can be calculated from the feed rate and the screw lead. If a frequency component corresponding to this period is detected in the spectrum, and its amplitude exceeds a preset threshold, then the node is determined to be a screw wear-type wear signal.

[0067] After classification and determination, the determination result is recorded as a wear signal type identifier in the node attributes. The wear signal type identifier is an enumerated value: contact oxidation type wear signal is recorded as TYPE_CONTACT_OXIDATION, clearance overload type wear signal is recorded as TYPE_BACKLASH_OVERLOAD, and lead screw wear type wear signal is recorded as TYPE_SCREW_WEAR. For nodes that simultaneously meet multiple determination conditions, multiple type identifiers can be recorded to reflect the complex wear state.

[0068] This embodiment achieves automatic classification and determination of wear signals through the above method, quantifying the abstract mechanical wear state into specific signal type identifiers, providing an accurate classification basis for subsequent coupling mapping and compensation control, and enabling the compensation module to adopt targeted compensation strategies according to different wear types.

[0069] In a preferred embodiment, after constructing the directed hypergraph G=(V, E), the following steps are further included: Iterate through all component nodes in the directed hypergraph, and for each component node v i Perform the following operations: With component node v i Starting from the signal flow dependent edge E, a depth-first search is performed. If no coil node is found, the element node v is marked. i There are no output nodes in the positive direction; With component node v i Starting from the endpoint, perform a depth-first search along the reverse direction of the signal flow dependent edge E. If no input node or constantly powered input node can be found, then mark the element node v. i For reverse no-input nodes; The element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction i It was determined to be an isolated node; Remove isolated nodes and their associated signal flow dependent edges E from the directed hypergraph G.

[0070] Specifically, this embodiment focuses on describing the implementation method for identifying and deleting isolated nodes. Old PLC programs, after years of field modifications and debugging, often contain a large number of invalid but not deleted zombie logic blocks. These logic blocks have no external input signals to drive them, nor do they output to any actuators; they are completely isolated, occupying PLC memory and increasing scan cycles. This embodiment uses a graph theory search method to automatically identify and delete these isolated nodes, optimizing the reconstructed program.

[0071] After constructing the directed hypergraph G=(V,E), the isolated node identification and deletion steps are performed. First, all component nodes in the directed hypergraph G are traversed, and forward reachability detection is performed for each component node vi. Forward reachability detection starts with v. i Starting from a given node, a depth-first search is performed along the positive direction of the signal flow-dependent edge E. Depth-first search is a graph traversal algorithm that starts from a starting node and searches as deep as possible along the edges until it cannot proceed further, then backtracks. During the search, all visited nodes are recorded. When the search is complete, it is checked whether any coil nodes have been visited. Coil nodes are the final output elements driving the actuator, and their address type is output coil. If no coil node is visited during the search, it indicates that the search started from v. i The originating signal stream cannot reach any actuator, i.e., v i It does not contribute to the actual movement of the machine tool, marked with v. i This is a positive, no-output node.

[0072] For example, consider an intermediate relay, designated as the first intermediate relay, whose coil is driven by a certain condition. However, its normally open contact is only used to control another intermediate relay (the second intermediate relay), whose contacts are not connected to any output coil. In this case, a forward search starting from the first intermediate relay will access the second intermediate relay but will not find a coil node. Therefore, the first intermediate relay is marked as having no output node in the forward search.

[0073] Secondly, reverse reachability detection is performed on each component node vi. Reverse reachability detection uses v... i With node v as the endpoint, a depth-first search is performed in the reverse direction of the signal flow dependent edge E. During the reverse search, the search proceeds in the opposite direction of the edge, i.e., from node v... i Set off, search for all routes that lead to v iThe search process checks whether any input nodes or constantly powered input nodes are accessed. Input nodes refer to physical input signals, such as buttons, switches, and sensors, whose addresses fall within the input address range. Constantly powered input nodes are those that maintain a high level continuously during normal machine tool operation, such as normal power signals and emergency stop untriggered signals. If no input nodes and no constantly powered input nodes are accessed during the reverse search, it indicates that v i There is no external input driver, i.e., v i Driven entirely by internal logic and whose driving source cannot be traced back to external input, marked v i This is a reverse no-input node.

[0074] Continuing with the example of the first intermediate relay, its coil is driven by the normally open contact of the second intermediate relay, and the coil of the second intermediate relay is in turn driven by the normally open contact of the first intermediate relay, forming a closed loop with no external input. A reverse search ending at the first intermediate relay will access the second intermediate relay, but no input node can be found. Therefore, the first intermediate relay is marked as having no input node in the reverse direction.

[0075] The component node v that simultaneously satisfies both the conditions of no output node in the forward direction and no input node in the reverse direction i These nodes are identified as isolated nodes. Isolated nodes cannot affect any actuators or be controlled by any external signals; they constitute completely invalid logic. For example, in the closed-loop structure formed by the first and second intermediate relays mentioned above, both nodes are marked as having no output in the forward direction and no input in the reverse direction, and therefore are both identified as isolated nodes.

[0076] Finally, the isolated node and all its associated signal flow dependent edges E are removed from the directed hypergraph G. The removal operation includes: removing the node from the node set V and removing all edges connected to the node from the edge set E. After the removal, the structure of the directed hypergraph G is simplified and no longer contains invalid logic. For the closed-loop structure of the first and second intermediate relays described above, both nodes and the edges between them are completely removed, and this part of the logic in the original program is completely eliminated.

[0077] This embodiment automatically identifies and deletes isolated nodes in the PLC program through forward and reverse depth-first searches, eliminating the impact of invalid logic on program size and scan cycle. After the isolated nodes are deleted, the reconstructed program is more streamlined, the running efficiency is improved, and the risk of accidental triggering caused by residual invalid logic is avoided.

[0078] In a preferred embodiment, the element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction... iAfter a node is determined to be isolated, before deleting the isolated node and its associated signal flow dependent edge E from the directed hypergraph G, the following steps are also included: For each component node v that simultaneously satisfies the conditions of no output node in the forward direction and no input node in the reverse direction i Execute path duplicate detection: With component node v i Starting from the signal flow dependent edge E, perform a depth-first search along the positive direction and record the sequence of all nodes traversed during the search process; If, during the search process, after passing through at least three different intermediate relay nodes, the search returns to the element node v... i Then determine v i It belongs to the ring self-locking node, and the ring self-locking node is excluded from the isolated node.

[0079] Specifically, a special case exists in the process of deleting isolated nodes: a ring-shaped self-locking structure composed of multiple intermediate relays, such as an oscillating circuit formed by two intermediate relays interlocking with each other, or a ring-shaped interlocking circuit composed of three or more intermediate relays. In both forward and reverse searches, this type of structure cannot find either the coil node or the input node, and will be incorrectly deleted as an isolated node. However, the ring-shaped self-locking structure is actually effective control logic, often used to implement functions such as alternating output, pulse generation, or state maintenance. This embodiment adds a ring-shaped self-locking structure identification step before deleting isolated nodes to avoid incorrect deletion.

[0080] When executing a component node v that simultaneously satisfies both the conditions of no output node in the forward direction and no input node in the reverse direction. i After a node is identified as an isolated node, but before it is removed from the directed hypergraph G along with its associated signal flow dependency edge E, a ring-locked structure identification process is performed. This process is repeated for each element node v that has been identified as an isolated node. i Execute path duplicate detection.

[0081] The specific process of path duplication detection is as follows: taking component node v i Starting from the beginning, a depth-first search is performed along the positive direction of the signal flow dependent edge E. During the depth-first search, the sequence of all nodes traversed is recorded, including the node's address, type, and access order. The search continues until no further progress is possible or the preset maximum search depth is reached. During the search, it is checked whether a node is visited repeatedly. If this is detected, the search returns to the starting node v. i Then record from v i From departure to return to v i The complete path taken.

[0082] For the detected loop path, further analysis of its node composition is performed. The number of intermediate relay nodes traversed in the loop path is checked; if it returns to v after traversing at least three different intermediate relay nodes... i Then determine v i This belongs to a ring-shaped self-locking structure. It requires at least three different intermediate relay nodes because while a simple interlocking circuit consisting of two intermediate relays also forms a loop, its typical structure involves each relay's normally closed contact connected in series with the coil circuit of another relay. This structure is usually not mistaken for an isolated node because it typically has an external input drive. However, a ring structure consisting of three or more intermediate relays is more prone to having neither external input nor final output, making it a key area to identify.

[0083] For example, an old machine tool PLC program contains a loop circuit consisting of three intermediate relays (first intermediate relay, second intermediate relay, and third intermediate relay). The coil of the first intermediate relay is driven by the normally open contact of the second intermediate relay, the coil of the second intermediate relay is driven by the normally open contact of the first intermediate relay, and the coil of the third intermediate relay is driven by the normally open contact of the second intermediate relay, forming a complete loop. No external input signals are connected, and the contacts of the three relays do not drive any output coils. During testing, the first, second, and third intermediate relays are all marked as no output nodes in the forward direction and no input nodes in the reverse direction, and are judged as isolated nodes. However, during path repetition detection, starting from the first intermediate relay and searching forward, passing through the second and third intermediate relays, and then returning to the first intermediate relay, the intermediate relay nodes traversed include the second and third intermediate relays. Including the starting first intermediate relay, there are three different intermediate relay nodes. Therefore, the first intermediate relay is judged as a loop self-locking node. Similarly, the second and third intermediate relays are also judged as loop self-locking nodes.

[0084] Once a node is identified as a circularly locked node, it is excluded from the list of isolated nodes. Exclusion means that in subsequent isolated node deletion operations, this node will not be considered an isolated node and will not be deleted. Specifically, a set of circularly locked nodes is maintained. After the isolated node determination is completed, nodes in this set are removed from the list of isolated nodes to be deleted. After removal, these nodes and their associated signal flow dependencies E are fully preserved and will not be deleted.

[0085] This embodiment uses a path duplication detection method to automatically identify circular self-locking structures and exclude them from isolated nodes, avoiding the accidental deletion of valid circular self-locking logic while maintaining the ability to delete truly isolated nodes. Identified circular self-locking nodes are retained, ensuring the complete functionality of the reconstructed program.

[0086] In a preferred embodiment, the step for each dual-coil collision set c i By analyzing the path reachability in the directed hypergraph G, the collision set c of the two coils is determined. i The timing mutual exclusion relationships between the included drive branches include the following steps: For the two-coil collision set c i Each pair of drive branches, including a first branch and a second branch, performs the following operations: Obtain the output node of the last control element in the first branch, and obtain the output node of the last control element in the second branch; In a directed hypergraph G, starting from two output nodes respectively, a search is performed along the positive direction of the signal flow dependent edge E. If the two search paths eventually converge at the same interlocked relay node, and the state change of the interlocked relay node can cut off the conduction condition of one of the branches, then it is determined that the first branch and the second branch have interlocking constraints in their logical structure. If all drive branches have interlocking constraints between each other, then the dual-coil conflict set c is determined. i Each driving branch contained herein has interlocking constraints in its logical structure; otherwise, it is determined that there are no interlocking constraints.

[0087] Specifically, when handling dual-coil conflicts, it is necessary to determine whether there are interlocking constraints between the drive branches. This embodiment details the specific implementation method for determining interlocking constraints through path reachability analysis.

[0088] For each double-coil collision set c i When determining the timing mutual exclusion relationships between each drive branch, perform the following operations. For the dual-coil conflict set c... i Each pair of driving branches is designated as the first branch and the second branch. A driving branch refers to the complete signal flow path that starts from the input signal, passes through a series of contacts, intermediate relays, timers, and other components, and finally reaches the driven coil. Each driving branch contains multiple component nodes and signal flow dependent edges.

[0089] Obtain the output node of the last control element in the first branch. The last control element is the element in the branch closest to the driven coil, typically a contact or a normally open / normally closed contact of an intermediate relay. This element is the final condition determining whether the coil is energized. Similarly, obtain the output node of the last control element in the second branch.

[0090] In the directed hypergraph G, a depth-first search is performed starting from each of the two output nodes and proceeding along the forward direction of the signal flow dependency edge E. The forward search refers to starting from the initial node and continuously traversing subsequent nodes along the direction of the signal flow until no further progress is possible. During the search, the path information visited at each node is recorded, including the sequence of nodes traversed from the initial node to that node.

[0091] Determine whether two search paths ultimately converge at the same interlocked relay node. An interlocked relay node is a relay node whose state change can interrupt the conduction condition of one of the branches. The method for identifying the convergence point is as follows: denot the set of nodes visited by the first branch search as S1, and the set of nodes visited by the second branch search as S2, and find the intersection of S1 and S2. If the intersection is not empty, further analyze whether each node in the intersection possesses interlocking functionality.

[0092] The method for analyzing whether a node has interlocking functionality is as follows: Check if the node is an intermediate relay node and if its contacts are connected in series in the drive branch in a normally closed manner. Specifically, in the original branch, if the normally closed contact of the relay node appears on the control path of the branch, when the relay is energized, its normally closed contact opens, thereby cutting off the branch. This structure allows the relay to interlock with other branches. For example, in a forward / reverse control circuit, the normally closed contact of the forward relay is connected in series in the reverse branch, and the normally closed contact of the reverse relay is connected in series in the forward branch. When the forward relay is energized, its normally closed contact opens, preventing the reverse branch from conducting, thus forming an interlock.

[0093] If two search paths converge at the same interlocked relay node, and the state change of this interlocked relay node can break the conduction condition of one of the branches, then it is determined that the first branch and the second branch have an interlocking constraint in their logical structure. The method to determine whether a state change can break the conduction condition is: check whether the normally closed contact of the interlocked relay node is located on the control path of the branch to be broken. If it is located on the branch to be broken, then when the relay is energized, the normally closed contact opens, and the branch is broken.

[0094] Taking a forward / reverse control circuit as an example, let the output coil corresponding to the dual-coil conflict set ci be the motor forward / reverse contactor. The first branch drives the forward contactor of the motor forward / reverse contactor, and its last control element is the normally open contact of the forward relay; the second branch drives the reverse contactor of the motor forward / reverse contactor, and its last control element is the normally open contact of the reverse relay. A forward search starting from the normally open contact of the forward relay will pass through the normally closed contact of the reverse relay; a forward search starting from the normally open contact of the reverse relay will also pass through the normally closed contact of the forward relay. The two search paths intersect at the forward and reverse relay nodes, both of which are interlocked relay nodes. The normally closed contact of the forward relay is located in the second branch; when the forward relay is energized, the second branch is disconnected. The normally closed contact of the reverse relay is located in the first branch; when the reverse relay is energized, the first branch is disconnected. Therefore, it is determined that there is an interlock constraint between the two branches.

[0095] For the two-coil collision set c i Then, perform the above-mentioned interlock constraint judgment on all pairs of drive branches contained therein. If there are interlock constraints between all pairs of drive branches, then determine c. i The included drive branches are logically interlocked, meaning the dual-coil conflict is decoupling. If at least one pair of drive branches lacks interlocking constraints, it is considered to have no interlocking constraints, meaning the dual-coil conflict is risky.

[0096] This embodiment achieves automatic judgment of interlock constraints in each drive branch of a dual-coil conflict set through path intersection analysis and interlock relay node identification. Based on the graph theory properties of directed hypergraphs, this method can accurately identify various interlocking forms such as forward / reverse interlocking and conditional interlocking, providing a reliable basis for classifying decoupling and risk types.

[0097] In a preferred embodiment, after removing the ring-shaped self-locking node from the isolated node, the method further includes the following steps: The excluded ring-shaped self-locking nodes are marked as ring-shaped self-locking structures in the directed hypergraph G; Preserve the ring-locked node and all its associated signal flow dependent edges E; When generating the reconstructed PLC program, nodes marked as ring self-locking structures are converted into their equivalent oscillation circuits or interlocking holding circuits.

[0098] Specifically, previously, the circular self-locking node was excluded from the isolated nodes to avoid accidental deletion. However, the excluded circular self-locking node is still retained in the directed hypergraph G and needs to be transformed with the correct semantics in the reconstruction process. This embodiment illustrates the method for labeling, retaining, and transforming the excluded circular self-locking node.

[0099] After excluding the circular self-locking nodes from the isolated nodes, subsequent processing of the circular self-locking nodes is performed. First, the excluded circular self-locking nodes are marked as circular self-locking structures in the directed hypergraph G. The marking method is to add a structure type field to the node attributes, and this field is set to "circular self-locking structure". The purpose of the marking is to identify the special properties of these nodes during subsequent program generation and to adopt a special transformation strategy.

[0100] After annotation, retain the ring-shaped self-locking node and all its associated signal flow dependent edges E. Retention means not deleting the ring-shaped self-locking node, maintaining its original node and edge relationships. For multiple intermediate relay nodes included in the ring-shaped self-locking structure, all are retained, and the interlocking or self-holding relationships between nodes are also fully preserved.

[0101] When generating the refactored PLC program, nodes marked as ring-locked structures are converted into their equivalent oscillating circuits or interlocking circuits. The specific conversion strategy depends on the specific type of ring-locked structure.

[0102] For an interlocking circuit consisting of two intermediate relays, its typical structure involves the two relays mutually locking and interlocking, typically used to achieve bistable or alternating outputs. In the refactoring program, it is converted into a standard bistable trigger circuit, implemented using set / reset instructions. For example, in an interlocking circuit consisting of a first and a second intermediate relay, when the first intermediate relay is energized, its normally closed contact cuts off the coil circuit of the second intermediate relay, while its normally open contact self-locks to maintain the energization of the first intermediate relay; the reverse is also true. In the target PLC system, this can be converted to an implementation using SET and RST instructions, making the program more concise.

[0103] For a ring oscillator circuit consisting of three or more intermediate relays, its typical structure involves the relays sequentially turning on to form a cycle, typically used to generate periodic pulses or achieve sequential control. In the refactoring program, based on the periodic characteristics of the ring structure, it is converted into a corresponding timer pulse circuit or step sequence control circuit. For example, a ring circuit consisting of a first intermediate relay, a second intermediate relay, and a third intermediate relay can be formed by the first intermediate relay turning on, then delaying the second intermediate relay to turn on, then delaying the second intermediate relay to turn on, then delaying the second intermediate relay to turn on, and finally delaying the third intermediate relay to turn on, thus forming a cycle. In the target PLC system, this can be converted into a ring timer circuit implemented using multiple timers connected in series, making the timing relationship clearer and more controllable.

[0104] During the conversion process, the original functional semantics of the ring-shaped self-locking structure are preserved to ensure that the behavior of the reconstructed program is consistent with that of the original program. Simultaneously, for intermediate relay nodes in the ring-shaped self-locking structure, their original addresses and comments are retained during program generation to facilitate maintenance personnel's understanding of the circuit function. If the original ring-shaped self-locking structure contains abnormal or unreasonable timing parameters, prompts can be provided through the user interface during conversion for user confirmation or adjustment.

[0105] This embodiment separates and correctly processes the circular self-locking structure from isolated nodes through annotation, preservation, and semantic transformation, ensuring that this special control logic is correctly implemented in the reconstructed program. The annotation and transformation methods not only maintain the functionality of the original program but also make the reconstructed program more standardized and maintainable, avoiding functional abnormalities caused by accidental deletion or transformation of the circular structure.

[0106] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A graphical reverse analysis and automatic reconfiguration method for PLC logic in old machine tools, characterized in that, Includes the following steps: The ladder diagram program file of the original CNC system is obtained through a hardware interface, and the ladder diagram program file is processed to standardize the format to generate a unified intermediate representation structure. The connection relationships of each contact, coil, timer, and counter in the intermediate representation structure are analyzed to construct a directed graph G=(V, E); where V represents a component node and E represents a signal flow dependent edge; and the type and timing attributes of each component node are labeled. Identify the timing logic chain in the intermediate representation structure and extract the timing constraint relationship T={(v i , v j , type, delay)};where, v i and v j For component nodes, type indicates the constraint type, and delay indicates the delay time; Based on a pre-defined safety logic pattern library, a graph pattern matching algorithm is used to automatically identify and label safety logic blocks in a directed graph G; based on the labeled directed graph G and timing constraint relationship T, combined with the programming model of the target PLC system, a reconstructed PLC program is generated. The safety logic mode library pre-stores various common safety logic diagrams, including emergency stop logic mode, limit protection logic mode, servo enable logic mode, and spindle brake logic mode. The diagram feature of the emergency stop logic mode is that an emergency stop button node is a normally closed contact, which is connected in series with multiple servo enable contacts, ultimately driving an emergency stop relay coil or directly controlling the enable signal of the servo driver. After constructing the directed graph G=(V, E), the following steps are also included: Iterate through all the component nodes in the directed graph, and for each component node v i Perform the following operations: With component node v i Starting from the signal flow-dependent edge E, a depth-first search is performed along the positive direction, recording the sequence of all nodes traversed, including the node's address, type, and access order. The search continues until it cannot proceed further or reaches the preset maximum search depth. If no coil node is found, the element node v is marked. i There are no output nodes in the positive direction; With component node v i Starting from the endpoint, perform a depth-first search along the reverse direction of the signal flow dependent edge E. If no input node or constantly powered input node can be found, then mark the element node v. i For reverse no-input nodes; The element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction i It was determined to be an isolated node; Remove isolated nodes and their associated signal flow dependent edges E from the directed graph G; The element node v that simultaneously satisfies both no output node in the forward direction and no input node in the reverse direction. i After a node is determined to be an isolated node, before deleting the isolated node and its associated signal flow dependent edge E from the directed graph G, the following steps are also included: For each component node v that simultaneously satisfies the conditions of no output node in the forward direction and no input node in the reverse direction i Execute path duplicate detection: With component node v i Starting from the signal flow dependent edge E, perform a depth-first search along the positive direction and record the sequence of all nodes traversed during the search process; If, during the search process, after passing through at least three different intermediate relay nodes, the search returns to the element node v... i Then determine v i It belongs to the ring-locked node, and the ring-locked node is excluded from the isolated node; After removing the ring-shaped self-locking node from the isolated node, the method further includes the following steps: The excluded ring-shaped self-locking nodes are marked as ring-shaped self-locking structures in the directed graph G; Preserve the ring-locked node and all its associated signal flow dependent edges E; When generating the reconstructed PLC program, nodes marked as ring self-locking structures are converted into their equivalent oscillation circuits or interlocking holding circuits.

2. The graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools according to claim 1, characterized in that, The construction of the directed graph G=(V,E) includes the following steps: Traverse the intermediate representation structure, identify all coil elements that are repeatedly assigned values, and construct a double-coil collision set C = {c1, c2, …, c k }, where each double-coil collision set c i For the same physical output address, there is a set of all logical blocks that drive that physical output address; For each double-coil collision set c i By analyzing the path reachability in the directed graph G, the collision set c of the double coil is determined. i The timing mutual exclusion relationships between the included drive branches: If path reachability analysis determines that each driving branch has interlocking constraints in its logical structure, then the conflict set c is... i It is labeled as a decoupled dual coil and a merged logic tree is generated to merge multiple drive branches into a single logic output; If path reachability analysis determines that there are no interlocking constraints in the logical structure of each driving branch, then the conflict set c is... i The double coil is marked as a risky type and triggers a user alert. Simultaneously, it represents the double coil collision set c in the directed graph G. i A mutual exclusion protection logic block is inserted before the corresponding physical output address node. The mutual exclusion protection logic block is used to ensure that only one drive branch can be turned on at any given time.

3. The graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools according to claim 1, characterized in that, The construction of the directed graph G=(V, E) includes the following steps: Analyze the long chain interlocking paths indirectly formed by multiple intermediate relays in the directed graph G, and identify the implicit interlocking structure that satisfies the following conditions: there are at least two signal flow paths that are not directly related to each other, each path passes through at least two intermediate relay nodes and finally converges to the same coil node, and the interruption of any signal flow path causes the coil node to lose power. The implicit interlocking structure is extracted from the distributed node relationship to generate an explicit interlocking logic block, and a virtual interlocking node is added to the directed graph G. The virtual interlocking node replaces the original multiple distributed interlocking paths, so that the implicit interlocking structure maintains topological integrity during the reconstruction process. Simultaneously, the original intermediate relay node information of each path in the explicit interlock logic block is recorded as a traceability annotation for the reconstructed program.

4. The graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools according to claim 1, characterized in that, The annotation of the type and timing attributes of each component node V includes the following steps: Traverse all input nodes in the intermediate representation structure and filter out candidate signal nodes related to mechanical wear state based on the signal change characteristics of each input node; According to the preset wear signal identification rules, the candidate signal nodes are classified and determined to identify the wear signal type of each candidate signal node; The input nodes that are identified as wear signals are marked with wear association attributes in the directed graph G, and the corresponding wear signal type identifier is recorded in the node attributes. Tracing downstream along the signal flow dependent edge E in the directed graph G, identify the coil nodes controlled by each wear signal node, and establish the coupling association path between the wear signal node and the coil node; The coupling association path is recorded in key-value pair form to generate a coupling mapping table. The coupling mapping table is used to reserve a communication interface between the wear signal node and the external compensation module when generating the reconstructed PLC program.

5. The graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools according to claim 4, characterized in that, The step of classifying and determining the wear signal type of each candidate signal node according to a preset wear signal identification rule includes the following steps: Obtain the signal change records of each candidate signal node and extract the number of state flips for each candidate signal node per unit time. Candidate signal nodes whose state flip count exceeds a preset threshold are marked as nodes to be classified; For each node to be classified, perform at least one of the following classification decisions: If the node to be classified is a digital input node and its pulse width is less than the minimum action response time of the corresponding mechanical switch, then the node is determined to be a contact oxidation wear signal. If the output address corresponding to the node to be classified is an overload protection signal, and the trigger frequency of the node exceeds a preset frequency threshold, then the node is determined to be a gap overload type wear signal. If the node to be classified is a position feedback signal node, and there is a periodic fluctuation component in its pulse sequence, then the node is determined to be a lead screw wear signal. The determination result is recorded in the node attributes as the wear signal type identifier.

6. The graphical reverse analysis and automatic reconfiguration method for PLC logic of old machine tools according to claim 2, characterized in that, The specific approach for each double-coil collision set c i By analyzing the path reachability in the directed graph G, the collision set c of the double coil is determined. i The timing mutual exclusion relationships between the included drive branches include the following steps: For the two-coil collision set c i Each pair of drive branches, including a first branch and a second branch, performs the following operations: Obtain the output node of the last control element in the first branch, and obtain the output node of the last control element in the second branch; In a directed graph G, starting from two output nodes respectively, a search is performed along the positive direction of the signal flow dependent edge E. If the two search paths eventually converge at the same interlocked relay node, and the state change of the interlocked relay node can cut off the conduction condition of one of the branches, then it is determined that the first branch and the second branch have interlocking constraints in their logical structure. If all drive branches have interlocking constraints between each other, then the dual-coil conflict set c is determined. i Each driving branch contained herein has interlocking constraints in its logical structure; otherwise, it is determined that there are no interlocking constraints.

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