A processor, a processor clock control method, a storage medium and a program product

Abstract

This invention discloses a processor, a processor clock control method, a storage medium, and a program product, relating to the field of computer technology. By adding a clock frequency control module connected to multiple functional units of the computing core on the processor, the module determines a combination of clock frequencies for multiple functional units that meet the performance requirements of the software task being run by the computing core, based on task information, execution time information required for the functional units to execute instructions, and performance requirements of the software task on the processor. This combination of clock frequencies is then sent to the computing core for adjustment of the clock frequencies of the functional units. This achieves precise calculation of the clock frequencies of each functional unit of the computing core based on the performance requirements of the software task being executed by the computing core. While meeting performance requirements, this significantly reduces the power consumption of the computing core, thus achieving power management of the processor.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a processor, a processor clock control method, a storage medium, and a program product. Background Technology

[0002] With the development of Reduced Instruction Set Computing V (RISC-V) processors, they have been widely used in high-performance computing, edge computing, and the Internet of Things (IoT). However, in traditional RISC-V processors, each functional unit defaults to the highest performance mode, resulting in wasted power consumption. Summary of the Invention

[0003] This invention provides a processor, a processor clock control method, a storage medium, and a program product to at least solve the problem of wasted power consumption caused by the fact that all functional units of open instruction set architecture processors are enabled at the highest performance by default in related technologies.

[0004] This invention provides a processor, comprising: at least one computing core and a clock frequency control module; The computing core includes multiple functional units; The clock frequency control module is connected to multiple functional units and is used to determine a combination of clock frequencies of multiple functional units that meet the performance requirements of the software task running by the computing core, the execution time information required by the functional units to execute instructions, and the performance requirements of the software task on the processor, and to send the information of the clock frequency combination to the computing core so that the computing core can adjust the clock frequency of the functional units.

[0005] The present invention also provides a processor clock control method, applied to the above-mentioned processor, comprising: Obtain task information of the software task running by the computing core of the processor, execution time information required by the computing core to execute instructions, and performance requirements of the software task on the processor; Based on the task information, the execution time information, and the performance requirement information, determine the clock frequency combination of multiple functional units that meet the performance requirements of the software task; The information of the clock frequency combination is sent to the computing core so that the computing core can adjust the clock frequency of the functional unit.

[0006] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the processor clock control methods described above.

[0007] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the processor clock control methods described above.

[0008] This invention adds a clock frequency control module to the processor for adjusting the clock frequency of functional units. This clock frequency control module is connected to multiple functional units of the computing core. Based on the task information of the software task being run by the computing core, the execution time information required for the functional units to execute instructions, and the performance requirements of the software task on the processor, it determines the combination of clock frequencies of multiple functional units that meet the performance requirements of the software task. This information is then sent to the computing core so that the computing core can adjust the clock frequency of the functional units. This achieves precise configuration of the clock frequency of each functional unit of the computing core according to the performance requirements of the software task being executed by the computing core. It avoids the problem of excessive clock frequency caused by defaulting to maximum performance for each functional unit in traditional solutions. Therefore, while meeting performance requirements, it can significantly reduce the power consumption of the computing core, achieving power management of the processor. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a diagram of a traditional multi-core processor architecture; Figure 2 A processor architecture diagram provided for an embodiment of the present invention; Figure 3 An architecture diagram of a clock frequency control module provided in an embodiment of the present invention; Figure 4 An architecture diagram of a clock switch control module provided in an embodiment of the present invention; Figure 5 An architecture diagram of a clock wake-up control module provided in an embodiment of the present invention; Figure 6 A flowchart of a processor clock control method provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0012] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Here, we will first explain some key terms used in the embodiments of the present invention.

[0015] The Reduced Instruction Set Computing V (RISC-V) architecture is an open-source instruction set architecture based on the principle of reduced instruction set computing. Its features include modularity and extensibility, allowing users to customize instructions according to application scenarios.

[0016] Figure 1 This is a diagram of a traditional multi-core processor architecture.

[0017] like Figure 1 As shown, a traditional RISC-V CPU consists of multiple computing cores (RISC-V Cores), each with its own Level 1 cache (L1 Cache). Multiple computing cores share a Level 2 cache (L2 Cache), and the microarchitecture of each computing core is consistent. For example... Figure 1 As shown, a typical computing core includes an instruction fetch unit, a decoding unit, an execution unit, a virtual address translation unit, and a load-memory unit. An external clock control unit sets the clock frequency for each computing core. In traditional solutions, the clock frequency of each functional unit within the computing core is fixed and uniform; for example, the instruction fetch unit and the execution unit are uniformly set to 1GHz. This results in a significant waste of clock resources.

[0018] To address the issue of wasted power consumption caused by defaulting to maximum performance for all functional units in open instruction set architecture processors, this invention provides a processor, processor clock control method, storage medium, and program product. By adding a clock frequency control module to the processor for adjusting the clock frequency of functional units, this module is connected to multiple functional units of the computing core. Based on task information of the software task running by the computing core, execution time information required for the functional units to execute instructions, and performance requirements of the software task on the processor, it determines a combination of clock frequencies for multiple functional units that meet the performance requirements of the software task. This clock frequency combination information is then sent to the computing core for adjustment of the clock frequencies of the functional units. This achieves precise configuration of the clock frequencies of each functional unit of the computing core according to the performance requirements of the software task executed by the computing core, avoiding the clock frequency overload problem caused by defaulting to maximum performance for each functional unit in traditional solutions. Therefore, while meeting performance requirements, it can significantly reduce the power consumption of the computing core, achieving power management of the processor.

[0019] Figure 2 A processor architecture diagram provided for an embodiment of the present invention; Figure 3 This is an architecture diagram of a clock frequency control module provided in an embodiment of the present invention.

[0020] like Figure 2 As shown, the processor provided in this embodiment of the invention may include at least one computing core and a clock frequency control module; the computing core includes multiple functional units; the clock frequency control module is connected to the multiple functional units and is used to determine the clock frequency combination of multiple functional units that meets the performance requirements of the software task based on the task information of the software task running by the computing core, the execution time information required by the functional units to execute instructions, and the performance requirements of the software task on the processor, and send the clock frequency combination information to the computing core so that the computing core can adjust the clock frequency of the functional units.

[0021] In this embodiment of the invention, the processor is an open instruction set architecture processor.

[0022] The functional units can be referred to in the above text. Figure 1 The introduction. Functional units may include Figure 2 The listed functional units may also include other types of functional units.

[0023] In this embodiment of the invention, the clock frequency control module is used to optimally set the clock frequency of the functional units based on the performance requirements of the software tasks running on the computing core. Optimal frequency setting means that each functional unit operates at the lowest possible clock frequency. Combined with the function of the functional unit clock dynamic management control module, this embodiment of the invention achieves optimal clock frequency settings for the functional units necessary for the current task, while ensuring that the overall operating performance of the computing core meets the performance requirements of the current software task. Here, performance requirements can refer to completing the software task within a specified time.

[0024] In this embodiment of the invention, the task information may include the instruction types and the corresponding number of instructions included in the process of the software task run by the computing core; the performance requirement information may include the maximum allowed time to complete the software task.

[0025] Because open instruction set architecture processors contain multiple computing cores, commonly 8, 16, 32, or 64 cores, and each core runs different software processes (the specific allocation of software process tasks is determined by the operating system), the minimum performance requirements for each computing core are different. Therefore, in this embodiment of the invention, the minimum frequency settings for the necessary functional units on each computing core within the multi-core processor are different. For example, the instruction fetch unit of RISC-V Core0 is set to 1GHz, the decoding unit to 800MHz, and the integer arithmetic subunit in the execution unit is set to 1.2GHz; the instruction fetch unit of RISC-V Core1 is set to 700MHz, the decoding unit to 1.2GHz, and the vector arithmetic subunit in the execution unit is set to 800MHz.

[0026] It should be noted that after a software task running on a computing core finishes, the optimal frequency of each functional unit needs to be reset before executing the next task. Furthermore, in this embodiment of the invention, if the processor includes multiple computing cores, the clock frequencies of the functional units on different computing cores are configured independently. This ensures that each computing core of the open instruction set architecture processor operates in the lowest power consumption mode that meets performance requirements when running multiple tasks, greatly reducing the processor's power consumption.

[0027] like Figure 3As shown, the clock frequency control module may include a functional unit instruction execution analysis submodule, a task instruction analysis submodule, and a functional unit clock frequency calculation and setting submodule. The functional unit instruction execution analysis submodule is used to obtain the execution time information required by the functional unit to execute instructions; the task instruction analysis submodule is used to obtain the task information of the software tasks run by the computing core and the performance requirements of the software tasks on the processor; the functional unit clock frequency calculation and setting submodule is used to determine the clock frequency combination of multiple functional units that meets the performance requirements of the software tasks, and sends the clock frequency combination information to the computing core so that the computing core can adjust the clock frequency of the functional units.

[0028] In this embodiment of the invention, determining the clock frequency combination of multiple functional units that meet the performance requirements of the software task based on task information, execution time information, and performance requirement information may include: determining the actual execution time of the computing core executing the software task based on the number of instructions of the instruction type and the execution time of the corresponding functional unit executing a single instruction; determining the target time for the functional unit to execute a single instruction if the actual execution time is less than or equal to the maximum allowed time; and obtaining the target clock frequency of the functional unit based on the target time.

[0029] Specifically, the functional unit instruction execution analysis submodule can be used to statistically analyze the time taken for each functional unit within the computing core to execute an instruction. Specifically, the fetch and decode functional units are necessary processing steps for each instruction; therefore, T_get can represent the time taken for the fetch unit to execute an instruction; T_decode can represent the time taken to parse (decode) an instruction; T_integer can represent the time taken to execute an integer instruction; T_float can represent the time taken to execute a floating-point instruction; T_vector can represent the time taken to execute a vector instruction; T_load can represent the time taken to execute a load instruction; and T_store can represent the time taken to execute a store instruction.

[0030] The task instruction analysis submodule can be used to analyze the number of various types of instructions in the current process on the current computing core. Specifically, it can include: the number of all instructions (num_all), the number of integer instructions (num_integer), the number of floating-point instructions (num_float), the number of vector instructions (num_vector), the number of load instructions (num_load), and the number of store instructions (num_store).

[0031] Additionally, the type of instruction can be determined based on its opcode field: the opcode field for integer instructions is 7'b0110011 / 7'b0010011; the opcode field for floating-point instructions is 7'b1010011; the opcode field for vector instructions is 7'b1010111; the opcode field for load instructions is 7'b0000011; and the opcode field for store instructions is 7'b0100011.

[0032] The functional unit clock frequency calculation and setting submodule can be used to calculate and set the minimum clock frequency combination of functional units that meet the performance requirements of the current process in the current computing core. The method involves first receiving the performance requirements of the current process for the computing core, that is, the maximum required time T to complete the current process.

[0033] The actual execution time of the computing core for executing software tasks is determined based on the number of instructions of each instruction type and the execution time of a single instruction by the corresponding functional unit. This can include: determining the first time (i.e., num_all × T_get) required for the computing core to execute the instruction fetch task based on the total number of instructions required for the software task process and the instruction fetch unit time of the computing core's instruction fetch function; determining the second time (i.e., num_all × T_decode) required for the computing core to execute the instruction decoding task based on the total number of instructions and the instruction decoding unit time of the computing core's decoding function; determining the third time (i.e., num_integer × T_integer) required for the computing core to execute the integer arithmetic task based on the number of integer instructions in the software task process and the unit time required for the integer arithmetic subunit of the computing core to execute integer instructions; and determining the third time (i.e., num_integer × T_integer) required for the computing core to execute the floating-point arithmetic subunit of the computing core based on the number of floating-point instructions in the software task process and the unit time required for the floating-point arithmetic subunit of the computing core to execute floating-point instructions. The fourth time (i.e., num_float × T_float) required for the computing core to execute floating-point operations is determined based on the number of vector instructions in the software task process and the unit time required for the computing core's vector operation subunit to execute vector instructions. The sixth time (i.e., num_load × T_load) required for the computing core to execute loading tasks is determined based on the number of loading instructions in the software task process and the unit time required for the computing core's load-store function unit to execute loading instructions. The seventh time (i.e., num_store × T_store) required for the computing core to execute storage tasks is determined based on the number of storage instructions in the software task process and the unit time required for the load-store function unit to execute storage instructions. The sum of the first, second, third, fourth, fifth, sixth, and seventh times is taken as the actual execution time.

[0034] Simultaneously satisfying the inequality: num_all×T_get+num_all×T_decode+num_integer×T_integer+num_float×T_float+num_vector×T_vector+num_load×T_load+num_store×T_store≤T.

[0035] Here, num_all represents the total number of instructions required to execute the software task, num_integer represents the number of integer instructions, num_float represents the number of floating-point instructions, num_vector represents the number of vector instructions, num_load represents the number of load instructions, and num_store represents the number of store instructions.

[0036] Solving the above equation yields the optimal combination of T_get, T_decode, T_integer, T_float, T_vector, T_load, and T_store.

[0037] In this embodiment of the invention, determining the target time for a functional unit to execute a single instruction based on the actual execution time being less than or equal to the maximum allowed time may include: prioritizing load instructions and store instructions as the highest priority, and then determining the maximum execution time of a single instruction corresponding to the instruction type in descending order of priority, such as vector instructions, floating-point instructions, and integer instructions, to obtain the target time corresponding to each instruction type whose actual execution time is less than or equal to the maximum allowed time.

[0038] Specifically, considering that load and store instructions consume the most power, followed by vector instructions, then floating-point instructions, and finally integer instructions, the priority of solving the above formula should be as follows: First priority: solve for the maximum value of T_load and T_store (to keep the execution clock frequency of load and store instructions as low as possible); Second priority: solve for the maximum value of T_vector (to keep the execution clock frequency of vector instructions as low as possible); Third priority: solve for the maximum value of T_float (to keep the execution clock frequency of floating-point instructions as low as possible); Fourth priority: solve for the maximum value of T_integer (to keep the execution clock frequency of integer instructions as low as possible).

[0039] The above calculation process completes the optimal frequency setting for each functional unit under the current process of the current core. The corresponding functional unit is then set according to the obtained frequency, where the clock frequency is the reciprocal of the corresponding instruction cycle. During calculation, the unit of clock frequency is gigahertz (GHz), and the unit of instruction cycle is nanoseconds (ns). Specifically: the clock frequency of the instruction fetch unit = 1 / T_get; the clock frequency of the decode unit = 1 / T_decode; the clock frequency of the integer arithmetic unit = 1 / T_integer; the clock frequency of the floating-point arithmetic unit = 1 / T_float; the clock frequency of the vector arithmetic unit = 1 / T_vector; and the clock frequency of the virtual address translation unit and the load / store unit = 1 / T_load or 1 / T_store (whichever is greater).

[0040] It should be noted that when calculating the above formula, users can set a maximum value for T_get, T_decode, T_integer, T_float, T_vector, T_load, and T_store according to their own needs. This is the minimum value of the corresponding clock frequency. The purpose is to ensure that the instruction will not be blocked in the processing between the preceding and following stages.

[0041] Figure 4 This is an architecture diagram of a clock switch control module provided in an embodiment of the present invention.

[0042] Based on the above embodiments, the processor provided in this embodiment of the invention may further include a clock switch control module; the clock switch control module is connected to multiple functional units and is used to obtain the instruction characteristics of the software task within a predetermined instruction cycle, determine the first set of functional units used and the second set of functional units not used within the predetermined instruction cycle according to the instruction characteristics, turn off the clock of each functional unit in the second set of functional units, and keep the clock of each functional unit in the first set of functional units enabled.

[0043] In practical implementation, the clock switch control module is used to enable the clock for only the functional units used within the agreed instruction cycle, while promptly turning off the corresponding clock for functional units that will not be used within the agreed instruction cycle. Optional functional units refer to... Figure 2 The execution function unit includes sub-units (including integer arithmetic sub-unit, floating-point arithmetic sub-unit, vector arithmetic sub-unit), virtual address translation function unit, and load-memory function unit.

[0044] Because open instruction set architecture processors contain multiple computing cores, commonly 8, 16, 32, or 64 cores, and each core runs different software processes (the specific allocation of software process tasks is determined by the operating system), the real-time clock enable status of the functional units on each RISC-V Core within the multi-core RISC-V CPU is different in this embodiment. For example, RISC-V Core0 enables the instruction fetch unit, decode unit (both of which must be enabled), integer arithmetic subunit in the instruction execution unit, virtual address translation unit, and load-memory unit during the agreed instruction cycle time; while RISC-V Core1 enables the instruction fetch unit, decode unit, and floating-point arithmetic subunit in the instruction execution unit during the agreed instruction cycle time. The clock enable of the functional units on each computing core also changes dynamically because the types of instructions differ in different agreed instruction cycles, therefore the required functional units to be enabled also change in real time.

[0045] The above functions enable dynamic management and control of the internal functional unit clock of the RISC-V CPU, enabling only the necessary functional units of each RISC-V Core, thereby greatly reducing the overall power consumption of the processor (in the traditional solution, the clocks of multiple functional units of multiple Cores of the RISC-V CPU are always enabled).

[0046] like Figure 4 As shown, the clock switch control module may include an instruction analysis submodule and a functional unit enable control submodule. The instruction analysis submodule is used to obtain the instruction characteristics of the software task within a predetermined instruction cycle. The functional unit enable control submodule is used to determine, based on the instruction characteristics, the first set of functional units used within the predetermined instruction cycle and the second set of unused functional units; it disables the clocks of each functional unit in the second set of functional units while keeping the clocks of each functional unit in the first set of functional units enabled.

[0047] Specifically, the instruction analysis submodule analyzes the instructions of the task processes currently running on the computing core (these instructions have not yet been executed and are cached in the Level 1 Cache (L1 Cache) corresponding to the computing core). After reading back the instructions (instructions within a specified instruction cycle, such as 100 instructions, which will be described in detail later), this submodule analyzes them and outputs different instruction type encoding formats according to the instruction types within the instruction cycle, passing them to the enable control submodule of the subsequent functional unit.

[0048] In this embodiment of the invention, the instruction analysis submodule may further be configured with a first correspondence between instruction type combinations and corresponding instruction type codes. Obtaining the instruction characteristics of a software task within a predetermined instruction cycle may include: obtaining the corresponding instruction type code based on the instruction type combinations within the predetermined cycle and the first correspondence.

[0049] Table 1 is the instruction type analysis table. The first correspondence can be shown in Table 1. Table 1

[0050] In this embodiment of the invention, the functional unit enable control submodule is used to determine whether to enable or disable the clock of the relevant functional unit within a predetermined instruction cycle based on the instruction type encoding output from the previous stage.

[0051] In this embodiment of the invention, the functional unit enable control submodule may also be deployed with a second correspondence between instruction type codes and clock switch combinations of functional units. Determining the first set of functional units used and the second set of functional units not used within a predetermined instruction cycle based on instruction characteristics may include: obtaining a target clock switch combination based on the corresponding instruction type codes and the second correspondence; and determining the first set of functional units and the second set of functional units from the target clock switch combination.

[0052] Table 2 is the clock control table for functional units. The second correspondence can be shown in Table 2. Table 2

[0053] like Figure 4 As shown, the clock switch control module may also include an instruction analysis cycle adjustment submodule, which is used to adjust the length of the agreed instruction cycle according to the number of branch instructions in the software task; wherein, the more branch instructions there are, the shorter the agreed instruction cycle is, and the fewer branch instructions there are, the longer the agreed instruction cycle is.

[0054] Specifically, the instruction analysis cycle adjustment submodule is used to adjust the aforementioned agreed instruction cycle. Because branch instructions inevitably exist within the instructions of a software process, and branch instructions have two outcomes: a jump or no jump. When the instruction analysis submodule in the clock switch control module encounters a branch instruction, it can only choose one direction (jump or no jump) to retrieve the subsequent instruction (the subsequent instructions corresponding to jump and no jump are different). However, the choice made by the instruction analysis submodule is not always correct. For example, if a jump is selected, but the correct calculation result of the branch instruction during instruction execution is no jump, it indicates that the previous choice by the instruction analysis submodule was incorrect. In this case, it is necessary to promptly enable the clock for all configurable functional units to avoid delaying normal instruction execution.

[0055] To minimize the likelihood of the aforementioned errors, in this embodiment of the invention, the agreed instruction cycle is determined based on the number of branch instructions. Specifically, the more branch instructions included, the fewer the agreed instruction cycles; conversely, the fewer branch instructions included, the more agreed instruction cycles. For example, when there are 3 branch instructions, the agreed instruction cycle count is 300; when there are 5 branch instructions, the agreed instruction cycle count is 100. This principle aims to reduce the probability of errors in branch prediction within the instruction cycle by the instruction analysis submodule, thereby maximizing the accuracy of the real-time setting of the functional unit enable clock and minimizing the dynamic power consumption of the computing core's functional units.

[0056] Figure 5 This is an architecture diagram of a clock wake-up control module provided in an embodiment of the present invention.

[0057] Based on the above embodiments, the processor provided in this embodiment of the invention may further include a clock wake-up control module; the clock wake-up control module is connected to the computing core and is used to monitor the frequency information of the wake-up event corresponding to the computing core when the computing core is in a sleep state, predict the next expected occurrence time of the wake-up event based on the frequency information of the wake-up event, and perform a wake-up operation on the computing core at a preset time before the next expected occurrence time.

[0058] In practical implementation, the clock wake-up control module is used to predict the arrival of critical tasks after one or more computing cores in the RISC-V CPU automatically enter sleep mode due to a long period of no task running, thereby realizing the function of intelligent wake-up to achieve the purpose of quickly executing critical tasks (traditional solutions do not have the function of predicting the arrival of critical tasks. Only when the critical task actually arrives will the RISC-V Core wake up from sleep mode, load cached data or context state from the Level 2 Cache (L2 Cache) / Double Data Rate Synchronous Dynamic Random Access Memory (DDR), and enable the clock for the corresponding Core. These operations take a long time, requiring hundreds of milliseconds, and cannot guarantee the rapid execution of critical tasks).

[0059] In this embodiment of the invention, the wake-up event may include an external hardware interrupt and / or a software task issued by the operating system.

[0060] Then as Figure 5 As shown, the clock wake-up control module may include an interrupt task prediction submodule, a kernel task prediction submodule, and a sleep mode graded wake-up submodule. The interrupt task prediction submodule listens for external hardware interrupts to the computing core when it is in sleep mode. The kernel task prediction submodule listens for software tasks issued to the computing core by the operating system when it is in sleep mode. The sleep mode graded wake-up submodule predicts the next expected occurrence time of a wake-up event based on the frequency of wake-up events; and performs a wake-up operation on the computing core at a preset time before the next expected occurrence time.

[0061] Specifically, the interrupt prediction submodule monitors the interrupt frequency, i.e., the interval T_out_irq (e.g., 10 minutes), of the external hardware interrupts corresponding to the computing core (in a RISC-V CPU, external interrupts are handled by a specific computing core). When the corresponding computing core enters sleep mode, this submodule outputs an indication signal pre_out_irq_come to the subsequent module (sleep mode graded wake-up submodule) at a time T_set0 before the next predicted interrupt arrival time (e.g., setting T_set0=10ms).

[0062] The kernel task prediction submodule monitors the time interval T_core_process (e.g., 5 minutes) at which the operating system issues software tasks to the computing cores. When the corresponding computing core enters sleep mode, this submodule outputs an indication signal pre_core_process_come to the downstream module (sleep mode graded wake-up submodule) at a time T_set1 before the next predicted arrival time of the software task issued by the operating system (e.g., setting T_set1=20ms).

[0063] In this embodiment of the invention, the sleep mode graded wake-up submodule performs a wake-up operation on the computing core, which may include: graded wake-up of the computing core; wherein, at least two wake-up levels are included: enabling the clock of the computing core and loading the cached data of the computing core.

[0064] The sleep mode graded wake-up submodule is used to wake up the corresponding computing cores in a graded manner upon receiving `pre_out_irq_come` or `pre_core_process_come`. The reason for graded wake-up is that the above predictions are not always accurate. If the prediction is wrong and the computing core is directly woken up to working mode, it will result in wasted power consumption. Therefore, this invention designs a graded wake-up mechanism. The graded wake-up in this scheme is divided into two levels: the first level is to enable the core's clock; the second level is to load cached data. Through step-by-step execution, a combination of ensuring timely execution of critical processes and power management is achieved.

[0065] In this embodiment of the invention, the interrupt task prediction submodule and the kernel task prediction submodule can also be used to adjust the advance of the preset time relative to the next expected occurrence time based on the consistency between the prediction result of the wake-up operation and the actual occurrence of the wake-up event; wherein, the advance is increased when the prediction result is consistent with the actual occurrence, and the advance is decreased when the prediction result is inconsistent with the actual occurrence.

[0066] That is to say, in the embodiments of the present invention, the above-mentioned T_set0 and T_set1 are dynamically changing: when the prediction is accurate, the value of T_set0 / T_set1 is adjusted to be larger; when the prediction is inaccurate, the value of T_set0 / T_set1 is adjusted to be smaller.

[0067] The purpose of the above adjustment strategy is to send an indication signal to the sleep mode graded wake-up submodule as early as possible when the prediction is accurate, and to send an indication signal to the graded wake-up submodule as late as possible when the prediction is inaccurate, so as to avoid the scenario of inaccurate prediction after wake-up as much as possible.

[0068] The embodiments of the present invention provide a processor clock control method. The method is described in detail below in conjunction with the execution flow of the processor clock control method.

[0069] Figure 6 A flowchart of a processor clock control method provided in an embodiment of the present invention.

[0070] The processor clock control method provided in this invention can be implemented based on the processor provided in any of the above embodiments. For example... Figure 6 As shown, the processor clock control method provided in this embodiment of the invention may include: S601: obtaining task information of the software task run by the processor's computing core, execution time information required by the computing core to execute instructions, and performance requirements of the software task on the processor.

[0071] S602: Based on task information, execution time information, and performance requirement information, determine the clock frequency combination of multiple functional units that meet the performance requirements of the software task.

[0072] S603: Sends information about the clock frequency combination to the computing core so that the computing core can adjust the clock frequency of the functional units.

[0073] In specific implementation, for S601, task information may include the instruction types and corresponding number of instructions included in the process of the software task run by the computing core; performance requirement information may include the maximum allowed time to complete the software task.

[0074] Specifically, task information can be obtained through the task instruction analysis submodule. This submodule analyzes the number of instructions (num_all), integer instructions (num_integer), floating-point instructions (num_float), vector instructions (num_vector), load instructions (num_load), and store instructions (num_store) of the current process on the current computing core. Furthermore, the type of each instruction can be determined based on its opcode field: the opcode field for integer instructions is 7'b0110011 / 7'b0010011, for floating-point instructions it's 7'b1010011, for vector instructions it's 7'b1010111, for load instructions it's 7'b0000011, and for store instructions it's 7'b0100011.

[0075] Execution time information can be obtained through the functional unit instruction execution analysis submodule, which calculates the time for each functional unit within the core to execute one instruction. Specifically, T_get represents the time for the instruction fetch unit to execute one instruction, T_decode represents the time for the instruction decode unit to execute one instruction, T_integer represents the time for the execution of an integer instruction, T_float represents the time for the execution of a floating-point instruction, T_vector represents the time for the execution of a vector instruction, T_load represents the time for the execution of a load instruction, and T_store represents the time for the execution of a store instruction.

[0076] Performance requirements information refers to the performance requirements of the current software task on the computing core, that is, the maximum time T required to complete the current process.

[0077] For S602, based on task information, execution time information, and performance requirement information, the clock frequency combination of multiple functional units that meet the performance requirements of the software task is determined, and can be executed through the functional unit clock frequency calculation and setting submodule.

[0078] For S603, information about the clock frequency combination is sent to the computing core so that the computing core can adjust the clock frequency of the functional units.

[0079] In this embodiment of the invention, when the processor includes multiple computing cores, the clock frequencies of the functional units on different computing cores are configured independently.

[0080] Specifically, the functional unit clock frequency calculation and setting submodule sends the target clock frequency information of each functional unit, calculated above, to the computing core. Upon receiving this information, the computing core independently configures the clock frequency of each functional unit. Since the software processes running on each computing core may differ, the minimum frequency settings for each functional unit on each computing core will also differ. When a software task running on a computing core finishes, before executing the next task, it needs to re-acquire the task information, execution time information, and performance requirement information of the new task, and recalculate and set the optimal frequency combination for each functional unit. This ensures that each computing core of the open instruction set architecture processor operates in the lowest power consumption mode that meets performance requirements when running multiple tasks.

[0081] The processor clock control method provided in this invention adds a clock frequency control module to the processor for adjusting the clock frequency of functional units. This clock frequency control module is connected to multiple functional units of the computing core. Based on the task information of the software task running by the computing core, the execution time information required for the functional units to execute instructions, and the performance requirements of the software task on the processor, it determines a combination of clock frequencies for multiple functional units that meet the performance requirements of the software task. This combination of clock frequencies is then sent to the computing core so that the computing core can adjust the clock frequency of the functional units. This achieves precise configuration of the clock frequency of each functional unit of the computing core according to the performance requirements of the software task executed by the computing core. It avoids the problem of excessive clock frequency caused by defaulting to maximum performance for each functional unit in traditional solutions. Therefore, while meeting performance requirements, it can significantly reduce the power consumption of the computing core and achieve power management of the processor.

[0082] Based on the above embodiments, in this embodiment of the invention, in S602, determining the clock frequency combination of multiple functional units that meet the performance requirements of the software task according to task information, execution time information, and performance requirement information may include: determining the actual execution time of the computing core executing the software task based on the number of instructions of the instruction type and the execution time of the corresponding functional unit executing a single instruction; determining the target time for the functional unit to execute a single instruction if the actual execution time is less than or equal to the maximum allowed time; and obtaining the target clock frequency of the functional unit based on the target time.

[0083] Specifically, the actual execution time of the computing core for executing software tasks is determined based on the number of instructions of each instruction type and the execution time of a single instruction by the corresponding functional unit. This can include: determining the first time (i.e., num_all × T_get) required for the computing core to execute the instruction fetch task based on the total number of instructions required for the software task process and the instruction fetch unit time of the computing core's instruction fetch function; determining the second time (i.e., num_all × T_decode) required for the computing core to execute the instruction decoding task based on the total number of instructions and the instruction decoding unit time of the computing core's decoding function; determining the third time (i.e., num_integer × T_integer) required for the computing core to execute the integer arithmetic task based on the number of integer instructions in the software task process and the unit time required for the computing core's integer arithmetic subunit to execute integer instructions; and determining the third time (i.e., num_integer × T_integer) required for the computing core to execute the floating-point instructions based on the number of floating-point instructions in the software task process and the unit time required for the computing core's floating-point arithmetic subunit to execute floating-point instructions. The following steps are taken to determine the execution time: First, the fourth time (num_float × T_float) required for the computing core to execute floating-point operations. Second, the fifth time (num_vector × T_vector) required for the computing core to execute vector operations is determined based on the number of vector instructions in the software task process and the unit time required for the computing core's vector operation subunit to execute vector instructions. Third, the sixth time (num_load × T_load) required for the computing core to execute loading instructions is determined based on the number of loading instructions in the software task process and the unit time required for the computing core's load-store function unit to execute loading instructions. Fourth, the seventh time (num_store × T_store) required for the computing core to execute storage instructions is determined based on the number of storage instructions in the software task process and the unit time required for the load-store function unit to execute storage instructions. The sum of these seven times is taken as the actual execution time.

[0084] The actual execution time can be calculated as: Actual execution time = num_all × T_get + num_all × T_decode + num_integer × T_integer + num_float × T_float + num_vector × T_vector + num_load × T_load + num_store × T_store.

[0085] Then, with the actual execution time being less than or equal to the maximum allowed time T as a constraint, the inequality is satisfied: num_all×T_get+num_all×T_decode+num_integer×T_integer+num_float×T_float+num_vector×T_vector+num_load×T_load+num_store×T_store≤T.

[0086] Here, num_all represents the total number of instructions required to execute the software task, num_integer represents the number of integer instructions, num_float represents the number of floating-point instructions, num_vector represents the number of vector instructions, num_load represents the number of load instructions, and num_store represents the number of store instructions.

[0087] Solving the above equation yields the optimal combination of T_get, T_decode, T_integer, T_float, T_vector, T_load, and T_store.

[0088] In this embodiment of the invention, determining the target time for a functional unit to execute a single instruction based on the actual execution time being less than or equal to the maximum allowed time may include: prioritizing load instructions and store instructions as the highest priority, and then determining the maximum execution time of a single instruction corresponding to the instruction type in descending order of priority, such as vector instructions, floating-point instructions, and integer instructions, to obtain the target time corresponding to each instruction type whose actual execution time is less than or equal to the maximum allowed time.

[0089] In other words, frequency resources can be allocated according to preset priorities. It can be understood that the lower the clock frequency, the longer the target time for a functional unit to execute a single instruction. Here, the target time is allocated from long to short as the priority from high to low, and then frequency resources are allocated accordingly: the first priority is to calculate the maximum value of T_load and T_store (to make the execution clock frequency of load and store instructions as low as possible), the second priority is to calculate the maximum value of T_vector (to make the execution clock frequency of vector instructions as low as possible), the third priority is to calculate the maximum value of T_float (to make the execution clock frequency of floating-point instructions as low as possible), and the fourth priority is to calculate the maximum value of T_integer (to make the execution clock frequency of integer instructions as low as possible).

[0090] Based on the obtained execution time parameters, the corresponding clock frequency combinations can be determined. The clock frequency is the reciprocal of the execution time. Specifically: the clock frequency of the fetch unit is 1 / T_get, the clock frequency of the decode unit is 1 / T_decode, the clock frequency of the integer arithmetic unit is 1 / T_integer, the clock frequency of the floating-point arithmetic unit is 1 / T_float, the clock frequency of the vector arithmetic unit is 1 / T_vector, and the clock frequency of the virtual address translation unit and the load / store unit is either 1 / T_load or 1 / T_store (whichever is larger).

[0091] In addition, when calculating the above formula, users can set a maximum value for T_get, T_decode, T_integer, T_float, T_vector, T_load, and T_store according to their own needs. This is the minimum value of the corresponding clock frequency. The purpose is to ensure that the instruction will not be blocked in the processing between the preceding and following stages.

[0092] The processor clock control method provided in this invention adds a clock frequency control module to the processor for adjusting the clock frequency of functional units. This clock frequency control module is connected to multiple functional units of the computing core. Based on the task information of the software task run by the computing core (including the number of various instructions), the execution time information required for each functional unit to execute instructions (including the time for each functional unit to execute a single instruction), and the performance requirements of the software task on the processor (including the maximum allowed time to complete the task), the method accurately calculates the combination of clock frequencies of multiple functional units that meet the performance requirements of the software task. This information is then sent to the computing core for the computing core to adjust the clock frequency of the functional units. This achieves precise configuration of the minimum clock frequency of each functional unit of the computing core according to the performance requirements of the software task executed by the computing core. It avoids the problem of excessive clock frequency caused by defaulting to the highest performance or a uniform fixed frequency for each functional unit in traditional solutions. Therefore, while meeting performance requirements, it can significantly reduce the dynamic power consumption of the computing core and achieve fine-grained power management of the processor.

[0093] Based on the above embodiments, the processor clock control method provided by the present invention may further include: acquiring the instruction characteristics of a software task within a predetermined instruction cycle; determining a first set of functional units used and a second set of functional units not used within the predetermined instruction cycle based on the instruction characteristics; turning off the clock of each functional unit in the second set of functional units, and keeping the clock of each functional unit in the first set of functional units enabled.

[0094] In practical implementation, the instruction analysis submodule can obtain the instructions of the task process running on the current computing core within a specified instruction cycle, and output the instruction type code based on the instruction type of the instructions within the instruction cycle. The functional unit enable control submodule determines whether to enable or disable the clock of each functional unit within the specified instruction cycle based on the instruction type code. Functional units used within the specified instruction cycle are grouped into the first functional unit set and their clocks are kept enabled, while unused functional units are grouped into the second functional unit set and their clocks are disabled. Because the software processes running on each computing core may be different, the real-time state of the clock enable of functional units on each computing core can be different and dynamically change.

[0095] The processor clock control method provided in this embodiment of the invention may further include: creating a first correspondence between instruction type combinations and corresponding instruction type codes. Obtaining the instruction characteristics of a software task within a predetermined instruction cycle may include: obtaining the corresponding instruction type code based on the instruction type combinations within the predetermined cycle and the first correspondence.

[0096] Specifically, the first correspondence can be represented as an instruction type analysis table (see Table 1 in the processor embodiment for details). This table records the correspondence between instruction type combinations (such as whether the instruction contains integer operations, floating-point operations, vector operations, memory access instructions, etc.) and instruction type codes. The instruction analysis submodule queries the first correspondence based on the instruction type combinations parsed within the agreed instruction cycle, and can then output the corresponding instruction type code.

[0097] The processor clock control method provided in this embodiment of the invention may further include: creating a second correspondence between instruction type codes and clock switch combinations of functional units. Determining a first set of functional units used and a second set of unused functional units within a predetermined instruction cycle based on instruction characteristics may include: obtaining a target clock switch combination based on the corresponding instruction type codes and the second correspondence; and determining the first set of functional units and the second set of functional units from the target clock switch combination.

[0098] Specifically, the second correspondence can be represented as a functional unit clock control table (see Table 2 in the processor embodiment for details). This table records the correspondence between instruction type codes and the clock enable or disable of each functional unit. The functional unit enable control submodule queries the second correspondence based on the received instruction type code to obtain the target clock switch combination corresponding to the code, and determines the functional units that need to enable the clock (i.e., the first set of functional units) and the functional units that need to disable the clock (i.e., the second set of functional units).

[0099] The processor clock control method provided in this embodiment of the invention may further include: adjusting the length of the agreed instruction cycle according to the number of branch instructions in the software task; wherein, the more branch instructions there are, the shorter the agreed instruction cycle is, and the fewer branch instructions there are, the longer the agreed instruction cycle is.

[0100] In practical implementation, the length of the agreed instruction cycle is adjusted through the instruction analysis cycle adjustment submodule. Since branch instructions can result in either a jump or no jump, the instruction analysis submodule may make prediction errors when selecting the branch direction. When a prediction error occurs, the clocks of all configurable functional units need to be enabled promptly to avoid delaying instruction execution. By dynamically adjusting the length of the agreed instruction cycle based on the number of branch instructions (a shorter cycle for more branch instructions and a longer cycle for fewer branch instructions), the probability of the instruction analysis submodule making errors in branch prediction within the instruction cycle can be reduced, maximizing the accuracy of the real-time settings for functional unit clock enable.

[0101] The processor clock control method provided in this invention obtains the instruction characteristics of a software task within a predetermined instruction cycle, determines the first set of functional units used and the second set of functional units not used within that cycle, shuts down the clocks of each functional unit in the second set of functional units, and keeps only the clocks of each functional unit in the first set of functional units enabled, thus achieving fine-grained clock switching control of the functional units inside the computing core. Because this invention can dynamically shut down unnecessary functional unit clocks according to the actual instruction requirements within the current instruction cycle, it avoids the power consumption waste caused by keeping all functional unit clocks enabled in traditional solutions, thereby significantly reducing the dynamic power consumption of open instruction set architecture processors while ensuring normal instruction execution.

[0102] Based on the above embodiments, the processor clock control method provided by the present invention may further include: when the computing core is in a sleep state, monitoring the frequency information of the wake-up event corresponding to the computing core; predicting the next expected occurrence time of the wake-up event based on the frequency information of the wake-up event; and performing a wake-up operation on the computing core at a preset time before the next expected occurrence time.

[0103] In practice, wake-up events can include external hardware interrupts and / or software tasks issued by the operating system.

[0104] Specifically, the interrupt task prediction submodule monitors the interrupt frequency (interval T_out_irq) of the external hardware interrupts corresponding to the computing core. When the computing core enters sleep mode, this submodule outputs an indication signal `pre_out_irq_come` T_set0 seconds before the next predicted interrupt arrival time. The kernel task prediction submodule monitors the time interval T_core_process at which the operating system issues software tasks to the computing core. When the computing core enters sleep mode, this submodule outputs an indication signal `pre_core_process_come` T_set1 seconds before the next predicted software task arrival time. The sleep mode graded wake-up submodule, based on the received indication signals, performs a wake-up operation in advance before the predicted wake-up event arrives, thereby achieving an early transition from sleep to working state and ensuring that critical tasks can be responded to in a timely manner.

[0105] In this embodiment of the invention, performing a wake-up operation on the computing core may include: tiered wake-up of the computing core; wherein, at least two wake-up levels are included: enabling the clock of the computing core and loading the cached data of the computing core.

[0106] Specifically, the sleep mode graded wake-up submodule, upon receiving `pre_out_irq_come` or `pre_core_process_come`, wakes up the corresponding computing core in a graded manner from sleep mode. The first level of wake-up enables the computing core's clock; the second level loads the computing core's cached data. By executing in steps, if a prediction error occurs, only the first level wake-up (enabling the clock) is completed without performing the second level wake-up (loading cached data). This avoids the power waste caused by fully waking the core to working mode due to prediction errors, achieving a combination of ensuring timely execution of critical processes and power management.

[0107] The processor clock control method provided in this embodiment of the invention may further include: adjusting the advance of a preset time relative to the next expected occurrence time based on the consistency between the prediction result of the wake-up operation and the actual occurrence of the wake-up event; wherein, the advance is increased when the prediction result is consistent with the actual occurrence, and decreased when the prediction result is inconsistent with the actual occurrence.

[0108] Specifically, T_set0 and T_set1 described above are dynamically changing. When the prediction is accurate, the value of T_set0 / T_set1 is adjusted to be larger to send an indication signal to the sleep mode graded wake-up submodule as early as possible for graded wake-up; when the prediction is inaccurate, the value of T_set0 / T_set1 is adjusted to be smaller to send an indication signal to the graded wake-up submodule as late as possible, thus minimizing the probability of "inaccurate prediction after wake-up". Through this adaptive adjustment strategy, the core can have more time to recover to the working state when the prediction is accurate, and unnecessary power consumption can be minimized when the prediction is inaccurate.

[0109] The processor clock control method provided in this invention monitors the frequency of wake-up events when the computing core is in sleep mode, predicts the next expected occurrence time of the wake-up event based on historical occurrence patterns, and executes the wake-up operation at a preset time before the expected occurrence time, thus achieving proactive predictive wake-up. Because this invention can initiate the wake-up process before the actual arrival of the wake-up event, it avoids the long wait (hundreds of milliseconds) caused by the traditional approach where the recovery process only begins after the wake-up event arrives. This significantly shortens the response latency of the computing core from sleep mode to working mode, ensuring that critical tasks can be executed promptly and quickly. Simultaneously, through a tiered wake-up mechanism and adaptive adjustment of the lead time, it can minimize power waste caused by prediction errors while ensuring timely response to critical tasks, achieving a dynamic balance between processor response speed and power management.

[0110] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Since the processor clock control method provided in the embodiments of the present invention corresponds to the processor provided in the embodiments of the present invention, the parts not described in the method embodiments can be referred to the description of the processor embodiments.

[0111] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the processor clock control method embodiments described above when running.

[0112] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0113] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the processor clock control method embodiments described above.

[0114] Embodiments of the present invention also provide another computer program product, including a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the processor clock control method embodiments described above.

[0115] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0116] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0117] The processor, processor clock control method, storage medium, and program product provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A processor, comprising: include: At least one computing core and clock frequency control module; The computing core includes multiple functional units; The clock frequency control module is connected to multiple functional units and is used to determine the clock frequency combination of multiple functional units that meet the performance requirements of the software task running by the computing core, the execution time information required by the functional units to execute instructions, and the performance requirements of the software task on the processor, and to send the information of the clock frequency combination to the computing core so that the computing core can adjust the clock frequency of the functional units. The task information includes the instruction types and the corresponding number of instructions included in the process of the software task run by the computing core; the performance requirement information includes the maximum allowed time to complete the software task. Based on the task information of the software task running by the computing core, the execution time information required for the functional units to execute instructions, and the performance requirements of the software task on the processor, a combination of clock frequencies of multiple functional units that meet the performance requirements of the software task is determined, including: The actual execution time of the computing core in executing the software task is determined based on the number of instructions of the instruction type and the execution time of a single instruction executed by the corresponding functional unit. The target time for the functional unit to execute a single instruction is determined based on the actual execution time being less than or equal to the maximum allowed time. The target clock frequency of the functional unit is obtained based on the target time.

2. The processor of claim 1, wherein, It also includes a clock switch control module; The clock switch control module is connected to multiple functional units and is used to obtain the instruction characteristics of the software task within a predetermined instruction cycle, determine the first set of functional units used and the second set of functional units not used within the predetermined instruction cycle based on the instruction characteristics, turn off the clock of each functional unit in the second set of functional units, and keep the clock of each functional unit in the first set of functional units enabled.

3. The processor of claim 1, wherein, It also includes a clock wake-up control module; The clock wake-up control module is connected to the computing core and is used to monitor the frequency information of the wake-up event corresponding to the computing core when the computing core is in a sleep state, predict the next expected occurrence time of the wake-up event based on the frequency information of the wake-up event, and perform a wake-up operation on the computing core at a preset time before the next expected occurrence time.

4. The processor of any one of claims 1 to 3, wherein, The processor is an open instruction set architecture processor.

5. A processor clock control method, characterized by, Applied to the processor according to any one of claims 1 to 4, comprising: Obtain task information of the software task running by the computing core of the processor, execution time information required by the computing core to execute instructions, and performance requirements of the software task on the processor; Based on the task information, the execution time information, and the performance requirement information, determine the clock frequency combination of multiple functional units that meet the performance requirements of the software task; The information of the clock frequency combination is sent to the computing core so that the computing core can adjust the clock frequency of the functional unit; The task information includes the instruction types and the corresponding number of instructions included in the process of the software task run by the computing core; the performance requirement information includes the maximum allowed time to complete the software task. Based on the task information, the execution time information, and the performance requirement information, determine a combination of clock frequencies for multiple functional units that meet the performance requirements of the software task, including: The actual execution time of the computing core in executing the software task is determined based on the number of instructions of the instruction type and the execution time of a single instruction executed by the corresponding functional unit. The target time for the functional unit to execute a single instruction is determined based on the actual execution time being less than or equal to the maximum allowed time. The target clock frequency of the functional unit is obtained based on the target time.

6. The processor clock control method of claim 5, wherein, The actual execution time of the computing core in executing the software task is determined based on the number of instructions of the instruction type and the execution time of a single instruction by the corresponding functional unit, including: Based on the total number of instructions required to be executed by the process of the software task and the instruction fetching unit time of the computing core, the first time required for the computing core to execute the instruction fetching task is determined. Based on the total number of instructions and the instruction decoding unit time of the decoding function unit of the computing core, the second time required for the computing core to execute the instruction decoding task is determined; Based on the number of integer instructions in the process of the software task and the unit time required for the integer operation subunit of the computing core to execute the integer instructions, a third time required for the computing core to execute the integer operation task is determined. Based on the number of floating-point instructions in the process of the software task and the unit time required for the floating-point operation subunit of the computing core to execute the floating-point instructions, the fourth time required for the computing core to execute the floating-point operation task is determined. Based on the number of vector instructions in the process of the software task and the unit time required for the vector operation subunit of the computing core to execute the vector instructions, the fifth time required for the computing core to execute the vector operation task is determined. Based on the number of loading instructions in the process of the software task and the unit time required for the loading and storage function unit of the computing core to execute the loading instructions, the sixth time required for the computing core to execute the loading task is determined. Based on the number of storage instructions in the process of the software task and the unit time required for the loading storage function unit to execute the storage instructions, the seventh time required for the computing core to execute the storage task is determined. The sum of the first time, the second time, the third time, the fourth time, the fifth time, the sixth time, and the seventh time is taken as the actual execution time.

7. The processor clock control method of claim 5, wherein, Determining the target time for the functional unit to execute a single instruction, based on the actual execution time being less than or equal to the maximum allowed time, includes: Load instructions and store instructions are given the highest priority. Then, vector instructions, floating-point instructions, and integer instructions are ordered in descending order of priority to determine the maximum execution time of a single instruction corresponding to each instruction type. This yields the target time for each instruction type whose actual execution time is less than or equal to the maximum allowed time.

8. The processor clock control method of claim 5, wherein, Also includes: Obtain the instruction characteristics of the software task within the agreed instruction cycle; Based on the instruction characteristics, determine the first set of functional units used and the second set of functional units not used within the agreed instruction cycle; Turn off the clocks of each functional unit in the second set of functional units, and keep the clocks of each functional unit in the first set of functional units enabled.

9. The processor clock control method of claim 8, wherein, Also includes: Establish the first correspondence between instruction type combinations and their corresponding instruction type codes; Obtaining the instruction characteristics of the software task within a predetermined instruction cycle includes: Based on the combination of instruction types within the agreed instruction cycle and the first correspondence, the corresponding instruction type code is obtained.

10. The processor clock control method of claim 8, wherein, Also includes: Create a second correspondence between the instruction type code and the clock switch combination of the functional unit; Determining the first set of functional units used and the second set of functional units not used within the agreed instruction cycle based on the instruction characteristics includes: The target clock switch combination is obtained based on the corresponding instruction type code and the second correspondence. The first set of functional units and the second set of functional units are determined from the target clock switch combination.

11. The processor clock control method of claim 8, wherein, Also includes: The length of the agreed instruction cycle is adjusted according to the number of branch instructions in the software task; The more branch instructions there are, the shorter the agreed instruction cycle is; the fewer branch instructions there are, the longer the agreed instruction cycle is.

12. The processor clock control method of claim 5, wherein, Also includes: When the computing core is in sleep mode, monitor the frequency information of the wake-up events corresponding to the computing core; Predict the next expected occurrence time of the wake-up event based on the frequency information of the wake-up event; A wake-up operation is performed on the computing core at a preset time before the next expected occurrence time.

13. The processor clock control method of claim 12, wherein, The wake-up event includes external hardware interrupts and / or software tasks issued by the operating system.

14. The processor clock control method of claim 12, wherein, Performing a wake-up operation on the computing core includes: The computing cores are activated in stages; This includes at least two wake-up levels: enabling the clock of the computing core and loading the cached data of the computing core.

15. The processor clock control method of claim 12, wherein, Also includes: Based on the consistency between the predicted result of the wake-up operation and the actual occurrence of the wake-up event, the advance amount of the preset time relative to the next expected occurrence time is adjusted. Specifically, the lead time is increased when the prediction result matches the actual occurrence, and decreased when the prediction result does not match the actual occurrence.

16. The processor clock control method according to any one of claims 5 to 14, wherein The processor includes multiple computing cores, and the clock frequency of the functional units on different computing cores is configured independently.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the processor clock control method as described in any one of claims 5 to 16.

18. A computer program product comprising a computer program, characterized in that, The computer program, which is executed by a processor, implements the steps of the processor clock control method according to any one of claims 5 to 16 when a processor executes the computer program.

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