Flash memory controller, control method of flash memory controller, and electronic device using the same
By switching the read voltage table using a multi-channel flash memory controller, the problems of long flash memory read operation time and frequent errors are solved, and more efficient read operation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 深圳市欣芯半导体有限公司
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Temperature variations in flash memory cause read operations to take too long and are prone to unpredictable errors. Existing flash memory controllers require the use of different read voltage tables multiple times during read operations, resulting in low efficiency.
By using a multi-channel coupled flash memory module, read operations are performed using first and second read voltage tables. When the first channel fails, the system switches to the second table, and upon success, it is defined as the target table for subsequent operations, reducing the time spent on repeated testing.
This improves the success rate of read operations, saves read time, and enhances the efficiency of the flash memory controller.
Smart Images
Figure CN122240006A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more particularly to a flash memory controller and its control method. Background Technology
[0002] Flash memory is a type of non-volatile solid-state storage, widely used in memory cards and USB flash drives, and in recent years has also been widely used in mobile electronic devices. In use, flash memory typically requires a flash memory controller to manage the data stored in it and to communicate with computers or electronic devices.
[0003] The reliability of data in flash memory is affected by temperature. For example, the temperature of flash memory increases as the data access speed increases. When the temperature exceeds the allowable operating range, unexpected errors are likely to occur when executing read or write commands, or even cause the flash memory to fail.
[0004] Flash memory controllers read contents of the flash memory by applying threshold voltages to its data lines. These threshold voltages are typically recorded in read voltage tables, and the controller may include multiple read voltage tables. For example, a flash memory controller can use the same threshold voltage setting to read multiple pages located in the same block, and it uses the read voltage tables in the same order for each read operation; that is, it uses different read voltage tables sequentially when a read failure occurs. Since memory cells that are frequently operated on together may have similar characteristics, this can lead to multiple read voltage table operations for each read, resulting in significant time consumption.
[0005] Therefore, providing an electronic device that can improve the above-mentioned problems, including a flash memory controller, a control method for the flash memory controller, and its application, is one of the important current research topics. Summary of the Invention
[0006] To achieve the above objectives, the present invention provides a flash memory controller, a control method for the flash memory controller, and an electronic device for the application of the same, which can save the time consumed by the read operation.
[0007] This invention provides a flash memory controller for coupling to a flash memory module via multiple channels, wherein the multiple channels include a first channel and a second channel. The flash memory controller includes a memory and a processor. The memory stores multiple read voltage tables and an index register, wherein the multiple voltage read tables include a first read voltage table and a second read voltage table. The processor is coupled to the memory and the flash memory module for performing a read operation via the multiple channels. When an error occurs during a read operation using the first read voltage table via the first channel, the second read voltage table is selected to perform the read operation via the first channel. When a read operation using the second read voltage table via the first channel is successful, the second read voltage table is defined as a target read voltage table, and a read operation is subsequently performed on the second channel using the target read voltage table.
[0008] In one embodiment, the flash memory module includes a plurality of chip enable spaces, each chip enable space including a plurality of chips, and each chip enable space is coupled to one of a plurality of channels.
[0009] In one embodiment, after a successful read operation on the first channel, the processor updates the index register to the index value corresponding to the target read voltage table.
[0010] In addition, to achieve the above objectives, the present invention also provides an electronic device including a flash memory module and a flash memory controller. The flash memory controller is coupled to the flash memory module via multiple channels, including a first channel and a second channel. The flash memory controller includes a memory and a processor. The memory stores multiple read voltage tables and an index register. The processor is coupled to the memory and the flash memory module and is used to perform a read operation via the multiple channels, wherein the multiple voltage read tables include a first read voltage table and a second read voltage table. When an error occurs during a read operation using the first read voltage table via the first channel, a second read voltage table is selected to perform the read operation via the first channel. When a read operation using the second read voltage table via the first channel is successful, the second read voltage table is defined as a target read voltage table, and a read operation is subsequently performed on the second channel using the target read voltage table.
[0011] Furthermore, to achieve the above objectives, the present invention also provides a control method for a flash memory controller, wherein the flash memory controller is coupled to a flash memory module via multiple channels, and the flash memory controller has a memory and a processor coupled to each other. The memory stores multiple read voltage tables, including a first read voltage table and a second read voltage table, and the multiple channels include a first channel and a second channel. The control method for the flash memory controller includes: performing a read operation on the flash memory module using the first read voltage table in the memory via the first channel; when an error occurs during the read operation, selecting the second read voltage table to perform a read operation on the flash memory module via the first channel; when the read operation on the flash memory module using the second read voltage table via the first channel is successful, defining the second read voltage table as a target read voltage table; and subsequently performing the read operation on the flash memory module using the target read voltage table via the second channel.
[0012] In one embodiment, the first read voltage table or the second read voltage table is selected by a processor of the flash memory controller in response to a received read instruction, corresponding to an initial index value stored in the index register.
[0013] In one embodiment, when the read operation is successful, the initial index value is updated to an index value of the corresponding target read voltage table. Attached Figure Description
[0014] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0015] Figure 1 This is a block diagram of an electronic device including a flash memory module and a flash memory controller according to a preferred embodiment of the present invention.
[0016] Figure 2 This is a schematic diagram of the architecture of a flash memory module according to a preferred embodiment of the present invention.
[0017] Figure 3 This is a schematic diagram of a map table according to a preferred embodiment of the present invention.
[0018] Figure 4 This is a schematic diagram showing the correspondence between the super page, the index register, and the read voltage table according to a preferred embodiment of the present invention.
[0019] Figure 5 This is a flowchart of the operation method of a flash memory controller according to a preferred embodiment of the present invention.
[0020] Figure 6 This is a schematic diagram illustrating the operation method of a flash memory controller using a read voltage table according to an embodiment of the present invention.
[0021] Figure 7 This is a schematic diagram of a method of operating a flash memory controller to read a voltage table according to another embodiment of the present invention.
[0022] Figure label:
[0023] 10: Electronic devices
[0024] 100: Memory device
[0025] 110: Flash memory module
[0026] 111: The First Chip Enables Space
[0027] 112: Second Chip Enablement Space
[0028] 113: The Third Chip Enables Space
[0029] 114: The Fourth Chip Enablement Space
[0030] C1~C16: Chips
[0031] SP0~SPn: Super Page
[0032] 120: Flash memory controller
[0033] 121: Processor
[0034] CH(0)~CH(3): Channels
[0035] CE(0)~CE(3): Chip enable signals
[0036] 122: Memory
[0037] ID0~IDn: Index Registers
[0038] TA: Image Table
[0039] TB0~TBk: Read voltage table
[0040] 123: Memory Interface
[0041] 124: Host Interface
[0042] 130: Host terminal device
[0043] P1: First period
[0044] P2: Second period
[0045] P3: Third period
[0046] P4: Fourth Period
[0047] P5: Fifth Period
[0048] P6: Sixth Period
[0049] S11-S14: Steps Detailed Implementation
[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0051] Figure 1 This is a schematic diagram of an electronic device 10 according to a preferred embodiment of the present invention. The electronic device 10 includes a host device 130 and a memory device 100. The memory device 100 includes a flash memory module 110 and a flash memory controller 120, wherein the flash memory controller 120 is used to access the flash memory module 110.
[0052] In this embodiment, the memory device 100 can be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the host device 130 is another electronic device that can be connected to the memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 can be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded MultiMedia Card (EMMC) specifications, and can be installed in the electronic device 10, such as in a mobile phone, laptop, or desktop computer. In this case, the host device 130 can be a processor of the electronic device 10.
[0053] The flash memory controller 120 includes a processor 121, a memory 122, a memory interface 123, and a host interface 124, all coupled to each other. The memory 122 stores multiple index registers ID0 to IDn, a mapping table TA, and multiple read voltage tables TB0 to TBk, where k is a positive integer greater than 1. The memory interface 123 serves as the connection interface between the flash memory controller 120 and the flash memory module 110 for data transfer. The host interface 124 serves as the connection interface between the flash memory controller 120 and the host device 130 for data transfer. In this embodiment, the host interface 124 can receive read, write, or erase commands sent by the host device 130.
[0054] The flash memory module 110 may store internal system program code, which may include write / read command program code associated with handling write or read operations, or error correction code (ECC) associated with handling error checking. Furthermore, as... Figure 2 As shown, the flash memory module 110 also includes multiple flash memory chips, such as chips C1, C2...CN, where N is a positive integer greater than 1. In this embodiment, the flash memory module 110 includes 16 chips (e.g., ...). Figure 2 (As shown) for example, but not as a limitation. Each chip C1 to C16 of the flash memory module 110 includes multiple blocks, and each block includes multiple pages. A page is typically the smallest unit of programming. That is, a page is the smallest unit for writing or reading data. When accessing one or more pages of data, the flash memory controller 120 accesses the data of one or more pages according to preset access parameters and performs decoding operations on the data of the accessed pages. In this embodiment, the flash memory module 110 is a NAND-type flash memory module, but not as a limitation.
[0055] Please also refer to Figure 1 and Figure 2The flash memory controller 120 accesses the flash memory module 110 in parallel via multiple channels. In this embodiment, the processor 121 of the flash memory controller 120 includes four channels CH(0) to CH(3), and each channel is shared by four chips, unless otherwise specified. The flash memory module 110 includes a first chip enable space 111, a second chip enable space 112, a third chip enable space 113, and a fourth chip enable space 114. The processor 121 of the flash memory controller 120 is coupled to the first chip enable space 111, the second chip enable space 112, the third chip enable space 113, and the fourth chip enable space 114 of the flash memory module 110 through channels CH(0) to CH(3) to transmit data and commands. The processor 121 of the flash memory controller 120 transmits chip enable signals CE(0) to CE(3) to access the corresponding chip enable space on the corresponding channel. Specifically, in this embodiment, the processor 121 uses multiple electronic signals to coordinate data and command transmission between the flash memory controller 120 and the flash memory module 110, including data lines, frequency signals, and control signals. The data lines can be used to transmit commands, addresses, and data for reading and writing. The control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE).
[0056] like Figure 2 As shown, chip enable signal CE(0) enables chips C1 to C4 located on all channels CH(0) to CH(3) and in the first chip enable space 111. Chip enable signal CE(1) enables chips C5 to C8 located on all channels CH(0) to CH(3) and in the second chip enable space 112. Chip enable signal CE(2) enables chips C9 to C12 located on all channels CH(0) to CH(3) and in the third chip enable space 113. Chip enable signal CE(3) enables chips C13 to C16 located on all channels CH(0) to CH(3) and in the fourth chip enable space 114. In this embodiment, chip enable signals CE(0), CE(1), CE(2), and CE(3) are enabled in an interleaved manner. Through multiple channels CH(0)~CH(3), the chip enable space 111~114, which is enabled by the chip enable signals CE(0)~CE(3) in one cycle, is accessed in parallel.
[0057] Figure 3This is a schematic diagram of the image table TA according to this embodiment. The image table TA contains multiple index values 0 to k, and records that index values 0 to k correspond to reading voltage tables TB0 to TBk respectively. Each of the index registers ID0 to IDn is used to store one of the index values 0 to k. For example, index registers ID0 and ID1 can store the same index value 1; index register ID2 can store index value 3, and so on.
[0058] Please refer to the following at the same time Figure 3 and Figure 4 ,in Figure 4 This is a schematic diagram illustrating the correspondence between the superpages SP0-SPn, the index registers ID0-IDn, and the read voltage tables TB0-TBk according to this embodiment. Here, Figure 4 Taking chips C1 to C4 as an example, pages with the same physical location in chips C1 to C4 can be merged into superpages SP0 to SPn. For example, multiple pages 0 are merged into superpage SP0; multiple pages 1 are merged into superpage SP2; and multiple pages n are merged into superpage SPn, and so on, where n is a positive integer greater than 1. Index registers ID0 to IDn correspond to superpages SP0 to SPn, respectively. A superpage is the smallest unit when processor 121 reads flash memory module 110. Processor 121 is used to read a superpage simultaneously through channels CH(0) to CH(3), and processor 121 will perform read operations on the superpage according to the stored data in the index register corresponding to the superpage.
[0059] For example, such as Figure 4 As shown, when processor 121 reads superpage SP0, it uses the read voltage table TB1 corresponding to index value 1, based on the index value 1 stored in index register ID0 and the mapping relationship of index value 1 in the mapping table TA, to read superpage SP0. Similarly, since index value 1 is stored in index register ID1, processor 121 uses read voltage table TB1 to read superpage SP1. And, for example, since index value k is stored in index register IDn, processor 121 uses read voltage table TBk to read superpage SPn.
[0060] The following explains the purpose of the read voltage tables TB1 to TBk. When reading the flash memory module 110, the processor 121 applies one or more threshold voltages sequentially to the data lines to determine the bit values stored in the memory cells of the flash memory module 110. Each of the read voltage tables TB0 to TBk records the offset of the aforementioned one or more threshold voltages. The processor 121 can adjust the threshold voltage applied to the data lines based on the offset recorded in the read voltage tables TB0 to TBk to compensate for the threshold voltage variations of the flash memory module 110 under different usage conditions (e.g., ambient temperature or total usage time).
[0061] When a read error occurs during the reading of a superpage by the processor 121 (e.g., an ECC check error occurs), the processor 121 can update the index value register corresponding to the superpage so that a read voltage table with better compensation effect can be used in subsequent read operations.
[0062] Figure 5 This is a flowchart illustrating the operation method of a flash memory controller according to a preferred embodiment of the present invention. The operation method is applicable to the aforementioned flash memory controller 120. In the following embodiments, it is assumed that the flash memory controller 120 reads superpage SP0 and adaptively updates the index register ID0 of superpage SP0, but the present invention is not limited thereto. The index registers ID1 to IDn of other superpages SP1 to SPn can also be adaptively updated in a similar manner; for the sake of brevity, they will not be repeated here.
[0063] In step S11, in response to receiving a read instruction for superpage SP0, processor 121 accesses index register ID0, which corresponds to superpage SP0, among the multiple index registers ID0 to IDn of memory 122. Therefore, processor 121 obtains the initial index value (e.g., index value 0) stored in index register ID0. In step S12, processor 121 executes a first process, which selects read voltage table TB0 from the multiple read voltage tables TB0 to TBk corresponding to the initial index value, based on the mapping relationship of the initial index value (e.g., index value 0) in the mapping table TA. Figure 4 As shown. Next, the first pass, through channel CH0, uses the read voltage table TB0 to perform a read operation on the portion of chip C1 belonging to super page SP0. Specifically, the first pass determines one or more threshold voltages applied to multiple data lines of the flash memory module 110 based on the read voltage table TB0 to perform its read operation on the portion of chip C1 belonging to super page SP0. For ease of understanding, the first pass... Figure 5In the embodiments described, a read operation is performed through channel CH0, but the invention is not limited thereto. In some embodiments, the first process can perform a read operation through any of channels CH0 to CH3. In step S13, when an error occurs in the read operation of the first process (or channel CH0) (e.g., an ECC check error occurs), the first process sequentially uses read voltage tables TB1 to TBk through channel CH0 to perform a first reread of chip C1 according to the previously used read voltage table TB0, until the first reread is successfully performed using one of the read voltage tables TB1 to TBk. Specifically, the first process first uses read voltage table TB1 to determine the threshold voltage applied to the data line, reads the bit value of the memory cell belonging to super page SP0 in chip C1, and determines whether an ECC check error has occurred. If an ECC check error occurs, it means that the first reread has failed, and the first process then uses read voltage table TB2 to determine the threshold voltage applied to the data line to read the bit value of the memory cell belonging to super page SP0 in chip C1, and determines whether an ECC check error has occurred, and so on. On the other hand, if the ECC check of the first reread is correct after using a certain read voltage table in the first stroke, it means that the first reread is successful, and the flash controller 120 ends step S13, and so on.
[0064] In step S14, when the first reread is successfully executed, the first process updates the index register ID0 to the index value corresponding to the read voltage table of the successful first reread. In this embodiment, for ease of explanation, the read voltage table corresponding to the successful first reread is defined as the target read table. In other words, the subsequent second process will use the target read voltage table as the initial read voltage table.
[0065] The following two embodiments illustrate the operation method of the flash memory controller according to a preferred embodiment of the present invention. The first embodiment is as follows: Figure 6As shown, in the first time period P1, the first process first attempts to reread the voltage table TB0 based on the index value 0 of the index register ID0, but this fails. In the second time period P2, the first process attempts to reread the voltage table TB1 again, but this also fails. In the third time period P3, the first process attempts to reread the voltage table TB2, and this succeeds. At this point, the index value 2 corresponding to the voltage table TB2 is written to the corresponding index register ID0. In the fourth time period P4, the second process attempts to reread the voltage table TB2 based on the index value 2 in the index register ID0, and this succeeds. In the fifth time period P5, the third process attempts to reread the voltage table TB2 based on the index value 2 in the index register ID0, and this succeeds. In the sixth time period P6, the fourth process attempts to reread the voltage table TB2 based on the index value 2 in the index register ID0, and this succeeds.
[0066] The second implementation example Figure 7 As shown, in time period P1, the first process first attempts to reread the voltage table TB0 based on the index value 0 of the index register ID0, but this fails. In the second time period P2, the first process attempts to reread the voltage table TB1, and this succeeds. At this time, the index value 1 corresponding to the voltage table TB1 is written to the corresponding index register ID0. In the third time period P3, the second process also attempts to reread the voltage table TB1 based on the index value 1 in the index register ID0, and this succeeds. In the fourth time period P4, the third process attempts to reread the voltage table TB1 based on the index value 1 in the index register ID0, but this fails. In the fifth time period P5, the third process attempts to reread the voltage table TB2, and this succeeds. At this time, the index value 2 corresponding to the voltage table TB2 is written to the corresponding index register ID0. In the sixth time period P6, the fourth process attempts to reread the voltage table TB2 based on the index value 2 in the index register ID0, and this succeeds.
[0067] Since flash memory modules that are frequently operated together (e.g., multiple pages within the same block) may have similar characteristics, directly selecting the read voltage table from the previous successful reread can effectively save time wasted from starting the test from the initial read voltage table. It is worth noting that the above embodiment selects the next read voltage table when a reread fails; however, this is not a limitation. In other embodiments, any other read voltage table can be selected after a reread failure. In other words, the main point of this invention is that when a reread is successful, the same read voltage table will be used in the next pass.
[0068] In summary, the flash memory controller, the control method for the flash memory controller, and the electronic device using the present invention, when a read operation is successful, define the corresponding read voltage table as the target read voltage table, and use the target read voltage table as the initial read voltage table for subsequent read operations. Since chips that are frequently operated together may have similar characteristics, the probability of successful reads can be significantly increased, thus saving read operation time.
[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A flash memory controller for coupling to a flash memory module via a plurality of channels, wherein the plurality of channels includes a first channel and a second channel, characterized in that, include: A memory for storing a plurality of voltage read tables and an index register, wherein the plurality of voltage read tables include a first voltage read table and a second voltage read table; as well as A processor, coupled to the memory and the flash memory module, is configured to perform a read operation through the plurality of channels. Specifically, when an error occurs during the read operation performed using the first read voltage table through the first channel, the second read voltage table is selected to perform the read operation through the first channel. When the read operation performed using the second read voltage table through the first channel is successful, the second read voltage table is defined as a target read voltage table, and the target read voltage table is subsequently used to perform the read operation through the second channel.
2. The flash memory controller as described in claim 1, characterized in that, The flash memory module includes multiple chip enable spaces, each chip enable space includes multiple chips, and each chip enable space is coupled to one of the multiple channels.
3. The flash memory controller as described in claim 1, characterized in that, After the read operation on the first channel is successful, the processor updates the index register to an index value corresponding to the target read voltage table.
4. An electronic device, characterized in that, include: One flash memory module; as well as A flash memory controller is configured to be coupled to the flash memory module via multiple channels, wherein the multiple channels include a first channel and a second channel, and wherein the flash memory controller includes: A memory for storing a plurality of voltage read tables and an index register, wherein the plurality of voltage read tables include a first voltage read table and a second voltage read table; and A processor, coupled to the memory and the flash memory module, is configured to perform a read operation through the plurality of channels. Specifically, when an error occurs during the read operation performed using the first read voltage table through the first channel, the second read voltage table is selected to perform the read operation through the first channel. When the read operation performed using the second read voltage table through the first channel is successful, the second read voltage table is defined as a target read voltage table, and the target read voltage table is subsequently used to perform the read operation through the second channel.
5. The electronic device as claimed in claim 4, characterized in that, The flash memory module includes multiple chip enable spaces, each chip enable space includes multiple chips, and each chip enable space is coupled to one of the multiple channels.
6. The electronic device as claimed in claim 4, characterized in that, After the read operation on the first channel is successful, the processor updates the index register to... Corresponding to the target read voltage table An index value.
7. A control method for a flash memory controller, wherein the flash memory controller is coupled to a flash memory module via multiple channels, the flash memory controller has a memory and a processor coupled to each other, the memory stores multiple read voltage tables, wherein the multiple read voltage tables include a first read voltage table and a second read voltage table, and the multiple channels include a first channel and a second channel, characterized in that, The control method of the flash memory controller includes: A read operation is performed on the flash memory module through the first channel using the first read voltage table; When an error occurs during the read operation, the second read voltage table is selected to perform the read operation on the flash memory module through the first channel; When the read operation performed on the flash memory module using the second read voltage table through the first channel is successful, the second read voltage table is defined as a target read voltage table; and The target read voltage table is then used to perform the read operation on the flash memory module through the second channel.
8. The control method as described in claim 7, characterized in that, The first read voltage table or the second read voltage table is selected by a processor of the flash memory controller in response to a received read instruction, corresponding to an initial index value stored in the index register.
9. The control method as described in claim 8, characterized in that, When the read operation is successful, the initial index value is updated to an index value of the corresponding target read voltage table.