An automatic vectorization acceleration method for a homemade mai create architecture and related device

Abstract

The application belongs to the technical field of artificial intelligence and high-performance computing, and discloses an automatic vectorization acceleration method for a domestic Maixian architecture and a related device, which comprises the following steps: obtaining a scalar program code segment provided by a user as source code; inputting the source code into an automatic vectorization tool MT-Vectorizer to output a vectorization version code; the automatic vectorization tool MT-Vectorizer comprises an analysis intelligent agent; the analysis intelligent agent is used for performing static analysis on the source code to obtain a source code static analysis result; based on the source code static analysis result, a function interface required by the source code and a vectorization strategy required by the source code are selected; based on the source code, the source code static analysis result, the function interface required by the source code, the vectorization strategy required by the source code and a predetermined standardized vectorization strategy template, a prompt word is constructed to obtain a customized prompt word; and the application realizes efficient and automatic generation of vectorization codes suitable for the domestic Maixian architecture.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence and high-performance computing technology, and relates to computer architecture and parallel programming technology. In particular, it relates to an automatic vectorization acceleration method and related device for the domestic Maichuang architecture. Background Technology

[0002] In data-driven high-performance computing (HPC) and artificial intelligence (AI) applications, loop vectorization plays a crucial role in accelerating computational performance. Through loop vectorization, processors can perform parallel operations on entire data blocks in a single instruction, significantly improving computational efficiency compared to element-wise processing. Over the past few decades, compilers have made continuous progress in automatic vectorization, playing a vital role in many scenarios. However, traditional compilers often fail to implement vectorization optimization when faced with complex control flows, alias relationships, and multi-level memory accesses due to the inaccuracy of static analysis. Furthermore, conservative performance overhead models make compilers cautious in determining the profitability of vectorization, easily missing potential optimization opportunities.

[0003] To enable users to directly leverage vectorization optimization opportunities, manual optimization methods based on vector component instruction sets such as Single Instruction Multiple Data (SIMD) have emerged. For example, efficient parallel computing can be achieved by calling low-level instructions through compiler-built-in functions in the C language. However, SIMD-based manual optimization methods rely on developers manually ensuring the correctness of the vectorized code, making the writing and debugging process complex and costly. This primarily targets expert users with experience in system architecture and vectorization, limiting its widespread application. With the rapid development of Large Language Models (LLMs), a new approach has been provided to address the shortcomings of SIMD-based manual optimization methods. LLMs demonstrate the potential to directly convert natural language instructions into high-performance code in the field of code generation and conversion, potentially making vectorization technology accessible to the general public rather than an expert skill.

[0004] However, when facing domestically developed architectures, such as the domestically produced heterogeneous processor (MT-3000 processor), large language models have a limited ability to understand and optimize the platform code, making it difficult to achieve the desired acceleration effect. Specifically, the compiler for the MT-3000 platform currently does not support automatic vectorization, which is in stark contrast to mainstream CPU platforms. Developers must manually write and debug complex vectorization code. Secondly, in terms of the software ecosystem, publicly available high-performance programs for the MT-3000 processor are extremely scarce. Almost all commercial large models have not encountered the platform code during their pre-training phase, making it difficult for large models to understand, optimize, or even refactor the platform code. In addition, the number of available high-quality programs is far from meeting the needs of large-scale fine-tuning, and the cost of fine-tuning is high. It is almost impossible to teach large models to optimize MT-3000 processor code through the traditional "pre-training + fine-tuning" approach. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention provides an automatic vectorization acceleration method and related device for the domestic Maichuang architecture, in order to solve the technical problem that when facing the domestic Maichuang architecture, the large language model has priority in understanding and optimizing its platform code, making it difficult to achieve the ideal acceleration effect.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This invention provides an automatic vectorization acceleration method for the domestically developed Mytron architecture, comprising: Obtain the scalar program code snippet provided by the user as the source code; Input the source code into the automatic vectorization tool MT-Vectorizer, and the output will be the vectorized version of the code; The automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module. An analytical agent is used to perform static analysis on the source code and obtain the static analysis results. Based on the static analysis results, the required function interfaces and vectorization strategies of the source code are selected. Based on the source code, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template, prompt words are constructed to obtain customized prompt words. Vectorized agents are used to generate initial vectorized code based on customized prompt words and a predefined large language model; The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code.

[0007] Furthermore, the process of performing static analysis on the source code and obtaining the static analysis results is as follows: Using a predefined lightweight large language model, static analysis is performed on the source code to identify the mathematical and computational functions called in the source code, as well as the memory access characteristics and computational logic of the source code. According to predefined algorithm types, combined with the memory access characteristics and computational logic of the source code, the source code is classified into algorithms to obtain the algorithm patterns contained in the source code. According to a preset output format, the mathematical functions called in the source code and the algorithm patterns contained in the source code are output to obtain the static analysis results of the source code.

[0008] Furthermore, the predefined algorithm types include Stencil, MatMul, MatVec, Elementwise, Factorization, and Irregular.

[0009] Furthermore, the predefined standardized vectorization strategy templates include multi-threaded task partitioning strategy templates, resource allocation and preprocessing strategy templates, block pipeline processing strategy templates, scalar tail processing strategy templates, and resource release strategy templates. The block pipeline processing strategy template is used to load data from off-chip global memory to on-chip vector cache via direct memory access; construct a vectorized loop to load data from on-chip vector cache to vector register, execute predetermined core calculation instructions, obtain updated data and write it back to on-chip vector cache; and write the updated data from on-chip vector cache back to off-chip global memory. A multi-threaded task partitioning strategy template is used to partition computational tasks and determine the data processing scope of the current thread; Resource allocation and preprocessing strategy templates are used to allocate on-chip vector cache space and complete the broadcast operation of scalar coefficients; Scalar tail processing strategy template, used to handle the tail of data that is not divisible by the vector length; Resource release strategy templates are used to explicitly release the allocated on-chip vector cache space.

[0010] Furthermore, the initial vectorized code was tested, and the resulting vectorized version of the code was output as follows: Perform syntax and functional correctness checks on the initial vectorized code and obtain the check results; If the verification result is successful, the initial vectorized code is directly output to obtain the vectorized version code; if the verification result is unsuccessful, compilation error information is generated and sent to the vectorized agent.

[0011] Furthermore, the vectorized agent is also used to respond to compilation error messages, iteratively repair the initial vectorized code, and output the repaired initial vectorized code.

[0012] This invention also provides an automatic vectorization acceleration system for the domestically developed Mytron architecture, comprising: The source code acquisition module is used to acquire scalar program code snippets provided by users as source code. The vectorization generation module is used to input source code into the automatic vectorization tool MT-Vectorizer and output vectorized version code. The automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module. An analytical agent is used to perform static analysis on the source code and obtain the static analysis results. Based on the static analysis results, the required function interfaces and vectorization strategies of the source code are selected. Based on the source code, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template, prompt words are constructed to obtain customized prompt words. Vectorized agents are used to generate initial vectorized code based on customized prompt words and a predefined large language model; The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code.

[0013] The present invention also provides an electronic device, comprising: A processor is used to execute computer programs; A computer-readable storage medium storing a computer program, which, when executed by the processor, performs the automatic vectorization acceleration method for the domestically developed Maichuang architecture.

[0014] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the automatic vectorization acceleration method for the domestically developed Maichuang architecture.

[0015] The present invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements the automatic vectorization acceleration method for the domestic Maichuang architecture.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides an automatic vectorization acceleration method for the domestic MAIChuang architecture. It acquires user-provided scalar program code snippets as source code and utilizes the automatic vectorization tool MT-Vectorizer to analyze, optimize, and verify the input source code. This achieves efficient and automated generation of vectorized code suitable for the domestic MAIChuang architecture, improving the execution efficiency of applications within this architecture. Specifically, the MT-Vectorizer performs end-to-end processing on the user-input scalar program code snippets. Users do not need to understand the instruction set details or SIMD programming specifications of the domestic MAIChuang architecture; they only need to provide the scalar code to be optimized, and a directly deployable vectorized version of the code is output. This significantly lowers the application threshold for high-performance computing on the domestic MAIChuang architecture and broadens the platform's applicable scenarios. Furthermore, the analysis agent performs static analysis on the source code. Based on the static analysis results, it selects the required function interfaces and vectorization strategies for the source code and constructs customized prompts using a pre-determined standardized vectorization strategy template. The system accurately understands and matches user-provided scalar code snippets with targeted optimization requirements, guiding general-purpose large language models to generate vectorized code adapted to the Maichuang architecture. This eliminates the need to collect large-scale Maichuang architecture code for large language model training; instead, lightweight semantic parsing and policy template matching enable general-purpose large language models to optimize code for the Maichuang architecture. This significantly reduces the time and economic costs of adapting large language models to domestic architectures, while avoiding poor fine-tuning results due to the scarcity of high-quality data, thus improving the feasibility and practicality of vectorization. Secondly, it automatically generates initial vectorized code using vectorized agents, eliminating reliance on manual SIMD coding and lowering the technical threshold for vectorization, requiring no expert-level architecture or vectorization experience. Furthermore, the compiler testing module verifies the initial vectorized code generated by the large language model, avoiding the complex and costly process of manual debugging, ensuring higher correctness and stability in the final output vectorized code, effectively improving the computational efficiency of the domestic Maichuang architecture in HPC and AI application scenarios.

[0017] The automatic vectorization acceleration system, electronic device, computer-readable storage medium, and computer program product provided by this invention for the domestically developed Maichuang architecture possess all the advantages of the aforementioned automatic vectorization acceleration method for the domestically developed Maichuang architecture. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a hardware architecture diagram of the MT-3000 processor in this invention; Figure 2 This is a schematic diagram of the user-layer programming model based on the MT-3000 processor in this invention; Figure 3 A flowchart of the automatic vectorization acceleration method for the domestic Maichuang architecture provided by this invention; Figure 4 This is a flowchart illustrating the working principle of the automatic vectorization tool MT-Vectorizer in Example 1; Figure 5 This is a flowchart illustrating the working principle of the intelligent agent in Example 1; Figure 6 A schematic diagram showing the passability test results of different experimental methods on the program set; Figure 7 This is Schematic diagram A showing the performance acceleration of the automatic vectorization tool MT-Vectorizer on the assembly in Example 1; Figure 8 This is Schematic B, illustrating the performance acceleration of the automatic vectorization tool MT-Vectorizer on the assembly in Example 1; Figure 9 This is a block diagram of the automatic vectorization acceleration system for the domestically developed Maichuang architecture provided in Example 2; Figure 10 This is a structural block diagram of the electronic device provided in Example 3. Detailed Implementation

[0020] To make the technical problems, technical solutions, and beneficial effects solved by this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] Before describing the specific embodiments of this application, some of the technical terms involved in the embodiments of this application are explained as follows: The domestically developed Maichuang architecture is a heterogeneous multi-core processor architecture independently developed in China. It integrates a general-purpose computing core and a dedicated acceleration array, and has high throughput and low power consumption heterogeneous computing capabilities, such as the MT-3000 processor.

[0022] As attached Figure 1 As shown, attached Figure 1 The hardware architecture diagram of the MT-3000 processor is shown in the appendix; Figure 1 As can be seen, the MT-3000 processor consists of a general-purpose processing area and four accelerated processing areas; the general-purpose area integrates 16 general-purpose CPU cores, and each accelerated area contains 24 accelerated arrays; they share 6MB of on-chip global memory (GSM), 48MB of high-bandwidth shared memory (HBSM), and 32GB of off-chip DDR memory; each accelerated array consists of a control core (Ctrl) and 16 accelerated cores (ACC), and uses an on-chip DMA engine to realize data transfer between different storage levels.

[0023] It is worth noting that the general-purpose processing zone can access all GSM and DDR resources across accelerated clusters, while the accelerated array can only access storage resources within its own cluster. Furthermore, unlike the general-purpose processing zone which runs a complete operating system, the accelerated processing zone runs in bare-metal mode; all hardware resources must be explicitly managed by user programs. Therefore, the MT-3000 processor uses the Hthreads programming framework to support task offloading and resource scheduling. Figure 1 The right side of the image shows the microarchitecture of a single acceleration array, which employs a Very Long Instruction Word (VLIW) design and includes three key functional units: a scalar processing unit (SPU), a vector processing unit (VPU), and a DMA engine. The SPU is responsible for control flow scheduling and scalar operations and is equipped with a dedicated 64KB scalar memory (SM). The VPU operates in SIMD mode and integrates 16 vector processing engines (VPEs). Each VPE has 64 64-bit vector registers and 3 vector floating-point multiply-accumulate units (VFMAs) and is equipped with a dedicated 768KB vector memory (AM).

[0024] As attached Figure 2 As shown, attached Figure 2 The document presents a user-level programming model based on the MT-3000 processor; Appendix Figure 2 The document outlines the multi-layered software interface stack provided by the MT-3000 processor to support heterogeneous computing, from bottom to top: (1) Low-level hardware interfaces (such as assembly instructions and acceleration array management APIs), providing direct access to the control core, vector processing unit, and DMA engine, offering fine-grained control but high development complexity; (2) The Hthreads heterogeneous multi-threaded framework, including the host side and the device side; the host side manages task thread groups in the acceleration area through a POSIX-like thread interface, while the device side implements hardware resource operations such as memory allocation and DMA transfer through lightweight system calls, and the two communicate with each other through shared memory and interrupt mechanisms with low overhead; (3) High-level abstract interfaces, such as the MOCL3 runtime based on the OpenCL 1.2 standard, which supports data parallel programming, but due to its high level of abstraction, it is difficult to adapt to the unique storage separation architecture and VPU execution characteristics of the MT-3000; Appendix Figure 2The document provides the basis for selecting the software operating environment and programming interface upon which this application depends.

[0025] LLM-Vectorizer, a CPU vectorization tool, refers to a first systematic exploration by Taneja et al. at the international conference CGO of the ability to automatically generate vectorized code on a general-purpose CPU processor architecture using large language models (such as GPT-4). The method adopts a multi-agent finite state machine framework, combined with compiler feedback and formal verification, to achieve high-performance vectorization of scalar loops.

[0026] On-chip vector cache (AM): refers to the private vector data storage area of ​​each acceleration array in the domestic Maichuang architecture, with a capacity of 768KB. Under the domestic Maichuang architecture, all data that needs to participate in vectorization calculation must be preloaded from off-chip DDR memory into AM, and then read from AM and imported into vector register by the vector processing unit (VPU) before vectorization operation can be performed.

[0027] As attached Figure 3 As shown, this invention provides an automatic vectorization acceleration method for the domestically developed Mytron architecture, comprising the following steps: Step 100: Obtain the scalar program code snippet provided by the user as the source code.

[0028] Step 200: Input the source code into the automatic vectorization tool MT-Vectorizer, and output the vectorized version of the code.

[0029] In this invention, the automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module.

[0030] An analytical agent is used to perform static analysis on the source code and obtain the static analysis results. Based on the static analysis results, the required function interfaces and vectorization strategies of the source code are selected. Based on the source code, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template, prompt words are constructed to obtain customized prompt words.

[0031] Vectorized agents are used to generate initial vectorized code based on customized prompts and a predefined large language model.

[0032] The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code.

[0033] In the above implementation, starting with a user-provided scalar program code snippet, the automatic vectorization tool MT-Vectorizer performs end-to-end processing on the user-provided scalar program code snippet. This enables efficient generation of high-performance vectorized code on the domestic Maichuang architecture, which lacks native automatic vectorization support. Specifically, an analytical agent performs static analysis on the source code to identify its mathematical and computational functions, as well as its memory access characteristics and computational logic. Based on the results of the static analysis, the required function interfaces and vectorization strategies for the source code are selected. Customized prompt words are constructed using the user-provided scalar program code snippet, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template. This achieves accurate understanding of the user's scalar program code and targeted decomposition of optimization needs, solving the problem of general-purpose large language models lacking native automatic vectorization support. This method addresses the issue of inaccurate adaptation to the Maichuang architecture code. Based on customized prompts and leveraging a pre-defined large language model to generate initial vectorized code, it eliminates the need for developers to manually write SIMD-related code, significantly lowering the technical barrier to vectorization optimization. The compiler testing module verifies the initial vectorized code, ensuring the correctness and usability of the generated vectorized version, effectively avoiding the complex and costly process of manual debugging. Furthermore, this method eliminates the need for large-scale fine-tuning of the large language model for the Maichuang architecture, avoiding the scarcity of high-quality training data and the high cost of fine-tuning. Given that the MT-3000 processor does not support automatic vectorization, it achieves automated and efficient conversion of scalar programs into vectorized code, significantly improving the computational efficiency of high-performance computing and AI applications under the domestic Maichuang architecture, and promoting the widespread application of vectorization technology in domestic heterogeneous processors.

[0034] The following specific embodiments further explain and illustrate the automatic vectorization acceleration method for the domestically developed Mytron architecture provided by this invention: Example 1 This embodiment 1 provides an automatic vectorization acceleration method for the domestically developed Mytron architecture, including the following steps: Step 1: Obtain the scalar program code snippet provided by the user. This user-provided scalar program code snippet serves as the source code and is input to the automatic vectorization tool MT-Vectorizer for subsequent vectorization code generation.

[0035] Step 2: Input the scalar program code snippet provided by the user into the automatic vectorization tool MT-Vectorizer, and output the vectorized version code.

[0036] In this embodiment 1, the automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module, as shown in the attached diagram. Figure 4As shown.

[0037] An analytical agent is used to perform static analysis on the source code of a scalar program code snippet provided by the user, and obtain the static analysis results. Based on the static analysis results, the agent selects the function interfaces and vectorization strategies required by the source code. Based on the source code, the static analysis results, the function interfaces and vectorization strategies required by the source code, and a pre-determined standardized vectorization strategy template, the agent constructs prompt words to obtain customized prompt words.

[0038] As attached Figure 5 As shown, the workflow of the intelligent agent is as follows: Step A1: Use a pre-defined lightweight large language model, such as Qwen3-Coder-Flash (an open-source programming model), to perform static analysis on the scalar program code snippets provided by the user and obtain the static analysis results of the source code.

[0039] Specifically, the scalar program code snippet provided by the user is used as the source code. After reading the source code using a predefined lightweight large language model, static analysis is performed on the syntax, semantics, and structure of the source code to identify the mathematical functions and computational functions called in the source code, such as exponential and logarithmic functions. At the same time, the memory access characteristics and computational logic of the source code are identified. Then, according to the predefined algorithm type, combined with the memory access characteristics and computational logic of the source code, the source code is classified into algorithms to obtain the algorithm patterns contained in the source code. Finally, according to the preset output format, the mathematical functions called in the source code and the algorithm patterns contained in the source code are output to obtain the static analysis results of the source code.

[0040] In this embodiment 1, the predefined algorithm types include Stencil, MatMul, MatVec, Elementwise, Factorization, and Irregular, as shown in Table 1.

[0041] Table 1 Predefined Algorithm Types

[0042] Step A2: Using regular expressions, extract the mathematical and computational functions contained in the source code from the static analysis results; based on the extracted mathematical and computational functions contained in the source code, search the pre-configured Maichuang interface function knowledge base, dynamically select the function interfaces required by the source code, and obtain the function interfaces required by the source code.

[0043] It should be noted that existing commercial large language models have not learned the vectorization knowledge of the domestic Maichuang architecture. Therefore, it is necessary to manually write the vectorization knowledge of the domestic Maichuang architecture into the prompt words so that the vectorized agent can generate the initial vectorized code. Since the vectorization involved in the domestic Maichuang architecture involves more than 400 function interfaces, this embodiment 1 dynamically selects the function interfaces required by the source code to avoid inputting irrelevant function interfaces into the predetermined large language model, thereby significantly reducing noise interference.

[0044] Step A3: Using regular expressions, extract the algorithm patterns contained in the source code from the static analysis results. Based on the extracted algorithm patterns, select and load vectorization strategies from a pre-set vectorization strategy library to obtain the vectorization strategies required by the source code. The vectorization strategies required by the source code serve as customized prompt word templates for different algorithm types, providing clear thought chain guidance for the vectorized agent, thereby significantly reducing the exploration cost of a pre-determined large language model on complex structures. The number of vectorization strategies selected by the source code is adapted to the number of algorithm patterns contained in the source code.

[0045] It is worth noting that for algorithm types with irregular memory access or complex dependencies in the source code, a conservative vectorization strategy is adopted in the static analysis results of the source code to indicate that the vectorized agent does not need to rewrite this type of code program.

[0046] Step A4: Construct prompt words based on the source code, the static analysis results of the source code, the function interfaces required by the source code, the vectorization strategy required by the source code, and the pre-determined standardized vectorization strategy template to obtain customized prompt words; specifically, assemble the source code, the static analysis results of the source code, the function interfaces required by the source code, the vectorization strategy required by the source code, and the pre-determined standardized vectorization strategy template in a structured form to obtain customized prompt words.

[0047] It should be noted that the pre-determined standardized vectorization strategy template is pre-designed based on the execution specifications of the domestic Maichuang architecture, such as the MT-3000 processor. In the design process of the pre-determined standardized vectorization strategy template, the hardware constraints of the target chip are first determined. Then, the hardware constraints of the target chip are abstracted into a fixed code skeleton, which yields the pre-determined standardized vectorization strategy template. This forces the pre-determined large language model to follow the correct hardware execution flow when generating vectorized code. Taking the MT-3000 processor as an example, the hardware constraints of the target chip include data transfer between DDR and on-chip vector cache AM, bit width limitations of vector registers, and pipeline mechanisms for parallel computing.

[0048] In this embodiment 1, the pre-determined standardized vectorization strategy template includes a multi-threaded task partitioning strategy template, a resource allocation and preprocessing strategy template, a block pipeline processing strategy template, a scalar tail processing strategy template, and a resource release strategy template. By embedding the standardized vectorization strategy template covering the multi-threaded task partitioning strategy template, resource allocation and preprocessing strategy template, block pipeline processing strategy template, scalar tail processing strategy template, and resource release strategy template into the customized prompt words in a structured form, it can be ensured that the optimized code generated by the vectorized agent conforms to the platform's hardware and software specifications.

[0049] Specifically, the multi-threaded task partitioning strategy template is used to partition computational tasks and determine the data processing range of the current thread; the resource allocation and preprocessing strategy template is used to allocate on-chip vector cache space and complete the broadcast operation of scalar coefficients; the block pipelined processing strategy template is used to load data from off-chip global memory to on-chip vector cache through direct memory access; construct a vectorized loop to load data from on-chip vector cache to vector registers, execute predetermined core computation instructions, obtain updated data and write it back to on-chip vector cache; and write the updated data from on-chip vector cache back to off-chip global memory; the scalar tail processing strategy template is used to handle the tail of data that is not divisible by the vector length; and the resource release strategy template is used to explicitly release the allocated on-chip vector cache space.

[0050] It should be noted that the predefined standardized vectorization strategy template introduced in the customized prompts is not merely a simple instruction replacement, but rather a defined complete set of data flow and control flow templates. This predefined standardized vectorization strategy template can standardize the execution flow of computational tasks into the following five key stages: (1) Multi-threaded task division: The computing tasks are divided and the data processing scope of the current thread is defined in order to make full use of the parallel computing capabilities of the many-core architecture of the MT-3000 platform.

[0051] (2) Resource allocation and preprocessing: Allocate on-chip vector cache (AM) space and complete the broadcast operation of scalar coefficients to prepare data for vector operations.

[0052] (3) Block pipeline processing: Load data from off-chip global (DDR) memory to on-chip vector cache (AM) via direct memory access (DMA); construct a vectorized loop to load data from on-chip vector cache (AM) to vector register, execute predetermined core calculation instructions such as vector multiplication and addition vec_mula, obtain updated data and write it back to on-chip vector cache (AM); write the updated data from on-chip vector cache (AM) back to off-chip global memory (DDR).

[0053] (4) Scalar tail processing: Process the tail of data that cannot be divided by the vector length to ensure the logical correctness of the calculation results.

[0054] (5) Resource release: Explicitly release the requested on-chip vector cache (AM) space to prevent memory leaks.

[0055] In this embodiment 1, a pre-determined standardized vectorization strategy template is introduced to optimize the vector cache and vector components, thereby filling the gap in the automatic vectorization function of the MT-3000 processor's compiler. This not only solves the problem of code generation correctness, but also has significant decoupling and scalability at the software engineering level. Secondly, the introduced standardized vectorization strategy template can reserve a standard interface for further performance tuning.

[0056] It is worth noting that in the MT-3000 processor, the ultimate performance release often relies on the collaborative work of a multi-level storage hierarchy of Global Shared Memory (GSM), High Bandwidth Shared Memory (HBSM), and Scalar Memory (SM). For example, GSM and HBSM are suitable for storing reusable data and intermediate results to optimize memory access bandwidth, while SM is used to store data that cannot be vectorized. Therefore, the code generated based on the predetermined standardized vectorization strategy template has a highly modular feature. If GSM / HBSM needs to be introduced, only the corresponding data transport code layer needs to be inserted between DDR and AM, and the source address pointer needs to be adjusted, without disrupting the core vector computation loop logic. Similarly, the allocation and data transport of SM can be performed outside the computation logic. This basic vectorization code has a clear structure and robust logic, which can serve as a starting point for manual optimization by supercomputing users and facilitate secondary optimization by subsequent automated tools. Taking the DAXPY operator as an example, the predetermined standardized vectorization strategy template is shown in Table 2 below.

[0057] Table 2. Predetermined standardized vectorization strategy templates (taking the DAXPY operator as an example)

[0058] Vectorized agents are used to generate initial vectorized code based on user-provided scalar program code snippets and customized prompts, utilizing a pre-determined large language model. The pre-determined large language model employs a large language model with strong code generation capabilities, such as DeepSeek-v3.2, Qwen3-Coder-Plus, or GLM-4.6.

[0059] Specifically, the vectorized agent, based on customized prompts provided by the analysis agent and combined with scalar program code snippets provided by the user, calls a large language model with strong code generation capabilities to transform the user-provided scalar program code snippets into an efficient vectorized implementation, thus obtaining initial vectorized code. During the process of generating the initial vectorized code using the large language model with strong code generation capabilities, guided by customized prompts, the large language model can fully consider the SIMD instruction set and memory hierarchy unique to the MT-3000 processor because the customized prompts embed pre-determined standardized vectorization strategy templates. This ensures that the generated code not only conforms to the hardware specifications of the MT-3000 processor but also has a good modular structure, facilitating subsequent expansion to multi-level storage optimizations such as GSM / HBSM.

[0060] The compiler testing module tests the initial vectorized code and outputs a vectorized version of the code. Specifically, the compiler testing model submits the initial vectorized code to the GCC compiler of the MT-3000 processor for syntax and functional correctness checks, obtaining the check results. If the check passes, the initial vectorized code is directly output, resulting in the vectorized version of the code. If the check fails, compilation error information is generated and sent to the vectorized agent. This compilation error information triggers the vectorized agent to iteratively repair the initial vectorized code and output the repaired initial vectorized code. In other words, the vectorized agent also responds to compilation error information, iteratively repairs the initial vectorized code, and outputs the repaired initial vectorized code.

[0061] When the vectorized agent receives a compilation error message, it generates a compilation error correction prompt based on the error message, calls a large language model with strong code generation capabilities to regenerate the initial vectorized code, and sends the regenerated initial vectorized code to the compiler test module for verification testing. If the verification result is successful, the regenerated initial vectorized code is output, resulting in the vectorized version code.

[0062] In this embodiment 1, the initial vectorized code is tested through the compiler testing module to ensure the correctness and compatibility of the generated code. At the same time, the code quality is continuously optimized through a feedback mechanism. The compilation error information is used to drive the vectorized agent to complete the repair within a finite number of iterations until a compilable and functionally equivalent vectorized version of the code is output. Through the closed-loop optimization mechanism, the quality and performance of the final code are guaranteed.

[0063] Experimental verification instructions: (1) To verify the effectiveness of the vectorization acceleration method described in Example 1, the PolyBench-MT benchmark suite was used to perform a complete vectorization generation and correctness test on all operator programs (at the kernel function granularity).

[0064] In the experimental process, an optimized vectorized version was generated for each kernel function at once, and the compiler syntax check iterations did not exceed 3 rounds. Then, checksum tests were used to automatically verify all kernel functions to evaluate the executability and functional correctness of the code.

[0065] In this experiment, three different configurations were set up, and three different methods were used for code vectorization rewriting. Specifically, the first method is direct vectorization of the large model, that is, vectorization is performed without using any additional strategies, relying only on the existing knowledge of the pre-determined large language model. The second method is LLM-Vectorizer, which adapts the existing CPU vectorization tool LLM-Vectorizer to the domestic Maichuang architecture platform, introduces the pre-determined standardized vectorization strategy template in Example 1, and adds the syntax checking mechanism of the MT-3000 platform compiler. The third method is MT-Vectorizer, which adopts the automatic vectorization acceleration method for the domestic Maichuang architecture described in Example 1.

[0066] Experimental results: The first method, which directly vectorizes a pre-defined large language model, yielded a 0% pass rate on the test set. This verifies that the general-purpose large language model did not interact with the MT-3000 platform code during the pre-training phase, and the generated results cannot directly meet the platform's syntax and interface specifications. (See attached image.) Figure 6 As shown, attached Figure 6 The diagram shows the passability test results of different experimental methods on the assembly, specifically the passability test results of the second and third methods on the assembly.

[0067] From the appendix Figure 6 As can be seen, compared to the second method, the third method, namely the automatic vectorization acceleration method for the domestic Michuang architecture described in Embodiment 1, significantly improves the pass rates of the three predefined large language models, such as DeepSeek-v3.2, Qwen3-Coder-Plus, and GLM-4.6, at all k levels. Specifically, taking k=1 as an example, the average improvement is approximately 8.0%; at k=10, the average improvement is approximately 2.6%. Overall, the automatic vectorization tool MT-Vectorizer in Embodiment 1 outperforms LLM across the entire range. Vectorizers offer significant advantages in small-k scenarios, maintaining a high vectorization success rate even with a limited number of candidates, thus effectively reducing generation and verification costs during actual deployment. In this embodiment 1, a dedicated analytical agent is introduced to structurally extract and summarize loop structures, array access patterns, and operator-level mathematical formulas. Combined with different algorithm categories, a classification vectorization strategy and customized prompt words are designed, significantly reducing the search space and invalid attempts of large models during the generation process. This allows the model to construct vectorized code along a more convergent generation path, thereby systematically reducing the proportion of syntax and semantic errors.

[0068] (2) In order to verify the actual acceleration effect of the automatic vectorization tool MT-Vectorizer proposed in this application on the MT-3000 platform, a comprehensive evaluation of three different data sizes, Mini, Medium and Exlarge, was carried out on the PolyBench-MT benchmark set; the speedup ratio after vectorization was calculated based on the running time of the scalar program.

[0069] As attached Figure 7-8 As stated, Appendix Figure 7 Figure A shows the performance acceleration diagram of the automatic vectorization tool MT-Vectorizer on the assembly in Example 1. Figure 8 Figure B shows the performance acceleration diagram of the automatic vectorization tool MT-Vectorizer on the assembly in Example 1; from Appendix Figure 7-8 As can be seen, the vectorized code generated by the automatic vectorization tool MT-Vectorizer achieves significant performance improvements in most operators. Among them, at the standard Medium scale, the average speedup of the program set reaches 6.8×, and the highest speedup occurs in the SYRK operator, reaching 23.37×. This fully demonstrates that the vectorization framework proposed in this paper can effectively utilize the vector components of the MT-3000 platform and greatly improve the computational throughput.

[0070] In typical application verification of Tianhe, the hotspot kernel function of the high-efficiency numerical simulation platform for internal flow of aero-engines is accelerated by more than 3 times using X-Blue, and the overall performance of the application is improved by 4.5%. The hotspot kernel function in the large-scale parallel molecular dynamics simulation software MISA-MD is 1.25% better than the artificial vectorized version.

[0071] The automatic vectorization acceleration method described in Embodiment 1 introduces the automatic vectorization tool MT-Vectorizer, which includes an analysis agent, a vectorization agent, and a compiler testing module. Through the collaborative work of multiple agents in the automatic vectorization tool MT-Vectorizer, the complexity of manual optimization is significantly reduced, and the success rate and efficiency of vectorized code generation are improved. In addition, by introducing a pre-determined standardized vectorization strategy template, even large language models without specific domain knowledge can effectively generate high-quality vectorized code, which greatly promotes the development of the high-performance software ecosystem.

[0072] Example 2 As attached Figure 9 As shown, this embodiment 2 provides an automatic vectorization acceleration system for the domestic Maichuang architecture, including a source code acquisition module and a vectorization generation module.

[0073] The source code acquisition module is used to acquire scalar program code snippets provided by the user.

[0074] The vectorization generation module is used to input user-provided scalar program code snippets into the automatic vectorization tool MT-Vectorizer, and output vectorized version code.

[0075] In this embodiment 2, the automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module.

[0076] The analysis agent performs lightweight semantic parsing on user-provided scalar program code snippets to obtain the mathematical function features and algorithm types in the source code; it classifies the algorithm types in the source code to obtain the algorithm patterns contained in the source code; and it constructs prompt words using the mathematical function features, algorithm patterns, and pre-determined standardized vectorization strategy templates to obtain customized prompt words.

[0077] Vectorized agents are used to generate initial vectorized code based on user-provided scalar program code snippets and customized prompts, using a predefined large language model.

[0078] The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code.

[0079] Example 3 As attached Figure 10As shown, this embodiment 3 provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the automatic vectorization acceleration method for the domestic Maichuang architecture; or, the processor executing the computer program to implement the functions of each module in the above-mentioned automatic vectorization acceleration system for the domestic Maichuang architecture.

[0080] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a preset function, the instruction segments describing the execution process of the computer program in the electronic device.

[0081] The electronic device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The electronic device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above are examples of electronic devices and do not constitute a limitation on the electronic device. It may include more components than described above, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0082] The processor can be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor, or any conventional processor, etc. The processor is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and lines.

[0083] The memory can be used to store the computer program and / or module. The processor implements various functions of the electronic device by running or executing the computer program and / or module stored in the memory and by calling the data stored in the memory.

[0084] The memory may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function (such as sound playback, image playback, etc.). The data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory may include high-speed random access memory and non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart memory cards, secure digital cards, flash memory cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0085] Example 4 This embodiment 4 also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the automatic vectorization acceleration method for the domestic Maichuang architecture.

[0086] If the modules / units of the automated vectorization acceleration system for the domestic Maichuang architecture are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0087] Based on this understanding, the present invention can implement all or part of the processes in the above-mentioned automatic vectorization acceleration method for the domestically developed Maichuang architecture, or it can be accomplished by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of the above-mentioned automatic vectorization acceleration method for the domestically developed Maichuang architecture. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or a preset intermediate form, etc.

[0088] The computer-readable storage medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory, random access memory, electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0089] Example 5 This embodiment 5 provides a computer product, which includes a computer program stored in a computer-readable storage medium. The processor of the electronic device reads the computer program from the computer-readable storage medium and executes the computer program, so that the electronic device can execute the automatic vectorization acceleration method for the domestic Maichuang architecture described in embodiment 1, which will not be repeated here.

[0090] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above methods.

[0091] The automatic vectorization acceleration method for the domestic Michuang architecture described in this invention utilizes the end-to-end automatic vectorization tool MT-Vectorizer, which is based on multi-agent collaboration, to analyze, optimize, and verify the input code, so as to efficiently generate high-performance vectorized code on the domestic heterogeneous processor MT-3000, which lacks native automatic vectorization support.

[0092] In this invention, the automatic vectorization tool MT-Vectorizer starts with a scalar program code snippet input by the user. Through an analysis agent, it performs static analysis on the user-input scalar program code snippet, identifying key mathematical functions and computational function calls, as well as memory access characteristics and computational logic. Based on these memory access and computational characteristics, the source code is categorized into predefined algorithm types. Subsequently, based on the static analysis results, function interfaces related to the code's functionality are dynamically selected from a pre-configured MT-Vectorizer interface function knowledge base. Simultaneously, based on the extracted algorithm patterns contained in the source code, a vectorization strategy is selected and loaded from a pre-set vectorization strategy library. Furthermore, a pre-determined standardized vectorization strategy template for the MT-Vectorizer architecture is introduced, ensuring that the code generated by the large model conforms to the hardware and software specifications of the MT-Vectorizer architecture. Finally, the static analysis results, the function interfaces required by the source code, the vectorization strategies required by the source code, and the pre-determined standardized vectorization strategy template are assembled in a structured form into customized prompt words, guiding the large language model to generate efficient vector code that conforms to hardware specifications.

[0093] Secondly, the vectorized agent receives customized prompts and calls a large model with strong code generation capabilities to directly generate initial vectorized code that conforms to the MT-3000 programming model. Since the customized prompts are embedded in a pre-determined standardized vectorization strategy template for the Guochuang Maichuang architecture, the generated code naturally possesses a modular structure and good scalability, facilitating the subsequent introduction of advanced storage optimizations such as GSM / HBSM. In addition, the generated code is submitted to the GCC compiler of the MT-3000 platform for syntax and functional correctness verification through the compiler testing module, and the compilation error information is fed back to the vectorized agent, driving it to complete the repair within a limited number of iterations, forming a closed-loop optimization mechanism, and finally outputting a compilable, functionally equivalent, and high-performance vectorized version.

[0094] Experiments show that the automatic vectorization tool MT-Vectorizer provided in this invention achieves an average operator speedup of 6.8 times on the PolyBench-MT benchmark; in the typical application X-Blue of the Tianhe supercomputer, it accelerates hotspot kernel functions by more than 3 times, improving overall application performance by 4.5%; and in MISA-MD, it outperforms manual vectorization by 1.25%. Furthermore, MT-Vectorizer can be adapted to the MT-3000 without fine-tuning the large language model, achieving a pass@1 pass rate of over 75%, which is superior to existing work. This invention effectively bridges the semantic gap between general-purpose large language models and domestically produced dedicated hardware, providing a feasible path for building a low-threshold, high-efficiency domestic heterogeneous computing software ecosystem, demonstrating outstanding technological advancement and broad application value.

[0095] The above embodiments are merely one of the implementation methods for achieving the technical solution of the present invention. The scope of protection claimed by the present invention is not limited to this embodiment, but also includes any variations, substitutions and other implementation methods that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention.

Claims

1. An automatic vectorization acceleration method for the domestically developed Mytron architecture, characterized in that, include: Obtain the scalar program code snippet provided by the user as the source code; Input the source code into the automatic vectorization tool MT-Vectorizer, and the output will be the vectorized version of the code; The automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module. An analytical agent is used to perform static analysis on the source code and obtain the static analysis results. Based on the static analysis results, the required function interfaces and vectorization strategies of the source code are selected. Based on the source code, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template, prompt words are constructed to obtain customized prompt words. Vectorized agents are used to generate initial vectorized code based on customized prompt words and a predefined large language model; The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code. The design process of the predetermined standardized vectorization strategy template includes: first, determining the hardware constraints of the target chip; then, abstracting the hardware constraints of the target chip into a fixed code skeleton to obtain the predetermined standardized vectorization strategy template, so as to force the predetermined large language model to follow the correct hardware execution flow when generating vectorized code; The predefined standardized vectorization strategy templates include multi-threaded task partitioning strategy templates, resource allocation and preprocessing strategy templates, block pipeline processing strategy templates, scalar tail processing strategy templates, and resource release strategy templates. The block pipeline processing strategy template is used to load data from off-chip global memory to on-chip vector cache via direct memory access; construct a vectorized loop to load data from on-chip vector cache to vector register, execute predetermined core calculation instructions, obtain updated data and write it back to on-chip vector cache; and write the updated data from on-chip vector cache back to off-chip global memory. A multi-threaded task partitioning strategy template is used to partition computational tasks and determine the data processing scope of the current thread; Resource allocation and preprocessing strategy templates are used to allocate on-chip vector cache space and complete the broadcast operation of scalar coefficients; Scalar tail processing strategy template, used to handle the tail of data that is not divisible by the vector length; Resource release strategy templates are used to explicitly release the allocated on-chip vector cache space.

2. The automatic vectorization acceleration method for the domestically developed Maichuang architecture according to claim 1, characterized in that, The process of performing static analysis on source code and obtaining the static analysis results is as follows: Using a predefined lightweight large language model, static analysis is performed on the source code to identify the mathematical and computational functions called in the source code, as well as the memory access characteristics and computational logic of the source code. According to predefined algorithm types, combined with the memory access characteristics and computational logic of the source code, the source code is classified into algorithms to obtain the algorithm patterns contained in the source code. According to a preset output format, the mathematical functions called in the source code and the algorithm patterns contained in the source code are output to obtain the static analysis results of the source code.

3. The automatic vectorization acceleration method for the domestically developed Maichuang architecture according to claim 1, characterized in that, Predefined algorithm types include Stencil, MatMul, MatVec, Elementwise, Factorization, and Irregular.

4. The automatic vectorization acceleration method for the domestically developed Maichuang architecture according to claim 1, characterized in that, The initial vectorized code was tested, and the resulting vectorized version of the code was output as follows: Perform syntax and functional correctness checks on the initial vectorized code and obtain the check results; If the verification result is successful, the initial vectorized code is directly output to obtain the vectorized version code; if the verification result is unsuccessful, compilation error information is generated and sent to the vectorized agent.

5. The automatic vectorization acceleration method for the domestically developed Maichuang architecture according to claim 4, characterized in that, The vectorized agent is also used to respond to compilation error messages, iteratively repair the initial vectorized code, and output the repaired initial vectorized code.

6. An automatic vectorization acceleration system for the domestically developed Mytron architecture, characterized in that, include: The source code acquisition module is used to acquire scalar program code snippets provided by users as source code. The vectorization generation module is used to input source code into the automatic vectorization tool MT-Vectorizer and output vectorized version code. The automatic vectorization tool MT-Vectorizer includes an analysis agent, a vectorization agent, and a compiler testing module. An analytical agent is used to perform static analysis on the source code and obtain the static analysis results. Based on the static analysis results, the required function interfaces and vectorization strategies of the source code are selected. Based on the source code, the static analysis results, the required function interfaces, the required vectorization strategies, and a pre-determined standardized vectorization strategy template, prompt words are constructed to obtain customized prompt words. Vectorized agents are used to generate initial vectorized code based on customized prompt words and a predefined large language model; The compiler testing module is used to test the initial vectorized code and output the vectorized version of the code. The design process of the predetermined standardized vectorization strategy template includes: first, determining the hardware constraints of the target chip; then, abstracting the hardware constraints of the target chip into a fixed code skeleton to obtain the predetermined standardized vectorization strategy template, so as to force the predetermined large language model to follow the correct hardware execution flow when generating vectorized code; The predefined standardized vectorization strategy templates include multi-threaded task partitioning strategy templates, resource allocation and preprocessing strategy templates, block pipeline processing strategy templates, scalar tail processing strategy templates, and resource release strategy templates. The block pipeline processing strategy template is used to load data from off-chip global memory to on-chip vector cache via direct memory access; construct a vectorized loop to load data from on-chip vector cache to vector register, execute predetermined core calculation instructions, obtain updated data and write it back to on-chip vector cache; and write the updated data from on-chip vector cache back to off-chip global memory. A multi-threaded task partitioning strategy template is used to partition computational tasks and determine the data processing scope of the current thread; Resource allocation and preprocessing strategy templates are used to allocate on-chip vector cache space and complete the broadcast operation of scalar coefficients; Scalar tail processing strategy template, used to handle the tail of data that is not divisible by the vector length; Resource release strategy templates are used to explicitly release the allocated on-chip vector cache space.

7. An electronic device, characterized in that, include: A processor is used to execute computer programs; A computer-readable storage medium storing a computer program, which, when executed by the processor, performs the automatic vectorization acceleration method for the domestically developed Maichuang architecture as described in any one of claims 1-5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the automatic vectorization acceleration method for the domestic Maichuang architecture as described in any one of claims 1-5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the automatic vectorization acceleration method for the domestically developed Maichuang architecture as described in any one of claims 1-5.

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