Memory access prediction method and system, computing device, storage medium and product

Abstract

This disclosure relates to a memory access prediction method and system, computing device, storage medium, and product. The memory access prediction method can be applied to a memory access prediction system, which may include a first processor and a second processor. The memory access prediction method includes: the first processor acquiring memory access record data of the memory in the memory access prediction system; the first processor determining access-related information for each of a plurality of accessed memory pages based on the access record data, the access-related information including information reflecting the characteristics of access operations for each memory page; the first processor determining heat data of the plurality of memory pages based on the access-related information; the first processor sending the heat data to the second processor; and the second processor predicting the target memory page to be accessed among the plurality of memory pages based on the heat data. According to this disclosure, the utilization rate and overhead of the second processor can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology. More specifically, this disclosure relates to a memory access prediction method and system, a computing device, a storage medium, and a computer program product. Background Technology

[0002] In modern computers, memory access performance is a key factor affecting application performance. Due to the limited cache capacity of the Central Processing Unit (CPU) and the high latency of remote memory access in Non-Uniform Memory Access (NUMA) systems, the computer's operating system needs to intelligently manage memory and place frequently accessed data in optimal locations.

[0003] Memory hotspot identification is fundamental to memory management optimization. By accurately identifying which memory pages are hot (i.e., hot spots or hot zones), the system can: 1. Migrate hot memory pages to the visitor's local NUMA node; 2. Lock hot memory pages in memory to prevent them from being swapped out; 3. Prefetch memory pages that are about to be accessed, reducing access latency.

[0004] However, traditional memory hotspot identification methods are mainly based on CPU software implementation, which leads to high CPU overhead. Summary of the Invention

[0005] One or more exemplary embodiments of this disclosure provide a memory access prediction method and system, computing device, storage medium, and computer program product that can reduce the occupancy and overhead of a second processor.

[0006] According to one or more exemplary embodiments of this disclosure, a memory access prediction method is provided, applied to a memory access prediction system, the memory access prediction system including a first processor and a second processor, the method comprising: the first processor acquiring memory access record data of the memory of the memory access prediction system; the first processor determining access-related information for each of a plurality of memory pages accessed by the memory based on the access record data, wherein the access-related information includes information reflecting characteristics of access operations for each memory page; the first processor determining heat data of the plurality of memory pages based on the access-related information; the first processor sending the heat data to the second processor; and the second processor predicting a target memory page to be accessed among the plurality of memory pages based on the heat data.

[0007] In an example embodiment, the access record data may include at least one of the following: the access virtual address of the memory that was accessed at least once, the access timestamp, the access subject, and the access latency. The access-related information may include at least one of the following: access frequency data, time decay heat data, access latency data, and cross-node access data.

[0008] In an example embodiment, the step of the first processor determining access-related information in multiple memory pages accessed by the memory based on the access record data may include the first processor performing at least one of the following operations: determining the multiple memory pages accessed by the memory using the access virtual address in the access record data; determining the access frequency data of each memory page from the access virtual address and the access timestamp in the access record data; determining the change data of the access frequency data of each memory page for each memory page, and determining the change data as the time decay heat data of each memory page; determining the access delay data of each memory page from the access virtual address and the access delay in the access record data; determining the node information of the access subject of each memory page from the access subject in the access record data, and determining the cross-node access data of each memory page by comparing the node information of each memory page and the node information of the access subject.

[0009] In an example embodiment, the step of determining the popularity data of the plurality of memory pages by the first processor based on the access-related information may include the first processor performing the following operations: for each of the plurality of memory pages, performing a weighted calculation on the access frequency data, the time decay popularity data, the access latency data, and the cross-node access data using a preset weight to obtain a popularity score for each of the plurality of memory pages; determining the popularity data of the plurality of memory pages based on the popularity score of each of the plurality of memory pages, wherein the step of predicting the target memory page to be accessed among the plurality of memory pages by the second processor based on the popularity data includes: the second processor predicting the memory page with the highest popularity score among the plurality of memory pages as the target memory page to be accessed among the plurality of memory pages.

[0010] In an example embodiment, determining the popularity data of the plurality of memory pages based on the popularity score of each memory page may include: classifying the plurality of memory pages into hot and cold categories using the popularity score of each memory page to obtain a hot and cold classification result for each memory page; and determining the popularity score and the hot and cold classification result of each memory page as the popularity data of the plurality of memory pages. The method may further include: the second processor determining a hot and cold migration scheme for the plurality of memory pages based on the hot and cold classification result.

[0011] In an example embodiment, the method may further include: the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain access pattern data of the plurality of memory pages; the first processor sending the access pattern data of the plurality of memory pages to the second processor; and the second processor predicting which memory pages among the plurality of memory pages will be accessed based on the popularity data and the access pattern data.

[0012] In an example embodiment, the access pattern data may include at least one of temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain the temporally correlated access pattern data of the plurality of memory pages may include the first processor performing the following operations: using the access timestamps in the access record data to obtain memory page pairs whose access time intervals satisfy a predetermined interval condition; determining temporally correlated memory page pairs whose association probability is greater than an association threshold; and determining the data related to the temporally correlated memory page pairs in the access record data and the temporal association relationships between the temporally correlated memory page pairs as the temporally correlated access pattern data of the plurality of memory pages. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain the spatially localized access pattern data of the plurality of memory pages may include the first processor performing the following operations: using the access virtual address in the access record data... The access timestamps are used to analyze whether adjacent memory pages in the plurality of memory pages are accessed consecutively, and to determine the number of times each memory page in the plurality of memory pages is accessed consecutively with adjacent memory pages. The data related to the consecutively accessed adjacent memory pages in the access record data and the number of accesses are determined as the spatial locality access pattern data of the plurality of memory pages. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain the periodic access pattern data of the plurality of memory pages may include the first processor performing the following operations: constructing an access time series of each memory page in the plurality of memory pages based on the access record data; determining the dominant frequency of the fast Fourier transform spectrum of the access time series; determining the memory pages whose dominant frequencies satisfy a predetermined frequency condition as at least a portion of the memory pages; determining the access period of the at least a portion of the memory pages; and determining the data related to the at least a portion of the memory pages in the access record data and the access period of the at least a portion of the memory pages as the periodic access pattern data of the plurality of memory pages.

[0013] In an example embodiment, the first processor may include at least one of a graphics processor, an artificial intelligence accelerator, a multi-core parallel central processing unit, and a field-programmable gate array, and the second processor may include a central processing unit.

[0014] In an example embodiment, the step of the second processor predicting the target memory page to be accessed from among the plurality of memory pages based on the heat data and the access pattern data may include the second processor performing the following operations: determining a first confidence level of a temporally correlated access pattern, a second confidence level of a spatially localized access pattern, and / or a third confidence level of a periodic access pattern; determining at least one of the temporally correlated access pattern, the spatially localized access pattern, and the periodic access pattern as a candidate access pattern based on whether the first confidence level, the second confidence level, and / or the third confidence level meet a confidence threshold condition; and predicting the target memory page to be accessed from among the plurality of memory pages by using the access record data, the heat data, and the candidate access patterns.

[0015] In an example embodiment, predicting the target memory page to be accessed from among the plurality of memory pages by using the access record data, the popularity data, and the candidate access patterns may include: when the candidate access patterns include one or more of the temporal correlation access pattern, the spatial locality access pattern, and the periodic access pattern, performing one or more of the following operations to obtain one or more of the first candidate memory page, the second candidate memory page, and the third candidate memory page related to the currently accessed memory page from among the plurality of memory pages: determining the memory page related to the currently accessed memory page from among the plurality of memory pages by using the popularity data and the temporal correlation access pattern data. The system identifies a first candidate memory page related to the current accessed memory page by using the heat data and the spatial locality access pattern data; a second candidate memory page related to the current accessed memory page is identified from the plurality of memory pages by using the heat data and the periodic access pattern data; and a third candidate memory page related to the current accessed memory page is identified from the plurality of memory pages by using one or more of the weights of the temporal correlation access pattern, the spatial locality access pattern, and the periodic access pattern. Finally, the system predicts the target memory page to be accessed from the plurality of memory pages by using one or more of the weights of the first candidate memory page, the second candidate memory page, and the third candidate memory page.

[0016] In an example embodiment, the method may further include: the second processor acquiring access record data of the memory within a preset time period; and the second processor writing the access record data into a shared memory buffer accessible by the first processor, so that the first processor can acquire the access record data.

[0017] In an example embodiment, the method may further include: the second processor determining a memory access prediction hit rate based on the target memory page and the actual memory page being accessed; and the second processor adjusting a predetermined interval condition and association threshold related to the time-series-related access pattern data, a predetermined frequency condition related to the periodic access pattern data, and the size of the preset time period based on the hit rate.

[0018] According to one or more exemplary embodiments of this disclosure, a memory access prediction system is provided, comprising: a first processor; a second processor; an access data acquisition unit configured to acquire access record data of memory of the memory access prediction system via the first processor; an access information determination unit configured to determine access-related information of each memory page among a plurality of accessed memory pages of the memory via the first processor based on the access record data, wherein the access-related information includes information reflecting the characteristics of an access operation for each memory page; a popularity data determination unit configured to determine popularity data of the plurality of memory pages via the first processor based on the access-related information; a popularity data sending unit configured to send the popularity data to the second processor via the first processor; and a memory page prediction unit configured to predict a target memory page to be accessed among the plurality of memory pages via the second processor based on the popularity data.

[0019] According to one or more example embodiments, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements a memory access prediction method according to one or more example embodiments.

[0020] According to one or more example embodiments, a computing device is provided, including: a first processor, a second processor, and a memory storing a computer program that, when executed by the first processor or the second processor, implements a memory access prediction method according to one or more example embodiments.

[0021] According to one or more example embodiments, a computer program product is provided, wherein instructions in the computer program product are executable by a processor of a computer device to perform a memory access prediction method according to one or more example embodiments.

[0022] According to embodiments of the present disclosure, the memory access prediction method and system, computing device, storage medium, and computer program product obtain memory access record data of the memory access prediction system by a first processor of the memory access prediction system, and determine access-related information for each of a plurality of memory pages accessed by the first processor based on the access record data. The access-related information includes information reflecting the characteristics of the access operation for each memory page. Based on the access-related information, the first processor determines the heat data of the plurality of memory pages, and sends the heat data to a second processor of the memory access prediction system. The second processor predicts the target memory page to be accessed among the plurality of memory pages based on the heat data, which can reduce the occupancy and overhead of the second processor.

[0023] Furthermore, the memory access prediction method and system, computing device, storage medium, and computer program product according to embodiments of this disclosure also improve the efficiency and accuracy of memory access prediction by leveraging the high efficiency and high accuracy of the first processor, thereby enhancing the effect of memory management optimization.

[0024] Further aspects and / or advantages of the general concept of this disclosure will be set forth in part in the description which follows, and in part will be clear from the description or may be learned by practice of the general concept of this disclosure. Attached Figure Description

[0025] The above and other objects and features of one or more exemplary embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, which exemplarily illustrate the embodiments.

[0026] Figure 1 A flowchart illustrating a memory access prediction method according to one or more example embodiments is shown.

[0027] Figure 2 A flowchart illustrating a memory access prediction method according to one or more example embodiments is shown.

[0028] Figure 3 This diagram illustrates the determination of access-related information according to one or more example embodiments.

[0029] Figure 4 This diagram illustrates the acquisition of time-related access pattern data according to one or more example embodiments.

[0030] Figure 5 A schematic diagram illustrating the acquisition of spatial locality access pattern data according to one or more example embodiments is shown.

[0031] Figure 6 A block diagram of a memory access prediction system according to one or more example embodiments is shown.

[0032] Figure 7 A schematic diagram of a computing device 700 according to one or more example embodiments is shown.

[0033] Figure 8 A schematic diagram of a memory access prediction system according to one or more example embodiments is shown. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0035] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following examples do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0036] It should be noted that the phrase "at least one of several items" in this disclosure refers to three parallel cases: "any one of the several items", "a combination of any number of the several items", and "all of the several items". For example, "including at least one of A and B" includes the following three parallel cases: (1) including A; (2) including B; (3) including A and B. Another example is "performing at least one of step one and step two", which means the following three parallel cases: (1) performing step one; (2) performing step two; (3) performing both step one and step two.

[0037] The following reference Figures 1 to 8 A memory access prediction method and system according to embodiments of the present disclosure are described in detail.

[0038] Figure 1 A flowchart illustrating a memory access prediction method according to one or more example embodiments is shown. Figure 2 A flowchart illustrating a memory access prediction method according to one or more example embodiments is shown. Figure 1 and Figure 2 The memory access prediction method is applicable to electronic devices or systems that include processors, and is particularly applicable to electronic devices or systems that include different processors (or different processors included in an electronic device or system). Figure 1The memory access prediction method described above can be applied to a memory access prediction system, which may include a first processor and a second processor.

[0039] Reference Figure 1 In step S101, the first processor acquires the memory access record data of the memory access prediction system. The first processor has excellent performance in terms of computational efficiency and accuracy.

[0040] In one or more example embodiments, the first processor may include at least one of a graphics processor, an artificial intelligence accelerator, a multi-core parallel central processing unit, and a field-programmable gate array (FPGA). For example, in step S101, the graphics processor may acquire memory access record data of the memory access prediction system. For example, in step S101, the artificial intelligence accelerator may acquire memory access record data of the memory access prediction system. For example, in step S101, the multi-core parallel central processing unit may acquire memory access record data of the memory access prediction system. For example, in step S101, the FPGA may acquire memory access record data of the memory access prediction system. For example, in step S101, the graphics processor and the multi-core parallel central processing unit, etc., may acquire memory access record data of the memory access prediction system.

[0041] In one or more example embodiments, the access log data may include at least one of the following: the access virtual address of the memory accessed at least once, the access timestamp, the access subject, and the access latency. The access timestamp may be, for example, but not limited to, nanosecond precision. The access subject may be, for example, but not limited to, the identity number (ID) of the accessed CPU core. Furthermore, the access log data may include the access type of the memory accessed at least once. The access type may be, for example, but not limited to, read / write.

[0042] In one or more example embodiments, such as Figure 2As shown, before step S101, the method may further include: in step S1003, the second processor acquires memory access record data of the memory of the memory access prediction system within a preset time period; in step S1006, the second processor writes the access record data into a shared memory buffer accessible by the first processor, so that the first processor can acquire the access record data. For example, the second processor performs Performance Monitoring Unit (PMU) event collection and page table access bit sampling to obtain access record data, and writes the access record data into the shared buffer for management. PMU events may include, for example, but not limited to, at least one of L3 cache miss, Remote Non-Inconsistent Memory Access Architecture (NUMA) node memory access, Translation Lookaside Buffer (TLB Miss), memory read / write events, etc.

[0043] In step S102, the first processor determines access-related information for each of the multiple memory pages accessed in the memory based on the access record data. The access-related information may include information reflecting the characteristics of the access operation for each memory page. The characteristics of the access operation may include, for example, but not limited to, temporal attributes, spatial attributes, etc.

[0044] In one or more example embodiments, access-related information may include at least one of access frequency data, time decay heat data, access latency data, and cross-node access data.

[0045] For example, in step S102, the first processor may determine the access-related information of each memory page among the multiple memory pages accessed in the memory in parallel based on the access record data. For example, the graphics processor may determine the access-related information of each memory page among the multiple memory pages accessed in the memory based on the access record data. For example, an artificial intelligence accelerator may determine the access-related information of each memory page among the multiple memory pages accessed in the memory based on the access record data. For example, a multi-core parallel central processing unit may determine the access-related information of each memory page among the multiple memory pages accessed in the memory based on the access record data. For example, a field-programmable gate array may determine the access-related information of each memory page among the multiple memory pages accessed in the memory based on the access record data. For example, the graphics processor and the multi-core parallel central processing unit may determine the access-related information of each memory page among the multiple memory pages accessed in the memory based on the access record data.

[0046] Furthermore, the first processor can preprocess the access record data in parallel, and based on the preprocessed access record data, determine the access-related information for each of the multiple memory pages accessed. For example, each first processor thread preprocesses a batch of access record data. For example, when preprocessing a batch of access record data, each first processor thread can perform the following operations: parse the virtual addresses of memory pages in the batch of access records, map the parsed virtual addresses to the page frame numbers of the physical addresses of the memory pages to determine the physical addresses of the memory pages; and determine the node to which the memory page belongs by querying the Non-Uniform Memory Access Architecture (NUMA) topology using the physical addresses. In addition, each first processor thread can filter out invalid record data in the access record data when preprocessing it.

[0047] In one or more example embodiments, the first processor determines access-related information in multiple memory pages accessed by the memory based on access record data. This may include the first processor performing at least one of the following operations: determining multiple memory pages accessed by the memory using access virtual addresses in the access record data; determining access frequency data for each memory page from the access virtual addresses and access timestamps in the access record data; determining change data of the access frequency data for each memory page for each memory page, and determining the change data as time decay heat data for each memory page; determining access latency data for each memory page from the access virtual addresses and access latency in the access record data; determining node information of the access subject for each memory page from the access subject in the access record data; and determining cross-node access data for each memory page by comparing the node information of each memory page with the node information of the access subject.

[0048] For example, Figure 3 This diagram illustrates the determination of access-related information according to one or more example embodiments. Figure 3As shown, in step S301, access record data or an access record array is read, and memory page and node information is parsed from the access record data or the access record array. In step S302, based on the access virtual address and access timestamp in the access record data, the access frequency of each memory page is determined by accumulating the access count, and the time decay heat of the memory page is determined by using the access frequency. In step S303, the node information of the access subject of each memory page in the multiple memory pages is determined from the access subject in the access record data, and whether each memory page is accessed across nodes is determined by comparing the node information of each memory page in the multiple memory pages with the node information of the access subject. Each time a yes is determined in step S303, the cross-node count is incremented in step S304; each time a no is determined in step S303, the current cross-node count remains unchanged in step S305. In step S306, based on the access virtual address and access latency in the access record data, the access latency data of each memory page in the multiple memory pages is determined, and the access subject (e.g., ...) is updated. Figure 3 The node distribution and access latency of visitors are determined. In step S307, it is determined whether there are any unprocessed access records in the access record data or access record array. If yes is determined in step S307, step S301 continues. If no is determined in step S307, in step S308, the data obtained in steps S301 to S306 is used as the obtained access-related information. Return to reference Figure 1 In step S103, the first processor determines the heat data of multiple memory pages based on access-related information. For example, in step S103, the first processor can determine the heat data of multiple memory pages in parallel based on access-related information. For example, a graphics processing unit (GPU) can determine the heat data of multiple memory pages based on access-related information. For example, an artificial intelligence accelerator can determine the heat data of multiple memory pages based on access-related information. For example, a multi-core parallel central processing unit (CPU) can determine the heat data of multiple memory pages based on access-related information. For example, a field-programmable gate array (FPGA) can determine the heat data of multiple memory pages based on access-related information. For example, a GPU and a multi-core parallel CPU, etc., can determine the heat data of multiple memory pages based on access-related information.

[0049] In one or more example embodiments, the first processor determines the popularity data of multiple memory pages based on access-related information. This may include the first processor performing the following operations: for each memory page in the multiple memory pages, using preset weights to perform weighted calculations on the memory page's access frequency data, time decay popularity data, access latency data, and cross-node access data to obtain a popularity score for each memory page in the multiple memory pages, and determining the popularity data of multiple memory pages based on the popularity scores of each memory page in the multiple memory pages, thereby improving the accuracy of the popularity data.

[0050] In one or more example embodiments, determining the popularity data of multiple memory pages based on the popularity score of each memory page in a plurality of memory pages may include: classifying the multiple memory pages into hot and cold categories by using the popularity score of each memory page in the plurality of memory pages, obtaining a hot and cold category result for each memory page in the plurality of memory pages, and determining the popularity score and hot and cold category result of each memory page in the plurality of memory pages as the popularity data of the plurality of memory pages. For example, when performing hot and cold category classification, memory pages with popularity scores greater than a hot zone threshold may be classified as hot zone pages, memory pages with popularity scores less than or equal to a hot zone threshold but greater than or equal to a cold zone threshold may be classified as warm zone pages, and memory pages with popularity scores less than a cold zone threshold may be classified as cold zone pages. In addition, the popularity scores of the multiple memory pages may be sorted in ascending / descending order.

[0051] In step S104, the first processor sends the heat data to the second processor. For example, the heat data may be sent to the second processor by the graphics processor. In one or more example embodiments, the first processor may outperform the second processor in terms of computational efficiency and accuracy. The high efficiency and high accuracy of the first processor can improve the efficiency and accuracy of memory access prediction, thereby enhancing the effectiveness of memory management optimization.

[0052] In one or more example embodiments, the second processor may include a central processing unit. For example, in step S104, the central processing unit may send heat data to the second processor.

[0053] In step S105, the second processor predicts the target memory page to be accessed from among multiple memory pages based on heat data.

[0054] For example, in step S105, the central processing unit can predict the target memory page to be accessed from among multiple memory pages based on heat data.

[0055] In one or more example embodiments, predicting the target memory page to be accessed from among multiple memory pages based on heat data by the second processor may include: the second processor predicting the memory page with the highest heat score among the multiple memory pages as the target memory page to be accessed. For example, the central processing unit predicts the memory page with the highest heat score among the multiple memory pages as the target memory page to be accessed.

[0056] In one or more example embodiments, after step S105 or step S108, the process may further include: the second processor determining a hot / cold migration scheme for multiple memory pages based on the hot / cold classification results in the heat data. For example, the central processing unit may migrate memory pages that are not located in hot zones from memory pages classified as hot zones to hot zones, memory pages that are not located in warm zones from memory pages classified as warm zones to warm zones, and memory pages that are not located in cold zones from memory pages classified as cold zones to cold zones.

[0057] In one or more example embodiments, step S104 may further include: as follows Figure 2 As shown, in step S106, the first processor analyzes the access patterns of multiple memory pages using access record data to obtain access pattern data of multiple memory pages, wherein the access pattern data indicates specific patterns of access operations for memory pages; in step S107, the first processor sends the access pattern data of multiple memory pages to the second processor; in step S108, the second processor predicts the memory pages that will be accessed among the multiple memory pages based on the heat data and access pattern data.

[0058] In one or more example embodiments, the access pattern data may include at least one of temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data. Temporally correlated access pattern data reflects specific patterns in temporal correlation of access operations to memory pages in the access record data. Spatially localized access pattern data reflects specific patterns in spatial locality of access operations to memory pages in the access record data. Periodic access pattern data reflects specific patterns in periodicity of access operations to memory pages in the access record data.

[0059] In one or more example embodiments, the first processor analyzes the access patterns of multiple memory pages using access record data to obtain temporally related access pattern data of the multiple memory pages. This may include the first processor performing the following operations: using access timestamps in the access record data to obtain memory page pairs whose access time intervals satisfy a predetermined interval condition; determining temporally related memory page pairs whose association probability is greater than an association threshold; and determining the data related to the temporally related memory page pairs in the access record data and the temporal association relationships between the temporally related memory page pairs as the temporally related access pattern data of the multiple memory pages. Here, the predetermined interval condition may be, for example, but not limited to, a predetermined time window. t (e.g., but not limited to, 10ms, 1s, 5ms, 50ms, etc.). Here, the timing-associated access pattern data may include timing-associated access pattern data corresponding to each timing-associated memory page.

[0060] For example, Figure 4 This diagram illustrates the acquisition of time-related access pattern data according to one or more example embodiments. Figure 4 As shown, in step S401, the access record data is sorted by time to determine memory page pairs and predetermined time windows. t. In step S402, memory page pairs (also known as) are selected in parallel. Figure 4 (Regarding the access record pairs in the memory), proceed to steps S403 to S405. In step S403, determine whether the time interval between memory page pairs is less than the time window. If yes is determined in step S403, the page pair co-occurrence matrix is ​​accumulated in step S404. If no is determined in step S403, the current memory page pair is skipped in step S405. In step S406, it is determined whether there are memory page pairs for which steps S403 to S405 have not been executed. In step S407, the association probability (also known as the probability of association) of each memory page pair is calculated in parallel. Figure 4 (Conditional probability in the context). In step S408, it is determined whether the association probability of each memory page pair is greater than the association threshold. If it is determined in step S408, in step S409, temporal association access pattern data (also known as...) is generated. Figure 4 Temporal association rules in the data). Temporal association access pattern data (e.g., Figure 4The temporal association rules (in the data) may include, for example, data related to temporally associated memory page pairs with an association probability greater than an association threshold in the access record data, and temporal association relationships between temporally associated memory page pairs with an association probability greater than an association threshold. If it is determined in step S408 that no such pair exists, in step S410, the current memory page pair is skipped. In step S411, it is determined whether there are memory page pairs for which steps S408 to S410 have not been executed.

[0061] In one or more example embodiments, a first processor analyzes the access patterns of multiple memory pages using access record data to obtain spatial locality access pattern data for the multiple memory pages. This may include the first processor performing the following operations: analyzing whether memory pages with adjacent addresses in the multiple memory pages are accessed consecutively using the access virtual addresses and access timestamps in the access record data, determining the number of times each memory page in the multiple memory pages is consecutively accessed with its adjacent memory pages; and determining the data and counts related to the consecutively accessed adjacent memory pages in the access record data as the spatial locality access pattern data for the multiple memory pages. Here, the spatial locality access pattern data may include spatial locality access pattern data corresponding to each spatial locality memory page.

[0062] For example, Figure 5 This diagram illustrates the acquisition of spatial locality access pattern data according to one or more example embodiments. Figure 5 As shown, in step S501, each memory page in the access record data (also referred to as...) is read in parallel. Figure 5 The page identifier of the page in the memory. In step S502, for each memory page, determine the spatial locality access pattern data (also known as the page in the memory). Figure 5 The set of adjacent offsets in the data is used to traverse spatial locality access pattern data. Figure 5 For each memory page adjacent to the current memory page address in the adjacent offset set (in the set of adjacent offsets), steps S503 to S506 are executed. In step S503, the page identifier of the adjacent memory page is determined. In step S504, it is determined whether the adjacent memory page was accessed within the time window. If yes is determined in step S504, in step S505, the space-related count is incremented. If no is determined in step S504, in step S506, the current count is maintained. In step S507, the spatial locality access pattern data (in the set of adjacent offsets) is determined. Figure 5 In step S508, the spatial correlation counts of each memory page are traversed in parallel. In step S509, adjacent memory pages accessed within the time window are marked as spatially local pages, and data related to spatially local pages are determined as spatially local access pattern data.

[0063] In one or more example embodiments, a first processor analyzes the access patterns of multiple memory pages using access record data to obtain periodic access pattern data for the multiple memory pages. This may include the first processor performing the following operations: constructing an access time series for each memory page in the multiple memory pages based on the access record data; determining the dominant frequency of the Fast Fourier Transform spectrum of the access time series; identifying memory pages whose dominant frequencies satisfy a predetermined frequency condition as at least a subset of memory pages; determining the access period of the at least a subset of memory pages; and determining the data related to the at least a subset of memory pages in the access record data and the access period of the at least a subset of memory pages as the periodic access pattern data for the multiple memory pages. Here, the predetermined frequency condition may be a predetermined frequency value. Here, the periodic access pattern data may include a set of periodic memory pages, which includes each periodic memory page in the multiple memory pages and its corresponding access period.

[0064] In one or more example embodiments, the second processor predicts the target memory page to be accessed among multiple memory pages based on heat data and access pattern data. This may include the second processor performing the following operations: determining a first confidence level for a temporally correlated access pattern, a second confidence level for a spatially localized access pattern, and / or a third confidence level for a periodic access pattern; determining at least one of the temporally correlated access pattern, spatially localized access pattern, and periodic access pattern as a candidate access pattern based on whether the first confidence level, the second confidence level, and / or the third confidence level meet a confidence threshold condition; and predicting the target memory page to be accessed among multiple memory pages by using access record data, heat data, and candidate access patterns, thereby improving the accuracy of the predicted target memory page. Here, the confidence threshold condition may be, for example, but not limited to, greater than a confidence threshold. The confidence threshold may also be referred to as a prediction threshold. The first confidence level, the second confidence level, and the third confidence level are calculated based on historical prediction accuracy, and different access patterns (temporally correlated access pattern, spatially localized access pattern, and periodic access pattern) have different confidence levels. Here, historical prediction accuracy refers to the accuracy rate of multiple predictions in history. For example, historical prediction accuracy = number of accurate historical predictions / total number of historical predictions. Furthermore, high-confidence access patterns can trigger prediction operations.

[0065] It should be noted that in step S108, the prediction is not limited to generating a prediction result based on only one of the temporal correlation access pattern data, spatial locality access pattern data, and periodic access pattern data. Alternatively, a unified prediction result can be generated by comprehensively integrating the three types of data (temporal correlation access pattern data, spatial locality access pattern data, and periodic access pattern data).

[0066] Specifically, when the current page is accessed, the system first queries the temporal correlation access pattern data, spatial locality access pattern data, and periodic access pattern data (which can also be referred to as temporal correlation features, spatial locality features, and periodic features, respectively). If the confidence level of one of the temporal correlation access pattern data, spatial locality access pattern data, and periodic access pattern data reaches a preset threshold, an access prediction can be directly generated based on that single access pattern data (i.e., a single feature). If two or three of the temporal correlation access pattern data, spatial locality access pattern data, and periodic access pattern data reach the preset threshold, the prediction results based on different access pattern data can be fused according to preset weights to obtain a comprehensive prediction result, and then prefetch suggestions or migration suggestions can be generated based on this result.

[0067] In one or more example embodiments, predicting a target memory page to be accessed from multiple memory pages using access record data, popularity data, and candidate access patterns may include: when the candidate access patterns include one or more of temporally related access patterns, spatially local access patterns, and periodic access patterns, performing one or more of the following operations to obtain one or more of a first candidate memory page, a second candidate memory page, and a third candidate memory page related to the currently accessed memory page from the multiple memory pages: determining the first candidate memory page related to the currently accessed memory page from the multiple memory pages using popularity data and temporally related access pattern data, and using popularity data... Using spatial locality access pattern data, a second candidate memory page related to the currently accessed memory page is identified from multiple memory pages. A third candidate memory page related to the currently accessed memory page is identified from multiple memory pages using popularity data and periodic access pattern data. By using one or more of the weights of temporal correlation access patterns, spatial locality access patterns, and periodic access patterns, the target memory page to be accessed is predicted from one or more of the first, second, and third candidate memory pages. Therefore, by combining multiple candidate memory pages and their different weights to predict the target memory page, the accuracy of the predicted target memory page can be improved. The first, second, and third candidate memory pages can be the same candidate memory page or different candidate memory pages. The sum of the weights of temporally associative access patterns, spatially locale access patterns, and periodic access patterns is 1. The weight of temporally associative access patterns indicates their importance in predicting target memory pages, the weight of spatially locale access patterns indicates their importance in predicting target memory pages, and the weight of periodic access patterns indicates their importance in predicting target memory pages.

[0068] For example, when the candidate access pattern includes only one of the following: temporal correlation access pattern, spatial locality access pattern, and periodic access pattern, the candidate memory page corresponding to the candidate access pattern is determined as the target memory page. For example, when the candidate access pattern includes only two of the following: temporal correlation access pattern, spatial locality access pattern, and periodic access pattern, if the candidate memory pages corresponding to the two candidate access patterns are the same, then that candidate memory page is determined as the target memory page; if the candidate memory pages corresponding to the two candidate access patterns are different, then the candidate memory page corresponding to the candidate access pattern with the larger weight among the two candidate access patterns is determined as the target memory page. For example, when the candidate access pattern includes only three of the following: temporal correlation access pattern, spatial locality access pattern, and periodic access pattern, if the first, second, and third candidate memory pages are the same candidate memory page, then that same candidate memory page is determined as the target memory page; if the first, second, and third candidate memory pages are three different candidate memory pages, then the candidate memory page corresponding to the candidate access pattern with the largest weight among the three candidate access patterns is determined as the target memory page. If the first candidate memory page and the second candidate memory page are the same candidate memory page, and the third candidate memory page is different from the first candidate memory page and the second candidate memory page, the weight of the same candidate memory page is determined according to the weight of the temporal correlation access mode and the weight of the spatial locality access mode, and the weight of the third candidate memory page is determined according to the weight of the periodic access mode. The candidate memory page with the larger weight among the same candidate memory page and the third candidate memory page is determined as the target memory page.

[0069] As an example, the weight of the temporally related access pattern is 0.4, the weight of the spatially local access pattern is 0.35, and the weight of the periodic access pattern is 0.25. The first candidate memory page, the second candidate memory page, and the third candidate memory page are three different candidate memory pages. Therefore, the first candidate memory page corresponding to the temporally related access pattern is determined as the target memory page.

[0070] As an example, the weight of the temporally related access pattern is 0.4, the weight of the spatially local access pattern is 0.35, and the weight of the periodic access pattern is 0.25. The first and third candidate memory pages are the same, and the second candidate memory page is different from the first and third candidate memory pages. The weight of the same candidate memory pages (the same first and third candidate memory pages) is determined to be the sum of 0.4 and 0.25, which is 0.65. Since 0.65 is greater than 0.35, the same candidate memory pages (the same first and third candidate memory pages) are determined as the target memory pages.

[0071] As an example, the weight of the temporally related access pattern is 0.4, the weight of the spatially local access pattern is 0.35, and the weight of the periodic access pattern is 0.25. The first and third candidate memory pages are the same, and the second candidate memory page is different from the first and third candidate memory pages. The weight of the same candidate memory pages (the same first and third candidate memory pages) is determined to be the average of 0.4 and 0.25, which is 0.325. Since 0.325 is less than 0.35, the second candidate memory page is determined as the target memory page.

[0072] For example, when determining the first candidate memory page related to the currently accessed memory page A among multiple memory pages by using heat data and time-series-related access pattern data, the time-series-related access pattern data (e.g., time-series association rules) related to the currently accessed memory page A is traversed. Based on the time-series-related access pattern data, the predicted access time of each time-series-related memory page among all time-series-related memory pages is determined. The time-series-related memory page whose predicted access time is closest to the current time is selected as the first candidate memory page.

[0073] For example, when identifying a second candidate memory page related to the currently accessed memory page A from multiple memory pages using heat data and spatial locality access pattern data, it is determined whether the currently accessed memory page A is a spatially local page based on the spatial locality access pattern data. If the currently accessed memory page A is a spatially local page, then the spatial locality access pattern data corresponding to the currently accessed memory page A (e.g., ...) included in the spatial locality access pattern data are used. Figure 5 The spatial locality memory page that is continuously accessed by the currently accessed memory page A in the set of adjacent offsets is selected as the second candidate memory page.

[0074] For example, when determining the third candidate memory page related to the currently accessed memory page A among multiple memory pages by using popularity data and periodic access pattern data, the set of periodic memory pages included in the periodic access pattern data is traversed, the next access time of each periodic memory page in the set of periodic memory pages is determined, and the periodic memory page whose next access time is closest to the current time is selected as the third candidate memory page.

[0075] In one or more example embodiments, after step S105 or step S108, the method may further include: generating a target memory page migration suggestion and a target memory page prefetch suggestion by using the target memory page. For example, the target memory page may be migrated to a preset location so that the target memory page is preferentially located near high-frequency access nodes. For example, the target memory page may be prefetched so that the target memory page can be accessed faster, thereby further reducing memory access latency.

[0076] In one or more example embodiments, after step S105 or step S108, the method may further include: determining the hit rate of memory access prediction by the second processor based on the target memory page and the actual memory page accessed; and adjusting, based on the hit rate, a predetermined interval condition and association threshold related to the time-series correlated access pattern data, a predetermined frequency condition related to the periodic access pattern data, and the size of a preset time period. For example, the second processor determines the hit rate and false alarm rate of memory access prediction by determining whether the target memory page predicted multiple times has actually been accessed. The predicted hit rate = the number of predicted hits / the total number of predictions. The predicted false alarm rate = the number of predicted misses / the total number of predictions. For example, the confidence threshold can be adjusted based on the hit rate, the association threshold can be adjusted based on the false alarm rate, and the time window (e.g., time window) can be dynamically adjusted based on the hit rate and the false alarm rate. The size of t). Here, the time window is used to determine the observation range of the access pattern data. For example, the parameters can be adjusted in segments according to the intervals where the predicted hit rate and false alarm rate fall.

[0077] As an example, when adjusting the confidence threshold based on the prediction hit rate, the following range adjustment method can be adopted: When the hit rate is below 40%, it indicates that there are many invalid predictions in the current prediction results, and the confidence threshold should be increased, for example, from 0.60 to 0.70, to suppress the execution of low-confidence predictions; when the hit rate is in the range of 40% to 70%, it indicates that the prediction effect is average, and the current confidence threshold can be kept unchanged, for example, kept at 0.60 or only slightly adjusted; when the hit rate is above 70%, it indicates that the prediction results are relatively reliable, and the confidence threshold can be appropriately reduced, for example, from 0.60 to 0.50, to expand the range of candidate pages that can trigger predictions.

[0078] As an example, when adjusting the association threshold based on the false positive rate, the following range adjustment method can be adopted: When the false positive rate is higher than 35%, it indicates that the association probability requirement is too lenient, and the association threshold should be increased, for example, from 0.50 to 0.65, retaining only strong association rules; when the false positive rate is in the range of 15% to 35%, it indicates that the association probability requirement is basically stable, and the association threshold can be kept unchanged; when the false positive rate is lower than 15%, it indicates that the association probability requirement is relatively conservative, and the association threshold can be appropriately reduced, for example, from 0.50 to 0.40, to discover more potential associated pages.

[0079] As an example, when adjusting the time window size based on both hit rate and false alarm rate, the following interval adjustment method can be adopted: When the hit rate is low and the false alarm rate is high, it indicates that the time window may be too large, mixing in too many old access behaviors. In this case, the time window can be reduced, for example, from 100ms to 50ms, to enhance the sensitivity to recent hot spots; when the hit rate is high and the false alarm rate is low, it indicates that access patterns can be captured stably. The time window can be appropriately increased, for example, from 50ms to 80ms or 100ms, to cover a more complete access cycle; when the hit rate is moderate but the false alarm rate is not high, the time window can be kept unchanged to avoid frequent oscillations.

[0080] As an example, the following control table can be preset: Hit rate < 40% and false alarm rate > 35%: Confidence threshold increased by 0.10, correlation threshold increased by 0.10, and time window reduced by 50%; Hit rate between 40% and 70% and false alarm rate between 15% and 35%: All parameters remain unchanged; Hit rate > 70% and false alarm rate < 15%: Confidence threshold decreased by 0.10, correlation threshold decreased by 0.05, and time window expanded by 20% to 50%.

[0081] The above range thresholds and adjustment ranges are only examples. In actual applications, they can be adaptively set according to the type of business load, memory page access density, GPU processing latency, and system bandwidth resources.

[0082] Furthermore, in this disclosure, temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data can also be stored in a pattern library. The pattern library is updated by storing the temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data obtained in subsequent memory access predictions. This allows for improved efficiency in determining candidate memory pages based on the pattern library, thereby improving the efficiency of memory access prediction and enhancing the effectiveness of memory management optimization.

[0083] The above has been combined Figures 1 to 5 A memory access prediction method according to one or more example embodiments has been described. Hereinafter, reference will be made to... Figures 6 to 8A memory access prediction system and its components, and a computing device, according to one or more example embodiments, are described.

[0084] Figure 6 A block diagram of a memory access prediction system according to one or more example embodiments is shown.

[0085] Reference Figure 6 The memory access prediction system 600 includes an access data acquisition unit 601, an access information determination unit 602, a popularity data determination unit 603, a popularity data sending unit 604, and a memory page prediction unit 605. Furthermore, the memory access prediction system 600 also includes a first processor (not shown) and a second processor (not shown).

[0086] The access data acquisition unit 601 is configured to acquire memory access record data of the memory access prediction system 600 through the first processor.

[0087] In one or more example embodiments, the first processor may include at least one of a graphics processor, an artificial intelligence accelerator, a multi-core parallel central processing unit, and a field-programmable gate array.

[0088] In one or more example embodiments, the access record data may include at least one of the following: the access virtual address of the memory that was accessed at least once, the access timestamp, the access subject, and the access delay.

[0089] In one or more example embodiments, the memory access prediction system 600 may further include: an access data determination unit (not shown), configured to acquire access record data of memory within a preset time period by a second processor; and an access data writing unit (not shown), configured to have the second processor write the access record data to a shared memory buffer accessible by a first processor, so that the first processor can acquire the access record data.

[0090] The access information determination unit 602 is configured to determine access-related information for each of a plurality of accessed memory pages based on access record data by a first processor. Here, the access-related information may include information reflecting the characteristics of the access operation for each memory page.

[0091] In one or more example embodiments, access-related information may include at least one of access frequency data, time decay heat data, access latency data, and cross-node access data.

[0092] In one or more example embodiments, the access information determination unit 602 may be configured to perform at least one of the following operations by a first processor: determining multiple memory pages accessed by using access virtual addresses in access record data; determining access frequency data for each memory page from the access virtual addresses and access timestamps in the access record data; determining change data of the access frequency data for each memory page for each memory page in the multiple memory pages, and determining the change data as time decay heat data for each memory page; determining access latency data for each memory page from the access virtual addresses and access latency in the access record data; determining node information of the access subject of each memory page from the access subject in the access record data; and determining cross-node access data for each memory page in the multiple memory pages by comparing the node information of each memory page in the multiple memory pages with the node information of the access subject.

[0093] The heat data determination unit 603 is configured to determine the heat data of multiple memory pages based on access-related information by the first processor.

[0094] In one or more example embodiments, the popularity data determination unit 603 may be configured to perform the following operations by a first processor: for each of the multiple memory pages, perform weighted calculations on access frequency data, time decay popularity data, access latency data, and cross-node access data using preset weights to obtain a popularity score for each of the multiple memory pages; and determine the popularity data of the multiple memory pages based on the popularity scores of each of the multiple memory pages.

[0095] In one or more example embodiments, the heat data determination unit 603 may be configured to perform the following operations by a first processor: classifying the multiple memory pages into hot and cold categories by using the heat score of each memory page in the multiple memory pages to obtain the hot and cold classification result of each memory page in the multiple memory pages; and determining the heat score and the hot and cold classification result of each memory page in the multiple memory pages as heat data of the multiple memory pages.

[0096] The heat data transmission unit 604 is configured to transmit heat data to the second processor via the first processor.

[0097] In one or more example embodiments, the second processor may include a central processing unit.

[0098] The memory page prediction unit 605 is configured to predict, based on heat data, a target memory page to be accessed from among multiple memory pages by a second processor.

[0099] In one or more example embodiments, the second processor predicts the target memory page to be accessed from among multiple memory pages based on heat data, including: the second processor predicts the memory page with the highest heat score among the multiple memory pages as the target memory page to be accessed from among the multiple memory pages.

[0100] In one or more example embodiments, the memory access prediction system 600 may further include: a migration scheme determination unit (not shown), configured to determine a scheme for cold and hot migration of multiple memory pages by a second processor based on cold and hot classification results in heat data.

[0101] In one or more example embodiments, the memory access prediction system 600 may further include: a pattern data determination unit (not shown), configured to analyze the access patterns of multiple memory pages by using access record data through a first processor to obtain access pattern data of multiple memory pages; a pattern data sending unit (not shown), configured to send the access pattern data of multiple memory pages to a second processor through the first processor; and a comprehensive prediction unit (not shown), configured to predict the memory pages to be accessed among the multiple memory pages based on heat data and access pattern data through the second processor.

[0102] In one or more example embodiments, access pattern data may include at least one of temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data.

[0103] In one or more example embodiments, the pattern data determination unit may be configured to perform the following operations by a first processor: obtaining memory page pairs in multiple memory pages whose access time intervals satisfy a predetermined interval condition by using access timestamps in access record data; determining time-related memory page pairs in memory page pairs whose association probability is greater than an association threshold; and determining the data related to time-related memory page pairs in access record data and the time-related association relationships between time-related memory page pairs as time-related access pattern data for multiple memory pages.

[0104] In one or more example embodiments, the pattern data determination unit may be configured to perform the following operations by a first processor: analyzing whether memory pages with adjacent addresses in a plurality of memory pages are accessed consecutively by using access virtual addresses and access timestamps in access record data, determining the number of times each memory page in the plurality of memory pages is accessed consecutively with memory pages with adjacent addresses; and determining the data and number of times in the access record data related to the memory pages with adjacent addresses that are accessed consecutively as spatial locality access pattern data of the plurality of memory pages.

[0105] In one or more example embodiments, the pattern data determination unit may be configured to perform the following operations by a first processor: constructing an access time series for each of a plurality of memory pages based on access record data; determining the dominant frequency of the fast Fourier transform spectrum of the access time series; identifying memory pages whose dominant frequencies satisfy a predetermined frequency condition as at least a subset of memory pages; determining the access period of at least a subset of memory pages; and determining the data related to at least a subset of memory pages in the access record data and the access period of at least a subset of memory pages as periodic access pattern data for the plurality of memory pages.

[0106] In one or more example embodiments, the comprehensive prediction unit may be configured to perform the following operations via a second processor: determining a first confidence level of a temporally correlated access pattern, a second confidence level of a spatially localized access pattern, and / or a third confidence level of a periodic access pattern; determining at least one of the temporally correlated access pattern, spatially localized access pattern, and periodic access pattern as a candidate access pattern based on whether the first confidence level, the second confidence level, and / or the third confidence level meet a confidence threshold condition; and predicting the target memory page to be accessed among multiple memory pages by using access record data, popularity data, and candidate access patterns.

[0107] In one or more example embodiments, the comprehensive prediction unit may be configured to perform the following operations via a second processor: when the candidate access patterns include one or more of temporally correlated access patterns, spatially localized access patterns, and periodic access patterns, perform one or more of the following operations to obtain one or more of a first candidate memory page, a second candidate memory page, and a third candidate memory page related to the currently accessed memory page from a plurality of memory pages: determining the first candidate memory page related to the currently accessed memory page from a plurality of memory pages by using heat data and temporally correlated access pattern data; determining the second candidate memory page related to the currently accessed memory page from a plurality of memory pages by using heat data and spatially localized access pattern data; determining the third candidate memory page related to the currently accessed memory page from a plurality of memory pages by using heat data and periodic access pattern data; predicting the target memory page to be accessed from a plurality of memory pages by using one or more of the weights of temporally correlated access patterns, spatially localized access patterns, and periodic access patterns.

[0108] In one or more example embodiments, the memory access prediction system 600 may further include a feedback optimization unit (not shown) configured to: determine the hit rate of memory access prediction based on the target memory page and the actual memory page being accessed by a second processor; and adjust, based on the hit rate, predetermined interval conditions and association thresholds related to time-series-related access pattern data, predetermined frequency conditions related to periodic access pattern data, and the size of a preset time period by the second processor.

[0109] Regarding the memory access prediction system in the above embodiments, the specific manner in which each unit performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0110] Furthermore, according to one or more example embodiments, a computer-readable storage medium is also provided having a computer program stored thereon that, when executed, implements the memory access prediction method according to one or more example embodiments.

[0111] In one or more example embodiments, the computer-readable storage medium may carry one or more computer programs that, when executed, perform the following steps: a first processor of the memory access prediction system acquires memory access record data of the memory access prediction system; the first processor determines access-related information for each of a plurality of memory pages accessed, based on the access record data, wherein the access-related information includes information reflecting the characteristics of the access operation for each memory page; the first processor determines heat data of the plurality of memory pages based on the access-related information; the first processor sends the heat data to a second processor of the memory access prediction system; and the second processor predicts the target memory page to be accessed among the plurality of memory pages based on the heat data.

[0112] Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a computer program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof. A computer-readable storage medium can be included in any apparatus; it can also exist independently without being assembled into that apparatus.

[0113] Furthermore, according to one or more example embodiments, a computer program product is also provided, wherein the instructions in the computer program product are executable by a processor of a computer device to perform a method for memory access prediction according to one or more example embodiments.

[0114] The above has been combined Figure 6 A memory access prediction system according to one or more example embodiments has been described. Next, in conjunction with... Figure 7 A computing device according to one or more example embodiments is described.

[0115] Figure 7 A schematic diagram of a computing device 700 according to one or more example embodiments is shown.

[0116] Reference Figure 7 A computing device 700 according to one or more example embodiments includes a memory 710 and a first processor 720 and a second processor 730. The memory 710 stores a computer program that, when executed by the first processor 720 or the second processor 730, implements a memory access prediction method according to one or more example embodiments.

[0117] As an example, computing device 700 may be a computer, smartphone, tablet device, personal digital assistant, or other electronic terminal capable of executing the aforementioned computer programs. In computing device 700, the first processor 720 may include at least one of a graphics processing unit (GPU), an artificial intelligence accelerator, a multi-core parallel central processing unit, a field-programmable gate array (FPGA), a dedicated processor system, a microcontroller, or a microprocessor, and the second processor 730 may include a central processing unit (CPU). By way of example and not limitation, the first processor 720 and the second processor 730 may each further include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The first processor 720 and the second processor 730 may each execute instructions or code stored in memory 710, which may also store data. Instructions and data may also be sent and received via a network through a network interface device, wherein the network interface device may employ any known transmission protocol. Memory 710 may be integrated with the first processor 720 and the second processor 730, for example, by arranging RAM or flash memory within an integrated circuit microprocessor. Furthermore, the memory 710 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 710, the first processor 720, and the second processor 730 may be operatively coupled or may communicate with each other, for example, via I / O ports, network connections, etc., enabling the first processor 720 and the second processor 730 to read files stored in the memory.

[0118] In addition, the computing device 700 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, touch input device, etc.). All components of the computing device 700 can be connected to each other via a bus and / or a network.

[0119] Figure 8 A schematic diagram of a memory access prediction system according to one or more example embodiments is shown.

[0120] Reference Figure 8 The memory access prediction system 800 includes a central processing unit (e.g., Figure 8 The data acquisition layer 801 in the CPU, and the graphics processor (e.g., Figure 8 The graphics processing unit (GPU) in the GPU (e.g., the graphics processing unit analysis layer) Figure 8 The GPU analysis layer (802), the prediction and decision layer in the central processing unit (803), and the feedback optimization layer in the central processing unit (804) are all part of this process.

[0121] The data acquisition layer 801 acquires memory access record data of the memory of the memory access prediction system 800 within a preset time period, and writes the access record data into a shared memory buffer accessible to the graphics processor, so that the graphics processor can obtain the access record data. For example, the data acquisition layer 801 obtains access record data by performing PMU event acquisition in step 8011 and page table access bit sampling in step 8012 (executed in parallel with step 8011), and writes the access record data into the shared buffer for management in step 8013.

[0122] The graphics processor analysis layer 802 acquires memory access record data. Based on the access record data, it determines access-related information for each of the multiple memory pages accessed. This access-related information includes information reflecting the characteristics of the access operations for each memory page. Based on the access-related information, it determines the popularity data of the multiple memory pages and sends this popularity data to the central processing unit. For example, in step 8021, the graphics processor analysis layer 802 performs data preprocessing on the access record data; in step 8022, it performs multi-dimensional popularity calculation based on the preprocessed access record data to obtain a popularity score; in step 8023, it performs hot / cold classification of the memory pages in the access record data based on the popularity score to obtain the hot / cold classification results; and in step 8024 (executed in parallel with step 8023), it extracts page features from the access record data to perform access pattern mining, obtaining memory page access pattern data.

[0123] The prediction and decision layer 803 predicts the target memory page to be accessed among multiple memory pages based on heat data. For example, in step 8031, the prediction and decision layer 803 performs access prediction based on the hot and cold classification results of memory pages obtained by the graphics processor analysis layer 802 in step 8023 and the access pattern data of memory pages obtained in step 8024, to predict the memory page to be accessed among multiple memory pages. In step 8032, page migration and prefetching decisions are made based on the prediction results (target memory page) and the currently accessed page.

[0124] The feedback optimization layer 804 determines the hit rate of memory access prediction based on the target memory page and the actual accessed memory page. Based on the hit rate, it adjusts the predetermined interval conditions and correlation thresholds related to time-series-related access pattern data, the predetermined frequency conditions related to periodic access pattern data, and the size of the preset time period. For example, in step 8041, the feedback optimization layer 804 evaluates the hit rate based on whether the prediction result (target memory page) is actually accessed; in step 8042, it performs adaptive parameter adjustment based on the hit rate evaluation result; and in step 8043, it updates the access pattern library.

[0125] Regarding the memory access prediction system in the above embodiments, the specific manner in which each layer performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0126] The above has been referred to Figures 1 to 8 A memory access prediction method and system according to one or more example embodiments are described. However, it should be understood that: Figure 6 The memory access prediction system and its units shown can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. Figure 7 The computing device shown is not limited to the components shown above, but some components may be added or removed as needed, and the above components may also be combined.

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0128] According to embodiments of the present disclosure, the memory access prediction method and system, computing device, storage medium, and computer program product obtain memory access record data of the memory access prediction system by a first processor of the memory access prediction system, and determine access-related information for each of a plurality of memory pages accessed by the first processor based on the access record data. The access-related information includes information reflecting the characteristics of the access operation for each memory page. Based on the access-related information, the first processor determines the heat data of the plurality of memory pages, and sends the heat data to a second processor of the memory access prediction system. The second processor predicts the target memory page to be accessed among the plurality of memory pages based on the heat data, which can reduce the occupancy and overhead of the second processor.

[0129] Furthermore, the memory access prediction method and system, computing device, storage medium, and computer program product according to embodiments of this disclosure also improve the efficiency and accuracy of memory access prediction by leveraging the high efficiency and high accuracy of the first processor, thereby enhancing the effect of memory management optimization.

[0130] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A memory access prediction method, characterized in that, The method is applied to a memory access prediction system, the memory access prediction system including a first processor and a second processor, and includes: The first processor acquires the memory access record data of the memory access prediction system; The first processor determines access-related information for each of the multiple memory pages accessed in the memory based on the access record data, wherein the access-related information includes information reflecting the characteristics of the access operation for each memory page; The first processor determines the heat data of the plurality of memory pages based on the access-related information; The first processor sends the heat data to the second processor; The second processor predicts the target memory page to be accessed from among the plurality of memory pages based on the heat data.

2. The method according to claim 1, characterized in that, The access record data includes at least one of the following: the access virtual address of the memory accessed at least once, the access timestamp, the access subject, and the access latency. The access-related information includes at least one of the following: access frequency data, time decay heat data, access latency data, and cross-node access data.

3. The method according to claim 2, characterized in that, The step of the first processor determining access-related information in multiple accessed memory pages based on the access record data includes the first processor performing at least one of the following operations: By using the access virtual address in the access record data, the accessed memory pages are determined, and the access frequency data of each memory page in the plurality of memory pages is determined from the access virtual address and the access timestamp in the access record data. For each of the plurality of memory pages, determine the change data of the access frequency data of each memory page, and determine the change data as the time decay heat data of each memory page; From the access virtual address and the access latency in the access record data, determine the access latency data for each of the plurality of memory pages; The node information of the access subject in each of the plurality of memory pages is determined from the access subject in the access record data, and the cross-node access data of each of the plurality of memory pages is determined by comparing the node information of each of the plurality of memory pages with the node information of the access subject.

4. The method according to claim 2, characterized in that, The step of the first processor determining the heat data of the plurality of memory pages based on the access-related information includes the first processor performing the following operations: For each of the plurality of memory pages, the access frequency data, the time decay heat data, the access latency data, and the cross-node access data are weighted using preset weights to obtain a heat score for each of the plurality of memory pages; The popularity data of the multiple memory pages is determined based on the popularity score of each memory page. The step of the second processor predicting the target memory page to be accessed from the plurality of memory pages based on the heat data includes: The second processor predicts the memory page with the highest heat score among the plurality of memory pages as the target memory page to be accessed.

5. The method according to claim 4, characterized in that, The process of determining the popularity data of the plurality of memory pages based on the popularity score of each memory page includes: The multiple memory pages are classified into hot and cold categories by using the heat score of each memory page, and the hot and cold category result of each memory page is obtained. The heat score and the hot / cold classification result of each of the plurality of memory pages are determined as the heat data of the plurality of memory pages. The method further includes: The second processor determines a cold / hot migration scheme for the multiple memory pages based on the cold / hot classification results.

6. The method according to claim 2, characterized in that, The method further includes: The first processor analyzes the access patterns of the plurality of memory pages using the access record data to obtain access pattern data of the plurality of memory pages; The first processor sends the access mode data of the plurality of memory pages to the second processor; The second processor predicts which memory pages will be accessed from among the plurality of memory pages based on the heat data and the access pattern data.

7. The method according to claim 6, characterized in that, The access pattern data includes at least one of temporally correlated access pattern data, spatially localized access pattern data, and periodic access pattern data. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain the time-related access pattern data of the plurality of memory pages includes the first processor performing the following operations: The memory page pairs whose access time intervals satisfy a predetermined interval condition are obtained by using the access timestamps in the access record data. Identify time-series associated memory page pairs whose association probability is greater than the association threshold. The data related to the time-series associated memory page pairs in the access record data, and the time-series association relationships between the time-series associated memory page pairs, are determined as the time-series associated access pattern data of the multiple memory pages. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain spatial locality access pattern data of the plurality of memory pages includes the first processor performing the following operations: By using the access virtual address and access timestamp in the access record data, we can analyze whether the memory pages with adjacent addresses in the plurality of memory pages are accessed consecutively, and determine the number of times each memory page in the plurality of memory pages is accessed consecutively with the memory pages with adjacent addresses. The data related to memory pages adjacent to consecutively accessed addresses in the access record data, along with the number of accesses, are determined as the spatial locality access pattern data of the multiple memory pages. The step of the first processor analyzing the access patterns of the plurality of memory pages using the access record data to obtain the periodic access pattern data of the plurality of memory pages includes the first processor performing the following operations: Based on the access record data, construct the access time sequence for each of the multiple memory pages; Determine the dominant frequency of the Fast Fourier Transform spectrum of the access time series; The memory pages whose main frequency meets a predetermined frequency condition among the plurality of memory pages are identified as at least a portion of the memory pages; Determine the access cycle of at least a portion of the memory pages; The data related to the at least some memory pages in the access record data and the access period of the at least some memory pages are determined as the periodic access pattern data of the plurality of memory pages.

8. The method according to claim 1, characterized in that, The first processor includes at least one of a graphics processor, an artificial intelligence accelerator, a multi-core parallel central processing unit, and a field-programmable gate array, and the second processor includes a central processing unit.

9. The method according to claim 7, characterized in that, The step of the second processor predicting the target memory page to be accessed from among the plurality of memory pages based on the heat data and the access pattern data includes the second processor performing the following operations: Determine the first confidence level of temporally correlated access patterns, the second confidence level of spatially localized access patterns, and / or the third confidence level of periodic access patterns; Based on whether the first confidence level, the second confidence level, and / or the third confidence level meet the confidence threshold condition, at least one of the temporal correlation access pattern, the spatial locality access pattern, and the periodic access pattern is determined as a candidate access pattern. By using the access record data, the popularity data, and the candidate access patterns, the target memory page to be accessed among the plurality of memory pages is predicted.

10. The method according to claim 9, characterized in that, The step of predicting the target memory page to be accessed from among the plurality of memory pages by using the access record data, the popularity data, and the candidate access patterns includes: When the candidate access pattern includes one or more of the temporally related access pattern, the spatially local access pattern, and the periodic access pattern, perform one or more of the following operations to obtain one or more of the first candidate memory page, the second candidate memory page, and the third candidate memory page related to the currently accessed memory page from the plurality of memory pages: By using the heat data and the time-series correlation access pattern data, a first candidate memory page related to the currently accessed memory page is determined from among the plurality of memory pages. By using the heat data and the spatial locality access pattern data, a second candidate memory page related to the currently accessed memory page is determined from among the plurality of memory pages. By using the heat data and the periodic access pattern data, a third candidate memory page related to the currently accessed memory page is determined from among the plurality of memory pages; By using one or more of the weights of temporal correlation access patterns, spatial locality access patterns, and periodic access patterns, the target memory page to be accessed is predicted from one or more of the first candidate memory page, the second candidate memory page, and the third candidate memory page.

11. The method according to claim 10, characterized in that, The method further includes: The second processor acquires the memory access record data within a preset time period; The second processor writes the access record data into a shared memory buffer accessible to the first processor, so that the first processor can obtain the access record data.

12. The method according to claim 11, characterized in that, The method further includes: The second processor determines the hit rate of memory access prediction based on the target memory page and the actual memory page being accessed; The second processor adjusts, based on the hit rate, the predetermined interval conditions and association thresholds related to the time-series-related access pattern data, the predetermined frequency conditions related to the periodic access pattern data, and the size of the preset time period.

13. A memory access prediction system, characterized in that, The system includes: First processor; Second processor; The access data acquisition unit is configured to acquire memory access record data of the memory access prediction system through the first processor; The access information determination unit is configured to determine access-related information for each of a plurality of accessed memory pages in the memory based on the access record data by the first processor, wherein the access-related information includes information reflecting the characteristics of the access operation for each memory page; The popularity data determination unit is configured to determine the popularity data of the plurality of memory pages based on the access-related information by the first processor; A heat data sending unit is configured to send the heat data to a second processor via the first processor; The memory page prediction unit is configured to predict, based on the heat data, a target memory page to be accessed from among the plurality of memory pages by the second processor.

14. A computing device, characterized in that, include: First processor; Second processor; as well as A memory storing a computer program that, when executed by the first processor or the second processor, implements the method of any one of claims 1 to 12.

15. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 12.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 12.

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