Cache circuit and method of operation thereof

By using a high-speed cache circuit with a low-power, high-efficiency access mechanism, and by combining a counting circuit and a temporary storage circuit, the efficiency and power consumption problems of memory circuit read-modify-write operations in high-bandwidth applications are solved, achieving high-efficiency operation and low power consumption per clock cycle.

CN122240534APending Publication Date: 2026-06-19REALTEK SEMICON CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
REALTEK SEMICON CORP
Filing Date
2024-12-18
Publication Date
2026-06-19

AI Technical Summary

⚠Technical Problem

In high-bandwidth applications, existing technologies cannot effectively perform read-modify-write operations per clock cycle, and also suffer from excessive power consumption.

⚗Method used

A high-speed cache circuit with a low-power, high-efficiency access mechanism is adopted. By combining a write counting circuit, an address temporary storage circuit, and a data temporary storage circuit, the count value is used to read and write the parallel cache in a cyclical sequence. Read and write operations are avoided when the valid bits of the address and data are invalid, thereby reducing power consumption.

🎯Benefits of technology

It enables read-modify-write operations to be performed every clock cycle in high-bandwidth applications while maintaining relatively low power consumption, thus improving memory access efficiency.

✦ Generated by Eureka AI based on patent content.

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Abstract

This application discloses a cache circuit with a low-power, high-efficiency access mechanism. A write counter circuit sequentially generates count values ​​corresponding to reference values. In the address buffer circuit, the address buffer demultiplexer receives a valid write address and writes it to the address buffer corresponding to the reference value according to the count value. A comparison circuit compares the read address content with the stored address content in the address buffer to generate a comparison result. A priority order decoding circuit determines the latest matching comparison result based on the count value to generate a selection signal. In the data buffer circuit, the data buffer demultiplexer receives valid write data corresponding to the valid write address and writes it to the data buffer corresponding to the reference value according to the count value. A selection circuit receives a selection signal to select either the stored data in the data buffer or the read data output from memory as the actual read data.
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