Anpc topology hardware-in-the-loop simulation method and system, electronic equipment and storage medium

Abstract

This application relates to an ANPC topology hardware-in-the-loop simulation method, system, electronic device, and storage medium. The method involves constructing a switching function model of the ANPC topology; constructing an interpolation calculation model for determining switching actions; embedding the switching function model into a real-time simulation platform and configuring the output of the interpolation calculation model to interface with the control end of the switching function model; controlling the switching function model through a precise switching control signal; connecting the real-time simulation platform to a real ANPC converter controller via a hardware interface; the ANPC converter controller outputs the original switching control signal to the interpolation calculation model and receives the voltage and current values ​​output by the switching function model; and forming a closed loop with the ANPC converter controller, the interpolation calculation model, and the switching function model for hardware-in-the-loop simulation testing.

Description

Technical Field

[0001] This application relates to the field of hardware simulation technology, and in particular to ANPC topology hardware-in-the-loop simulation methods, systems, electronic devices, and storage media. Background Technology

[0002] Currently, real-time simulation of power electronic equipment often requires the use of specific hardware-in-the-loop simulation platforms. This involves using FPGAs (Field-Effect Programmable Logic Arrays) to achieve small-step real-time simulation of power electronic equipment, combined with conventional large-step simulation based on CPUs (Central Processing Units) to complete the simulation task. ANPC three-level converters, with their advantages of low output voltage harmonics, uniform device losses, and high power handling capacity, have become one of the core topologies in high-power power electronic conversion fields (such as grid connection of new energy power generation and high-end industrial drives). When applied to hardware-in-the-loop real-time simulation scenarios, ANPC three-level converters require simulation steps smaller than those used in conventional electromagnetic transient simulations to achieve accurate simulation of high-frequency power electronic switches.

[0003] However, hardware-in-the-loop simulation methods for ANPC topologies face two major technical bottlenecks: First, in terms of modeling methods, while traditional detailed physical models can guarantee accuracy, their complexity and computational burden make it difficult to meet the real-time requirements of extremely small step sizes. On the other hand, while simplification methods such as averaging models improve speed, they cannot accurately simulate the transient switching process, resulting in a significant decrease in simulation accuracy. In other words, there is an irreconcilable contradiction between model detail and real-time performance. Second, at the simulation algorithm level, fixed-step simulation will produce significant time quantization errors due to the asynchrony between the switching action time and the simulation step size, leading to waveform distortion and harmonic analysis distortion. Although interpolation algorithms have been proposed to correct the switching time, they are often computationally complex and introduce additional delays, making it difficult to meet the requirements of high real-time performance and high determinism in hardware-in-the-loop simulation.

[0004] Therefore, existing simulation schemes suffer from a lack of proprietary models for ANPC topology electronic devices, as well as low simulation accuracy and efficiency in real-time simulation scenarios. Summary of the Invention

[0005] This application provides an ANPC topology hardware-in-the-loop simulation method, system, electronic device, and storage medium to at least solve the problems of low simulation accuracy and low simulation efficiency of ANPC topology in real-time simulation scenarios in related technologies.

[0006] In a first aspect, this application provides a hardware-in-the-loop simulation method for ANPC topology, the method comprising the following steps: Construct a switching function model for the ANPC topology; wherein, the switching function model is based on the voltage and current relationship between the AC and DC sides of the ANPC topology, and is obtained by introducing a switching function that characterizes the on / off state of the switch for external characteristic modeling; An interpolation calculation model is constructed to determine the switching action; wherein, the interpolation calculation model calculates the time-corrected accurate switching control signal by detecting the edge of the original switching control signal and combining the modulation signal and the carrier signal. The switching function model is embedded into a real-time simulation platform, and the output of the interpolation calculation model is configured to be interface-bound with the control end of the switching function model. The switching function model is then controlled by the precise switching control signal. The real-time simulation platform is connected to a real ANPC converter controller via a hardware interface. The ANPC converter controller outputs the original switching control signal to the interpolation calculation model and receives the voltage and current values ​​output by the switching function model. The ANPC converter controller, the interpolation calculation model, and the switching function model form a closed loop for hardware-in-the-loop simulation testing.

[0007] Preferably, the switching function model is as follows:

[0008] Among them, U dc_up U is the DC-side bus voltage. dc_down I is the DC side lower bus voltage. p I is the DC-side upper bus current. n For the DC side lower bus current, SW 01 -SW 12 This represents a switch signal, where 0 indicates off and 1 indicates on. a For the output current of phase A, I b For the output current of phase B, I c Given the output current of phase C, the equivalent circuit of the ANPC switching function model can be constructed based on the above formula.

[0009] Preferably, the interpolation calculation model calculates a time-corrected precise switching control signal by detecting the edges of the original switching control signal and combining the modulation signal and the carrier signal, including: Calculate the signal difference between the modulated signal and the carrier signal, and calculate the change in the signal difference between the current simulation time step and the previous simulation time step. The signal difference and the change amplitude of the current simulation time step are normalized to obtain the first normalized value of the current simulation time step. The signal difference and the change amplitude of the previous simulation time step are normalized to obtain the second normalized value of the previous simulation time step. Edge detection is performed on the original switching control signal from the ANPC converter controller. When a rising edge is detected, the first normalized value is selected to correct the switching action time. When a falling edge is detected, the second normalized value is selected to correct the switching action time. At non-edge times, the original switching control signal remains unchanged.

[0010] Preferably, the step of embedding the switching function model into the real-time simulation platform and configuring the output of the interpolation calculation model to interface-bind with the control end of the switching function model includes: The interpolation calculation model and the switching function model are compiled and deployed on the same real-time simulation platform. Within the real-time simulation platform, a data interface is established through registers or on-chip memory, enabling the precise switching control signal output by the interpolation calculation model to be received by the switching function model in an event-driven manner within a defined clock cycle and used to update its internal switching function state.

[0011] Preferably, the method further includes a performance index evaluation step: During the hardware-in-the-loop simulation test, the maximum time taken for the real-time simulation platform to complete a single-step simulation calculation was measured. The real-time margin of the system is calculated based on the preset simulation step size and the maximum single-step time. Determine whether the real-time margin is greater than a preset threshold. If the determination result is yes, then the performance indicators of the system meet the requirements.

[0012] Preferably, the method further includes: During the hardware-in-the-loop simulation test, a fault condition test is performed. By injecting preset fault parameters into the switching function model, the dynamic response characteristics of the ANPC converter controller are tested.

[0013] Preferably, the fault condition test includes simulation of at least one of the following faults: A sudden drop or rise in DC bus voltage; AC-side grid voltage asymmetry drop or harmonic injection fault; Simulate open-circuit or shoot-through faults of specific switches in an ANPC topology.

[0014] Secondly, this application provides an ANPC topology hardware-in-the-loop simulation system, the system being used to perform the method as described in any of the preceding claims, the system comprising: A real-time simulation platform for running switching function models and interpolation calculation models with integrated related interfaces; The actual ANPC converter controller is connected to the real-time simulation platform through a hardware input / output interface to form a closed-loop test environment; The test management unit is used to configure simulation parameters, select and inject fault conditions, and collect and analyze test data.

[0015] Thirdly, this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the ANPC topology hardware-in-the-loop simulation method as described in the first aspect above.

[0016] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the ANPC topology hardware-in-the-loop simulation method as described in the first aspect above.

[0017] The ANPC topology hardware-in-the-loop simulation method, system, electronic devices, and storage media provided in this application have at least the following technical advantages: The switching function model in this application significantly reduces model complexity through mathematical description of external characteristics, enabling the simulation step size to be shortened to the order of 5 microseconds, thus ensuring real-time performance. Simultaneously, the interpolation calculation model, through edge detection and normalization processing, accurately corrects the switching action timing, effectively eliminating the time quantization errors and waveform distortion inherent in traditional fixed-step simulations. In summary, this application, by constructing a switching function model with an ANPC topology and combining it with an interpolation calculation model, achieves a synergistic improvement in accuracy and efficiency in hardware-in-the-loop simulation.

[0018] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of an ANPC topology hardware-in-the-loop simulation method in one embodiment of this application; Figure 2 This is a circuit diagram of the detailed model topology of ANPC in one embodiment of this application; Figure 3 yes Figure 2 Equivalent circuit diagram of the detailed model topology of ANPC in the embodiment; Figure 4 This is a structural block diagram of an interpolation calculation model in one embodiment of this application; Figure 5 This is a flowchart of the signal control forming a closed loop in one embodiment of this application; Figure 6 This is a flowchart of an ANPC topology hardware-in-the-loop simulation method in another embodiment of this application; Figure 7 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0021] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0022] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0023] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0024] Existing ANPC three-level electromagnetic transient modeling methods suffer from shortcomings in model detail and real-time performance, making it difficult to balance simulation accuracy and efficiency, and unsuitable for real-time simulation applications in hardware-in-the-loop simulation scenarios. Traditional fixed-step simulations suffer from problems such as time quantization errors caused by the asynchrony between the switching action and the simulation step size, waveform distortion during the switching transient process leading to harmonic analysis distortion, and the high computational complexity of existing interpolation algorithms, making it difficult to meet real-time requirements.

[0025] To address this, this invention proposes a hardware-in-the-loop simulation method for ANPC topology based on a switching function model and interpolation calculation. This method aims to solve the problems of low simulation accuracy and low simulation efficiency of ANPC topology in real-time simulation scenarios, and is verified through hardware-in-the-loop simulation.

[0026] Firstly, embodiments of this application provide an ANPC topology hardware-in-the-loop simulation method, such as... Figure 1 As shown, the implementation process of the ANPC topology hardware-in-the-loop simulation method of this application is described below.

[0027] Step S1: Construct the switching function model of the ANPC topology; wherein, the switching function model is based on the voltage and current relationship between the AC and DC sides of the ANPC topology, and is obtained by introducing a switching function that characterizes the on / off state of the switch to model the external characteristics.

[0028] Specifically, the switching function model implementation of the ANPC topology is an external characteristic modeling method. It models the external characteristics based on the input-output relationship of the converter. By introducing the switching function corresponding to the on and off states of the switch, the switching characteristics of the converter are described by mathematical expressions. Since it is not necessary to simulate the specific process of each switching device, the model complexity can be optimized and the simulation efficiency can be improved.

[0029] ANPC's detailed model topology is as follows: Figure 2 As shown, Figure 2 This is a detailed topology diagram of an ANPC (Active Neutral Point Clamping) converter, a typical topology of a multilevel converter, primarily used for power conversion in high-voltage, high-power scenarios. Specifically, Figure 2 The left side is the DC side structure, including the upper bus P, midpoint O, and lower bus N, corresponding to a DC voltage of U. dc_up (between PO) and U dc_down (between ON and ON), usually U dc_up =U dc_down Together, they constitute the DC-side power supply unit.

[0030] Figure 2 The core components are the switching devices and the topology path. Each phase (A / B / C phases) corresponds to 4 sets of switching devices (e.g., SW for phase A). 01 -SW 04 SW of phase B 05 -SW 08 SW of phase C 09 -SW 12 Each group contains an IGBT (switching transistor) and an anti-parallel diode (for freewheeling). Taking phase A as an example, SW 01 / SW 02 Connect phase A to upper busbar P, SW 03 / SW 04 Connect phase A to the lower busbar N, with the midpoint O connected via a clamping switch (i.e., SW). 19 / SW 20 Connected to A, by combining different switches, multi-level (such as three-level / five-level) voltage outputs can be achieved. Figure 2 The right side is the AC side structure, which includes three-phase output terminals A / B / C, with corresponding output currents of Ia / Ib / Ic. The AC voltage / current is regulated by switching devices, and finally connected to the power grid or load.

[0031] The ANPC topology of this application reduces the voltage stress on the switching devices and improves the output power quality through clamping control of multiple sets of clamping switches; and the switching function model of this application is based on Figure 2 The ANPC topology simplifies the simulation modeling process by replacing actual switching devices with switching functions.

[0032] according to Figure 2 The voltage and current relationship on both the AC and DC sides of the ANPC converter is obtained, and the external characteristics are modeled by introducing a switching function that characterizes the switching state. The switching function model is shown in Equation (1): (1) Among them, U dc_up U is the DC-side bus voltage. dc_down I is the DC side lower bus voltage. p I is the DC-side upper bus current. n For the DC side lower bus current, SW 01 -SW 12 This represents a switch signal, where 0 indicates off and 1 indicates on. a For the output current of phase A, I b For the output current of phase B, I c This is the output current for phase C.

[0033] The equivalent circuit of the ANPC switching function model can be constructed according to the above formula (1). For details of the equivalent circuit, please refer to [reference needed]. Figure 3 . Figure 3 The left side is the DC side, where P is the upper DC bus, O is the DC midpoint, N is the lower DC bus, and U... dc_up For the upper bus voltage, U dc_down Ip is the lower bus voltage, In is the upper bus current, and Io is the lower bus current. In this embodiment, the nodes, voltages, and currents are associated with the AC side current through a switching function, as shown in formula (1).

[0034] Figure 3 The right side is the AC side, including the three-phase output terminals A / B / C, the three-phase output voltages Va / Vb / Vc, and the three-phase output currents Ia / Ib / Ic. The voltage is obtained by combining the DC side voltage and the switching function, as shown in formula (1). The current is the load current of the ANPC converter and also participates in the calculation of the DC side current (Ip / In / Io). In the equivalent circuit of this embodiment, the actual switching devices are replaced by controlled sources (diamond symbols). The DC side Ip / Io / In are current sources controlled by "AC side current + switching function"; the AC side Va / Vb / Vc are voltage sources controlled by "DC side voltage + switching function".

[0035] This embodiment does not simulate the on / off process of a single switch, but only uses the switching function (SW) 01 -SW 12The "0 / 1" states of the model directly output the electrical quantities on the AC and DC sides, greatly simplifying the model complexity and adapting to the real-time simulation requirements of hardware-in-the-loop. The equivalent circuit determines the state of the switching function by the output precise switching control signal, which in turn controls the output of the controlled source in the equivalent circuit, ultimately achieving a synergistic effect of "efficient modeling + precise output".

[0036] Step S2: Construct an interpolation calculation model for determining the switching action; wherein, the interpolation calculation model calculates the time-corrected precise switching control signal by detecting the edge of the original switching control signal and combining the modulation signal and the carrier signal.

[0037] This embodiment of the application processes the original switch control signal using an interpolation calculation model to generate a precise switch control signal. Specifically, it calculates the signal difference between the input modulation signal and the carrier signal, and calculates the change amplitude between the signal difference at the current simulation time step and the signal difference at the previous simulation time step. It then normalizes the signal difference and the change amplitude at the current simulation time step to obtain a first normalized value for the current simulation time step, and normalizes the signal difference and the change amplitude at the previous simulation time step to obtain a second normalized value for the previous simulation time step. It performs edge detection on the original switch control signal from the ANPC converter controller. When a rising edge is detected, the first normalized value is selected to correct the switch action timing; when a falling edge is detected, the second normalized value is selected to correct the switch action timing; and at non-edge times, the original switch control signal remains unchanged.

[0038] This embodiment constructs an interpolation calculation algorithm model and combines it with a switching function model. The control block diagram of the interpolation calculation model in this embodiment is as follows: Figure 4 As shown. Figure 4 In this context, Ref and Carrier represent the modulating signal and the carrier signal, respectively. The difference between the modulating signal and the carrier signal is processed through a delay element. The absolute value of the difference between the signal before and after the delay is taken to obtain the amplitude of change. The normalized values ​​of the amplitude changes at the current time step and the previous time step are then calculated respectively. sw is the actual controller's original switching control signal. Edge detection is performed on the switching signal. At the edge moments (rising and falling edges) of the switching signal, the normalized value of the modulating signal (at the current or previous time step) is captured. At non-edge moments, the original value of the switching signal is maintained. That is, at the rising edge of the switching signal (Ctrl ≥ 0.5), the normalized value of the current time step is selected; at the falling edge of the switching signal (Ctrl < -0.5), the normalized value of the previous time step is selected. At other times, the sw signal is directly transmitted.

[0039] More specifically, the input signals Ref and Carrier are differentially calculated to obtain the signal difference Ref - Carrier, which is then processed by the delay stage e.-sT The signal difference from the previous time step is generated. This difference is then subtracted from the current time step's signal difference, and the signal change amplitude is calculated using the |x| module. The signal change amplitude is then fed into the N / D module (numerical division) to obtain a normalized value (standardizing the change amplitude to the 0-1 range). This embodiment uses a two-stage cascaded N / D module to normalize the signal difference between two consecutive time steps, thereby further optimizing the normalization accuracy. The original switch control signal sw output by the controller, combined with the normalized signal, is used to determine the switch action type through edge detection logic. The edge detection logic is as follows: when Ctrl ≥ 0.5 (rising edge), path A is selected, and the normalized value of the current time step is output; when Ctrl < 0.5 (falling edge), path B is selected, and the normalized value of the previous time step is output; at non-edge moments, the original switch signal sw is directly transmitted. Finally, a high-precision switch control signal sw_NEW is obtained, which drives the switch function model and ensures the accuracy of the simulation waveform.

[0040] The interpolation calculation model in this application uses the logic of "difference calculation → change amplitude normalization → edge detection and value selection" to accurately match the switching action and simulation step size without increasing computational complexity, thereby improving the accuracy of real-time simulation.

[0041] Step S3: Embed the switching function model into the real-time simulation platform, and configure the output end of the interpolation calculation model to interface with the control end of the switching function model. The switching function model is then controlled via the precise switching control signal. In this embodiment, the switching function model of the ANPC topology is embedded into the real-time simulation platform, the device simulation step size is 5μs, and the interpolation calculation algorithm model of this embodiment is configured and interface-bound with the switching function model.

[0042] Step S4: Connect the real-time simulation platform to the actual ANPC converter controller via a hardware interface. The ANPC converter controller outputs the original switching control signal to the interpolation calculation model and receives the voltage and current values ​​output by the switching function model. The ANPC converter controller, the interpolation calculation model, and the switching function model form a closed loop for hardware-in-the-loop simulation testing. In this embodiment, the actual ANPC converter controller is connected via a hardware interface. Based on the switching function model and interpolation algorithm, the voltage and current values ​​on the AC and DC sides are calculated in real time and output to the controller. Simultaneously, the controller's control signals are received to form a closed loop. (Refer to...) Figure 5 .

[0043] The more precise switching control signal obtained through interpolation in this embodiment is not ultimately used to control a real physical device, but rather to control a virtual model in a "hardware-in-the-loop simulation system"—namely, the switching function model of the ANPC topology. The hardware-in-the-loop simulation system in this embodiment consists of a real device and a virtual device forming a closed loop. The real device is the actual controller of the ANPC converter, capable of generating the original switching control signal sw. The virtual device is the ANPC switching function model running in a real-time simulator (such as an FPGA platform).

[0044] The actual controller sends its raw switching control signal (sw), containing time quantization errors, to the real-time simulation platform. Inside the real-time simulator, the interpolation module intercepts this raw sw signal. By detecting signal edges and combining this with modulation information, it calculates the precise timing at which the switching action should occur, thus generating a time-corrected, high-precision switching control signal. This corrected, precise switching control signal is immediately fed into the ANPC switching function model within the same simulator. The model adjusts its internal switching function (SW) based on this precise signal. 01 ……SW 12 The state of the switching function model changes, and its port voltage and current outputs (Va / Vb / Vc, Ia / Ib / Ic) change precisely accordingly. These voltage and current values ​​serve as feedback and are sent back to the actual controller through a hardware interface (such as an AD / DA board) to complete the closed-loop test.

[0045] Therefore, the control signal obtained by interpolation calculation in the embodiments of this application is used to control the ANPC switching function model (virtual converter) in the simulation system, thereby providing a more accurate and realistic simulation environment for the actual ANPC converter controller, so as to safely and efficiently verify and test the performance of the controller in the laboratory.

[0046] After deploying the switching function model and interpolation calculation model on the real-time simulation platform and connecting them to the ANPC converter controller, performance evaluation and fault condition testing will be performed.

[0047] In this embodiment, performance evaluation involves conducting real-time testing to verify the system's real-time margin at a simulation step size of 5μs, ensuring no data loss or excessive latency. Specifically, during the hardware-in-the-loop simulation test, the maximum time taken for the real-time simulation platform to complete a single-step simulation calculation is measured. Based on the preset simulation step size and the maximum single-step time, the system's real-time margin is calculated, and it is determined whether the real-time margin is greater than a preset threshold. If the determination result is yes, the system's performance meets the requirements.

[0048] Specifically, in this embodiment, the simulation step size is set to 5μs. In actual calculation time, the system needs to complete the following tasks in each step: receiving the original switching control signal from the controller, running an interpolation algorithm to correct the switching timing, updating the state of the switching function model based on the corrected precise switching control signal, calculating the new voltage and current values, and outputting the calculation results to the controller through the hardware interface. In the test, the longest time to complete all the above tasks was measured. Assuming that the maximum single-step time was measured to be 3.8μs under the most complex calculation conditions, the real-time margin of the system is 5μs - 3.8μs = 1.2μs.

[0049] Setting the preset threshold to 0, a real-time margin greater than 0 proves that the system is capable of deterministically completing the task before the deadline, meeting real-time requirements, and that the simulation results are strictly synchronized with physical time, thus being reliable. If the actual maximum computation time is 5.1μs, then the real-time margin is -0.1μs. A real-time margin less than 0 indicates that the system cannot complete the calculation within the specified time, leading to data frame loss, delayed output, simulation out-of-sync failure, and loop closure failure.

[0050] Fault condition testing verifies the robustness of the proposed method under multiple operating conditions by testing the dynamic response characteristics of the ANPC topology converter controller under fault conditions. Specifically, during the hardware-in-the-loop simulation test, fault condition testing is performed by injecting preset fault parameters into the switching function model to test the dynamic response characteristics of the ANPC converter controller. The fault condition test in this embodiment includes the simulation of at least one of the following faults: DC-side bus voltage drop or rise fault; AC-side grid voltage asymmetry drop or harmonic injection fault; and simulation of open-circuit or shoot-through faults of specific switches in the ANPC topology. This application, through hardware-in-the-loop simulation testing, verifies the correctness of the ANPC hardware-in-the-loop simulation method based on the switching function model and interpolation calculation, providing a new method for hardware-in-the-loop simulation of ANPC models.

[0051] In another preferred embodiment, reference Figure 6 First, a switching function model of the ANPC topology is constructed, and then interpolation calculations are combined with this model. Next, the model is deployed to a real-time simulation platform, and the interface binding of the interpolation algorithm is completed. A signal closed loop is formed by connecting to the actual ANPC converter controller through a hardware interface. If a timeout or data frame loss occurs, the process returns to adjust the combination of the model and interpolation. If no abnormalities occur, dynamic response testing of the controller under fault conditions is performed, ultimately completing the simulation process. This process achieves closed-loop verification of the "model-algorithm-hardware," ensuring both the real-time performance and accuracy of the simulation, and verifying the multi-condition robustness of the controller.

[0052] In summary, the hardware-in-the-loop simulation method for ANPC topology provided in this application simplifies the model complexity significantly by constructing a dedicated switching function model for the ANPC topology. Instead of simulating the specific on / off process of individual switching devices, it directly outputs external characteristic parameters based solely on the "0 / 1" states of the switching function, thus meeting the 5μs real-time requirement of hardware-in-the-loop simulation. Simultaneously, by combining an interpolation calculation model with the modulation signal from the ANPC converter controller and the carrier signal from the real-time simulation platform, it accurately locates the switching action moment through difference calculation, amplitude normalization, and edge detection logic. This effectively eliminates time quantization errors and waveform distortion caused by the asynchrony between switching action and simulation step size, significantly improving PWM modulation accuracy and harmonic analysis accuracy. Furthermore, through hardware-in-the-loop verification including model deployment, real-time closed-loop simulation, performance evaluation, and fault condition testing, robust operation under multiple operating conditions is achieved. Ultimately, this method achieves a dual breakthrough in ANPC topology simulation efficiency and accuracy in a hardware-in-the-loop scenario, filling the gap in dedicated real-time simulation models for this topology and providing an efficient and accurate technical solution for the testing and verification of actual ANPC converters.

[0053] Secondly, embodiments of this application provide an ANPC topology hardware-in-the-loop simulation system, the system being used to perform the method as described in any of the preceding embodiments, the system comprising: A real-time simulation platform for running switching function models and interpolation calculation models with integrated related interfaces; The ANPC converter controller is used to connect to the real-time simulation platform through a hardware input / output interface to form a closed-loop test environment. The test management unit is used to configure simulation parameters, select and inject fault conditions, and collect and analyze test data.

[0054] It should be noted that the ANPC topology hardware-in-the-loop simulation system provided in this embodiment is used to implement the above-described ANPC topology hardware-in-the-loop simulation method implementation method, and will not be repeated where already described. As used above, the terms "module," "unit," "subunit," etc., can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the above embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0055] Thirdly, embodiments of this application provide an electronic device, Figure 7 This is a block diagram illustrating an electronic device according to an exemplary embodiment. (e.g.) Figure 7 As shown, the electronic device may include a processor 11 and a memory 12 storing computer program instructions.

[0056] Specifically, the processor 11 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0057] The memory 12 may include a large-capacity storage device for data or instructions. For example, and not limitingly, the memory 12 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 12 may include removable or non-removable (or fixed) media. Where appropriate, the memory 12 may be internal or external to a data processing device. In a particular embodiment, the memory 12 is non-volatile memory. In a particular embodiment, the memory 12 includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), an electrically alterable read-only memory (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random-Access Memory (FPMDRAM), Extended Data Out Dynamic Random-Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0058] The memory 12 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 11.

[0059] The processor 11 reads and executes computer program instructions stored in the memory 12 to implement any of the ANPC topology hardware-in-the-loop simulation methods in the above embodiments.

[0060] In one embodiment, the electronic device may further include a communication interface 13 and a bus 10. Wherein, as... Figure 7 As shown, the processor 11, memory 12, and communication interface 13 are connected through bus 10 and communicate with each other.

[0061] The communication interface 13 is used to enable communication between the various modules, devices, units, and / or equipment in the embodiments of this application. The communication interface 13 can also enable data communication with other components such as external devices, image / data acquisition devices, databases, external storage, and image / data processing workstations.

[0062] Bus 10 includes hardware, software, or both, that couples components of an electronic device together. Bus 10 includes, but is not limited to, at least one of the following: data bus, address bus, control bus, expansion bus, and local bus. For example, and not as a limitation, bus 10 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 10 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application considers any suitable bus or interconnection.

[0063] Fourthly, embodiments of this application provide a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the ANPC topology hardware-in-the-loop simulation method provided in the first aspect.

[0064] The readable storage medium may be more specifically adopted, including but not limited to: portable disk, hard disk, random access memory, read-only memory, erasable programmable read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof.

[0065] In a possible implementation, the present invention can also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform steps implementing the ANPC topology hardware-in-the-loop simulation method provided in the first aspect.

[0066] The program code for executing the present invention can be written in any combination of one or more programming languages. The program code can be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on a remote device.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An ANPC topology hardware-in-the-loop simulation method, characterized in that, The method includes the following steps: Construct a switching function model for the ANPC topology; wherein, the switching function model is based on the voltage and current relationship between the AC and DC sides of the ANPC topology, and is obtained by introducing a switching function that characterizes the on / off state of the switch for external characteristic modeling; An interpolation calculation model is constructed to determine the switching action; wherein, the interpolation calculation model calculates the time-corrected accurate switching control signal by detecting the edge of the original switching control signal and combining the modulation signal and the carrier signal. The switching function model is embedded into a real-time simulation platform, and the output of the interpolation calculation model is configured to be interface-bound with the control end of the switching function model. The switching function model is then controlled by the precise switching control signal. The real-time simulation platform is connected to a real ANPC converter controller via a hardware interface. The ANPC converter controller outputs the original switching control signal to the interpolation calculation model and receives the voltage and current values ​​output by the switching function model. The ANPC converter controller, the interpolation calculation model, and the switching function model form a closed loop for hardware-in-the-loop simulation testing.

2. The method according to claim 1, characterized in that, The switching function model is as follows: wherein U dc_up is the upper DC-side bus voltage, U dc_down is the lower DC-side bus voltage, I p is the upper DC-side bus current, I n is the lower DC-side bus current, SW 01 -SW 12 denotes a switching signal, wherein 0 means off and 1 means on, I a is the A-phase output current, I b is the B-phase output current, I c is the C-phase output current.

3. The method according to claim 1, characterized in that, The interpolation calculation model calculates a time-corrected, precise switching control signal by detecting the edges of the original switching control signal and combining the modulation signal and the carrier signal, including: Calculate the signal difference between the modulated signal and the carrier signal, and calculate the change in the signal difference between the current simulation time step and the previous simulation time step. The signal difference and the change amplitude of the current simulation time step are normalized to obtain the first normalized value of the current simulation time step. The signal difference and the change amplitude of the previous simulation time step are normalized to obtain the second normalized value of the previous simulation time step. Edge detection is performed on the original switching control signal from the ANPC converter controller. When a rising edge is detected, the first normalized value is selected to correct the switching action time. When a falling edge is detected, the second normalized value is selected to correct the switching action time. At non-edge times, the original switching control signal remains unchanged.

4. The method according to claim 1, characterized in that, The step of embedding the switching function model into the real-time simulation platform and configuring the output of the interpolation calculation model to interface with the control end of the switching function model includes: The interpolation calculation model and the switching function model are compiled and deployed on the same real-time simulation platform. Within the real-time simulation platform, a data interface is established through registers or on-chip memory, enabling the precise switching control signal output by the interpolation calculation model to be received by the switching function model in an event-driven manner within a defined clock cycle and used to update its internal switching function state.

5. The method according to claim 1, characterized in that, The method also includes a performance evaluation step: During the hardware-in-the-loop simulation test, the maximum time taken for the real-time simulation platform to complete a single-step simulation calculation was measured. The real-time margin of the system is calculated based on the preset simulation step size and the maximum single-step time. Determine whether the real-time margin is greater than a preset threshold. If the determination result is yes, then the performance indicators of the system meet the requirements.

6. The method according to claim 1, characterized in that, The method further includes: During the hardware-in-the-loop simulation test, a fault condition test is performed. By injecting preset fault parameters into the switching function model, the dynamic response characteristics of the ANPC converter controller are tested.

7. The method according to claim 6, characterized in that, The fault condition test includes simulation of at least one of the following faults: A sudden drop or rise in DC bus voltage; AC-side grid voltage asymmetry drop or harmonic injection fault; Simulate open-circuit or shoot-through faults of specific switches in an ANPC topology.

8. An ANPC topology hardware-in-the-loop simulation system, characterized in that, The system is used to perform the method as described in any one of claims 1 to 7, the system comprising: A real-time simulation platform for running switching function models and interpolation calculation models with integrated related interfaces; The ANPC converter controller is used to connect to the real-time simulation platform through a hardware input / output interface to form a closed-loop test environment. The test management unit is used to configure simulation parameters, select and inject fault conditions, and collect and analyze test data.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the ANPC topology hardware-in-the-loop simulation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the ANPC topology hardware-in-the-loop simulation method as described in any one of claims 1 to 7.

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