Circuit design system based on dynamic pins

Abstract

The application relates to the technical field of electronic design automation, in particular to a circuit design system based on dynamic pins, which sets dynamic pins for a device symbol and sets size configuration items corresponding to the dynamic pins, so that the device symbol can flexibly configure the size configuration items corresponding to the dynamic pins according to actual pin bit width requirements when applied to different scenes, unified description of different pin bit width requirement scenes by a single device symbol is realized, the conciseness of a device symbol library is improved, moreover, the cumbersome work of creating corresponding device symbols for each bit width configuration is avoided, the maintainability and reusability of the device symbol library are significantly improved, and when facing the demand of bit width change, the device symbol can also be quickly made compatible with the scene by changing the setting, the adaptability of the device symbol library to new scenes is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a circuit design system based on dynamic pins. Background Technology

[0002] In existing electronic design automation (EDA) tools, the number of pins and the bit width of each pin in a device symbol are usually fixed. Therefore, if designers need to adapt a functional device to multiple application scenarios with different data widths, they must create and maintain multiple independent symbols for the same device in different data width scenarios. For example, for a single pin, if the bit width of the address or data line it connects to changes, even if the device's logic function remains the same, a separate device symbol must be drawn for each bit width version. When the pin assignments of a device change, or when design specifications need to be adjusted, designers have to modify all symbols related to that device one by one and then update the already drawn schematics synchronously.

[0003] However, to ensure data consistency, modifications to device symbols are typically only permitted from the management side of the device symbol library. When the application side of the device symbol library (such as project designers) finds that the existing device symbols in the library cannot meet design requirements, and the management side fails to update the device symbol library in a timely manner, the application side is often forced to build a temporary symbol library locally to support local design needs as quickly as possible. However, if the device symbols in the local temporary symbol library do not conform to the management side's specifications, the subsequent merging and submission process will be extremely cumbersome, and may even require the management side to readjust, resulting in a significant increase in communication costs, management costs, and design iteration time. Therefore, due to the dynamic requirements for the number of pins of the same device in different application scenarios, the maintenance and management efficiency of device symbol libraries in existing technologies is low, making it difficult to support flexible and efficient circuit design.

[0004] Therefore, improving the efficiency of device symbol library maintenance and management has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A circuit design system based on dynamic pins, the circuit design system including a device symbol library, wherein the device symbol library includes M device symbols, M being a positive integer; The device symbol includes several dynamic pins, wherein the dynamic pins include size configuration items and their corresponding maximum configuration size; When a symbol instance is placed in the schematic diagram according to the device symbol, for any dynamic pin in the device symbol, the size configuration item of the dynamic pin is set to the target size corresponding to the dynamic pin under the symbol instance, wherein the target size corresponding to the dynamic pin is less than or equal to the maximum configuration size corresponding to the dynamic pin.

[0006] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the circuit design system based on dynamic pins provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages: This invention sets dynamic pins for device symbols and corresponding size configuration items for these dynamic pins. This allows device symbols to be flexibly configured with the size configuration items corresponding to the dynamic pins according to the actual pin width requirements when applied to different scenarios. This achieves a unified description of different pin width requirements for a single device symbol, improving the simplicity of the device symbol library. Moreover, it avoids the tedious work of creating corresponding device symbols for each bit width configuration, significantly improving the maintainability and reusability of the device symbol library. When faced with the requirement of bit width changes, the device symbol can be quickly made compatible with the scenario by changing the settings, improving the adaptability of the device symbol library to new scenarios. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of the device symbol structure in a circuit design system based on dynamic pins, provided for an embodiment of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] This embodiment provides a circuit design system based on dynamic pins. See [link to documentation]. Figure 1This is a schematic diagram of the device symbol structure in a circuit design system based on dynamic pins provided by an embodiment of the present invention. The circuit design system includes a device symbol library, wherein the device symbol library includes M device symbols, where M is a positive integer. The device symbol includes several dynamic pins, wherein the dynamic pins include size configuration items and their corresponding maximum configuration size; When a symbol instance is placed in the schematic diagram according to the device symbol, for any dynamic pin in the device symbol, the size configuration item of the dynamic pin is set to the target size corresponding to the dynamic pin under the symbol instance, wherein the target size corresponding to the dynamic pin is less than or equal to the maximum configuration size corresponding to the dynamic pin.

[0011] Among them, the device symbol library refers to a database used to store the graphical representation of each device in a circuit design system. The graphical representation of a device is called a device symbol.

[0012] Dynamic pins refer to pins whose actual bit width is not fixed and can be configured by the schematic designer. Size configuration items are parameters used to specify the bit width of the corresponding dynamic pin. The maximum configuration size is used to determine the maximum bit width that a dynamic pin can be extended to, and is used to constrain the upper limit of the corresponding size configuration item.

[0013] A schematic diagram is a graphical representation of a circuit design, used to show the components and the connections between them. In schematic design, symbol instances are placed in the schematic to realize a specific use of the component symbols. A symbol instance refers to a specific component symbol.

[0014] The target size refers to the specific value of the size configuration item that the circuit designer configures for the corresponding dynamic pin under the corresponding symbol instance.

[0015] It should be noted that, depending on the actual function of the device symbol, the device symbol may also include non-dynamic pins.

[0016] For example, a device symbol's data bus pin is a dynamic pin with a maximum configuration size of 32 bits. When a 16-bit data bus is needed, the size configuration item in the symbol instance of the device symbol is set to 16 bits. When a 32-bit data bus is needed, the size configuration item in the symbol instance of the device symbol is set to 32 bits. The two symbol instances essentially share the same device symbol, and there is no need to maintain two independent device symbols.

[0017] In one implementation, the target size corresponding to each dynamic pin in the symbol instance can also be configured in batches according to an external configuration file or script. In this case, the circuit designer sets the external configuration file or script accordingly based on the application scenario.

[0018] In one specific implementation, the dynamic pin also includes electrical and shape attributes.

[0019] Among them, electrical attributes are used to describe the functional type of the corresponding dynamic pin in the circuit. The functional types include input, output, bidirectional, power supply, ground, etc.

[0020] Shape attributes are used to describe the appearance of the corresponding dynamic pin in the device symbol, such as length, position, orientation, and whether it is hidden.

[0021] In one specific implementation, when the target size corresponding to the dynamic pin is set to 1, the dynamic pin is used to be directly connected to the signal line.

[0022] In this context, a signal line refers to a single electrical connection used in a schematic diagram to connect two pins.

[0023] Specifically, when the target size corresponding to the dynamic pin is set to 1, the dynamic pin behaves the same as a fixed pin and can be directly connected to a single signal line.

[0024] In one specific implementation, when the target size corresponding to the dynamic pin is set to a value greater than 1, the dynamic pin is used to connect to the bus.

[0025] In this context, a bus refers to a set of functionally related signal lines, which are usually represented by thick lines or labels in schematic diagrams.

[0026] Specifically, when the target size corresponding to the dynamic pin is set to a value greater than 1, it indicates that the dynamic pin corresponds to a set of signals that can be connected to the bus network as a whole.

[0027] In one specific implementation, the bus has a standard bit width, which is 8 bits, 16 bits, or 32 bits.

[0028] The standard bit width refers to the commonly used data bus width, including 8-bit, 16-bit, and 32-bit.

[0029] In one specific implementation, the bus is formed by N signal lines, and correspondingly, the bit width of the bus is N, where N is an integer greater than 1.

[0030] The bus can be formed by combining signal lines instead of directly using a data bus. The bit width of the bus indicates the number of signal lines contained in the bus. In this case, the bit width of the bus can be a non-standard bit width, thereby further improving the compatibility of the device symbol with various scenarios.

[0031] In one specific implementation, for any given device symbol, K symbol instances are placed in the schematic diagram to represent the device corresponding to that single device symbol, wherein the target size corresponding to the w-th dynamic pin of the k-th symbol instance is L. w k K is an integer greater than 0, k is an integer in the range [1, K], w is an integer in the range [1, W], and W is the number of dynamic pins contained in the device symbol. The maximum configuration size is less than or equal to the wth dynamic pin of the device symbol.

[0032] For a single device symbol, multiple symbol instances can be placed in the schematic. These symbol instances physically belong to the same device, and the sum of the target dimensions of the same dynamic pin in each symbol instance must not exceed the maximum configuration size of that dynamic pin.

[0033] For example, if the application scenario only supports signal line connection and the device symbol is a multi-channel device, then the symbol instance of the number of channels can be placed in the schematic diagram to realize the device splitting function, without having to set a corresponding device symbol for each channel.

[0034] In one specific implementation, the circuit design system further includes a netlist output module, which is used to merge Q symbol instances corresponding to the same device symbol into a single device during the netlist output stage, wherein the target size corresponding to the r-th dynamic pin of the q-th symbol instance is L. r q Q is an integer greater than 1, q is an integer in the range [1, Q], r is an integer in the range [1, R], and R is the number of dynamic pins contained in the device symbol. The maximum configuration size is less than or equal to the r-th dynamic pin of the device symbol.

[0035] The netlist output module refers to the functional module in the circuit design system used to generate a netlist, which is used for simulation or PCB layout and routing.

[0036] Specifically, in schematic design, for ease of reading, a device may be split into multiple symbol instances for display. When generating the netlist, the netlist output module can merge these symbol instances to ensure that the total number of output device pins does not exceed the maximum configuration size and that the connection information is complete. This ensures the consistency between the physical netlist and the design intent and avoids netlist errors introduced by splitting.

[0037] In this embodiment, by setting dynamic pins for device symbols and configuring the corresponding size settings for the dynamic pins, the device symbols can be flexibly configured with the corresponding size settings for the dynamic pins according to the actual pin width requirements when applied to different scenarios. This achieves a unified description of different pin width requirements for a single device symbol, improving the simplicity of the device symbol library. Moreover, it avoids the tedious work of creating corresponding device symbols for each bit width configuration, significantly improving the maintainability and reusability of the device symbol library. When faced with the requirement of bit width changes, the device symbols can be quickly made compatible with the scenario by changing the settings, improving the adaptability of the device symbol library to new scenarios.

[0038] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A circuit design system based on dynamic pins, characterized in that, The circuit design system includes a device symbol library, wherein the device symbol library includes M device symbols, where M is a positive integer; The device symbol includes several dynamic pins, wherein the dynamic pins include size configuration items and their corresponding maximum configuration size; When a symbol instance is placed in the schematic diagram according to the device symbol, for any dynamic pin in the device symbol, the size configuration item of the dynamic pin is set to the target size corresponding to the dynamic pin under the symbol instance, wherein the target size corresponding to the dynamic pin is less than or equal to the maximum configuration size corresponding to the dynamic pin; For any given device symbol, K symbol instances are placed in the schematic diagram to represent the device corresponding to that single device symbol, where the target size of the w-th dynamic pin of the k-th symbol instance is L. w k K is an integer greater than 0, k is an integer in the range [1, K], w is an integer in the range [1, W], and W is the number of dynamic pins contained in the device symbol. The maximum configuration size is less than or equal to the wth dynamic pin of the device symbol.

2. The circuit design system based on dynamic pins according to claim 1, characterized in that, The dynamic pins also include electrical and shape attributes.

3. The circuit design system based on dynamic pins according to claim 1, characterized in that, When the target size corresponding to the dynamic pin is set to 1, the dynamic pin is used to connect directly to the signal line.

4. The circuit design system based on dynamic pins according to claim 1, characterized in that, When the target size corresponding to the dynamic pin is set to a value greater than 1, the dynamic pin is used to connect to the bus.

5. The circuit design system based on dynamic pins according to claim 4, characterized in that, The bus has a standard bit width, which can be 8 bits, 16 bits, or 32 bits.

6. The circuit design system based on dynamic pins according to claim 4, characterized in that, The bus is formed by N signal lines, and correspondingly, the bit width of the bus is N, where N is an integer greater than 1.

7. The circuit design system based on dynamic pins according to claim 1, characterized in that, The circuit design system also includes a netlist output module, which is used to merge Q symbol instances corresponding to the same device symbol into a single device during the netlist output stage. The target size corresponding to the r-th dynamic pin of the q-th symbol instance is L. r q Q is an integer greater than 1, q is an integer in the range [1, Q], r is an integer in the range [1, R], and R is the number of dynamic pins contained in the device symbol. The maximum configuration size is less than or equal to the r-th dynamic pin of the device symbol.

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