A buried information and warning screen control method, system, device and equipment based on radar waveform state recognition

Abstract

This invention discloses a control method, system, device, and equipment for underground information and warning screens based on radar waveform state recognition. Applied to the field of data processing technology, the control system is built around radar waveform segmentation recognition, FPGA / MCU dual-control arbitration, and non-blocking scheduling. Through millimeter-wave radar acquisition and dual-mode waveform recognition, accurate alarm state determination is achieved, reducing false triggering. A stable determination and takeover hold mechanism enables oscillation-free switching between dual controls, eliminating control conflicts. When the MCU takes over, display resynchronization is performed to eliminate anomalies such as ghosting and misalignment. A unified state machine enables audio-visual coordinated triggering, and Tick non-blocking scheduling ensures the parallel real-time performance of multiple tasks. Finally, alarm gating, takeover hold, and failure reset form a closed-loop control, achieving low false triggering, seamless switching, and stable and reliable full-process control of the underground warning screen.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a method, system, device, and equipment for controlling underground information and warning screens based on radar waveform state recognition. Background Technology

[0002] Currently, in-ground LED warning screens are widely used in densely populated areas such as platforms and transportation hubs, primarily employing radar or infrared sensors to detect approaching personnel. Existing control schemes generally use single-threshold level triggering, single-control-source direct drive, or simple hard switching, which have the following technical drawbacks in practical applications: Existing solutions only determine whether an alarm is triggered based on instantaneous high or low levels or single-duration thresholds. They do not perform segmented semantic recognition of radar input waveforms, and cannot effectively distinguish between valid waveforms of personnel approaching and noise waveforms such as environmental vibrations, electromagnetic interference, and ground shaking. This can easily lead to problems such as false alarms without targets and repeated triggering due to short-term shaking, resulting in insufficient alarm stability and reliability.

[0003] In scenarios where FPGA and MCU are used for collaborative control, existing technologies often employ simple priority judgment or direct hard switching, lacking signal stability determination and takeover holding mechanisms. This can lead to oscillations such as back-and-forth control battles and frequent jumps, posing risks of control intermediate states and logic disorder, resulting in system instability.

[0004] When switching between FPGA and MCU, no special resynchronization processing is performed on the display driver link, which can easily cause display defects such as afterimages, ghosting, line offset, misalignment, and short-term black screen. The readability of warning information is poor, affecting safety and user experience.

[0005] Display warnings and voice broadcasts often use independent triggering or simple delay triggering, without timing coordination through a unified state machine. This can easily lead to situations where the display and voice are out of sync or out of order, resulting in inconsistent on-site warning perception and weakened warning effect.

[0006] Existing solutions mostly adopt blocking task scheduling, with tasks such as display refresh, radar acquisition, control arbitration, alarm judgment, and temperature and humidity acquisition being executed sequentially. When MCU resources are limited, problems such as display lag, unsmooth refresh, and delayed control response are likely to occur, which cannot meet the long-term unattended operation and high real-time requirements of buried warning screens. Summary of the Invention

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A control method for an underground information and warning screen based on radar waveform state recognition includes: constructing an underground LED warning screen control system based on radar waveform segment recognition + FPGA / MCU dual-control arbitration + non-blocking scheduling; acquiring the original waveform of personnel approach through millimeter-wave radar pulse acquisition and edge detection, adapting to dual-control source collaborative scenarios, and completing semantic judgment of radar signals and stable switching of control rights; achieving accurate waveform state determination through mode 0 initialization segment recognition + mode 1 decision window feature statistics; using single-segment single-counting and continuous state gating to suppress noise and jitter, and outputting stable alarm enable / disable commands; employing a stable control right determination + takeover holding window mechanism to achieve oscillatory switching between FPGA and MCU, and forcibly reverting to FPGA control when the alarm is closed, eliminating control right conflicts and intermediate states; and in MC... The U-series takeover instantly executes the display driver resynchronization process, sequentially completing output shutdown, line scan complete shutdown, driver reconfiguration, frame loading, and line start point reset, eliminating afterimages, ghosting, line offset, and short-term black screen. Based on a unified alarm stage state machine, it achieves sound and light coordinated triggering, aligning the timing of the display scrolling inverted color warning and asynchronous voice broadcast to ensure consistent warning perception. It adopts a Tick non-blocking main loop scheduling architecture, periodically polling display refresh, radar identification, control arbitration, alarm judgment, and temperature and humidity acquisition tasks, processing time-consuming tasks asynchronously to ensure real-time display and system responsiveness under MCU resource constraints. Through alarm state gating + takeover holding + failure reset, a closed-loop control is formed. When there is an abnormality or no target, the alarm is automatically turned off, the state is reset, and the system returns to standby monitoring, achieving stable, low-false-triggering, and seamless switching of the buried screen warning control throughout the entire process.

[0008] A ground-mounted information and warning screen control device based on radar waveform state recognition is provided. The device is used to execute executable instructions to perform the above-mentioned ground-mounted information and warning screen control method based on radar waveform state recognition.

[0009] A control system for an underground information and warning screen based on radar waveform state recognition is provided. The system is used to execute executable instructions to perform the above-mentioned control method for an underground information and warning screen based on radar waveform state recognition.

[0010] Its beneficial effects are as follows: it adopts mode 0 / mode 1 segmented identification, and statistically analyzes long high-level features that meet the duration condition within the decision window. Furthermore, it uses a "count at most once" rule for the same high-level segment to avoid misjudgment caused by repeated accumulation. Based on this, it combines consecutive occurrence counts and minimum flip interval gating to suppress back-and-forth state flipping. This application elevates "instantaneous level triggering" to a combined judgment of "waveform semantics + time window statistics + gating flipping," making the decision based on a repeatable and interpretable feature, thus reducing the impact of random noise on the final gating state from a mechanistic perspective.

[0011] Set a stable duration for the takeover trigger signal (high level must be stable to be effective, low level can fail quickly); after triggering, enter the holding window, and continue or release according to the rules during the holding period; when the alarm gate is on the closed side, force the FPGA control to be maintained and reset the MCU side display output related status to block unstable switching paths.

[0012] When it is detected that the display link needs to be taken over by the MCU, a resynchronization process is executed: first, the output is turned off and the line scan is completely blanked (repeatedly cleared if necessary), then the drive parameters are reconfigured and the output is enabled, then the frame data is loaded and the line start point is reset, and then the periodic scan refresh begins. During the switching of the display link, there are often inconsistencies in "output status, drive configuration, line scan position, and frame data"; by first blanking, then reconfiguring, then loading, and then resetting the line start point, the states of each layer are aligned in a fixed order, reducing abnormal display caused by old frame residue and line count misalignment from an engineering perspective.

[0013] Under the premise of effective MCU control, a phased triggering strategy is adopted: first, takeover and display side preparations are completed, and then the alarm stage is entered after a set delay. During this stage, scrolling display and asynchronous audio playback are started. When the MCU loses control or the gating is rolled back, the alarm stage is reset to avoid residual triggering from the old stage. The audio-visual triggers are bound to the same alarm stage state machine, rather than simple parallel triggering; the delay is used to cover the time window required for takeover and resynchronization, so that the broadcast and the screen enter the output range of "the same alarm semantics". Attached Figure Description

[0014] Figure 1 A flowchart illustrating a method for controlling an underground information and warning screen based on radar waveform state recognition, provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the system layered architecture and module interaction provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of system working state switching and control transfer provided in an embodiment of the present invention; Figure 4 This is a flowchart of the main loop non-blocking task scheduling process provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a module for a buried information and warning screen control device based on radar waveform state recognition, provided in an embodiment of the present invention. Detailed Implementation

[0015] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention. In one embodiment, this application also proposes a method for controlling an underground information and warning screen based on radar waveform state recognition.

[0016] The underground information and warning screen control system based on radar waveform state recognition of this invention adopts a three-layer architecture design, such as... Figure 2 As shown, the system is divided into an input layer, a decision layer, and an execution layer, with each layer achieving closed-loop control through signal flow and feedback lines. The input layer provides three core input signals: radar waveform input, control input signals, and temperature and humidity acquisition signals. Radar waveform input is the core basis for alarm triggering, control input signals are used for manual intervention in the alarm process, and temperature and humidity acquisition signals are used for environmental status monitoring and system reliability maintenance. The decision layer uses non-blocking task scheduling as its core, sequentially completing five major logics: waveform state recognition, warning state gating, control arbitration, takeover hold / release, and display resynchronization. Specifically, the waveform state recognition module segments the radar waveform for identification; the warning state gating module achieves anti-jitter through continuous judgment and interval gating; the control arbitration module coordinates the control permissions of the FPGA and MCU; the takeover hold / release module ensures state stability; and the display resynchronization module eliminates display ghosting and misalignment issues. The execution layer includes an LED display driver module and a voice broadcast module. The LED display driver module drives the buried LED screen to achieve display output, and the voice broadcast module implements audio alarms through asynchronous broadcasting. Under the control of the decision layer, the two form a sound-light linkage. In the system, four types of signal flows—main flow, warning linkage, feedback line, and non-blocking task scheduling—work together to achieve complete closed-loop control from signal input to alarm output.

[0017] like Figure 4 As shown, to ensure system real-time performance and multi-task parallel processing capabilities, this invention employs a main loop scheduler to implement non-blocking task scheduling, such as... Figure 4 As shown, the main loop schedules five core tasks in parallel. LED Refresh Task: Responsible for the routine display refresh of the buried LED screen, maintaining image stability in standby mode. Radar Identification Task: Segmented identification and status determination of radar waveforms, providing a basis for alarm triggering. Control Arbitration Task: Executes branch logic based on alarm status: When the alarm is off, FPGA control is forced and the screen is turned off to clear the status; when the alarm is allowed and the input is stable, the MCU takes over and enters the hold window; when the hold window expires, control is continued or released based on personnel status. Alarm Phase Task: Executes branch logic based on whether the alarm delay has been reached: If the delay has not been reached, the alarm is not triggered; if the delay has been reached and the system is under MCU control, scrolling display and asynchronous audio playback are initiated. Temperature and Humidity Acquisition Task: Monitors ambient temperature and humidity, continuing to poll while reading; if the reading is successful, the data is updated and the corresponding LED indicator is lit; if the reading fails, error handling or retry is performed. This scheduling method avoids task blocking, ensuring the real-time nature of alarm response and the stability of system operation.

[0018] In this application embodiment, a method for controlling an underground information and warning screen based on radar waveform state recognition is provided, such as... Figure 1 As shown: S101 is a control system for buried LED warning screens built on radar waveform segmentation recognition, FPGA / MCU dual-control arbitration, and non-blocking scheduling. It acquires the original waveform of personnel approaching through millimeter-wave radar pulse acquisition and edge detection, adapts to dual-control source collaborative scenarios, and completes semantic judgment of radar signals and stable switching of control.

[0019] In one implementation, a comprehensive control scheme for an underground LED warning screen suitable for station scenarios is built around a core architecture based on radar waveform segmentation recognition, FPGA and MCU dual control source arbitration, and non-blocking scheduling. Upon power-on, the system prioritizes the initialization and configuration of hardware interfaces and functional modules. The radar input port is configured for level acquisition and edge detection mode; the display driver circuit is configured for continuous scanning output and frame buffer synchronization mode; the voice broadcast module is configured for asynchronous playback and non-blocking main process mode; and the temperature and humidity acquisition module is configured for I2C asynchronous triggering and polling mode. Simultaneously, unified initialization of GPIO, serial port, SPI, display controller, interrupt priority, and system clock is completed. This unified initialization establishes a stable and reliable operating environment, ensuring the orderly execution of subsequent signal acquisition, logic decision-making, and control output processes.

[0020] The system uses a millimeter-wave radar module to collect personnel proximity sensing signals in real time. It continuously reads the radar output level status at fixed millisecond intervals, synchronously identifying and recording the rising and falling edge transitions of the level, and continuously calculating the duration of each high-level segment. This results in raw waveform data containing real-time level status, edge transition information, and high-level duration. This data serves as input for waveform semantic recognition, distinguishing between valid target signals generated by personnel approach and invalid noise signals generated by environmental vibrations, electromagnetic interference, and ground shaking. For example, when a person normally approaches the radar detection area, it outputs one or more continuous and stable high-level waveforms; while environmental electromagnetic interference typically manifests as narrow pulses, glitches, or random level jumps, which can be filtered out through waveform feature statistics.

[0021] The system divides the waveform recognition process into two sequentially executed working modes. These two modes operate mutually exclusively, are cascaded in timing, and do not overlap or jump around. Mode 0 is the initialization segment waiting recognition mode, used to monitor the continuous high-level signal sent by the FPGA and determine whether the high level has reached the preset minimum duration threshold. After confirming the end of a valid initialization segment, it automatically switches to Mode 1 and starts the decision window timing. For example, if the minimum duration of the initialization segment is set to 100ms, when the high level sent by the FPGA lasts for 100ms and a falling edge appears, it is determined that the valid initialization segment has ended, and the system immediately enters Mode 1. Mode 1 is the decision segment feature statistics mode, which counts the number of long high-level segments that meet the minimum duration requirement within a preset time window. The statistics process follows the rule that the same high-level segment is counted only once, avoiding duplicate counting due to the level continuously crossing the threshold, thus improving the accuracy of the decision. For example, if the decision window duration is set to 500ms and the minimum effective duration of a long high level is 80ms, if a high level lasts for 150ms, the system will only count it as 1 time; if 3 high levels that meet the duration requirements occur, the count value will be 3, and the count will not be repeated.

[0022] After the decision window timeout ends, the system generates a basic state for alarm enable or alarm disable based on the statistical count of long high-level segments. It then accumulates the number of consecutively generated alarm disable states and sets a minimum time interval for state transitions to suppress frequent state jumps and jitter, ultimately outputting a stable and reliable alarm gating signal. For example, setting a threshold of 3 consecutive alarm disable times and a minimum state transition interval of 300ms, the alarm gating is only updated to disable when three consecutive alarm disable results are obtained and more than 300ms have passed since the last state transition; otherwise, the original state remains unchanged to avoid repeated state switching due to short-term jitter. This alarm gating signal is synchronously sent to the control arbitration unit along with the radar control input signal, completing the conversion of the radar signal from its original level waveform to semantic control decision.

[0023] In scenarios where FPGA and MCU work together as dual control sources, the system uses alarm gating signals as a prerequisite to determine the stability and validity of radar control input signals. A high-level signal must persist for a set duration to be considered valid, while a low-level signal is directly deemed invalid. For example, if the valid stable duration is set to 200ms, the radar control input high level must last for a full 200ms to be considered a valid takeover request; if the high level disappears after only 50ms, it is considered invalid jitter and does not trigger takeover. When the alarm gating is closed, the system immediately forcibly releases all control permissions of the MCU, automatically reverts to the FPGA's default control state, and simultaneously resets the display driver, frame buffer, line scan pointer, and alarm status flag. This achieves a smooth switch of control between the FPGA and MCU, effectively avoiding frequent control jitter, alternating preemption, and intermediate states, ensuring the stable operation of the buried warning screen throughout.

[0024] S102 achieves accurate waveform state determination through mode 0 initialization segment recognition and mode 1 decision window feature statistics. It uses single-segment single-count and continuous state gating to suppress noise and jitter, and outputs stable alarm enable / disable commands.

[0025] In one implementation, combining the segmented decision requirements of radar waveform state recognition with dual-mode state machine logic, an initialization segment matching rule and a decision window feature statistics mechanism are introduced to build a hierarchical recognition system for Mode 0 and Mode 1. The system constructs a dual-mode state machine to form a hierarchical recognition architecture based on the actual needs of segmented radar waveform decision-making. This architecture consists of an initialization segment detection unit, a decision window management unit, and a waveform feature statistics unit connected sequentially. The initialization segment detection unit is at the front end of the recognition link, used to receive the level signals acquired by the radar and the control signals issued by the FPGA in real time. The decision window management unit is located in the middle layer, used to receive the initialization segment end signal output from the initialization segment detection unit and immediately start the decision window timing upon receiving the signal. The waveform feature statistics unit is located at the back end of the architecture, performing waveform feature extraction and statistical calculation based on the timing information provided by the decision window management unit.

[0026] Mode 0 is the initialization segment waiting recognition mode, serving as the pre-judgment stage of the entire recognition system, mainly responsible for the identification and confirmation of valid initialization segments. Mode 1 is the decision segment feature statistics mode, serving as the core judgment stage of the recognition system, used to complete target feature statistics within a specified time window. The two modes operate sequentially in series, together forming a complete hierarchical recognition system, realizing the entire process from raw waveform acquisition to alarm status output.

[0027] After the system powers on and initializes, it preferentially enters mode 0. In mode 0, the system continuously monitors the level signals sent by the FPGA to determine whether the current high level meets the preset minimum duration condition. Only high-level segments that meet the duration requirement are considered valid initialization segments. Before the initialization segment is confirmed to have ended, the system remains in mode 0 and does not enter the feature statistics process.

[0028] When Mode 0 successfully detects the end of a valid initialization segment, the system automatically switches from Mode 0 to Mode 1. Upon startup, Mode 1 immediately begins timing the decision window and performs waveform feature statistics according to preset rules. Modes 0 and 1 are executed in a strictly sequential manner; only one mode runs at a time, and there is no parallel or overlapping execution between the two modes, ensuring an orderly and stable recognition process.

[0029] After the system is powered on, it is in mode 0 and continuously monitors the level sent by the FPGA. When the high level that has been continuously high for the required duration ends, it immediately switches to mode 1 and opens the decision window. Feature statistics are completed within the window. There will be no repeated mode or disordered execution throughout the process.

[0030] Following the timing specifications for waveform segmentation identification, the detection result of the initial high-level segment completed in Mode 0 is directly connected to the decision window of Mode 1, completing the timing cascade adaptation between the initialization segment and the decision segment. The system executes signal transmission and node connection according to the timing specifications for waveform segmentation identification, designing Mode 0 and Mode 1 as a strictly timing cascaded relationship, with no parallelism, no nesting, and no additional jumps. Upon detecting the end of a valid initial high-level segment, Mode 0 immediately outputs a timing synchronization signal, which is a level transition edge or pulse signal, directly transmitted to the start port of the decision window in Mode 1, serving as the sole trigger condition for Mode 1 to begin operation, without passing through intermediate register buffers, adding software delays, or inserting conditional branch judgments. Upon receiving the trigger signal, Mode 1 immediately records the start time of the decision window, synchronously clears the feature statistics counter, high-level duration timer, and edge flag, and starts the waveform feature statistics process. The entire process does not include any additional delays or logical jumps, ensuring that the end time of the initialization segment is strictly aligned with the start time of the decision segment. This achieves seamless timing cascading of the two recognition processes, avoiding the omission of effective features or the premature inclusion of interference signals due to timing misalignment, and improving the timing consistency of waveform recognition.

[0031] For example, if the minimum duration threshold for the initialization high-level segment is preset to 100ms, when the high-level signal sent by the FPGA lasts for 100ms and a falling edge is detected, Mode 0 immediately determines that the valid initialization segment has ended and synchronously outputs a rising edge synchronization signal to Mode 1. Within the same system clock cycle that captures the rising edge, Mode 1 immediately updates the start time of the decision window to the current timestamp and starts a decision window timing with a duration of 500ms. At the same time, it starts the long high-level segment statistical logic. There is no time gap or state wait between the two processes.

[0032] When Mode 0 detects that the initial high level sent by the FPGA has been continuously met and has ended, it immediately sends a synchronization signal to Mode 1. This synchronization signal is directly connected to the decision window enable terminal of Mode 1 to ensure zero triggering delay. Upon receiving the signal, Mode 1 opens the decision window at the same moment and immediately enters the feature statistics state. It collects and calculates the real-time level and edge information of the radar input, ensuring that the two recognition segments are continuously connected in time, without losing the first valid level change after the initialization segment ends, and without mixing the signal from the initialization segment into the decision window statistics, thereby improving the accuracy and stability of alarm judgment.

[0033] Based on the core requirement of waveform characteristic stability judgment, a constraint of counting only once per segment is applied to the high-level segment, limiting feature counting to triggering only within the effective long high-level segment, thus completing the counting constraint setting of the statistical rules. The system establishes high-level segment counting constraint rules based on the core requirement of waveform characteristic stability judgment. These rules are used to accurately count the high-level segments input by the radar within the Mode 1 judgment window, avoiding duplicate counting and miscounting from the algorithm source, and ensuring the reliability of the alarm judgment basis. The system pre-configures a threshold for the effective duration of long high-level signals. Only when the duration of the high-level signal strictly exceeds this threshold is the segment considered a valid feature segment; short-term levels, interference spikes, and random jitter pulses that do not reach the duration threshold are directly judged as invalid signals and do not participate in feature statistics.

[0034] The system applies a unique single-segment counting constraint to each independent high-level segment. Specifically, the rising edge of the high-level signal is used as the start marker for a segment, and the corresponding falling edge is used as the end marker. Regardless of whether the duration of a high-level segment far exceeds the threshold or whether it crosses the effective duration threshold multiple times during its duration, it is counted only once when the effective duration condition is met for the first time. After counting, a "counted" flag is set for this segment, and counting is not repeated until the end of the segment. Within the decision window, the system only performs statistics on independent high-level segments that meet the effective duration, excluding interference pulses, short-term jitter signals, and segments that do not meet the standard level, ensuring that the statistical results only reflect the effective waveform characteristics generated by the actual approach of personnel.

[0035] For example, if the preset effective duration threshold for a long high-level signal is 80ms, when the radar inputs a high-level signal lasting 220ms, the system completes a count when it detects that the high-level signal has lasted for 80ms, and marks this segment as counted. It will not repeat the count for the remaining duration, and ultimately, this high-level signal is counted as only one valid feature. As another example, if five consecutive short jitter pulses, each 30ms in duration, appear within the decision window, the system considers all of these pulses invalid interference because none of their durations reach the 80ms effective threshold, and they are not included in the count. Furthermore, if two independent high-level signals with durations of 90ms and 120ms appear within the decision window, both meeting the effective duration requirement and belonging to different level segments, the system counts each signal once, resulting in a final count of two, perfectly matching the actual target waveform characteristics.

[0036] Through the above counting constraint rules, the system can effectively filter out invalid waveforms caused by environmental vibration, electromagnetic interference, and ground shaking, and avoid false reversals of alarm gate status due to repeated counting and miscounting. From the algorithm level, it ensures that the statistical results in the decision window are true, stable, and reproducible, accurately reflecting the actual status of personnel in the detection area, and providing reliable data support for subsequent alarm enable / disable command output.

[0037] The system inputs the radar's real-time level and edge status into the hierarchical identification system. After the initialization segment is identified in Mode 0, it enters Mode 1. Within the decision window, the number of long high-level segments that meet the duration requirement is counted, and an initial alarm state is generated based on the count value. The system also sends the real-time level status, rising edge, and falling edge transition information collected by the millimeter-wave radar as input data to the hierarchical identification system, providing complete original evidence for waveform status determination. The system prioritizes running Mode 0 to complete the initialization segment identification and verification. Only after confirming that the initialization high-level segment issued by the FPGA meets the duration requirement and has completed normally will it automatically switch to Mode 1. If the condition is not met, it will remain in Mode 0 and wait, without prematurely starting feature statistics.

[0038] After entering mode 1, the system continuously samples the radar level and calculates the duration of each high-level segment in real time within the preset decision window duration. At the same time, it strictly follows the dual constraint rules of single-segment single-count and effective duration threshold, and only counts independent long high-level segments that meet the minimum duration requirement. Short-term interference, glitch pulses and substandard level segments are not counted. During the operation of the decision window, there is no repeated counting and no missed valid segments.

[0039] After the decision window timeout ends, the system will compare the total number of valid long high-level segments with the preset alarm trigger threshold, and generate an initial alarm state based on the comparison result: when the count is greater than or equal to the trigger threshold, the system will output the alarm enabled initial state; when the count is less than the trigger threshold or there are no valid high-level segments in the window, the system will output the alarm disabled initial state.

[0040] For example: The preset decision window duration is 500ms, the minimum effective duration of a long high level is 80ms, and the alarm trigger threshold is 2 segments. If two independent effective high levels with durations of 90ms and 120ms appear successively within the decision window, the system counts 2, meeting the threshold condition, and generates an alarm-allowed initial state. If only a 60ms jitter pulse and a 70ms interference level appear within the decision window, neither of which meets the effective duration requirement, the count is 0, which is below the threshold, and the system generates an alarm-closed initial state. If three independent high levels, each meeting the effective duration, appear within the decision window, the count is 3, also meeting the threshold, and an alarm-allowed initial state is output.

[0041] Through the above-mentioned hierarchical identification, window statistics and threshold comparison process, the system can transform the original radar waveform into a stable initial alarm state, providing an accurate and reliable basis for subsequent alarm gating anti-shake processing and control arbitration, effectively distinguishing between valid target signals of approaching personnel and environmental interference noise signals, and improving the accuracy of alarm judgment and anti-interference capability.

[0042] State debouncing is achieved through continuous state determination and minimum toggle interval gating. The alarm gating state is updated only when the consecutive shutdown count and toggle interval conditions are met, generating stable alarm enable / disable commands with dual constraints of waveform semantics and debouncing rules, thus achieving precise alignment between radar waveforms and alarm decisions. After generating the initial alarm state, the system further performs debouncing processing on the state to eliminate frequent state transitions caused by environmental interference and level jitter, ensuring stable and reliable output alarm commands. This system employs a dual constraint mechanism of continuous state determination and minimum toggle interval to achieve debouncing and locking of the alarm gating state.

[0043] The system records and accumulates the number of consecutive occurrences of the alarm shutdown state output in the decision window in real time, and stores the timestamp of the last alarm gating state flip. State updates follow strict composite conditions: the system only performs an alarm gating state update when both conditions are met simultaneously—the number of consecutive alarm shutdowns reaches a preset threshold and the time difference between the current moment and the last state flip exceeds the minimum flip interval. If either condition is not met, the current alarm gating state remains unchanged, and no flip operation is performed. The system combines radar waveform semantic recognition results with dual anti-jitter rules to ultimately output stable, jitter-free alarm permission or alarm shutdown commands, ensuring precise alignment between radar waveform recognition results and the final alarm decision, effectively suppressing false triggering.

[0044] For example, the threshold for consecutive shutdowns is set to 3 times, and the minimum state transition interval is 300ms. If the system's identification result for 3 consecutive decision cycles is alarm shutdown, and more than 300ms has passed since the last state transition, the system will update the alarm gating to shutdown. If only 2 consecutive output shutdowns are performed, or the time interval is less than 300ms, the original state will remain unchanged, and no transition will be performed to avoid malfunctions caused by short-term interference.

[0045] Based on this, the system sends the real-time level status, rising edge and falling edge transition information acquired by the millimeter-wave radar into the hierarchical identification system as the raw input for waveform determination. The system prioritizes running mode 0, identifying and verifying the initial high-level segment issued by the FPGA. Only when the high level meets the preset minimum duration and ends normally will it automatically switch from mode 0 to mode 1; otherwise, it will remain in mode 0 waiting and will not start feature statistics.

[0046] Upon entering Mode 1, the system continuously samples the radar level within a preset decision window, calculates the duration of each high-level segment in real time, and strictly follows the rules of single-segment, single-time counting and effective duration threshold: only independent long high-level segments that meet the minimum duration are counted; interference pulses, short-term jitter, and substandard high-level segments are not included in the statistics. After the decision window ends, the system compares the total number of effective long high-level segments with a preset trigger threshold to generate an initial alarm state: if the number of segments reaches or exceeds the threshold, an alarm-allowed initial state is output; if the threshold is not reached or there are no effective segments, an alarm-off initial state is output.

[0047] For example, the decision window duration is set to 500ms, the effective threshold for a long high level is 80ms, and the alarm trigger threshold is 2 segments. If 3 effective long high level segments are counted within the window, meeting the triggering conditions, the system generates an alarm-allowed initial state; if there are no effective high level segments within the window, an alarm-closed initial state is generated. Through a complete process of hierarchical identification, window statistics, and dual anti-jitter, the system can accurately distinguish between valid personnel approach signals and environmental noise, providing a stable and reliable control basis for subsequent control arbitration and audible and visual alarms.

[0048] In another implementation, such as Figure 3 As shown, this system adopts a dual control mode of FPGA standby and MCU alarm, and uses a state machine to achieve smooth switching of control, such as... Figure 3 As shown, the system operates in three phases: standby, alarm preparation, and alarm. Standby (FPGA control): The screen displays a normal image or text, the voice is muted, and control is held by the FPGA. This is the system's default state, characterized by low power consumption and stable display. Alarm preparation (MCU in transit): When an alarm enable signal is received, the control input is valid, and the takeover condition is triggered, the system enters the alarm preparation state, and control is taken over by the MCU. During this phase, the screen undergoes resynchronization, resulting in a very brief black screen (milliseconds) and no voice announcement, to eliminate display anomalies during the switching process. Alarm state (MCU effective control): When the alarm delay is reached and resynchronization is complete, the system enters the alarm state. At this time, the screen displays alarm text scrolling and periodically inverts colors, and the voice synchronously plays alarm prompts; control remains with the MCU. When the alarm times out, a command to close the alarm state is received, or control needs to be released, the system returns from the alarm state to the standby state, control is returned to the FPGA, the screen resumes normal display, and the voice is muted again.

[0049] S103 adopts a control stability determination + takeover hold window mechanism to achieve oscillation-free switching between FPGA and MCU, and forces FPGA control to fall back when the alarm is closed, thus eliminating control conflicts and intermediate states.

[0050] In one implementation, combining the collaborative control requirements of FPGA and MCU dual control sources and the logic of a stable control switching state machine, a control signal stability determination and takeover hold window mechanism is introduced to establish a dual control source control arbitration and switching process for an underground warning screen. Based on the actual needs of collaborative control of FPGA and MCU dual control sources, the system constructs a stable control switching state machine to uniformly schedule the allocation of permissions, switching timing, and hold logic of the dual control sources, eliminating control conflicts, frequent oscillations, and intermediate states at the architectural level. This state machine consists of four functional modules connected in series: a signal stability determination module, a takeover hold window module, a control arbitration module, and a forced rollback module, forming a closed-loop arbitration process. Specifically, the signal stability determination module receives radar control input signals and alarm gating signals, completing the validity verification and anti-jitter identification of the access signals; the takeover hold window module receives valid signals output by the signal stability determination module and performs control hold and delayed release management; the control arbitration module, in conjunction with the output results of the first two modules, comprehensively determines the current control ownership; and the forced rollback module directly receives alarm gating closing signals, and immediately performs forced permission revocation and state reset once the alarm is closed. The four modules work together to achieve secure switching of control, stable maintenance, and reliable rollback.

[0051] After the system powers on and initializes, the FPGA automatically takes full control of the buried LED warning screen, handling routine display output, scanning drive, and basic standby monitoring. At this time, the MCU does not participate in display control and remains in standby mode, ensuring a unique and conflict-free control path during system startup. The state machine will trigger the MCU takeover process only when two conditions are met simultaneously: the alarm gating signal is in an alarm-enabled state; and the radar control input signal is verified as a valid and stable signal by the stability determination module. If either condition is not met, the state machine maintains the FPGA's default control and does not perform any switching actions, ensuring the control path remains unique and stable.

[0052] Specifically, the system sets the effective stabilization time of the radar control input to 200ms. When the alarm gate is in the allowed state and the radar control input remains high for 200ms without jitter, the signal stability judgment module outputs a valid signal, and the control arbitration module determines that the MCU has the conditions to take over, triggering the takeover process. If the radar control input high level disappears after only 50ms, or the alarm gate is in the closed state, the MCU takeover is not triggered, and FPGA control is maintained. Through the above state machine architecture and decision rules, the system can achieve oscillation-free switching and conflict-free operation of control rights in a dual-control source collaborative working scenario, providing a stable control foundation for subsequent display driver resynchronization and audible and visual alarm triggering.

[0053] According to the dual-control-source control switching rules, the radar control input signal is tested for a stable duration under alarm-allowed conditions. A high level indicates validity if the stable duration is met, while a low level indicates failure. This completes the validity and anti-jitter determination before control switching. The system follows the dual-control-source control switching rules, using the alarm gating state as a prerequisite for control switching. Validity testing of the radar control input signal is only initiated when the alarm gating is in an allowed state; if the alarm gating is in a closed state, the switching detection channel is directly closed, maintaining FPGA default control at all times, thus preventing invalid switching and control oscillations from the logic source.

[0054] Provided the alarm gating is enabled, the system performs stable duration detection on the radar control input signal, employing a high-low level differential judgment strategy: for high-level signals, they must remain unchanged for a preset stable duration threshold to be considered a valid takeover signal; for low-level signals, no duration detection is required, and they are directly judged as invalid signals, without triggering any takeover action. Through this differential judgment rule, the system can effectively filter out short-term pulses and random jitter caused by electromagnetic interference, ground vibration, signal glitches, etc., completing the validity verification and anti-jitter processing before control handover, ensuring that only genuine and stable personnel approach signals can trigger MCU takeover.

[0055] For example, the system presets the effective stabilization time of the radar control input to 200 milliseconds. When the radar control input remains high for 200 milliseconds without any transition, the system determines that the signal is a valid takeover request and allows the subsequent MCU takeover process to be executed. If the radar control input remains high for only 50 milliseconds, 80 milliseconds, or 150 milliseconds before a falling edge transition, it is considered a short-term jitter or interference signal. The system directly determines it to be invalid, does not initiate any switching action, and continues to maintain FPGA control to avoid erroneous switching due to signal instability.

[0056] Based on the takeover hold and release strategy, after the MCU triggers takeover, it enters a hold window. Within this window, short-term jitter is shielded. Upon expiration, control is either renewed or released based on the target detection result, completing the stable hold and exit judgment. According to the preset takeover hold and release strategy, after the MCU successfully acquires display control of the buried LED warning screen, it immediately enters a fixed-duration hold window operation phase. This window provides a stable control hold period for the system, avoiding frequent releases and re-entries of control due to instantaneous signal fluctuations, further improving the smoothness of dual control source switching. During the hold window operation, the system implements a jitter shielding mechanism: regardless of whether the radar input level experiences a brief drop, spike, or small fluctuation, it is determined as an invalid signal, and the control release process is not triggered, ensuring that the MCU control state is not interrupted by interference signals, and guaranteeing continuous and uninterrupted warning display and voice broadcasting.

[0057] When the hold window timer expires, the system immediately reads the latest radar waveform recognition result and target presence status, and makes the final judgment on whether to maintain or exit control according to the following rules: If the detection result shows that there are still personnel in the detection area and the waveform characteristics meet the valid target conditions, the MCU continues to maintain control over the warning screen, and a new hold window can be opened according to the system configuration; if the detection result shows that no target exists and the waveform characteristics are only environmental noise or no valid high-level segment, the MCU immediately releases all control, and the system automatically returns to the FPGA default control state. Through the hold window mechanism and target re-detection rules, stable maintenance and orderly exit of control are achieved, eliminating control jitter and display interruption.

[0058] The system is configured to maintain a hold window of 1000 milliseconds. After successful MCU takeover, it enters the hold window. During this period, even if the radar signal experiences three brief drops, each lasting 50 milliseconds, the system will block them and not release control. When the 1000-millisecond countdown ends, if the radar waveform recognition result still indicates personnel presence, MCU control will continue; if the detection result indicates no valid target, MCU control will be immediately released, and control will switch back to FPGA.

[0059] The system uses a control arbitration module to comprehensively determine the validity of alarm gating status and control signals. When an alarm is closed, the MCU control is forcibly released and the system reverts to FPGA control, achieving secure switching and state locking between the two control sources. The control arbitration module uses a comprehensive logical judgment to determine the control ownership between the FPGA and MCU, ensuring that the two control sources operate without conflict and maintain a unique state. The control arbitration module prioritizes alarm gating as the highest-priority judgment condition: when the alarm gating is closed, regardless of whether the radar input signal is high, low, or exhibits jitter, the system directly determines that the MCU has no control authority, immediately forcibly releasing all display and drive permissions of the MCU, and reverting all control permissions, including screen scanning, image output, and parameter configuration, to the FPGA's default control state.

[0060] During the rollback switching process, the system strictly locks the intermediate state, disallowing any intermediate state of "FPGA half-control, MCU half-control" or simultaneous output of control commands from both sources. This prevents display errors, ghosting, line offsets, or drive conflicts caused by overlapping control. Through this forced rollback and state locking mechanism, secure switching and stable locking of dual control source permissions are achieved.

[0061] In actual execution, once the alarm gate switches from the enabled state to the disabled state, the system will immediately perform the following operations: immediately cut off all control outputs of the MCU to the LED driver, line scan, and display buffer; reset all status variables such as display flag, scan pointer, alarm status, and takeover flag; re-enable the FPGA to control the display driver and restore the FPGA's default display output; latch the current control state to ensure that the MCU no longer responds to any input signals.

[0062] Once personnel leave the detection area, the radar waveform recognition results continuously indicate no target, and the alarm gate switches from allowed to disabled. Even if the radar input still has a brief high-level signal at this time, the system immediately cuts off MCU control, resets the display and control flags, and switches the screen back to FPGA control. This prevents simultaneous control by the FPGA and MCU, ensuring the screen stably returns to standby display mode.

[0063] Following the execution logic of prioritizing alarm status judgment, stable control takeover, priority continuation of the hold window, and immediate rollback upon failure, the system completes the entire process of control arbitration, switching, holding, and release, generating stable control information for FPGA and MCU without oscillation switching, control conflicts, or intermediate states. The system operates stably according to the preset priority execution logic, consistently adhering to the execution sequence of prioritizing alarm status judgment, stable control takeover, priority continuation of the hold window, and immediate rollback upon failure or closure, ensuring an orderly, conflict-free, and oscillating workflow for both control sources. First, the system uses the alarm gating status as the highest priority judgment condition. Only when the alarm gating is in an allowed state will the subsequent control takeover detection process be initiated; if the alarm gating is in a closed state, the takeover process is skipped, maintaining the FPGA's default control, thus avoiding invalid switching from the source. Second, under the premise of alarm permission, the system determines the stability duration of the radar control input signal. Only when the signal remains consistently stable and meets the standard will MCU control takeover be executed, preventing false takeovers due to pulse interference.

[0064] Upon entering MCU control, the system automatically opens a hold window. Within this window, it prioritizes the execution of control retention logic, shielding all short-term level jitter and interference signals, and refraining from responding to invalid release requests. This ensures continuous and complete actions such as warning display and voice broadcast. When the hold window expires, the target disappears, the alarm gate closes, or the control signal fails, the system immediately performs a rollback operation, unconditionally releasing MCU control and returning to FPGA control. Through this logic, the system fully realizes a closed-loop control process encompassing control arbitration, permission switching, hold management, and release rollback. Ultimately, it outputs stable control information between the FPGA and MCU without oscillation switching, control conflicts, or intermediate states, providing a reliable control foundation for the buried warning screen.

[0065] When an alarm is enabled and the radar input is valid and stable, MCU takeover is completed. For example, if alarm gating is enabled and the radar high level remains valid for 200ms, the system switches to MCU control. If a target is continuously detected within the hold window, MCU control is maintained. For example, if a person remains within the hold window for 1 second, MCU control continues after the hold window expires. If no target is detected after the hold window ends, MCU control is released, and the system automatically switches back to FPGA. Once the alarm gating is turned off, regardless of the current state, the system immediately forces a return to FPGA control and resets the display and status flags.

[0066] S104 executes the display driver resynchronization process the instant the MCU takes over, sequentially completing the output shutdown, horizontal scan complete shutdown, driver reconfiguration, frame loading, and horizontal start point reset, eliminating afterimages, ghosting, horizontal offset, and short-term black screen.

[0067] In one implementation, the system immediately initiates a display driver resynchronization process the instant it detects that control is about to switch from the FPGA to the MCU. This process consists of five steps executed in a fixed sequence to eliminate afterimages, ghosting, line offsets, and short-term black screens caused by the control switch, ensuring that the display is clean, stable, and error-free after the switch.

[0068] Before the MCU takes over, the system prioritizes cutting off the LED screen's drive output enable signal, stopping all scanning and data output. This prevents the screen from responding to residual drive signals from the FPGA and from receiving unstable control signals from the MCU. This blocks the signal superposition of old and new control sources, providing a clean, interference-free, and residue-free starting state for subsequent resynchronization. At the switching trigger moment, the system immediately pulls low on the display enable pin, stopping the screen refresh and preventing screen tearing caused by simultaneous FPGA scanning and MCU initialization.

[0069] The system sequentially performs a low-level clearing operation on all line scan channels, shutting down the driver line by line to release residual charge within the screen and clear the display data left over from the previous frame. By completely extinguishing each line, afterimages, ghosting, and lingering glow are completely eliminated, ensuring the screen returns to a completely black state with no content. For a 16-line scan buried LED screen, the system sequentially shuts down the driver from line 1 to line 16 to ensure all pixels are completely extinguished, with no residual light spots.

[0070] Based on the physical specifications of the buried LED screen, the system reconfigures parameters such as scanning timing, drive current, refresh rate, row latch timing, and communication phase to ensure a complete match between the MCU-side drive circuit and the screen hardware. All parameters are configured according to the standard values ​​in the hardware manual to avoid issues such as dim lighting, misaligned rows, and flickering caused by driver mismatch. The scanning frequency is restored to 120Hz, the drive current is set to the rated value, and the row scanning timing is re-aligned to establish a standard communication relationship between the MCU driver and the screen.

[0071] The system writes preset alarm frame data, including warning text, scrolling direction, scrolling speed, inverted color flashing cycle, and display brightness, into the display cache and performs verification. This ensures the data in the cache is complete and correctly formatted, preparing the content for stable display later. Parameters such as the "Caution: Safety" scrolling warning text, the 200ms inverted color cycle, and the left scrolling mode are also written into the cache to ensure data accuracy.

[0072] The system resets the line scan counter to the starting position of the first line, ensuring that subsequent scans begin from the first line. This unifies the correspondence between line addresses and displayed data, eliminating line offsets, misalignments, and vertical misalignments. After resetting, a loop scan is initiated, ensuring precise alignment of the output screen. The line counter is then reset to zero, and output resumes from the first line, preventing text from shifting upwards, downwards, or becoming fragmented.

[0073] Through the above steps, the system completes full-link resynchronization of the display driver, achieving complete alignment across five dimensions: output enable, pixel status, driver parameters, frame data, and line position. After resynchronization, the screen exhibits no ghosting, misalignment, blackouts, or garbled characters, and can directly enter the scrolling warning and inverted color flashing states, providing a stable and reliable display output foundation for audio-visual coordinated alarms.

[0074] S105, based on a unified alarm stage state machine, achieves sound and light coordinated triggering, aligns the timing of the scrolling inverted color warning display with the asynchronous voice broadcast, and ensures consistent warning perception.

[0075] In one implementation, the system establishes a unified alarm phase state machine to coordinate the entire process timing of display output and voice broadcast. The state machine includes four levels: standby state, alarm preparation state, alarm execution state, and exit reset state. In the standby state, it receives FPGA control commands; in the alarm preparation state, it is associated with the display driver resynchronization process; in the alarm execution state, it synchronously triggers display and voice actions; and in the exit reset state, it stops the audio-visual output and restores the initial state. Each state transitions in a fixed order, and the states are linked through control authority activation signals, resynchronization completion signals, and alarm gating signals to ensure that display and voice are always in the same execution phase. The system only starts the visual alert and voice broadcast simultaneously after entering the alarm execution state, preventing situations where there is only display without sound or only sound without display.

[0076] After the MCU successfully takes over control, the system enters the alarm preparation phase. The system prioritizes the display driver resynchronization process, sequentially completing operations such as turning off display output, extinguishing all line scans, reconfiguring driver parameters, loading frame data, and resetting the line start point. Only after all display resynchronization is complete is the state machine allowed to jump to the next stage; no audio or visual actions are triggered if resynchronization is incomplete. After the MCU takes over, it must wait for the display resynchronization to finish before the system enters the alarm-ready state to prevent audio and video asynchrony caused by the display not being ready.

[0077] During the alarm execution phase, the system initiates display output, driving the buried screen to scroll and display warning text according to preset rules. The system switches display brightness and color at fixed intervals to achieve a flashing warning effect. Display actions are uniformly scheduled by a state machine, synchronized with the state machine's clock cycle to ensure stable and controllable scrolling rhythm and color-reversal frequency. The warning text scrolls at a fixed speed, while simultaneously displaying inverted colors at fixed intervals. All display changes are timed uniformly by the state machine to maintain regularity and stability.

[0078] The system initiates an asynchronous voice broadcast process simultaneously with entering the alarm execution phase. Voice playback does not block the display refresh task and maintains the same start time and running cycle as the scrolling, inverted display. The state machine provides unified enable control for both display and voice execution, ensuring simultaneous activation and deactivation for complete timing alignment. The voice broadcast begins synchronously the instant the warning text starts scrolling and inverting; display actions continue uninterrupted during voice playback without any delay.

[0079] When the alarm gate is closed, the target leaves, or control is released, the state machine transitions to the exit reset state. The system simultaneously stops the scrolling color-reversed display and voice announcements, and disables all audio-visual outputs. The system resets display parameters and voice indicators, returning to standby mode, awaiting the next alarm trigger. After personnel leave the detection area, the system immediately stops displaying warnings and voice announcements, synchronously resets all relevant modules, and quickly returns to standby mode.

[0080] The system uses a unified alarm phase state machine to strongly bind visual warnings and voice announcements. All audio and visual actions are scheduled by the same state machine, avoiding decentralized control methods such as independent triggering or delayed triggering. From triggering to operation and then to exiting, the display and voice maintain time synchronization and phase consistency, achieving a stable and unified on-site warning perception effect. Regardless of whether the system is in the triggering, holding, or exiting phase, the display and voice always act in sync, providing on-site personnel with a consistent and coherent warning experience.

[0081] The S106 adopts a Tick non-blocking main loop scheduling architecture, periodically polling display refresh, radar identification, control arbitration, alarm judgment, and temperature and humidity acquisition tasks. Time-consuming tasks are processed asynchronously, ensuring the real-time display and system responsiveness under MCU resource constraints.

[0082] In one implementation, a Tick non-blocking main loop scheduling technique is used to uniformly schedule the multi-task execution process of the buried warning screen, generating parallel execution results for LED display refresh, radar waveform recognition, control arbitration, alarm stage judgment, and temperature and humidity acquisition. The system employs Tick non-blocking main loop scheduling technology to construct a unified multi-task scheduling architecture adapted to the buried warning screen scenario, enabling parallel execution and real-time response of multiple core tasks under hardware conditions with limited MCU resources. This scheduling architecture covers five core tasks: LED display refresh, radar waveform recognition, control arbitration, alarm stage judgment, and temperature and humidity acquisition. All tasks share the same system clock reference and proceed independently in a polling manner, without using blocking delays or waiting for synchronization signals, ensuring that tasks do not interfere with each other.

[0083] Under the non-blocking scheduling mechanism, the system uses fixed time slices as the smallest scheduling unit to execute each task in stages and slices. Among them, LED display refresh, as a high real-time task, is executed first in each loop to ensure that the screen is flicker-free, black screen, and lag-free; radar waveform recognition, control arbitration, and alarm stage judgment are executed immediately afterward to ensure the real-time performance of sensing and control logic; relatively slow peripheral tasks such as temperature and humidity acquisition are processed using asynchronous triggering and background querying methods, without occupying the main thread time.

[0084] The system uses a fixed time slice as the scheduling benchmark, breaking down display refresh and radar signal acquisition into the smallest execution units. These units are executed separately within a single main loop, achieving parallel operation. The display refresh task advances one scan line or one frame refresh per loop, while the radar identification task completes one level reading and edge recording per loop. The two tasks are interleaved in timing and do not wait for each other, preventing display refresh from being slowed down due to radar acquisition waiting or radar sampling from being missed due to prolonged display scanning.

[0085] For example, within a 10ms tick scheduling cycle, the system first completes one line of LED display refresh output, then completes one radar level sampling and status update, followed by control arbitration and alarm judgment, and finally starts temperature and humidity acquisition and exits immediately without waiting for the acquisition results. Each task runs in a "segmented execution, progress saving" manner, ensuring smooth display, timely radar response, no control delay, and no missed acquisition steps even with limited MCU resources. Through the tick non-blocking scheduling architecture, the system changes the traditional blocking process to a no-wait polling mode, ensuring that display real-time priority, control logic real-time response, and peripheral tasks are completed asynchronously. The overall operation is stable and smooth, fully adapting to the long-term, reliable, and unattended working requirements of buried warning screens.

[0086] The system integrates fixed-period polling order, inter-task state variable coordination rules, and non-blocking execution constraints to establish an adaptation relationship between multi-task non-blocking operation and MCU resource-constrained scenarios, generating a standardized system task scheduling process. The system unifies and integrates fixed-period polling order, inter-task state variable coordination rules, and non-blocking execution constraints to form a standardized scheduling process suitable for buried warning screens. This process uses a Tick non-blocking main loop as its core, strictly adhering to a fixed priority order of display refresh priority, radar identification following, control arbitration synchronization, alarm judgment linkage, and environmental data acquisition following. The entire process does not employ blocking delays or wait for peripheral device responses; tasks only exchange running results and execution conditions through state variables, thus highly adapting to embedded operating scenarios with limited MCU resources.

[0087] During the scheduling and execution process, each main loop of the system calls various tasks sequentially in a fixed order. After the previous task is completed, it only updates its own status flag without occupying additional CPU waiting time, and immediately enters the scheduling and execution of the next task, so that the main loop always keeps running continuously and efficiently. The specific scheduling rules are as follows: the LED display refresh task is executed first to ensure the real-time refresh of the screen and avoid flickering and lag; then the radar waveform recognition task is executed to complete level sampling, edge detection and waveform segmentation recognition; the control arbitration task is executed synchronously to determine the FPGA / MCU permission ownership based on alarm gating and signal validity; the alarm judgment task is executed in conjunction with the alarm judgment task to output alarm enable / disable instructions based on waveform results and state machine logic; finally, environmental monitoring tasks such as temperature and humidity acquisition are executed, using an asynchronous triggering method to avoid blocking the main loop.

[0088] Tasks do not use delays or waiting periods; they coordinate solely through status flags. For example, the alarm judgment task will only make an alarm decision after the radar identification task updates the "valid target" status flag; and the display resynchronization and audible / visual alarm tasks will only be initiated when the control arbitration task outputs the "MCU has taken over" flag.

[0089] Within a single tick cycle, the system first refreshes the LED display and updates the "Line Scan Complete" flag; then it reads the radar level and updates the "Radar Sampling Complete" flag; next, it reads the radar status to complete control arbitration and updates the "Control Source Switching" flag; then, based on the arbitration result, it completes alarm judgment and updates the "Alarm Allowed" flag; finally, it starts temperature and humidity acquisition and marks it as "Acquisition in Progress," then exits the current loop. The entire process is seamless and unblocked, ensuring smooth execution even with limited MCU clock speeds and scarce resources, maintaining smooth display, timely radar response, undelayed control, and accurate data acquisition.

[0090] Based on a standardized task scheduling process, the system extracts core scheduling information and uses fixed-sequence periodic calls as the execution method, state variables and time thresholds as collaborative parameters, and a Tick polling mechanism as the judgment basis to achieve precise scheduling and execution of display refresh, radar identification, control arbitration, alarm judgment, and environmental acquisition tasks. The system sequentially schedules and executes these five tasks. The scheduling process employs a segmented, non-blocking, and non-waiting mechanism. Each loop advances only one step of logic for each task, avoiding complete blocking operations to ensure that MCU resources are not occupied for extended periods and that the system maintains a consistently high response speed.

[0091] The specific scheduling and execution method is as follows: Within each tick cycle, the system strictly follows a fixed order of priority: display refresh first, radar identification second, control arbitration synchronization, alarm judgment linkage, and environmental data acquisition last. There is no delay between tasks, and tasks do not wait for external device responses; progress is determined solely by status flags and time thresholds. Each loop only allows each task to advance a small segment, avoiding continuous, time-consuming execution to prevent blocking of high real-time tasks such as display refresh.

[0092] In a typical loop, the system executes as follows: First, it prioritizes refreshing one line of LED display, exiting immediately after completing the current line scan without waiting for the entire frame to finish. Second, it immediately performs radar level sampling and edge recording, proceeding to the next step immediately upon completion. Third, based on the radar status and alarm gating, it performs a round of control arbitration to quickly determine permissions. Fourth, combining the arbitration result, it performs an alarm status check and updates the alarm enable / disable flags. Fifth, it finally triggers temperature and humidity acquisition, exiting immediately after startup without waiting for ADC or I2C completion. Each step executes and exits quickly, without blocking or waiting, ensuring the main loop always operates at high speed.

[0093] Within a 10ms tick scheduling cycle, the system first refreshes the 5th row of LED pixels, then immediately reads the radar level; next, it uses this level to determine whether the FPGA / MCU needs to switch permissions; then it uses the permission result to update whether an alarm should be triggered; finally, it starts temperature and humidity acquisition and exits directly. The entire process is seamless and unblocked, ensuring no missed radar samples, no display lag, no arbitration delays, and no slowing down of the system for environmental data acquisition. This scheduling method is perfectly suited for embedded scenarios with limited MCU resources, ensuring that the buried warning screen remains flicker-free, the radar does not misjudge, the switching is smooth, and alarms are timely during long-term operation.

[0094] Combining the resource allocation requirements of prioritizing real-time display and asynchronous processing of time-consuming tasks, the system optimizes the execution methods of each task for non-blocking and asynchronous processing. It clarifies the scheduling logic of continuous execution of critical tasks and background polling of non-critical tasks, generating scheduling control information that minimizes MCU resource consumption, ensures smooth display refresh, and eliminates system response delays. The system optimizes the execution methods of various tasks based on the resource allocation rules prioritizing real-time display and asynchronous processing of time-consuming tasks, achieving parallel and non-blocking operation of multiple tasks on an embedded platform with limited MCU resources. The system sets LED display refresh as the highest priority high-real-time task, prioritizing its execution and advancing it in segments within each tick main loop to ensure uninterrupted, flicker-free, and stutter-free screen scanning. Simultaneously, time-consuming operations such as temperature and humidity acquisition, which require peripheral communication and have slower response times, are set as asynchronous background tasks. These tasks only trigger startup and status queries, without waiting for data acquisition to complete; data is read only after the sensor is ready, avoiding the blocking of the entire main loop by slow peripherals.

[0095] For display refresh tasks: Executed in every loop, advancing one line or one frame at a time, refreshing line by line and frame by frame to ensure real-time performance. For radar identification, control arbitration, and alarm judgment: Executed sequentially following display tasks, with rapid judgment and exit. For temperature and humidity acquisition: An asynchronous start mode is adopted. The system only issues a start command, without waiting for I2C or ADC conversion to complete, and immediately returns to the main loop to continue running other tasks; data is read and updated only after the acquisition completion flag is found in the next loop.

[0096] In one loop, the system first refreshes one row of LED displays, then performs radar sampling and control arbitration, followed by initiating temperature and humidity acquisition and marking it as "acquiring," before immediately ending the current loop. When the next loop arrives, the system first proceeds to refresh the next row of displays, then checks the temperature and humidity status. If the task is complete, it reads the data; otherwise, it skips the waiting period. The entire process is unblocked and uninterrupted, ensuring a continuous and stable display flow.

[0097] Through the aforementioned non-blocking scheduling mechanism, the system significantly reduces MCU resource utilization, ensuring smooth and lag-free display refresh throughout. Simultaneously, it improves the response speed of events such as radar identification, control switching, and alarm output, ultimately achieving a low-load, high-real-time, flicker-free, and latency-free scheduling and control effect. Even with multiple tasks running concurrently, the LED display remains stable and flicker-free, radar identification and control arbitration can respond in real time, temperature and humidity data acquisition can be completed normally in the background, and various tasks do not interfere with each other. The overall system operates stably and reliably, providing solid support for the long-term unattended operation of the buried warning screen.

[0098] The S107 forms a closed-loop control system through alarm status gating, takeover holding, and failure reset. When there is an abnormality or no target, it automatically shuts down the alarm, resets the status, and returns to standby monitoring, achieving stable, low-false-trigger, and seamless switching of the buried screen warning control throughout the entire process.

[0099] In one implementation, based on the stable control requirements of the entire process of the buried warning screen, the FPGA / MCU dual-control switching rules, and the alarm triggering and exit logic, the core components, state transition conditions, and execution sequence of the alarm status gating, takeover holding mechanism, and failure reset process are integrated to clarify the judgment criteria and operational constraints of closed-loop control. Based on the actual needs of long-term stable operation of the buried warning screen, and combining the permission switching rules of the FPGA and MCU dual control sources, as well as the alarm triggering and exit logic, the system integrates the three core components—alarm status gating, takeover holding mechanism, and failure reset process—to form a closed-loop control architecture.

[0100] The system uniformly plans the state transition conditions, execution timing, and linkage relationships of each link, and clearly defines radar waveform recognition results, valid control signals, and alarm gate levels as the core basis for closed-loop decision-making. It also strictly limits state transitions to meet timing constraints and anti-jitter constraints, thereby eliminating problems such as random state jumps, permission jitter, and display anomalies from the rule level, and establishing a complete rule foundation for the stable operation of the entire process.

[0101] Under the closed-loop control architecture, the system incorporates all actions such as alarm activation, MCU takeover, hold-up, anomaly reset, and standby return into unified timing management. All state transitions must meet preset duration thresholds and signal validity conditions, and arbitrary jumps without basis or constraints are not allowed. Any state change must simultaneously meet three conditions: valid waveform recognition, stable control signal, and compliant timing interval, thereby ensuring smooth system operation, consistent decision-making, and reliable switching.

[0102] The alarm process will only begin if the radar waveform continuously identifies a valid target, the alarm gating is repeatedly deemed permissible, and the state transition interval exceeds 300ms. Switching from FPGA control to MCU takeover requires alarm permission, a sustained high-level radar signal for over 200ms, and the system being in a non-anti-jitter disabled period before the switch. Reset and rollback from MCU hold to FPGA control requires multiple consecutive target absences, the alarm gating being closed, and the hold window expiring before a reset and rollback will occur. Any signal anomaly or control conflict will immediately trigger a forced reset, returning the system to FPGA standby and clearing all status flags.

[0103] Through this integrated and unified timing management, the system achieves closed-loop control of the entire process from monitoring, identification, judgment, takeover, display, alarm to exit and reset. The entire process is free from conflicts, jitter, afterimages, and disorder, truly meeting the long-term stable, low-false-trigger, and unattended operation requirements of buried warning screens in complex environments such as platforms.

[0104] Based on the design goals of low false triggering, no control conflicts, and seamless display switching, the closed-loop control execution logic is standardized, clarifying the correspondence between core judgment conditions and trigger scenarios. The core judgment conditions include alarm gating status, hold window expiration result, and control validity status. Trigger scenarios include personnel approach, personnel departure, control failure, and system anomaly. The system standardizes and unifies the execution logic of closed-loop control, ensuring that each operating scenario corresponds to clear judgment conditions and processing procedures. The system sets alarm gating status, hold window expiration result, and control validity status as the three core judgment criteria, establishing a one-to-one correspondence with four actual trigger scenarios: personnel approach, personnel departure, control failure, and system anomaly. This ensures that the system executes according to preset rules in any scenario, without misjudgment, erratic behavior, or control conflicts.

[0105] For scenarios involving personnel approaching, the corresponding judgment conditions are: alarm gating is in an allowed state + valid control signal. The system allows the MCU to take over, enter the alarm process, and activate audible and visual alarms. For scenarios involving personnel leaving, the corresponding judgment conditions are: alarm gating is closed + hold window expires. The system releases MCU control, closes the alarm, switches back to FPGA control, and resets the state. For scenarios involving control failure, the corresponding judgment conditions are: invalid control signal, interruption, or abnormal transition. The system immediately cuts off MCU control, forcibly reverts to FPGA, and masks invalid commands. For scenarios involving system abnormalities, the corresponding judgment conditions are: abnormal waveform, timing error, or state exceeding limits. The system immediately turns off the screen, clears the buffer, resets all flags, and returns to standby.

[0106] When personnel leave the detection area, the radar continuously identifies no valid targets, the alarm gating switches to off, and the window timer expires. The system matches the "personnel departure" scenario and immediately executes the following: stop the audible and visual alarms, release MCU control, switch back to the FPGA default display, and clear all status flags, completing a safe rollback. If the radar input signal suddenly interrupts or becomes abnormal, the system identifies this as a "control failure" scenario. Regardless of the current state, it immediately forces a disconnect from MCU control, locks the rollback to the FPGA, and prevents erroneous output.

[0107] By combining radar waveform recognition results with control arbitration status, a closed-loop execution rule is set: if the alarm gating is valid, takeover is maintained; if there is no target or the gating is closed, release and reset are performed; and if an anomaly occurs, forced rollback is initiated. This ensures a smooth, uninterrupted, and logically sound process. The system, combining radar waveform recognition results with the real-time status of control arbitration, establishes hierarchical and prioritized closed-loop execution rules to ensure stable switching and conflict-free operation of the buried warning screen under various working conditions. The system uses alarm gating status as the highest priority, and, based on target detection results and control signal validity, executes control logic in three levels: alarm gating valid, alarm gating invalid, and system anomaly or control failure.

[0108] When the alarm gating is deemed valid, the system maintains the MCU's control over the display and alarm functions, sustaining audible and visual alarm outputs and scrolling color-inverted displays. Simultaneously, it blocks unexpected level jitter and interference signals to ensure the MCU's control is not interrupted and premature release does not occur. As long as the radar continues to identify a valid target, control remains stably held by the MCU and does not return to the FPGA.

[0109] When the radar fails to identify a valid target multiple times consecutively, or when the alarm gating switches from enabled to disabled, the system immediately executes a control release procedure, stopping the audible and visual alarms, resetting the display driver and status flags, and returning all control authority to the FPGA, restoring standby display. This process is completed according to a predetermined sequence, without any status residue or display ghosting.

[0110] When abnormal control signals, waveform errors, communication interruptions, or system operation exceeding limits occur, the system immediately enters the abnormal handling process, unconditionally and forcibly cuts off the MCU output, quickly returns to the FPGA default control state, and clears all display buffers, scan pointers, and alarm flags to ensure that the abnormal state does not spread and does not cause abnormal display on the screen.

[0111] During the execution of all the above rules, the system synchronously locks the intermediate state, does not allow the ambiguous state of "FPGA half-control, MCU half-control", and does not allow the dual control sources to output instructions at the same time, thus avoiding problems such as control jitter, display ghosting, and logic malfunction from both hardware and software levels.

[0112] If the alarm gating remains active and the radar continuously detects personnel, the system maintains stable MCU control, and the warning screen and audio output continue normally. If the alarm gating is active but the target is not detected for several consecutive decision cycles, the system determines that the personnel have left, immediately releases the MCU, and switches back to the FPGA. If the alarm gating is closed, regardless of whether there is a signal, the system forcibly reverts to the FPGA, disables the alarm, and resets all states. If the radar input signal is suddenly lost or exhibits a continuous abnormal level, the system determines that control has failed, immediately cuts off MCU control, forcibly reverts, and resets the screen to zero.

[0113] The system integrates alarm status determination, takeover and hold management, failure reset execution, and standby state rollback processes into a unified whole, generating a closed-loop warning control information system encompassing status locking, access control, anomaly reset, and cyclic monitoring. The system unifies and schedules the four core processes—alarm status determination, takeover and hold management, failure reset execution, and standby state rollback—ensuring each step executes sequentially and forms a complete, autonomous, and long-term unattended closed-loop control mechanism. The system ensures overall stability through four core mechanisms: status locking to prevent operational status jumps and fluctuations; access control to strictly define the FPGA and MCU control boundaries, eliminating dual-source conflicts; anomaly reset to quickly restore a safe state during faults; and cyclic monitoring for continuous standby monitoring, enabling automatic restart and automatic reassessment. Ultimately, this forms a complete closed-loop warning control information system covering status management, access control switching, anomaly handling, and cyclic monitoring, providing complete, reliable, and continuous operational data for buried warning screens.

[0114] The alarm status determination process is based on dual-mode radar waveform recognition, combined with continuous state anti-jitter and minimum flip interval constraints, to output a stable alarm enable / disable signal, which serves as the highest priority decision criterion for the entire system. The takeover and hold management process enters a fixed-duration hold window after successful MCU takeover, shielding against short-term jitter. Upon expiration, it executes either continuation or release based on the presence of the target, ensuring complete and uninterrupted alarm actions. The failure reset execution process immediately cuts off MCU output, resets the display driver, clears the buffer and flags, and forces a rollback to FPGA control when the alarm is disabled, the target disappears, or control fails, eliminating afterimages, misalignments, and intermediate states. The standby state rollback process restarts radar sampling and tick scheduling after reset, restores the initialization state, continuously monitors in a loop, and waits for the next personnel approach trigger.

[0115] The four processes are sequentially linked and automatically flow, completing a full closed loop from triggering, running, exiting, to returning to standby without manual intervention. For example, when personnel approach the platform, the radar identifies a valid target, the system enters alarm-enabled state, the MCU takes over and activates audible and visual warnings; after personnel leave, continuous absence of targets triggers alarm closure, the system performs a release reset, stops the warnings, and returns to FPGA standby; if a signal abnormality occurs midway, the system immediately performs a forced reset and screen shutdown, quickly restoring a safe state; after the reset is completed, it automatically returns to loop monitoring and continues to wait for the next trigger.

[0116] Through the above-mentioned closed-loop scheduling of the entire process, the system realizes autonomous operation from alarm triggering, maintaining operation, exiting reset and returning to standby. Abnormalities can be automatically recovered and automatic monitoring can be performed after termination. It can operate stably for a long time without external operation, fully meeting the actual use requirements of buried warning screens in complex environments such as platforms and transportation hubs for long-term unattended operation, high reliability and low false triggering.

[0117] like Figure 5 As shown, a buried information and warning screen control device based on radar waveform state recognition includes: The radar waveform acquisition and preprocessing module 501 is used to acquire the original waveform of the approaching person through millimeter-wave radar pulse acquisition and edge detection, providing basic data on level, edge transition and duration for subsequent segmentation identification, and supporting semantic decision-making of radar signals. The radar waveform state recognition module 502 is used to complete waveform determination by recognizing the initialization segment of mode 0 and performing feature statistics of the decision window of mode 1. It uses single-segment single-counting and continuous state gating to suppress noise jitter and outputs stable alarm enable / disable commands. The dual-control-source control arbitration module 503 is used to achieve oscillation-free switching between FPGA and MCU by adopting a control stability determination and takeover hold window mechanism, and to force FPGA control to fall back when the alarm is closed, thus eliminating control conflicts and intermediate states. The display driver resynchronization module 504 is used to perform the following processes at the moment the MCU takes over: output off, line scan all off, driver reconfiguration, frame loading, and line start reset, to eliminate afterimages, ghosting, line offset and short-term black screen. The sound and light coordinated alarm control module 505 is used to realize the synchronous triggering of sound and light based on a unified alarm stage state machine, control the timing alignment of the scrolling reverse color warning display and the asynchronous voice broadcast, and improve the consistency of warning perception. The non-blocking multi-task scheduling module 506 is used to adopt a Tick non-blocking main loop architecture to periodically poll display refresh, radar identification, control arbitration, alarm judgment, and temperature and humidity acquisition tasks. Time-consuming tasks are processed asynchronously to ensure real-time performance in scenarios where MCU resources are limited. The closed-loop control and status reset module 507 is used to form a closed-loop logic through alarm status gating, takeover holding, and failure reset. When there is an abnormality or no target, the alarm is automatically turned off, the status is reset and the system returns to standby, so as to achieve stable and low false triggering control throughout the process.

[0118] A computing device includes a memory for storing computer program instructions and a processor for executing the computer program instructions, wherein when the computer program instructions are executed by the processor, the device is triggered to execute any one of the control methods for an underground information and warning screen based on radar waveform state recognition.

[0119] The methods and / or embodiments in this application can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. When the computer program is executed by a processing unit, it performs the functions defined in the methods of this application.

[0120] It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0121] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application.

Claims

1. A control method for an underground information and warning screen based on radar waveform state recognition, characterized in that, include: The underground LED warning screen control system is built based on radar waveform segmentation recognition + FPGA / MCU dual-control arbitration + non-blocking scheduling. It obtains the original waveform of personnel approach through millimeter-wave radar pulse acquisition and edge detection, adapts to the dual control source collaborative scenario, and completes the semantic judgment of radar signal and stable switching of control. The waveform state is accurately determined by using mode 0 initialization segment recognition and mode 1 decision window feature statistics. Single-segment single-counting and continuous state gating are used to suppress noise and jitter, and output stable alarm enable / disable commands. Mode 0 is the initialization segment waiting recognition mode, which is used to monitor the continuous high-level signal sent by the FPGA; mode 1 is the decision segment feature statistics mode, which counts the number of long high-level segments that meet the minimum duration requirement within a preset time window. The system employs a control stability determination and takeover hold window mechanism to achieve oscillation-free switching between FPGA and MCU, and forces FPGA control to revert when an alarm is turned off, thus eliminating control conflicts and intermediate states. The display driver resynchronization process is executed the moment the MCU takes over, sequentially completing the following steps: output off, all horizontal scans are turned off, driver reconfiguration, frame loading, and horizontal start reset, eliminating afterimages, ghosting, horizontal offset, and short-term black screen. Based on a unified alarm phase state machine, sound and light coordinated triggering is achieved, and the timing of the scrolling inverted color warning and the asynchronous voice broadcast is aligned to ensure consistent warning perception. The system adopts a Tick non-blocking main loop scheduling architecture, which periodically polls display refresh, radar identification, control arbitration, alarm judgment, and temperature and humidity acquisition tasks. Time-consuming tasks are processed asynchronously to ensure the real-time display and system responsiveness under MCU resource constraints. A closed-loop control system is formed by alarm status gating, takeover holding, and failure reset. When there is an abnormality or no target, the alarm is automatically turned off, the status is reset, and the system returns to standby monitoring, achieving stable, low false triggering, and seamless switching of the buried screen warning control throughout the entire process.

2. The control method for buried information and warning screens based on radar waveform state recognition according to claim 1, characterized in that, Accurate waveform state determination is achieved through mode 0 initialization segment recognition and mode 1 decision window feature statistics. Single-segment single-counting and continuous state gating are used to suppress noise and jitter, outputting stable alarm enable / disable commands, including: Combining the segmented decision requirements of radar waveform state recognition with the dual-mode state machine logic, an initialization segment matching rule and a decision window feature statistical mechanism are introduced to build a hierarchical recognition system for mode 0 and mode 1. According to the timing specifications of waveform segmentation recognition, the detection results of the initial high-level segment completed in mode 0 are directly connected to the decision window of mode 1 to complete the timing cascade adaptation of the initialization segment and the decision segment. Based on the core requirement of waveform characteristic stability judgment, a constraint of counting at most once per segment is applied to the high-level segment, limiting the feature count to be triggered only within the effective long high-level segment, thus completing the counting constraint setting of the statistical rules; The radar real-time level and edge state are input into the hierarchical identification system. After the initialization segment of mode 0 identification is completed, mode 1 is entered. The number of long high-level segments that meet the duration condition is counted in the decision window, and the initial alarm state is generated based on the count value. State debouncing is achieved through continuous state determination and minimum flip interval gating. The alarm gating state is updated only when the conditions of consecutive shutdown number and flip interval are met, generating stable alarm enable / disable commands with dual constraints of waveform semantics and debouncing rules, thus achieving precise alignment between radar waveform and alarm decision.

3. The control method for buried information and warning screens based on radar waveform state recognition according to claim 1, characterized in that, Employing a control stability determination + takeover hold window mechanism, this system achieves oscillation-free switching between FPGA and MCU, and forcibly reverts FPGA control when alarms are disabled, eliminating control conflicts and intermediate states. This includes: Combining the collaborative control requirements of dual control sources of FPGA and MCU and the state machine logic for stable switching of control rights, a control signal stability judgment and takeover hold window mechanism is introduced to build a dual control source control arbitration and switching process for buried warning screens. According to the dual control source control switching rule, the radar control input signal is tested for stable duration under alarm permission. A high level is determined to be valid if it meets the stable duration, and a low level is directly determined to be invalid, thus completing the validity and anti-shake determination before the control switch. Based on the takeover hold and release strategy, after the MCU triggers takeover, it enters the hold window. Short-term jitter is blocked within the window. Upon expiration, the control right is continued or released according to the target detection result, thus completing the judgment of stable control right hold and exit. The control arbitration module comprehensively judges the alarm gating status and the validity of the control signal. When the alarm is closed, the MCU control is forcibly released and the control is returned to the FPGA control, realizing safe switching of dual control source permissions and state locking. Following the execution logic of prioritizing alarm status judgment, stable takeover of control, priority continuation of the holding window, and immediate rollback upon failure, the entire process of control arbitration, switching, holding, and release is completed, generating stable control information for FPGA and MCU without oscillation switching, control conflicts, or intermediate states.

4. The method for controlling an underground information and warning screen based on radar waveform state recognition according to claim 1, characterized in that, The system employs a Tick non-blocking main loop scheduling architecture, periodically polling display refresh, radar identification, control arbitration, alarm judgment, and temperature and humidity acquisition tasks. Time-consuming tasks are processed asynchronously, ensuring real-time display performance and system responsiveness under MCU resource constraints. This includes: The Tick non-blocking main loop scheduling technology is used to uniformly schedule the multi-task execution process of the buried warning screen, generating parallel execution results for LED display refresh, radar waveform recognition, control arbitration, alarm stage judgment, and temperature and humidity acquisition. The fixed-period polling order, inter-task state variable coordination rules, and non-blocking execution constraints are integrated and processed to establish the adaptation relationship between multi-task non-blocking operation and MCU resource-constrained scenarios, and generate a standardized system task scheduling process. Based on the standardized task scheduling process, core scheduling information is extracted. The fixed-sequence periodic call is used as the execution method, the state variables and time thresholds are used as the coordination parameters, and the Tick polling mechanism is used as the judgment basis to achieve precise scheduling and execution of tasks such as display refresh, radar identification, control arbitration, alarm judgment, and environmental acquisition. Based on the resource allocation requirements of prioritizing real-time display and asynchronous processing of time-consuming tasks, the execution mode of each task is optimized to be non-blocking and asynchronous. The scheduling logic of continuous execution of critical tasks and background polling of non-critical tasks is clarified, and scheduling control information with low MCU resource consumption, smooth display refresh, and no system response delay is generated.

5. The control method for buried information and warning screens based on radar waveform state recognition according to claim 4, characterized in that, A closed-loop control system is formed through alarm status gating, takeover holding, and failure reset. In case of abnormality or lack of target, the alarm is automatically shut down, the status is reset, and the system returns to standby monitoring. This achieves stable, low-false-trigger, and seamless switching of the buried screen warning control throughout the entire process, including: Based on the requirements for stable control of the entire process of the buried warning screen, the switching rules of FPGA / MCU dual control and the alarm triggering and exit logic, the core links of alarm status gating, takeover holding mechanism, failure reset process, status jump conditions and execution sequence are integrated to clarify the judgment basis and operation constraints of closed-loop control. Based on the design goals of low false triggering, no control conflict, and seamless display switching, the closed-loop control execution logic is standardized, and the correspondence between core judgment conditions and triggering scenarios is clarified. The core judgment conditions include alarm gate status, hold window expiration result, and control right effective status. The triggering scenarios include personnel approach, personnel departure, control failure, and system anomaly. By combining radar waveform recognition results with control arbitration status, a closed-loop execution rule is set to maintain takeover if the alarm gate is valid, release and reset if there is no target or the gate is closed, and force rollback if there is an anomaly, ensuring that the entire process is free of jitter, afterimages, and logical disorder. The alarm status determination, takeover maintenance management, failure reset execution, and standby status rollback process are uniformly integrated to generate a closed-loop alarm control information system that includes status locking, access control, abnormal reset, and cyclic monitoring.

6. A buried information and warning screen control device based on radar waveform state recognition, characterized in that, The device is used to execute executable instructions to perform the underground information and warning screen control method based on radar waveform state recognition as described in any one of claims 1 to 5.

7. A buried information and warning screen control system based on radar waveform state recognition, characterized in that, The system is used to execute executable instructions to perform the underground information and warning screen control method based on radar waveform state recognition as described in any one of claims 1 to 5.

8. An electronic device, characterized in that, include: First processor; The processor also includes a memory for storing executable instructions of the first processor; wherein the first processor is configured to execute the underground information and warning screen control method based on radar waveform state recognition as described in any one of claims 1 to 5 by executing the executable instructions.

9. A computing device, the device comprising a memory for storing computer program instructions and a processor for executing the computer program instructions, wherein, When the computer program instructions are executed by the processor, the device is triggered to execute the buried information and warning screen control method based on radar waveform state recognition as described in any one of claims 1 to 5.

Images