Display device and pixel driving circuit thereof

Abstract

This application discloses a display device and its pixel driving circuit, applied in the field of display technology. The output terminal of the data writing circuit is connected to the first terminal of the self-discharge circuit, the second terminal of the self-discharge circuit is connected to the first terminal of the first switching circuit, and the second terminal of the first switching circuit is connected to both the second switching circuit and the light-emitting circuit. The data writing circuit is used to: output a reference voltage in the first stage of each working cycle, turn off in the second and fourth stages, and output a data voltage in the third stage to control the brightness of the light-emitting circuit. The self-discharge circuit is used to: charge in the first stage, discharge through the first and second switching circuits in the second stage, and end the second stage when the gate-source voltage of the driving transistor reaches a set state, so that in the fourth stage, the output current is not affected by the threshold voltage of the driving transistor. Applying the solution of this application helps to ensure the quality of the display image and the small size of the pixel driving circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display device and its pixel driving circuit. Background Technology

[0002] Currently, to achieve better image quality, the pixel driving circuits used in OLED (Organic Light Emitting Diode) displays should be as small as possible. The smaller the pixel driving circuit, the more circuits can be arranged in the same space, which is more conducive to achieving high resolution and allowing the same area of ​​display to display richer details. Furthermore, due to factors such as manufacturing processes, there can be uniformity issues with the driving transistors in different pixel driving circuits. This means that the threshold voltages of different driving transistors may differ, causing the driving transistors in different pixel driving circuits to not provide a uniform and stable current output, resulting in uneven display brightness and affecting the quality of the displayed image. In addition, some current solutions generate through-current, which also affects the quality of the displayed image.

[0003] In summary, how to effectively ensure the quality of the display image and the small size of the pixel driving circuit are technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a display device and its pixel driving circuit to effectively ensure the quality of the displayed image and the small size of the pixel driving circuit.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides a pixel driving circuit, comprising: a data writing circuit, a self-discharge circuit, a first switching circuit, a second switching circuit, and a light-emitting circuit.

[0007] The output terminal of the data writing circuit is connected to the first terminal of the self-discharge circuit, the second terminal of the self-discharge circuit is connected to the first terminal of the first switching circuit, and the second terminal of the first switching circuit is connected to the second switching circuit and the light-emitting circuit respectively.

[0008] The data writing circuit is used to: output a reference voltage in the first stage of each working cycle to turn on the driving tube in the self-discharge circuit; turn off in the second and fourth stages of each working cycle; and output a data voltage in the third stage of each working cycle to control the light emission brightness of the light-emitting circuit in the fourth stage of the current working cycle.

[0009] The self-discharge circuit is used to: charge through the reference voltage in the first stage, discharge through the first and second switching circuits in the second stage, and end the second stage when the gate-source voltage of the driving transistor reaches a set state, so that in the fourth stage, the output current of the self-discharge circuit is not affected by the threshold voltage of the driving transistor.

[0010] In the first stage, the first switching circuit is turned off; in the second stage, both the first and second switching circuits are turned on; in the third stage, the first switching circuit is turned off; and in the fourth stage, the first switching circuit is turned on and the second switching circuit is turned off.

[0011] In one embodiment, the self-discharge circuit includes a third switching circuit, a first capacitor, a second capacitor, and a driving transistor.

[0012] The second terminal of the first capacitor is connected to the control terminal of the driving transistor, and the connection terminal serves as the first terminal of the self-discharge circuit; the first terminal of the first capacitor is connected to the second terminal of the second capacitor, the second terminal of the third switching circuit, and the first terminal of the driving transistor; the first terminal of the second capacitor is connected to the first terminal of the third switching circuit, and the connection terminal is connected to the positive terminal of the first power supply; the second terminal of the driving transistor serves as the second terminal of the self-discharge circuit.

[0013] In the first stage, the third switch circuit is turned on; in the second stage, the third switch circuit is turned off; in the third stage, the third switch circuit is turned off; and in the fourth stage, the third switch circuit is turned on.

[0014] In one embodiment, the third switching circuit includes a third switching transistor;

[0015] The first terminal of the third switching transistor serves as the first terminal of the third switching circuit, and the second terminal of the third switching transistor serves as the second terminal of the third switching circuit.

[0016] In one embodiment, the driving transistor is a PMOS transistor, the gate of the PMOS transistor serves as the control terminal of the driving transistor, the source of the PMOS transistor serves as the first terminal of the driving transistor, and the drain of the PMOS transistor serves as the second terminal of the driving transistor.

[0017] In one implementation, during the fourth stage, the third switching circuit remains on, or the duty cycle of the third switching circuit's on-time conforms to the current first set value.

[0018] In one embodiment, the data writing circuit includes a fourth switching transistor;

[0019] The first terminal of the fourth switch is used as the input terminal of the data writing circuit, and the second terminal of the fourth switch is used as the output terminal of the data writing circuit.

[0020] In the first stage, the fourth switch is turned on and the input terminal of the data writing circuit receives a reference voltage; in the second stage, the fourth switch is turned off; in the third stage, the fourth switch is turned on and the input terminal of the data writing circuit receives a data voltage; and in the fourth stage, the fourth switch is turned off.

[0021] In one embodiment, the first switching circuit includes a first switching transistor;

[0022] The first terminal of the first switching transistor serves as the first terminal of the first switching circuit, and the second terminal of the first switching transistor serves as the second terminal of the first switching circuit.

[0023] The second switching circuit includes a second switching transistor;

[0024] The first terminal of the second switching transistor serves as the first terminal of the second switching circuit, and the second terminal of the second switching transistor serves as the second terminal of the second switching circuit.

[0025] In one implementation, the second switching circuit is turned on during the first stage and / or the third stage.

[0026] In one implementation, during the fourth stage, the first switching circuit remains on, or the duty cycle of the first switching circuit's on-time conforms to the current second set value.

[0027] In a second aspect, the present invention provides a display device, comprising: a pixel driving circuit as described above.

[0028] By applying the technical solution provided in this embodiment of the invention, the self-discharge circuit in the pixel driving circuit enables the pixel driving circuit to compensate for the threshold voltage of the driving transistor. Therefore, when the light-emitting circuit emits light in the fourth stage, the current is not affected by the threshold voltage deviation of the driving transistor, which is beneficial for achieving uniformity in the pixel array display. Specifically, the output terminal of the data writing circuit is connected to the first terminal of the self-discharge circuit, the second terminal of the self-discharge circuit is connected to the first terminal of the first switching circuit, and the second terminal of the first switching circuit is connected to both the second switching circuit and the light-emitting circuit. In the first stage of each working cycle, the first switching circuit is turned off, and the data writing circuit outputs a reference voltage, causing the driving transistor in the self-discharge circuit to conduct. In the second stage, the data writing circuit is turned off, and both the first and second switching circuits are turned on. At this time, the self-discharge circuit discharges through the turned-on first and second switching circuits, and ends the second stage when the gate-source voltage of the driving transistor reaches a set state. This ensures that in the fourth stage, the output current of the self-discharge circuit is not affected by the threshold voltage of the driving transistor. In the third stage, the first switching circuit is turned off, and the data writing circuit outputs a data voltage, thereby controlling the brightness of the light-emitting circuit in this working cycle in the fourth stage. In the fourth stage, the first switching circuit is turned on and the second switching circuit is turned off. At this time, the current generated by the driving transistor is independent of its threshold voltage. This means that when the light-emitting circuit emits light in the fourth stage, the current is not affected by the threshold voltage deviation of the driving transistor, which is beneficial to achieving uniformity in the pixel array display. Furthermore, in this application, the pixel driving circuit includes a data writing circuit, a self-discharge circuit, a first switching circuit, a second switching circuit, and a light-emitting circuit. Its structure is simple and highly reliable, which is beneficial for miniaturizing the pixel driving circuit. In addition, in this application, because the first switching circuit is provided and is turned off in both the first and third stages, no through current is generated in the first and third stages, which also helps to ensure the quality of the displayed image. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the pixel driving circuit provided in a specific embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the pixel driving circuit provided in another specific embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the pixel driving circuit provided in another specific embodiment of the present invention. Detailed Implementation

[0033] The core of this invention is to provide a pixel driving circuit that helps ensure the quality of the display image and the small size of the pixel driving circuit, and also helps improve the contrast of the light-emitting circuit.

[0034] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a pixel driving circuit provided in a specific embodiment of the present invention. The pixel driving circuit may include: a data writing circuit 10, a self-discharge circuit 20, a first switching circuit 30, a second switching circuit 40, and a light-emitting circuit 50.

[0036] The output terminal of the data writing circuit 10 is connected to the first terminal of the self-discharge circuit 20, the second terminal of the self-discharge circuit 20 is connected to the first terminal of the first switching circuit 30, and the second terminal of the first switching circuit 30 is connected to the second switching circuit 40 and the light-emitting circuit 50 respectively.

[0037] The data writing circuit 10 is used to: output a reference voltage in the first stage of each working cycle to turn on the driving transistor TD in the self-discharge circuit 20; turn off in the second and fourth stages of each working cycle; and output a data voltage in the third stage of each working cycle to control the light emission brightness of the light-emitting circuit 50 in the fourth stage of this working cycle.

[0038] The self-discharge circuit 20 is used to: charge through a reference voltage in the first stage, discharge through the first switch circuit 30 and the second switch circuit 40 in the second stage, and end the second stage when the gate-source voltage of the driving transistor TD reaches a set state, so that in the fourth stage, the output current of the self-discharge circuit 20 is not affected by the threshold voltage of the driving transistor TD.

[0039] In the first stage, the first switching circuit 30 is turned off; in the second stage, both the first switching circuit 30 and the second switching circuit 40 are turned on; in the third stage, the first switching circuit 30 is turned off; and in the fourth stage, the first switching circuit 30 is turned on and the second switching circuit 40 is turned off.

[0040] Specifically, in the scheme of this application, in the first stage of each working cycle, the data writing circuit 10 needs to output a reference voltage, so that the reference voltage is applied to the self-discharge circuit 20. Specifically, it can be applied to the control terminal of the driving transistor TD in the self-discharge circuit 20, so that the driving transistor TD is turned on. The self-discharge circuit 20 can also be charged through the reference voltage, specifically by charging the relevant capacitors in the self-discharge circuit 20, depending on the specific structural design of the self-discharge circuit 20.

[0041] The specific configurations of the data writing circuit 10 and the self-discharge circuit 20 can be set and adjusted according to actual needs. However, it is understood that in order to achieve the functional requirements of the data writing circuit 10 and the self-discharge circuit 20 in this application, for example, in a specific embodiment of the present invention, please refer to... Figure 2 This is a schematic diagram of the pixel driving circuit provided in another specific embodiment of the present invention. Figure 2 In a specific implementation, the self-discharge circuit 20 specifically includes a third switching circuit 21, a first capacitor C1, a second capacitor C2, and a driving transistor TD.

[0042] The second end of the first capacitor C1 is connected to the control terminal of the driving transistor TD, and the connection terminal serves as the first terminal of the self-discharge circuit 20; the first end of the first capacitor C1 is connected to the second end of the second capacitor C2, the second end of the third switching circuit 21, and the first end of the driving transistor TD; the first end of the second capacitor C2 is connected to the first end of the third switching circuit 21, and the connection terminal is connected to the positive terminal of the first power supply; the second end of the driving transistor TD serves as the second terminal of the self-discharge circuit 20.

[0043] In the first stage, the third switch circuit 21 is turned on; in the second stage, the third switch circuit 21 is turned off; in the third stage, the third switch circuit 21 is turned off; and in the fourth stage, the third switch circuit 21 is turned on.

[0044] In this embodiment, the self-discharge circuit 20 is specifically composed of a third switching circuit 21, a first capacitor C1, a second capacitor C2, and a driving transistor TD. It has a simple structure and high reliability.

[0045] The third switching circuit 21 and the driving transistor TD can typically both be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), which have low power consumption, are easy to integrate, and are suitable for large-scale integrated circuits and applications requiring fast switching speeds.

[0046] For example in Figure 3In a specific embodiment, the third switching circuit 21 includes a third switching transistor Q3; the first terminal of the third switching transistor Q3 serves as the first terminal of the third switching circuit 21, and the second terminal of the third switching transistor Q3 serves as the second terminal of the third switching circuit 21. Furthermore, Figure 3 In the specific implementation, the third switch Q3 is a PMOS switch. Its source serves as the first terminal of the third switch circuit 21, its drain serves as the second terminal of the third switch circuit 21, and its gate is used for on / off control, that is, to determine the on / off state of the third switch circuit 21.

[0047] exist Figure 3 In a specific implementation, the driving transistor TD is a PMOS transistor, and the gate of the PMOS transistor serves as the control terminal of the driving transistor TD. Figure 3 The PMOS transistor is denoted as G, and its source is used as the first terminal of the driver transistor TD. Figure 3 The terminator is denoted as S, and the drain of this PMOS transistor serves as the second terminal of the driver transistor TD. Figure 3 It is written as D. Furthermore, Figure 2 and Figure 3 In this context, the positive terminal of the first power supply is specifically represented as VDD.

[0048] In one specific embodiment of the present invention, see [reference needed]. Figure 3 The data writing circuit 10 specifically includes the fourth switching transistor Q4;

[0049] The first terminal of the fourth switch Q4 serves as the input terminal of the data writing circuit 10, and the second terminal of the fourth switch Q4 serves as the output terminal of the data writing circuit 10.

[0050] In the first stage, the fourth switch Q4 is turned on and the input terminal of the data writing circuit 10 receives the reference voltage; in the second stage, the fourth switch Q4 is turned off; in the third stage, the fourth switch Q4 is turned on and the input terminal of the data writing circuit 10 receives the data voltage; and in the fourth stage, the fourth switch Q4 is turned off.

[0051] In this implementation, the data writing circuit 10 is implemented using a single switching transistor, resulting in a simple structure and high reliability. Similarly, as mentioned above, the fourth switching transistor Q4 can typically also be a MOSFET. Figure 3 In this specific implementation, the fourth switch Q4 is a PMOS transistor, with its source and drain serving as the first and second terminals, respectively, which are also the input and output terminals of the data writing circuit 10. Since this implementation uses a single switch to realize the data writing circuit 10, the on / off states of the fourth switch Q4 in each operating cycle are consistent with the on / off states of the data writing circuit 10 in each operating cycle.

[0052] The following is based on Figure 3 The implementation method is used as an example to explain the four stages in each work cycle.

[0053] The first stage in each working cycle is the initialization stage. As described above, the data writing circuit 10 needs to output a reference voltage to the control terminal of the driver transistor TD, i.e., the gate of the driver transistor TD, so that the driver transistor TD is turned on. Figure 3 In the specific implementation, in the first stage, the fourth switch Q4 is turned on, and the input terminal of the data writing circuit 10 receives a reference voltage. For example, the reference voltage received at the reference voltage terminal of the data writing circuit 10 is denoted as Vref. Since the third switch Q3 is turned on in the first stage, the reference voltage can be applied to the gate of the driving transistor TD, that is, to the lower plate of the first capacitor C1, while the first power supply VDD is applied to the upper plate of the first capacitor C1 through the third switch Q3. Therefore, in the first stage, if the voltage across the first capacitor C1 at this time is denoted as Vini, then Vini = VDD - Vref. Furthermore, it can be understood that the specific values ​​of the reference voltage Vref and the first power supply voltage VDD can be set and adjusted according to actual needs.

[0054] In the second phase of each work cycle, the data writing circuit 10 is turned off. Figure 3 In a specific implementation, the fourth switch Q4 is controlled to be in the off state in the second stage. It can be understood that in the second stage, the data writing circuit 10 does not need to use the reference voltage Vref or the data voltage Vdata. Therefore, in the second stage, the pixel driving circuit of this application does not occupy the input signal line of the data writing circuit 10.

[0055] In the second phase of each work cycle, the third switching circuit 21 is turned off. Figure 3 In a specific implementation, the third switch Q3 is controlled to be in the off state in the second stage. Furthermore, in the second stage of each working cycle, the self-discharge circuit 20 needs to discharge through the first switch circuit 30 and the second switch circuit 40, and the second stage ends when the gate-source voltage of the driving transistor TD reaches the set state. Therefore, in the second stage of each working cycle, both the first switch circuit 30 and the second switch circuit 40 need to be turned on.

[0056] Since this application requires on / off control of the first switching circuit 30 and the second switching circuit 40, and to ensure structural simplicity and reliability, both the first switching circuit 30 and the second switching circuit 40 can typically be implemented using switching transistors, for example in... Figure 3In the implementation manner, the first switch circuit 30 specifically includes a first switching transistor Q1; the first end of the first switching transistor Q1 serves as the first end of the first switch circuit 30, and the second end of the first switching transistor Q1 serves as the second end of the first switch circuit 30;

[0057] The second switch circuit 40 includes a second switching transistor Q2; the first end of the second switching transistor Q2 serves as the first end of the second switch circuit 40, and the second end of the second switching transistor Q2 serves as the second end of the second switch circuit 40.

[0058] And in Figure 3 the specific implementation manner, the first switching transistor Q1 is specifically a PMOS transistor, and its source and drain respectively serve as the first end and the second end of the first switching transistor Q1. The second switching transistor Q2 is specifically an NMOS transistor, and its source and drain respectively serve as the second end and the first end of the second switching transistor Q2. MOS transistors have advantages such as low power consumption and small size. In Figure 3 the second switching transistor Q2's first end is connected to the second end of the first switching transistor Q1, and the second end of the second switching transistor Q2 is connected to a preset voltage VAR. Through the respective gates of the first switching transistor Q1 and the second switching transistor Q2, the on-off states of the first switching transistor Q1 and the second switching transistor Q2 can be conveniently controlled.

[0059] In Figure 3 the implementation manner, in the second stage of each working cycle, the first capacitor C1 in the self-discharge circuit 20 is specifically discharged through the driving transistor TD, and the turned-on first switching transistor Q1 and second switching transistor Q2, such that the potential of the upper plate of the first capacitor C1 (that is, the potential of node S) starts to decrease from VDD. Affected by the body bias modulation effect, the effective threshold voltage of the driving transistor TD will start to increase.

[0060] The effective threshold voltage V TH0 ,

[0063] , TH0 ,

[0062] , TH_EF , ,

[0061] , , of the driving transistor TD can be expressed as:

[0061] |V TH_EF | = a × (VDD - VS) + |V TH0 |; in this formula, |V TH0 | is the threshold voltage not affected by the body bias modulation effect, the coefficient a is a coefficient related to the body bias modulation effect, and VS is the source potential of the driving transistor TD.

[0062] As the potential of the upper plate of the first capacitor C1 decreases, when the potential of the upper plate of the first capacitor C1 decreases to make the effective threshold voltage of the driving transistor TD equal to the voltage Vini stored on the first capacitor C1, the discharge ends, that is, the gate-source voltage of the driving transistor TD reaches the set state, and at this time the second stage ends.

[0063] Therefore, when the second stage ends, it satisfies Vini = a × (VDD - VS阶段2 )+|V TH0 |, where VS 阶段2 represents the source potential of the driving transistor TD at the end of the second stage, which is also the potential of the upper plate of the first capacitor C1. Therefore, at the end of the second stage, the potential VS of node S 阶段2 is:

[0064] VS 阶段2 = VDD - 1 / a (Vini - |V TH0 |). And the potential VG of node G 阶段2 is:

[0065] VG 阶段2 = VG 阶段1 - |ΔVS 阶段2 | = Vref - ΔVS 阶段2 . Here, VG 阶段1 represents the potential of node G at the end of the first stage, specifically Vref, and ΔVS 阶段2 represents the change amount of the potential of node S in the second stage.

[0066] It can be seen that at the end of the second stage, the potential of node S is related to the threshold voltage of the driving transistor TD. For this reason, in the subsequent fourth stage, when the light-emitting circuit 50 emits light, the current can be unaffected by the deviation of the threshold voltage of the driving transistor TD. The specific principle is described in the following analysis.

[0067] In the third stage of each working cycle, it is the data writing stage. The data writing circuit 10 outputs a data voltage to control the light-emitting brightness of the light-emitting circuit 50 in the fourth stage of this working cycle. And in the third stage, the first switching circuit 30 needs to be turned off. In Figure 3 a specific example, in the third stage, the first switching transistor Q1 and the third switching transistor Q3 are both turned off, and the fourth switching transistor Q4 is turned on. At this time, the data voltage output by the data writing circuit 10 is denoted as Vdata.

[0068] Since the first capacitor C1 and the second capacitor C2 are in series in the third stage, after the data voltage Vdata is divided by the series-connected first capacitor C1 and second capacitor C2, the potential of node S becomes:

[0069] VS 阶段3 = VDD + (1 - b) × (Vdata - Vref) - b × |ΔVS 阶段2 |.

[0070] VS 阶段3 represents the potential of node S at the end of the third stage, and b is the voltage division coefficient of the first capacitor C1 and the second capacitor C2, specifically expressed as b = C2 / (C1 + C2).

[0071] In addition, it should be noted that, as can be seen from the above description, the series connection of the first capacitor C1 and the second capacitor C2 plays a voltage dividing role in the third stage, which enables the improvement of the range broadening ability of the data voltage Vdata. That is, through the series connection of the first capacitor C1 and the second capacitor C2, the voltage of Vdata is divided, making the difference between the data voltage Vdata required for the maximum brightness (for example, the maximum brightness is 255 gray levels, corresponding to the maximum output current) and the minimum brightness (for example, the minimum brightness is 0 gray levels, corresponding to the minimum output current) larger. That is, the range of Vdata is large, making it easier to adjust the step between adjacent gray levels, thereby reducing the performance requirements for the driving circuit of the output data voltage Vdata.

[0072] In the fourth stage of each working cycle, it is the light emitting stage. The data writing circuit 10 is turned off, the first switching circuit 30 is turned on and the second switching circuit 40 is turned off. The self-discharge circuit 20 outputs current to the light emitting circuit 50, and the magnitude of the output current is not affected by the threshold voltage of the driving transistor TD. In Figure 2 the example of, specifically, the fourth switching transistor Q4 is turned off, the first switching transistor Q1 is turned on, the second switching transistor Q2 is turned off, and the third switching transistor Q3 is turned on. At this time, during the process that the potential of the node S becomes VDD, the voltage between the upper and lower plates of the first capacitor C1 remains unchanged, making the potential of the node G change accordingly to:

[0073] VG 阶段4 = (1 - b - b / a) × Vref + (b / a) × VDD + b × Vdata - (b / a) × 丨V TH0 丨.

[0074] Since the current flowing through the driving transistor TD can be expressed as .

[0075] Therefore, based on the foregoing expression, it can be known that:

[0076] .

[0077] The coefficient a is only related to the process and is a constant when the process is selected. Therefore, by setting a suitable self-discharge circuit 20, in Figure 3 the example of, specifically, by selecting a suitable ratio of the first capacitor C1 and the second capacitor C2, making the coefficient b = a, then 1 - b / a = 0. At this time, in the above current expression, the term related to the threshold voltage V TH0 is 0, which means that after applying the solution of the present application, in the fourth stage, the current generated by the driving transistor TD has nothing to do with the threshold voltage V TH0It is unrelated to the data voltage Vdata. Therefore, when establishing a pixel array using the pixel driving circuit of this application, the shift in the threshold voltage of different driving transistors TD caused by the process will not cause the output current I to shift. This makes the display product designed based on the pixel driving circuit of this application have good display uniformity and can obtain better display effect.

[0078] In one specific embodiment of the present invention, in the fourth stage, the third switching circuit 21 remains on, or the duty cycle of the on-time of the third switching circuit 21 meets the current first set value.

[0079] As described above, in the fourth stage, the current I flowing through the driving transistor TD is controlled by the data voltage Vdata. This implementation further considers that, in addition to controlling the current I via Vdata, the magnitude of the current I can also be controlled by controlling the duty cycle of the third switching circuit 21, thereby achieving brightness control of the light-emitting circuit 50. In this implementation, in the fourth stage, the third switching circuit 21 can remain on continuously, or it can be set to have its duty cycle equal to the current first set value, improving the brightness control flexibility of this application. Furthermore, in some cases, the light-emitting circuit 50 can allow a large current to flow for a short period to achieve high brightness, but it does not support a large current flowing for a long time. Therefore, this implementation can also be used, where the first set value allows the third switching circuit 21 to achieve a suitable on-time value in the fourth stage, achieving the desired light-emitting effect.

[0080] The specific circuit configuration of the light-emitting circuit 50 can be set and adjusted according to actual needs, for example, in Figure 3 In the implementation method, the light-emitting circuit 50 is specifically a light-emitting diode D1, which realizes the light-emitting function. For example, the light-emitting diode D1 can be an OLED light-emitting diode D1.

[0081] In one specific embodiment of the present invention, the second switching circuit 40 is turned on in the first stage and / or the third stage.

[0082] In the fourth stage, since the light-emitting circuit 50 needs to emit light, the second switching circuit 40 needs to be turned off. In the second stage, since the self-discharge circuit 20 needs to discharge through the conducting first switching circuit 30 and second switching circuit 40, the second switching circuit 40 also needs to be turned off.

[0083] In the first and third stages, since the present application includes a first switching circuit 30 which is turned off in both stages, no through-current is generated in the first and third stages. However, this embodiment further considers that in some cases, due to device quality or other reasons, current still flows to the light-emitting circuit 50 in the first or third stage. In this embodiment, turning on the second switching circuit 40 in the first and / or third stages can prevent excessive black-state current in the light-emitting circuit 50, which is beneficial for further improving contrast. Figure 3 The voltage connected to the second terminal of the second switching transistor Q2 is denoted as VAR. Its specific value can be set as needed, but it is usually a relatively low voltage value.

[0084] In one specific embodiment of the present invention, in the fourth stage, the first switching circuit 30 remains on, or the duty cycle of the first switching circuit 30 meets the current second set value.

[0085] Similarly, this embodiment further considers that, in addition to controlling the current I through Vdata, the magnitude of I can also be controlled by controlling the duty cycle of the first switching circuit 30, thereby achieving brightness control of the light-emitting circuit 50. In this embodiment, in the fourth stage, the first switching circuit 30 can remain on continuously, or it can be set to have its duty cycle equal to the current second set value, thus improving the brightness control flexibility of this application.

[0086] By applying the technical solution provided in this embodiment of the invention, the self-discharge circuit 20 in the pixel driving circuit enables the pixel driving circuit to compensate for the threshold voltage of the driving transistor TD. Therefore, when the light-emitting circuit 50 emits light in the fourth stage, the current is not affected by the threshold voltage deviation of the driving transistor TD, which is beneficial for achieving uniformity in the pixel array display. Specifically, the output terminal of the data writing circuit 10 is connected to the first terminal of the self-discharge circuit 20, the second terminal of the self-discharge circuit 20 is connected to the first terminal of the first switching circuit 30, and the second terminal of the first switching circuit 30 is connected to both the second switching circuit 40 and the light-emitting circuit 50. In the first stage of each working cycle, the first switching circuit 30 is turned off, and the data writing circuit 10 outputs a reference voltage, causing the driving transistor TD in the self-discharge circuit 20 to conduct. In the second stage, the data writing circuit 10 is turned off, and both the first switching circuit 30 and the second switching circuit 40 are turned on. At this time, the self-discharge circuit 20 discharges through the turned-on first switching circuit 30 and second switching circuit 40, and ends the second stage when the gate-source voltage of the driving transistor TD reaches the set state. This ensures that in the fourth stage, the output current of the self-discharge circuit 20 is not affected by the threshold voltage of the driving transistor TD. In the third stage, the first switching circuit 30 is turned off, and the data writing circuit 10 outputs a data voltage, thereby controlling the brightness of the light-emitting circuit 50 in this working cycle in the fourth stage. In the fourth stage, the first switching circuit 30 is turned on and the second switching circuit 40 is turned off. At this time, the current generated by the driving transistor TD is independent of its threshold voltage, which means that when the light-emitting circuit 50 emits light in the fourth stage, the current is not affected by the threshold voltage deviation of the driving transistor TD, which is beneficial to achieving the display uniformity of the pixel array. Furthermore, in this application, the pixel driving circuit includes a data writing circuit 10, a self-discharge circuit 20, a first switching circuit 30, a second switching circuit 40, and a light-emitting circuit 50. Its structure is simple and highly reliable, which is beneficial for miniaturizing the pixel driving circuit. In addition, in this application, because the first switching circuit 30 is provided and is turned off in both the first and third stages, no through-current is generated in the first and third stages, which also helps to ensure the quality of the displayed image.

[0087] Corresponding to the above embodiments of the pixel driving circuit, this embodiment of the invention also provides a display device that may include the pixel driving circuit as described in any of the above embodiments. Reference can be made in conjunction with the description above.

[0088] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0089] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention. Specific examples have been used in this application to illustrate the principles and implementation methods of the invention. The description of the above embodiments is only for the purpose of helping to understand the technical solution and core ideas of the invention. It should be noted that those skilled in the art can make several improvements and modifications to the invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the invention.

Claims

1. A pixel driving circuit, characterized in that, include: The circuit includes a data writing circuit, a self-discharge circuit, a first switching circuit, a second switching circuit, and a light-emitting circuit. The output terminal of the data writing circuit is connected to the first terminal of the self-discharge circuit, the second terminal of the self-discharge circuit is connected to the first terminal of the first switching circuit, and the second terminal of the first switching circuit is connected to the second switching circuit and the light-emitting circuit respectively. The data writing circuit is used to: output a reference voltage in the first stage of each working cycle to turn on the driving tube in the self-discharge circuit; turn off in the second and fourth stages of each working cycle; and output a data voltage in the third stage of each working cycle to control the light emission brightness of the light-emitting circuit in the fourth stage of the current working cycle. The self-discharge circuit is used to: charge through the reference voltage in the first stage, discharge through the first and second switching circuits in the second stage, and end the second stage when the gate-source voltage of the driving transistor reaches a set state, so that in the fourth stage, the output current of the self-discharge circuit is not affected by the threshold voltage of the driving transistor. In the first stage, the first switching circuit is turned off; in the second stage, both the first and second switching circuits are turned on; in the third stage, the first switching circuit is turned off; and in the fourth stage, the first switching circuit is turned on and the second switching circuit is turned off.

2. The pixel driving circuit according to claim 1, characterized in that, The self-discharge circuit includes a third switching circuit, a first capacitor, a second capacitor, and a driving transistor. The second terminal of the first capacitor is connected to the control terminal of the driving transistor, and the connection terminal serves as the first terminal of the self-discharge circuit; the first terminal of the first capacitor is connected to the second terminal of the second capacitor, the second terminal of the third switching circuit, and the first terminal of the driving transistor; the first terminal of the second capacitor is connected to the first terminal of the third switching circuit, and the connection terminal is connected to the positive terminal of the first power supply; the second terminal of the driving transistor serves as the second terminal of the self-discharge circuit. In the first stage, the third switch circuit is turned on; in the second stage, the third switch circuit is turned off; in the third stage, the third switch circuit is turned off; and in the fourth stage, the third switch circuit is turned on.

3. The pixel driving circuit according to claim 2, characterized in that, The third switching circuit includes a third switching transistor; The first terminal of the third switching transistor serves as the first terminal of the third switching circuit, and the second terminal of the third switching transistor serves as the second terminal of the third switching circuit.

4. The pixel driving circuit according to claim 2, characterized in that, The driving transistor is a PMOS transistor, with the gate of the PMOS transistor serving as the control terminal, the source of the PMOS transistor serving as the first terminal, and the drain of the PMOS transistor serving as the second terminal.

5. The pixel driving circuit according to claim 2, characterized in that, In the fourth stage, the third switching circuit remains on, or the duty cycle of the third switching circuit's on-time meets the current first set value.

6. The pixel driving circuit according to claim 1, characterized in that, The data writing circuit includes a fourth switching transistor; The first terminal of the fourth switch is used as the input terminal of the data writing circuit, and the second terminal of the fourth switch is used as the output terminal of the data writing circuit. In the first stage, the fourth switch is turned on and the input terminal of the data writing circuit receives a reference voltage; in the second stage, the fourth switch is turned off; in the third stage, the fourth switch is turned on and the input terminal of the data writing circuit receives a data voltage; and in the fourth stage, the fourth switch is turned off.

7. The pixel driving circuit according to claim 1, characterized in that, The first switching circuit includes a first switching transistor; The first terminal of the first switching transistor serves as the first terminal of the first switching circuit, and the second terminal of the first switching transistor serves as the second terminal of the first switching circuit. The second switching circuit includes a second switching transistor; The first terminal of the second switching transistor serves as the first terminal of the second switching circuit, and the second terminal of the second switching transistor serves as the second terminal of the second switching circuit.

8. The pixel driving circuit according to claim 1, characterized in that, In the first stage and / or the third stage, the second switching circuit is turned on.

9. The pixel driving circuit according to any one of claims 1 to 8, characterized in that, In the fourth stage, the first switching circuit remains on, or the duty cycle of the first switching circuit's on-time meets the current second set value.

10. A display device, characterized in that, include: The pixel driving circuit as described in any one of claims 1 to 9.

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