Display device including drive transistor

Abstract

The display device includes: a display panel; a first transistor that switches according to the voltage of a second node and is connected to the first node and a third node; a second transistor that switches according to a scan 1 signal and is connected to the second node and the third node; a third transistor that switches according to a scan 2 signal and is connected to the first node; a fourth transistor that switches according to a light emission signal and is connected to the first node; a fifth transistor that switches according to a light emission signal and is connected to the third node and the fourth node; a sixth transistor that switches according to a scan 4 signal and is connected to the second node; a seventh transistor that switches according to a scan 3 signal and is connected to the fourth node; an eighth transistor that switches according to a scan 3 signal and is connected to the first node; and a light-emitting diode connected to the fourth node.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0188625, filed on December 17, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to display devices. Background Technology

[0004] Recently, various flat panel display devices, such as liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), and field emission displays (FEDs), with excellent characteristics of thin profiles, light weight, and low power consumption have been developed and applied in various fields. Summary of the Invention

[0005] In one aspect of this disclosure, a display device includes: a display panel comprising a display area having a plurality of sub-pixels and a non-display area at the periphery of the display area; a first transistor in each of the plurality of sub-pixels, the first transistor being switched according to a voltage of a second node and connected to a first node and a third node; a second transistor in each of the plurality of sub-pixels, the second transistor being switched according to a scan 1 signal and connected to a second node and a third node, and the second transistor having a dual-gate type; a third transistor in each of the plurality of sub-pixels, the third transistor being switched according to one of an odd scan 2 signal and an even scan 2 signal and connected to a data signal and a first node; and a fourth transistor in each of the plurality of sub-pixels, the fourth transistor being switched according to a voltage of a second node and connected to a third node. The light signal is switched and connected to the high-level signal and the first node; the fifth transistor in each of the plurality of sub-pixels is switched according to the light emission signal and connected to the third node and the fourth node; the sixth transistor in each of the plurality of sub-pixels is switched according to the scan 4 signal and connected to the initial signal and the second node; the seventh transistor in each of the plurality of sub-pixels is switched according to the scan 3 signal and connected to the anode reset signal and the fourth node; the eighth transistor in each of the plurality of sub-pixels is switched according to the scan 3 signal and connected to the stress signal and the first node; and the light-emitting diode in each of the plurality of sub-pixels is connected to the low-level signal and the fourth node.

[0006] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0007] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0008] In the attached diagram:

[0009] Figure 1 This is a view showing a display device according to a first embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating a first gate driving unit, a second gate driving unit, and a display panel of a display device according to a first embodiment of the present disclosure.

[0011] Figure 3 This is a circuit diagram showing a sub-pixel of a display device according to a first embodiment of the present disclosure.

[0012] Figure 4 This is a cross-sectional view showing the sub-pixels of the display panel of a display device according to a first embodiment of the present disclosure.

[0013] Figure 5 This is a plan view showing the first transistor, the second transistor, and the sixth transistor of a display device according to a first embodiment of the present disclosure.

[0014] Figure 6 It is along Figure 5 The cross-sectional view taken from line VI-VI.

[0015] Figure 7 This is a view showing a frame of multiple signals of a display device according to a first embodiment of the present disclosure.

[0016] Figure 8A This is a view showing the second node voltage of a display device according to a comparison example.

[0017] Figure 8B This is a view showing the second node voltage of a display device according to a first embodiment of the present disclosure.

[0018] Figure 9 This is a circuit diagram showing a sub-pixel of a display device according to a second embodiment of the present disclosure.

[0019] Figure 10 This is a view showing the first gate driving unit and the display panel of a display device according to a second embodiment of the present disclosure.

[0020] Figure 11This is a cross-sectional view showing the output line and carry line of the first gate driving unit of a display device according to a second embodiment of the present disclosure.

[0021] Figure 12 This is a view showing the scan 1 signal and scan 2 signal of the display device according to the second embodiment of the present disclosure.

[0022] Figure 13 This is a view showing the sub-pixels of a display device according to a third embodiment of the present disclosure.

[0023] Figure 14 This is a plan view showing the first transistor, the second transistor, and the sixth transistor of a display device according to a third embodiment of the present disclosure.

[0024] Figure 15 It is along Figure 14 A cross-sectional view taken from line XV-XV.

[0025] Figure 16 It is along Figure 14 A cross-sectional view taken from line XVI-XVI. Detailed Implementation

[0026] Display devices typically include a display panel for displaying images and a driving unit for supplying signals and power to the display panel. The driving unit includes a gate driving unit and a data driving unit that supply gate voltage and data voltage to each pixel of the display panel, respectively.

[0027] Display devices can display images by compensating for the threshold voltage of the driving transistor for each sub-pixel. However, due to the mobility difference between the transistor used to detect the threshold voltage and the driving transistor, the measured threshold voltage may vary within the display device, potentially causing problems. Therefore, degradation such as localized brightness deviations may occur.

[0028] Embodiments of this disclosure may provide a display device in which the gate electrodes of the driving transistors are charged to the same voltage, regardless of the mobility deviation of the sampling transistors.

[0029] In some embodiments, a display device is provided in which degradation such as local brightness deviation can be mitigated and display quality can be improved. This improvement can be achieved by reducing the difference in the measured threshold voltages by decreasing the width of the initialization period and charging the gate electrodes of the driving transistors to the same voltage, regardless of the mobility deviation of the sampling transistors.

[0030] Furthermore, embodiments of this disclosure can provide a display device in which degradation such as local brightness deviation can be mitigated, and low power drive can be achieved by reducing the difference in the measured threshold voltages through forming a coupling capacitor between the scan 1 signal and the scan 2 signal and increasing the on-state current of the sampling transistor.

[0031] Further features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained through the written description and its claims, as well as the structures particularly pointed out in the accompanying drawings.

[0032] The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary aspects described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of this disclosure. Furthermore, this disclosure is limited only by the scope of the claims.

[0033] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe various exemplary aspects of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise stated, similar reference numerals refer to similar elements throughout the specification.

[0034] In the following description, where a detailed description of a known function or configuration may unnecessarily obscure a feature or aspect of this disclosure, such a detailed description may be omitted or a brief description may be provided.

[0035] When using terms such as “including,” “having,” “comprising,” etc., one or more additional elements may be added unless a term such as “only” is used. Unless the context clearly indicates otherwise, elements described in the singular are intended to include multiple elements, and vice versa.

[0036] When interpreting a component, even if no explicit description of the error or tolerance range is provided, the component should be interpreted as including such error or tolerance range.

[0037] When describing positional relationships, such as using terms like "on," "above," "below," "over," "below," "next to," or "adjacent" to describe the positional relationship between two components, one or more other components may be located between the two components unless more restrictive terms such as "immediately," "directly," or "nearly" are used. For example, if an element or layer is set "on" another element or layer, a third layer or element may be inserted between them.

[0038] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to refer to various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] The term "at least one" should be understood to include all combinations of one or more of the relevant elements. For example, the term "at least one of the first element, the second element, and the third element" can include all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0040] The term "display device" can include, in a narrow sense, display devices such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot (QD) modules, which include a display panel and driving units for driving the display panel. Additionally, the term "display device" can include: complete products (or end products) including LCMs, OLED modules, and QD modules, such as notebook computers, televisions, computer monitors, device display devices including automotive displays, or other industrial or consumer display devices, as well as assemblies of electronic equipment or assemblies (or complete sets of equipment) such as smartphones or tablets.

[0041] Therefore, the display device of this disclosure may include: application products or complete sets of end-user devices including LCM, OLED modules and QD modules, as well as display devices in the narrow sense such as LCM, OLED modules and QD modules.

[0042] Depending on the context, an LCM, OLED, and QD module having a display panel and driving unit can be described as a "display device," and an electronic device comprising a complete product including an LCM, OLED, and QD module can be described as an "assembly." For example, a display device in a narrow sense can include a liquid crystal, organic light-emitting diode, and quantum dot display panel and a source printed circuit board (PCB) for a control unit to drive the display panel, and an assembly can also include an assembly PCB electrically connected to an assembly control unit for controlling the entire assembly.

[0043] The display panel described in this disclosure can include all types of display panels, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, quantum dot display panels, and electroluminescent display panels. The display panel described in this disclosure is not limited to a specific display panel having a curved frame with a flexible substrate for an OLED display panel and a lower backplate support. The shape or size of the display panel used in the display device described in this disclosure is not limited thereto.

[0044] For example, when the display panel is an organic light-emitting diode (OLED) display panel, the display panel may include multiple gate lines, multiple data lines, and sub-pixels in the intersection regions of the multiple gate lines and multiple data lines. The display panel may include: an array of thin-film transistors having elements for selectively applying voltage to each sub-pixel; a light-emitting element layer on the array; and a packaging substrate or package covering the light-emitting element layer. The package can protect the thin-film transistors and the light-emitting element layer from external impacts and can prevent or at least reduce the penetration of moisture or oxygen into the light-emitting element layer. Additionally, the light-emitting element layer on the array may include an inorganic light-emitting layer, such as a nanoscale material layer or quantum dots.

[0045] The thin-film transistors disclosed herein may include one of oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, and low-temperature polycrystalline silicon thin-film transistors.

[0046] Features of the various embodiments of this disclosure may be coupled or combined with each other, either partially or completely. They may be technically linked and operated in a variety of ways that will be fully understood by those skilled in the art. These aspects may be implemented independently or in various combinations in association with each other.

[0047] In the following, various exemplary embodiments of a display device according to the present disclosure will be described in detail with reference to the accompanying drawings, wherein the effect on the oxide semiconductor layer of the thin-film transistor of the driving element is reduced by shielding light emitted and transmitted from the sub-pixels and / or light input from the outside.

[0048] Figure 1This is a view illustrating a display device according to a first embodiment of the present disclosure. While the display device may be an organic light-emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device.

[0049] exist Figure 1 In the first embodiment of the present disclosure, the display device 110 includes a timing control unit 120 (e.g., a circuit), a data driving unit 122 (e.g., a circuit), a first gate driving unit 124 and a second gate driving unit 126 (e.g., a circuit), and a display panel 128.

[0050] The timing control unit 120 uses an image signal IS and multiple timing signals to generate image data RGB, a data control signal DCS, and a gate control signal GCS. The multiple timing signals include a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY, and a clock signal CLK sent from an external system such as a graphics card or a television system.

[0051] The timing control unit 120 sends the image data RGB and the data control signal DCS to the data driving unit 122, and sends the gate control signal GCS to the first gate driving unit 124 and the second gate driving unit 126.

[0052] The data driving unit 122 uses the image data RGB and data control signal DCS sent from the timing control unit 120 to generate ( Figure 3 The data signal (data voltage) Vda is applied to the data line DL of the display panel 128.

[0053] The first gate driving unit 124 and the second gate driving unit 126 use the gate control signal GCS sent from the timing control unit 120 to generate ( Figure 3 The gate signals (gate voltages) Sc1(n), Sc2o(n), Sc2e(n), Sc3(n), Sc4(n) and Em(n) are applied to the gate line GL of the display panel 128.

[0054] The first gate driving unit 124 and the second gate driving unit 126 may have an in-panel gate (GIP) type to be formed in the non-display area NDA, and the substrate has a display panel 128 with gate lines GL, data lines DL and pixels P.

[0055] Although Figure 1In the first embodiment, the first gate driving unit 124 and the second gate driving unit 126 are disposed on two sides of the display panel 128, but in another embodiment, a single gate driving unit may be disposed on one side of the display panel 128.

[0056] Display panel 128 includes a display area DA at its central portion and a non-display area NDA surrounding the display area DA. Display panel 128 displays images using gate signals Sc1(n), Sc2o(n), Sc2e(n), Sc3(n), Sc4(n), and Em(n) and a data signal Vda. For displaying images, display panel 128 includes multiple pixels P, multiple gate lines GL, and multiple data lines DL in the display area DA.

[0057] Each of the plurality of pixels P includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. A gate line GL and a data line DL intersect each other to define the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4, and each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 is connected to the gate line GL and the data line DL.

[0058] For example, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can correspond to red, green, blue, and white, respectively.

[0059] Although Figure 1 In a first embodiment, a pixel P exemplarily includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. However, in another embodiment, a pixel P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 corresponding to red, green, and blue, respectively.

[0060] When the display device 110 is an organic light-emitting diode (OLED) display device, each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may include multiple transistors (e.g., switching transistors, driving transistors, and sampling transistors), a storage capacitor, and a light-emitting diode.

[0061] The structure of the display panel 128 and sub-pixels SP1 to SP4 of the display device 110 will be described with reference to the accompanying drawings.

[0062] Figure 2 This is a block diagram illustrating a first gate driving unit, a second gate driving unit, and a display panel of a display device according to a first embodiment of the present disclosure. Figure 3This is a circuit diagram showing a sub-pixel of a display device according to a first embodiment of the present disclosure.

[0063] exist Figure 2 In the first embodiment of the display device 110 according to the present disclosure, the first gate driving unit 124 includes one scanning block Bsc1, two odd-scanning blocks Bsc2o, two even-scanning blocks Bsc2e, and three scanning blocks Bsc3. The second gate driving unit 126 of the display device 110 according to the first embodiment of the present disclosure includes two odd-scanning blocks Bsc2o, two even-scanning blocks Bsc2e, four scanning blocks Bsc4, and a light-emitting block Bem. The display area DA of the display panel 128 is disposed between the first gate driving unit 124 and the second gate driving unit 126.

[0064] In another embodiment, the arrangement structure of scanning block Bsc1, odd-numbered scanning block Bsc2o, even-numbered scanning block Bsc2e, scanning block Bsc3, scanning block Bsc4, and light-emitting block Bem in the first gate driving unit 124 and the second gate driving unit 126 can be changed differently.

[0065] For example, in Figure 2 In a first embodiment, scanning block 1 (Bsc1) can be configured to be further away from the center of the display panel 128 than scanning block 3 (Bsc3), and scanning block 4 (Bsc4) can be configured to be further away from the center of the display panel 128 than scanning block Bem. In another embodiment, scanning block 3 (Bsc3) can be configured to be further away from the center of the display panel 128 than scanning block 1 (Bsc1), and scanning block Bem can be configured to be further away from the center of the display panel 128 than scanning block 4 (Bsc4).

[0066] The first gate driving unit 124, including scanning block Bsc1, odd-numbered scanning block Bsc2o, even-numbered scanning block Bsc2e, and scanning block Bsc3, and the second gate driving unit 126, including odd-numbered scanning block Bsc2o, even-numbered scanning block Bsc2e, scanning block Bsc4, and light-emitting block Bem, can be a level of a shift register, and the shift register can include multiple levels connected to each other in a cascaded manner.

[0067] In the first gate driving unit 124, scanning one Bsc1 block, odd-numbered scanning two Bsc2o blocks, even-numbered scanning two Bsc2e blocks, and scanning three Bsc3 blocks respectively generate ( Figure 3 (of) scan 1 signal Sc1(n), ( Figure 3 (of) odd-numbered scan 2 signals Sc2o(n), ( Figure 3 (of) even-numbered scan 2 signals Sc2e(n) and ( Figure 3 The scan signal Sc3(n) is scanned.

[0068] In the second gate driving unit 126, odd-numbered scans of 2 Bsc2o blocks, even-numbered scans of 2 Bsc2e blocks, scans of 4 Bsc4 blocks, and the light-emitting block Bem respectively generate ( Figure 3 (of) odd-numbered scan 2 signals Sc2o(n), ( Figure 3 (of) even-numbered scan 2 signals Sc2e(n), ( Figure 3 The scan signal Sc4(n) and ( Figure 3 The luminous signal Em(n).

[0069] The scan 1 signal Sc1(n) of scan block Bsc1 is supplied through gate line GL to each sub-pixel SP1 to SP4 of the odd-numbered and even-numbered horizontal pixel lines of the display area DA. Figure 3 The second transistor T2. The odd scan 2 signal Sc2o(n) of the odd scan 2 block Bsc2o is supplied through the gate line GL to each sub-pixel SP1 to SP4 of the odd horizontal pixel line of the display area DA. Figure 3 The third transistor T3, and the even scan 2 signal Sc2e(n) of the even scan 2 blocks Bsc2e are supplied through the gate line GL to the third transistor T3 in each sub-pixel SP1 to SP4 of the even horizontal pixel line of the display area DA.

[0070] The scan 3 signal Sc3(n) of the three scan blocks Bsc3 is supplied through the gate line GL to each sub-pixel SP1 to SP4 of the odd-numbered and even-numbered horizontal pixel lines of the display area DA. Figure 3 The seventh transistor T7 and the eighth transistor T8, and the scan 4 signal Sc4(n) of the four blocks Bsc4 are supplied through the gate line GL to each sub-pixel SP1 to SP4 of the odd-numbered and even-numbered horizontal pixel lines of the display area DA. Figure 3 The sixth transistor T6. The light-emitting signal Em(n) of the light-emitting block Bem is supplied through the gate line GL to each sub-pixel SP1 to SP4 of the odd-numbered and even-numbered horizontal pixel lines of the display area DA. Figure 3 (The fourth transistor T4 and the fifth transistor T5.)

[0071] In another embodiment, the first gate driving unit 124 and the second gate driving unit 126 may have a symmetrical structure. For example, each of the first gate driving unit 124 and the second gate driving unit 126 may include scanning one block Bsc1, scanning two blocks Bsc2o in odd numbers, scanning two blocks Bsc2e in even numbers, scanning three blocks Bsc3, scanning four blocks Bsc4, and a light-emitting block Bem.

[0072] exist Figure 3In the first embodiment of the display device 110 according to the present disclosure, each of the first sub-pixels SP1 to the fourth sub-pixels SP4 of the display panel 128 includes a first transistor T1 to an eighth transistor T8, a storage capacitor Cs, and a light-emitting diode De. At least one of the first transistors T1 to the eighth transistor T8 may be an oxide semiconductor thin-film transistor, and the other transistors of the first transistors T1 to the eighth transistor T8 may be low-temperature polycrystalline silicon thin-film transistors.

[0073] For example, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 can be p-type low-temperature polycrystalline silicon thin-film transistors, and the second transistor T2 and the sixth transistor T6 can be n-type oxide semiconductor thin-film transistors.

[0074] Furthermore, the second transistor T2 and the sixth transistor T6 can be dual-gate transistors. As described herein, a dual-gate transistor refers to a transistor having two gate electrodes located on opposite sides of a semiconductor layer (one on top and one on the bottom), the two gate electrodes being electrically connected to and driven by the same control signal.

[0075] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first capacitor electrode of the storage capacitor Cs. The gate electrode of the first transistor T1 is connected to the second node N2, the source electrode of the first transistor T1 is connected to the first node N1, and the drain electrode of the first transistor T1 is connected to the third node N3.

[0076] The second transistor T2, which serves as the sampling transistor, is switched according to the scan 1 signal Sc1(n). The gate electrodes (top gate electrode and bottom gate electrode) of the second transistor T2 are connected to the scan 1 signal Sc1(n), the source electrode of the second transistor T2 is connected to the third node N3, and the drain electrode of the second transistor T2 is connected to the second node N2.

[0077] The third transistor T3, acting as a switching transistor, is switched according to either the odd-scan 2 signal Sc2o(n) or the even-scan 2 signal Sc2e(n). The gate electrode of the third transistor T3 is connected to either the odd-scan 2 signal Sc2o(n) or the even-scan 2 signal Sc2e(n), the source electrode of the third transistor T3 is connected to the first node N1, and the drain electrode of the third transistor T3 is connected to the data signal Vda.

[0078] The fourth transistor T4, which acts as a light-emitting transistor, switches according to the light-emitting signal Em(n). The gate electrode of the fourth transistor T4 is connected to the light-emitting signal Em(n), the source electrode of the fourth transistor T4 is connected to the second capacitor electrode of the storage capacitor Cs and the high-level signal Vdd, and the drain electrode of the fourth transistor T4 is connected to the first node N1.

[0079] The fifth transistor T5, which is a light-emitting transistor, is switched according to the light-emitting signal Em(n). The gate electrode of the fifth transistor T5 is connected to the light-emitting signal Em(n), the source electrode of the fifth transistor T5 is connected to the third node N3, and the drain electrode of the fifth transistor T5 is connected to the fourth node N4.

[0080] The sixth transistor T6, which serves as the initialization transistor, is switched according to the scan 4 signal Sc4(n). The gate electrode (top and bottom electrode) of the sixth transistor T6 is connected to the scan 4 signal Sc4(n), the source electrode of the sixth transistor T6 is connected to the initial signal (initial voltage) Vin (e.g., about -5 V), and the drain electrode of the sixth transistor T6 is connected to the second node N2.

[0081] The seventh transistor T7, which acts as a reset transistor, is switched according to the scan 3 signal Sc3(n). The gate electrode of the seventh transistor T7 is connected to the scan 3 signal Sc3(n), the source electrode of the seventh transistor T7 is connected to the fourth node N4, and the drain electrode of the seventh transistor T7 is connected to the anode reset signal (anode reset voltage) Var.

[0082] The eighth transistor T8, which acts as a reset transistor, is switched according to the scan 3 signal Sc3(n). The gate electrode of the eighth transistor T8 is connected to the scan 3 signal Sc3(n), the source electrode of the eighth transistor T8 is connected to the first node N1, and the drain electrode of the eighth transistor T8 is connected to the stress signal (stress voltage) Vobs.

[0083] The storage capacitor Cs stores the data signal Vda and the threshold voltage Vth. The first capacitor electrode of the storage capacitor Cs is connected to the second node N2, and the second capacitor electrode of the storage capacitor Cs is connected to the high-level signal Vdd and the source electrode of the fourth transistor T4.

[0084] LED De is connected between the fourth node N4 and the low-level signal Vss to emit light with a brightness proportional to the current of the first transistor T1. The anode of LED De is connected to the fourth node N4, and the cathode of LED De is connected to the low-level signal Vss.

[0085] The source electrode of the first transistor T1, the source electrode of the third transistor T3, the drain electrode of the fourth transistor T4, and the source electrode of the eighth transistor T8 constitute the first node N1. The gate electrode of the first transistor T1, the drain electrode of the second transistor T2, the first capacitor electrode of the storage capacitor Cs, and the drain electrode of the sixth transistor T6 constitute the second node N2. The drain electrode of the first transistor T1, the source electrode of the second transistor T2, and the source electrode of the fifth transistor T5 constitute the third node N3. The drain electrode of the fifth transistor T5, the source electrode of the seventh transistor T7, and the anode of the light-emitting diode De constitute the fourth node N4.

[0086] The cross-sectional structure of each sub-pixel SP1 to SP4 of the display panel 128 of the display device 110 will be described with reference to the accompanying drawings.

[0087] Figure 4 This is a cross-sectional view showing the sub-pixels of the display panel of a display device according to a first embodiment of the present disclosure.

[0088] exist Figure 4 In the first sub-pixel SP1 to the fourth sub-pixel SP4, a first light-shielding pattern 132 is provided on the substrate 130, and a first buffer layer 134 is provided on the first light-shielding pattern 132 over the entire substrate 130.

[0089] The first light-shielding pattern 132 can block light incident from the lower part of the substrate 130. For example, the first light-shielding pattern 132 can have a single layer or multiple layers of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0090] The first buffer layer 134 can block moisture or oxygen from penetrating from the outside. For example, the first buffer layer 134 can be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0091] A first semiconductor layer 136 is disposed on the first buffer layer 134 corresponding to the first light-shielding pattern 132, and a first gate insulating layer 138 is disposed on the first semiconductor layer 136 over the entire substrate 130.

[0092] The first semiconductor layer 136 includes an undoped first channel region 136a at its central portion and doped first source regions 136b and first drain regions 136c at two sides of the first channel region 136a. For example, the first semiconductor layer 136 may include a polycrystalline semiconductor material such as polycrystalline silicon.

[0093] For example, the first gate insulating layer 138 may be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0094] A first gate electrode 140 is disposed on the first gate insulating layer 138 corresponding to the first channel region 136a of the first semiconductor layer 136, and a first capacitor electrode 142, separate from the first gate electrode 140, is disposed on the first gate insulating layer 138. A first interlayer insulating layer 144 is disposed over the entire substrate 130 on the first gate electrode 140 and the first capacitor electrode 142.

[0095] The first gate electrode 140 and the first capacitor electrode 142 may have the same layers and the same materials. For example, the first gate electrode 140 and the first capacitor electrode 142 may have a single layer or multiple layers of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0096] For example, the first interlayer insulation layer 144 may be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0097] A second capacitor electrode 146 is disposed on the first interlayer insulating layer 144 corresponding to the first capacitor electrode 142, and a second light-shielding pattern 148 separate from the second capacitor electrode 146 is disposed on the first interlayer insulating layer 144. A second buffer layer 150 is disposed over the entire substrate 130 on the second capacitor electrode 146 and the second light-shielding pattern 148.

[0098] The second capacitor electrode 146 and the second light-shielding pattern 148 may have the same layers and the same materials. For example, the second capacitor electrode 146 and the second light-shielding pattern 148 may have a single layer or multiple layers of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0099] The first capacitor electrode 142, the first interlayer insulating layer 144, and the second capacitor electrode 146 can constitute a storage capacitor Cst.

[0100] The second buffer layer 150 can block moisture or oxygen from penetrating from the outside. For example, the second buffer layer 150 can be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0101] A second semiconductor layer 152 is disposed on the second buffer layer 150 corresponding to the second light-shielding pattern 148, and a second gate insulating layer 154 is disposed on the second semiconductor layer 152 over the entire substrate 130.

[0102] The second semiconductor layer 152 includes a non-conductive second channel region 152a at its central portion and conductive second source regions 152b and second drain regions 152c at two sides of the second channel region 152a. For example, the second semiconductor layer 152 may include an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0103] For example, the second gate insulating layer 154 may be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0104] A second gate electrode 156 is disposed on the second gate insulating layer 154 corresponding to the second channel region 152a of the second semiconductor layer 152, and a second interlayer insulating layer 158 is disposed on the second gate electrode 156 over the entire substrate 130.

[0105] For example, the second gate electrode 156 may have a single layer or multiple layers of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0106] For example, the second interlayer insulation layer 158 may be a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx).

[0107] A first source electrode 160, a first drain electrode 162, a second source electrode 164, and a second drain electrode 166 spaced apart from each other are disposed on the second interlayer insulating layer 158, and a first planarization layer 168 is disposed on the first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 over the entire substrate 130.

[0108] The first source electrode 160 and the first drain electrode 162 are connected to the first source region 136b and the first drain region 136c of the first semiconductor layer 136 through contact holes in the second interlayer insulating layer 158, the second gate insulating layer 154, the second buffer layer 150, the first interlayer insulating layer 144, and the first gate insulating layer 138, respectively. The first source electrode 160 is connected to the second capacitor electrode 146 through contact holes in the second interlayer insulating layer 158, the second gate insulating layer 154, and the second buffer layer 150.

[0109] The second source electrode 164 and the second drain electrode 166 are respectively connected to the second source region 152b and the second drain region 152c of the second semiconductor layer 152 through contact holes penetrating the second interlayer insulating layer 158 and the second gate insulating layer 154.

[0110] The first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 may have the same layers and the same materials. For example, the first source electrode 160, the first drain electrode 162, the second source electrode 164, and the second drain electrode 166 may have a single layer or multiple layers of metallic materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0111] For example, the first planarization layer 168 may have a single layer or multiple layers of organic insulating materials such as photoacryl and benzocyclobutene (BCB).

[0112] The first semiconductor layer 136, the first gate electrode 140, the first source electrode 160, and the first drain electrode 162 can form a fourth transistor T4, and the second semiconductor layer 152, the second gate electrode 156, the second source electrode 164, and the second drain electrode 166 can form a second transistor T2.

[0113] The first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 may have the same cross-sectional structure as the fourth transistor T4, and the sixth transistor T6 may have the same cross-sectional structure as the second transistor T2.

[0114] A connection electrode 170 is disposed on the first planarization layer 168 corresponding to the first source electrode 160, and a second planarization layer 172 is disposed on the connection electrode 170 over the entire substrate 130.

[0115] The connection electrode 170 is connected to the drain electrode of the fifth transistor T5 or the source electrode of the seventh transistor T7 through a contact hole in the first planarization layer 168. For example, the connection electrode 170 may be connected to the drain electrode of the fifth transistor T5 or the source electrode of the seventh transistor T7 having the same cross-sectional structure as the fourth transistor T4, but is not limited thereto. For example, the connection electrode 170 may be electrically connected to the second transistor T2, and the connection electrode 170 may be electrically connected to the sixth transistor T6 having the same cross-sectional structure as the second transistor T2.

[0116] For example, the connecting electrode 170 may have three layers of metallic materials such as aluminum (Al) and titanium (Ti).

[0117] For example, the second planarization layer 172 may be a single layer or multiple layers of organic insulating materials such as photoacrylic resin and benzocyclobutene (BCB).

[0118] A first electrode 174 is disposed on the second planarization layer 172 corresponding to the connecting electrode 170, and a dam layer 176 is disposed on the first electrode 174.

[0119] The first electrode 174 is connected to the connecting electrode 170 through a contact hole in the second planarization layer 172.

[0120] For example, the first electrode 174 can be an anode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or an opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0121] The embankment 176 covers the edge portion of the first electrode 174 and has an opening that exposes the central portion of the first electrode 174.

[0122] For example, the dam layer 176 may have a single or multiple layers of organic insulating materials such as photoacrylic resin and benzocyclobutene (BCB).

[0123] A spacer 178 is provided on the embankment layer 176, a light-emitting layer 180 is provided on the spacer 178 above the entire substrate 130, and a second electrode 182 is provided on the light-emitting layer 180 above the entire substrate 130.

[0124] For example, spacer 178 may have a single layer or multiple layers of organic insulating material such as photoacrylic resin and benzocyclobutene (BCB).

[0125] The light-emitting layer 180 is in contact with the first electrode 174 exposed through the opening of the dam 176, the sidewall of the opening of the dam 176, the top surface of the dam 176, and the side and top surfaces of the spacer 178.

[0126] The light-emitting layer 180 may include a hole auxiliary layer such as a hole injection layer and a hole transport layer, a light-emitting material layer, and an electron auxiliary layer such as an electron transport layer and an electron injection layer.

[0127] For example, the second electrode 182 can be a cathode and can be a single layer or multiple layers of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a semi-transparent or opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0128] The first electrode 174, the light-emitting layer 180, and the second electrode 182 can form a light-emitting diode (LED) Del.

[0129] An encapsulation layer 184 is provided on the second electrode 182 above the entire substrate 130 to prevent moisture penetration. The encapsulation layer 184 includes a first encapsulation layer 184a, a second encapsulation layer 184b, and a third encapsulation layer 184c sequentially disposed on the second electrode 182.

[0130] For example, the first encapsulation layer 184a and the third encapsulation layer 184c may have a single layer or multiple layers of inorganic insulating materials such as silicon dioxide (SiO2) and silicon nitride (SiNx), and the second encapsulation layer 184b may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0131] The structure of the first transistor T1, the second transistor T2, and the sixth transistor T6 of each sub-pixel SP1 to SP4 of the display device 110 will be described with reference to the accompanying drawings.

[0132] Figure 5 This is a plan view showing the first transistor, second transistor, and sixth transistor of a display device according to a first embodiment of the present disclosure, and Figure 6 It is along Figure 5 The cross-sectional view taken from line VI-VI.

[0133] exist Figure 5 In the first embodiment of the display device 110 according to the present disclosure, in each of the first sub-pixel SP1 to the fourth sub-pixel SP4, a base line BL and a gate line GL for transmitting the (n)th scan 4 signal Sc4(n) and a base line BL and a gate line GL for transmitting the (n)th scan 1 signal Sc1(n) are sequentially arranged along the horizontal direction, and a first semiconductor layer 136 and a second semiconductor layer 152 are sequentially arranged along the vertical direction. The first semiconductor layer 136 can be bent along the horizontal direction to connect to the second semiconductor layer 152.

[0134] The base line BL and gate line GL of the (n)th scan 4 signal Sc4(n) intersect with the second semiconductor layer 152 to form the sixth transistor T6, and the base line BL and gate line of the scan 1 signal Sc1(n) intersect with the second semiconductor layer 152 to form the second transistor T2.

[0135] The first transistor T1 includes a portion of the first semiconductor layer 136, the second transistor T2 includes a portion of the base line BL and the gate line GL for transmitting the (n)th scan 1 signal Sc1(n), and the sixth transistor T6 includes a portion of the base line BL and the gate line GL for transmitting the (n)th scan 4 signal Sc4(n).

[0136] exist Figure 6 In the first sub-pixel SP1 to the fourth sub-pixel SP4, a first buffer layer 134, a first gate insulating layer 138, and a first interlayer insulating layer 144 are sequentially disposed on the substrate 130, and the base line BL for transmitting the (n)th scan 4 signal Sc4(n) and the base line BL for transmitting the (n)th scan 1 signal Sc1(n) are arranged as follows: Figure 5 They are spaced apart from each other on the first interlayer insulating layer 144 in the vertical direction shown.

[0137] The second buffer layer 150 is disposed on the base line BL for transmitting the (n)th scan 4 signal Sc4(n) and the base line BL for transmitting the (n)th scan 1 signal Sc1(n), and the second semiconductor layer 152 is disposed on the second buffer layer 150.

[0138] The second gate insulating layer 154 is disposed on the second semiconductor layer 152, and the gate line GL that transmits the (n)th scan 4 signal Sc4(n) and the gate line GL that transmits the (n)th scan 1 signal Sc1(n) are disposed on the second semiconductor layer 152. Figure 5 The two layers are spaced apart on the second gate insulating layer 154 in the vertical direction shown. The second interlayer insulating layer 158 is disposed on the gate line GL that transmits the (n)th scan 4 signal Sc4(n) and the gate line GL that transmits the (n)th scan 1 signal Sc1(n).

[0139] A portion of the base line BL for transmitting the nth scan signal Sc4(n), the second buffer layer 150, the second semiconductor layer 152, the second gate insulating layer 154, and a portion of the gate line GL for transmitting the nth scan signal Sc4(n) constitute a dual-gate type sixth transistor T6. A portion of the base line BL for transmitting the nth scan signal Sc4(n) and a portion of the gate line GL for transmitting the nth scan signal Sc4(n) serve as the bottom gate electrode and top gate electrode of the sixth transistor T6, respectively.

[0140] A portion of the base line BL that transmits the (n)th scan 1 signal Sc1(n), the second buffer layer 150, the second semiconductor layer 152, the second gate insulating layer 154, and a portion of the gate line GL that transmits the (n)th scan 1 signal Sc1(n) constitute a dual-gate type second transistor T2. A portion of the base line BL that transmits the (n)th scan 1 signal Sc1(n) and a portion of the gate line GL that transmits the (n)th scan 1 signal Sc1(n) serve as the bottom gate electrode and the top gate electrode of the second transistor T2, respectively.

[0141] The reduction in the width of the initialization period of the display device 110 will be explained with reference to the accompanying drawings.

[0142] Figure 7 This is a view showing a frame of multiple signals of a display device according to a first embodiment of the present disclosure.

[0143] exist Figure 7 In the first time period TP1 (reset time period) of a frame F of the display device 110 according to the first embodiment of the present disclosure, the nth light emission signal Em(n), the nth scan 1 signal Sc1(n), the nth odd scan 2 signal Sc2o(n), and the nth even scan 2 signal Sc2e(n) of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines have a logic high voltage Vh (e.g., a voltage sufficient to put the transistor to which the voltage is applied to in the on state), and the nth scan 3 signal Sc3(n) and the nth scan 4 signal Sc4(n) of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines have a logic low voltage Vl (e.g., a voltage sufficient to put the transistor to which the voltage is applied to in the off state).

[0144] Therefore, transistors T1, T2, T7, and T8 are turned on, while transistors T3, T4, T5, and T6 are turned off. The stress signal Vobs is applied to nodes N1, N3, and N2 via transistor T8, T1, and T2, and the anode reset signal Var is applied to node N4 via transistor T7.

[0145] During the first time period TP1, the first node N1, the second node N2, the third node N3, and the fourth node N4 of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines are reset to prevent lag caused by previous frames.

[0146] During the second time period TP2, which serves as the initialization period, the nth emission signal Em(n), the nth scan 1 signal Sc1(n), the nth odd scan 2 signal Sc2o(n), the nth even scan 2 signal Sc2e(n), the nth scan 3 signal Sc3(n), and the scan 4 signal Sc4(n) have a logic high voltage Vh.

[0147] Therefore, transistors T1, T2, and T6 are turned on, while transistors T3, T4, T5, T7, and T8 are turned off. The initial signal Vin is applied to nodes N2, N3, and N1 through transistors T6, T2, and T1.

[0148] During the second time period TP2, the second node N2, the third node N3, and the first node N1 of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines are reset for initialization.

[0149] Therefore, the second time period TP2, which is the initialization period, is included in the period of the logic high voltage Vh of the (n)th scan 1 signal Sc1(n), and thus can have a relatively small first width w1.

[0150] During the third time period TP3, which is the sampling period, the nth emission signal Em(n), the nth scan 1 signal Sc1(n), the nth even scan 2 signal Sc2e(n), and the nth scan 3 signal Sc3(n) of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines have a logic high voltage Vh, and the nth odd scan 2 signal Sc2o(n) and the nth scan 4 signal Sc4(n) of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines have a logic low voltage Vl.

[0151] Therefore, the first transistor T1 and the second transistor T2 for odd-numbered and even-numbered horizontal pixel lines, as well as the third transistor T3 for odd-numbered horizontal pixel lines, are turned on, while the third transistor T3 for even-numbered horizontal pixel lines, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 for both odd-numbered and even-numbered horizontal pixel lines, are turned off. The data signal Vda is applied to the second node N2 through the third transistor T3, the first transistor T1, and the second transistor T2.

[0152] During the third time period TP3, the data signal Vda is applied to the second node N2 of the odd-numbered horizontal pixel line, and the sum of the data signal Vda and the threshold voltage Vth of the first transistor T1 (Vda+Vth) is applied to the gate electrode of the first transistor T1 and stored in the storage capacitor Cs.

[0153] During the fourth time period TP4, which is the sampling period, the nth emission signal Em(n), the nth scan 1 signal Sc1(n), the nth odd scan 2 signal Sc2o(n), and the nth scan 3 signal Sc3(n) of the odd-numbered and even-numbered horizontal pixel lines have a logic high voltage Vh, and the nth even scan 2 signal Sc2e(n) and the nth scan 4 signal Sc4(n) of the odd-numbered and even-numbered horizontal pixel lines have a logic low voltage Vl.

[0154] Therefore, the first transistor T1 and the second transistor T2 for odd-numbered and even-numbered horizontal pixel lines, as well as the third transistor T3 for even-numbered horizontal pixel lines, are turned on, while the third transistor T3 for odd-numbered horizontal pixel lines, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 for both odd-numbered and even-numbered horizontal pixel lines, are turned off. The data signal Vda is applied to the second node N2 through the third transistor T3, the first transistor T1, and the second transistor T2.

[0155] During the fourth time period TP4, the data signal Vda is applied to the second node N2 of the even-numbered horizontal pixel line, and the sum of the data signal Vda and the threshold voltage Vth of the first transistor T1 (Vda+Vth) is applied to the gate electrode of the first transistor T1 and stored in the storage capacitor Cs.

[0156] During the fifth period TP5, which is the reset period, the nth emission signal Em(n), the nth odd scan 2 signal Sc2o(n), and the nth even scan 2 signal Sc2e(n) of the odd and even horizontal pixel lines have a logic high voltage Vh, and the nth scan 1 signal Sc1(n), the nth scan 3 signal Sc3(n), and the nth scan 4 signal Sc4(n) of the odd and even horizontal pixel lines have a logic low voltage Vl.

[0157] Therefore, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 of the odd-numbered and even-numbered horizontal pixel lines are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 of the odd-numbered and even-numbered horizontal pixel lines are turned off. The stress signal Vobs is applied to the first node N1 and the third node N3 through the eighth transistor T8 and the first transistor T1, and the anode reset signal Var is applied to the fourth node N4 through the seventh transistor T7.

[0158] During the fifth time period TP5, the first node N1, the third node N3, and the fourth node N4 of the odd-numbered horizontal pixel lines and the even-numbered horizontal pixel lines are reset to prevent lag caused by previous timing.

[0159] During the sixth period TP6, which is the light emission period, the (n)th odd scan 2 signal Sc2o(n), the (n)th even scan 2 signal Sc2e(n), and the (n)th scan 3 signal Sc3(n) of the odd-numbered horizontal pixel lines and even-numbered horizontal pixel lines have a logic high voltage Vh, and the (n)th light emission signal Em(n), the scan 1 signal Sc1(n), and the (n)th scan 4 signal Sc4(n) of the odd-numbered horizontal pixel lines and even-numbered horizontal pixel lines have a logic low voltage Vl.

[0160] Therefore, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 of the odd-numbered and even-numbered horizontal pixel lines are turned on, while the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 of the odd-numbered and even-numbered horizontal pixel lines are turned off. A high-level signal Vdd is applied to the fourth node N4 through the fourth transistor T4, the first transistor T1, and the fifth transistor T5. Threshold voltage (Vth) compensation is implemented in the turned-on first transistor T1, and the current corresponding to the data signal Vda flows through the turned-on first transistor T1.

[0161] During the sixth time period TP6, the light-emitting diode De emits light corresponding to the data signal Vda of the current frame.

[0162] The first width w1 of the time period of the logic high voltage Vh of the nth scan 4 signal Sc4(n) of the display device 110 according to the first embodiment of this disclosure is smaller than the second width w2 of the time period of the logic high voltage Vh of the nth scan 4 signal Sc4(n) of the display device according to the comparative example. Therefore, even when the second transistor T2 of the sampling transistor has a different mobility, the second node N2 is charged to the same voltage.

[0163] Figure 8A This is a view showing the second node voltage of a display device according to a comparative example, and Figure 8B This is a view showing the second node voltage of a display device according to a first embodiment of the present disclosure.

[0164] exist Figure 8A In the comparative example, the period of logic high voltage Vh of the (n)th scan 4 signal Sc4(n) of the display device has a relatively large second width w2, and therefore the sixth transistor T6 is turned on during a relatively long period. Therefore, in both the case G1 (solid curve) where the second transistor T2 and the sixth transistor T6 have relatively high mobility and the case G2 (dashed curve) where the second transistor T2 and the sixth transistor T6 have relatively low mobility, the second node voltage Vn2 of the second node N2 reaches saturation during the width w2 period of logic high voltage Vh of the (n)th scan 4 signal Sc4(n) to charge the initial signal Vin.

[0165] Next, during the third time period TP3 and the fourth time period TP4 of the logic low voltage Vl of the (n)th odd-scan 2 signal Sc2o(n) and the (n)th even-scan 2 signal Sc2e(n), the third transistor T3 is turned on. In case G1 (where the second transistor T2 and the sixth transistor T6 have relatively high mobility), the second node voltage Vn2 (solid curve) rises rapidly to a first voltage V1 higher than the initial signal Vin due to the relatively high charging speed. However, in case G2 (where the second transistor T2 and the sixth transistor T6 have relatively low mobility), the second node voltage Vn2 (dashed curve) rises more slowly to a second voltage V2 lower than the first voltage V1 due to the relatively low charging speed.

[0166] Therefore, in the display device according to the comparative example, during the third time period TP3 and the fourth time period TP4 of the sampling period, due to the mobility deviation of the second transistor T2 and the sixth transistor T6, the threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node N2 can have different magnitudes. This results in a threshold voltage difference across different areas of the display panel. Consequently, degradation such as local brightness deviation occurs, and the display quality is reduced.

[0167] In contrast, Figure 8B In the first embodiment of the display device 110 according to the present disclosure, the second time period TP2 of the logic high voltage Vh of the (n) scan 4 signal Sc4(n) has a relatively small first width w1, and therefore the sixth transistor T6 is turned on during the relatively short time period. As explained below, therefore, in both case G1 (where the second transistor T2 and the sixth transistor T6 have relatively high mobility) and case G2 (where the second transistor T2 and the sixth transistor T6 have relatively low mobility), the second node voltage Vn2 of the second node N2 is not saturated during the short first width w1 time period of the logic high voltage Vh of the (n) scan 4 signal Sc4(n).

[0168] Specifically, such as Figure 8BAs shown, in case G1 (where the second transistor T2 and the sixth transistor T6 have relatively high mobilities), despite the relatively high charging speed, the small first width w1 ensures that the second node voltage Vn2 (solid curve) of the second node N2 only charges to a third voltage V3 higher than the initial signal Vin. Therefore, the second node voltage Vn2 of the second node N2 does not saturate during the second period TP2 of the logic high voltage Vh of the (n)th scan 4 signal Sc4(n). Furthermore, in case G2 (where the second transistor T2 and the sixth transistor T6 have relatively low mobilities), the relatively low charging speed ensures that the second node voltage Vn2 (dashed curve) of the second node N2 charges to a fourth voltage V4 higher than the third voltage V3 (and also higher than the initial signal Vin). Therefore, the second node voltage Vn2 of the second node N2 also does not saturate during the second period TP2 of the logic high voltage Vh of the (n)th scan 4 signal Sc4(n).

[0169] Next—that is, during the third time period TP3 and the fourth time period TP4 (where the (n)th odd-scan 2 signal Sc2o(n) and the (n)th even-scan 2 signal Sc2e(n) are each logic low voltage V1)—the benefits of the aforementioned non-saturation in the second time period TP2 are shown. Specifically, in case G1 (where the second transistor T2 and the sixth transistor T6 have relatively high mobilities), the second node voltage Vn2 (solid curve) rises rapidly from the third voltage V3 to the fifth voltage V5 due to the relatively high charging speed. In case G2 (where the second transistor T2 and the sixth transistor T6 have relatively low mobilities), the second node voltage Vn2 (dashed curve) rises more slowly from the fourth voltage V4 to the same fifth voltage V5 due to the relatively low charging speed. Therefore, regardless of the mobility deviation of the second transistor T2 and the sixth transistor T6 (e.g., regardless of case G1 or G2), the second node voltage Vn2 of the second node N2 can have the same magnitude (the fifth voltage V5).

[0170] Therefore, in the display device 110 according to the first embodiment of this disclosure, during the third time period TP3 and the fourth time period TP4 of the sampling period, the threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node N2 has the same magnitude and is not affected by the mobility deviation of the second transistor T2 and the sixth transistor T6. This can help reduce the threshold voltage difference across different areas of the display panel 128. Therefore, degradation such as local brightness deviation is prevented, and the display quality is improved.

[0171] In the display device 110 according to the first embodiment of the present disclosure, during the second time period TP2, which is the initialization period, the second node voltage Vn2 is not saturated regardless of the region mobility deviation between the second transistor T2 and the sixth transistor T6. This can be achieved by determining the first width w1 to a relatively small value, during which the second node voltage Vn2 is charged to different voltages according to the region mobility of the second transistor T2 and the sixth transistor T6.

[0172] In addition to using a smaller first width w1 or as an alternative, some implementations can also ensure unsaturation by using a lower initial signal Vin. For example, during the second time period TP2, by determining the initial signal Vin to be a relatively low voltage, such as a voltage lower than the normal value by a predetermined value (e.g., about -6 V to about -10 V), the second node voltage Vn2 can be charged to different voltages depending on the region mobility of the second transistor T2 and the sixth transistor T6. Therefore, the second node voltage Vn2 can remain unsaturated regardless of the deviation in the region mobility of the second transistor T2 and the sixth transistor T6.

[0173] In some implementations, the voltage of scan 1 signal Sc1(n) may be increased due to the coupling of scan 2 signal Sc2(n).

[0174] Figure 9 This is a circuit diagram showing a sub-pixel of a display device according to a second embodiment of the present disclosure. The parts that are the same as in the first embodiment will not be described again.

[0175] exist Figure 9 In the second embodiment of the display device according to this disclosure, each of the first sub-pixel SP1 to the fourth sub-pixel SP4 includes a first transistor T1 to an eighth transistor T8, a storage capacitor Cs, a coupling capacitor Cc, and a light-emitting diode De. At least one of the first transistors T1 to the eighth transistor T8 may be an oxide semiconductor thin-film transistor, and the other transistors of the first transistors T1 to the eighth transistor T8 may be low-temperature polycrystalline silicon thin-film transistors.

[0176] The connection structure and operation of the first transistor T1 to the eighth transistor T8, the storage capacitor Cs and the light-emitting diode De in the second embodiment are the same as those in the first embodiment, except that a coupling capacitor Cc is connected between the scan 1 signal Sc1(n) and the odd scan 2 signal Sc2o(n-1) or between the scan 1 signal Sc1(n) and the even scan 2 signal Sc2e(n-1).

[0177] The coupling capacitor Cc can be formed due to the overlap of the output line of the first gate drive unit's scan block 1 and the carry line in the even scan block 2.

[0178] Figure 10 This is a view showing the first gate driving unit and the display panel of a display device according to a second embodiment of the present disclosure, and Figure 11 This is a cross-sectional view showing the output line and carry line of the first gate driving unit of a display device according to a second embodiment of the present disclosure. Detailed descriptions of portions identical to those in the first embodiment will be omitted.

[0179] exist Figure 10 In the second embodiment of the present disclosure, the first gate driving unit 124 in the non-display area NDA of the display panel 128 of the display device includes a (n-1)th scan 1 block Bsc1(n-1), a (n)th scan 1 block Bsc1(n), a (n-1)th odd scan 2 block Bsc2o(n-1), a (n)th odd scan 2 block Bsc2o(n), a (n-1)th even scan 2 block Bsc2e(n-1), a (n)th even scan 2 block Bsc2e(n), a (n-1)th scan 3 block Bsc3(n-1), and a (n)th scan 3 block Bsec3(n).

[0180] The (n-1)th scan block Bsc1(n-1) generates the (n-1)th scan 1 signal Sc1(n-1), and supplies the (n-1)th scan 1 signal Sc1(n-1) to the odd-numbered horizontal pixel line HLo(n-1) and even-numbered horizontal pixel line HLe(n-1) of the (n-1)th horizontal pixel line pair HLP(n-1) in the display area DA through the output line OL.

[0181] The (n)th scan 1 block Bsc1(n) generates the (n)th scan 1 signal Sc1(n), and supplies the (n)th scan 1 signal Sc1(n) to the (n)th horizontal pixel line pair HLP(n) of the display area DA via the output line OL to the odd horizontal pixel line HLo(n) and the even horizontal pixel line HLe(n) of the (n)th horizontal pixel line pair HLP(n).

[0182] The (n-1)th odd-scan 2-block Bsc2o(n-1) generates the (n-1)th odd-scan 2 signal Sc2o(n-1), which is supplied to the odd-numbered horizontal pixel line HLo(n-1) of the (n-1)th horizontal pixel line pair HLP(n-1) in the display area DA through the output line OL. The (n-1)th odd-scan 2 signal Sc2o(n-1) is also supplied to the (n-1)th even-scan 2-block Bsc2e(n-1) in the next level in the non-display area NDA through the carry line CL.

[0183] The (n-1)th even-numbered scan 2 blocks Bsc2e(n-1) generate the (n-1)th even-numbered scan 2 signal Sc2e(n-1), which is supplied to the even-numbered horizontal pixel line HLe(n-1) of the (n-1)th horizontal pixel line pair HLP(n-1) in the display area DA through the output line OL, and the (n-1)th even-numbered scan 2 signal Sc2e(n-1) is supplied to the next level of the (n)th odd-numbered scan 2 blocks Bsc2o(n) in the non-display area NDA through the carry line CL.

[0184] The (n)th odd scan 2 blocks Bsc2o(n) generates the (n)th odd scan 2 signal Sc2o(n), which is supplied to the (n)th horizontal pixel line HLo(n) of HLP(n) in the display area DA through the output line OL. The (n)th odd scan 2 signal Sc2o(n) is also supplied to the (n)th even scan 2 blocks Bsc2e(n) in the next level in the non-display area NDA through the carry line CL.

[0185] The (n)th even-numbered scan 2 blocks Bsc2e(n) generates the (n)th even-numbered scan 2 signal Sc2e(n), which is supplied to the (n)th horizontal pixel line pair HLP(n) HLe(n) in the display area DA through the output line OL. The (n)th even-numbered scan 2 signal Sc2e(n) is supplied to the (n+1)th odd-numbered scan 2 blocks Bsc2o(n+1) in the next level in the non-display area NDA through the carry line CL.

[0186] In the non-display area NDA, the carry line CL of the (n-1)th even scan 2 signal Sc2e(n-1) and the output line OL of the (n)th scan 1 signal Sc1(n) overlap to form a coupling capacitor Cc.

[0187] Despite Figure 10 In the second embodiment, the output line OL of the (n)th scan of the 1st Bsc1(n) block can overlap with the carry line CL of the (n-1)th even scan of the 2nd Bsc2e(n-1) block. However, in another embodiment, the output line OL of the (n)th scan of the 1st Bsc1(n) block can overlap with the carry line CL of the (n-1)th odd scan of the 2nd Bsc2o(n-1) block.

[0188] exist Figure 11In the non-display area NDA, a first buffer layer 134, a first gate insulating layer 138, and a first interlayer insulating layer 144 are sequentially disposed on the substrate 130, and the carry line CL for sending the (n-1)th even scan 2 signal Sc2e(n-1) is disposed on the first interlayer insulating layer 144.

[0189] The second buffer layer 150 and the second gate insulating layer 154 are sequentially disposed on the carry line CL for transmitting the (n-1)th even scan 2 signal Sc2e(n-1), the output line OL for transmitting the (n)th scan 1 signal Sc1(n) is disposed on the second gate insulating layer 154, and the second interlayer insulating layer 158 is disposed on the output line OL for transmitting the (n)th scan 1 signal Sc1(n).

[0190] The output line that sends the (n)th scan 1 signal Sc1(n) overlaps with the carry line CL that sends the (n-1)th even scan 2 signal Sc2e(n-1), with a second gate insulating layer 154 and a second buffer layer 150 sandwiched between them to form a coupling capacitor Cc.

[0191] The voltage of the (n)th scan 1 signal Sc1(n) is increased due to the coupling of the (n-1)th even scan 2 signal Sc2e(n-1) through the coupling capacitor Cc.

[0192] Figure 12 This is a view showing scan 1 signal and scan 2 signal of a display device according to a second embodiment of this disclosure. Detailed descriptions of parts identical to those in the first embodiment will be omitted.

[0193] exist Figure 12 In the signal, the period of logic high voltage Vh of the (n)th scan 1 signal Sc1(n) overlaps with the fourth period TP4 of logic low voltage Vl of the (n-1)th even scan 2 signal Sc2e(n-1). The period of logic high voltage Vh of the (n)th scan 1 signal Sc1(n) has voltage changes at the falling timing FT and rising timing RT of the (n-1)th even scan 2 signal Sc2e(n-1) through the coupling capacitor Cc between the output line OL of the (n)th scan 1 signal Sc1(n) and the carry line CL of the (n-1)th even scan 2 signal Sc2e(n-1).

[0194] The voltage of the (n)th scan 1 signal Sc1(n) drops from the logic high voltage Vh at the falling timing FT of the (n-1)th even scan 2 signal Sc2e(n-1), and rises again at the rising timing RT of the (n-1)th even scan 2 signal Sc2e(n-1) to become a sixth voltage V6, which is greater than the logic high voltage Vh. Because a relatively high voltage is applied to the gate electrode of the second transistor T2, the on-current of the second transistor T2 increases, and the mobility of the second transistor is compensated.

[0195] In the display device according to the second embodiment of this disclosure, by forming a coupling capacitor Cc between the output line OL of the scan 1 signal Sc1 and the carry line CL of the scan 2 signal Sc2 in the first gate driving unit 124 and the second gate driving unit 126, the voltage of the scan 1 signal increases and the on-state current of the second transistor T2 of the sampling transistor increases. Therefore, the regional threshold voltage difference in the display panel is minimized, preventing degradation such as local brightness deviation, and the display quality is improved.

[0196] In another embodiment, the coupling capacitor can be disposed in the sub-pixel.

[0197] Figure 13 This is a view showing the sub-pixels of a display device according to a third embodiment of the present disclosure. The parts that are the same as in the first and second embodiments will not be described again.

[0198] exist Figure 13 In the third embodiment of the display device according to this disclosure, each of the first sub-pixel SP1 to the fourth sub-pixel SP4 includes a first transistor T1 to an eighth transistor T8, a storage capacitor Cs, a coupling capacitor Cc, and a light-emitting diode De. At least one of the first transistors T1 to the eighth transistor T8 may be an oxide semiconductor thin-film transistor, and the other transistors of the first transistors T1 to the eighth transistor T8 may be low-temperature polycrystalline silicon thin-film transistors.

[0199] The connection structure and operation of the first transistor T1 to the eighth transistor T8, the storage capacitor Cs, and the light-emitting diode De in the third embodiment are the same as those in the first embodiment, except that the sixth transistor T6 has a single-gate type, wherein the gate electrode is disposed on the semiconductor layer to form a channel region on the upper part of the semiconductor layer, and a coupling capacitor Cc is connected between the scan 1 signal Sc1(n) and the odd scan 2 signal Sc2o(n-1) or between the scan 1 signal Sc1(n) and the even scan 2 signal Sc2e(n-1).

[0200] When the sixth transistor T6 has a single-gate type, the channel region is formed only on the upper part of the semiconductor layer, and the conduction current is reduced. Therefore, during the second period TP2 of the logic high voltage Vh of the (n)th scan signal Sc4(n), the second node N2 is charged at a relatively low charging rate due to the initial signal Vin.

[0201] Similar to the first embodiment, the second node voltage Vn2 of the second node N2 is unsaturated and charged to a voltage higher than the initial voltage Vin, and the threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node N2 has the same magnitude during the third time period TP3 and the fourth time period TP4, regardless of whether the second transistor T2 and the sixth transistor T6 have mobility deviations. Therefore, the regional threshold voltage difference in the display panel is minimized, preventing degradation such as local brightness deviations, and improving display quality.

[0202] The coupling capacitor Cc can be formed due to the overlap of the gate line GL of scan 1 signal Sc1 and the base line BL of scan 2 signal Sc2 in each sub-pixel SP1 to SP4.

[0203] Figure 14 This is a plan view showing the first transistor, the second transistor, and the sixth transistor of a display device according to a third embodiment of the present disclosure. Figure 15 It is along Figure 14 The cross-sectional view taken by line XV-XV, and Figure 16 It is along Figure 14 A cross-sectional view taken along line XVI-XVI. Detailed descriptions of parts identical to those in the first and second embodiments will be omitted.

[0204] exist Figure 14 In the display device according to the third embodiment of the present disclosure, in each of the first sub-pixel SP1 to the fourth sub-pixel SP4, a base line BL for transmitting the (n-1)th odd-numbered scan 2 signal Sc2o(n-1) or the (n-1)th even-numbered scan 2 signal Sc2e(n-1), a gate line GL for transmitting the (n)th scan 4 signal Sc4(n), and a base line BL and a gate line GL for transmitting the (n)th scan 1 signal Sc1(n) are sequentially arranged along the horizontal direction, and a first semiconductor layer 136 and a second semiconductor layer 152 are sequentially arranged along the vertical direction. The first semiconductor layer 136 can be bent along the horizontal direction to connect to the second semiconductor layer 152.

[0205] The gate line GL of the (n)th scan 4 signal Sc4(n) intersects with the second semiconductor layer 152 to form the sixth transistor T6, and the base line BL and gate line of the (n)th scan 1 signal Sc1(n) intersect with the second semiconductor layer 152 to form the second transistor T2.

[0206] The first transistor T1 includes a portion of the first semiconductor layer 136, the second transistor T2 includes a portion of the base line BL and the gate line GL for transmitting the (n)th scan 1 signal Sc1(n), and the sixth transistor T6 includes a portion of the gate line GL for transmitting the (n)th scan 4 signal Sc4(n).

[0207] The base line BL of the (n-1)th odd-scan 2 signal Sc2o(n-1) or the (n-1)th even-scan 2 signal Sc2e(n-1) bends vertically to form a bent portion BP, and the gate line GL of the (n)th scan 1 signal Sc1(n) protrudes vertically to form a protruding portion PP. The bent portion BP of the base line BL of the (n-1)th odd-scan 2 signal Sc2o(n-1) or the (n-1)th even-scan 2 signal Sc2e(n-1) overlaps with the protruding portion PP of the gate line GL of the (n)th scan 1 signal Sc1(n) to form a coupling capacitor Cc.

[0208] exist Figure 15 In the display area DA, in each of the first sub-pixels SP1 to the fourth sub-pixels SP4, a first buffer layer 134, a first gate insulating layer 138 and a first interlayer insulating layer 144 are sequentially disposed on the substrate 130, and the base line BL that transmits the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1) and the base line BL that transmits the (n)th scan 1 signal Sc1(n) are spaced apart from each other on the first interlayer insulating layer 144.

[0209] The second buffer layer 150 and the second gate insulating layer 154 are sequentially disposed on the base line BL for transmitting the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1) and the base line BL for transmitting the (n)th scan 1 signal Sc1(n).

[0210] The gate line GL that transmits the (n)th scan 4 signal Sc4(n) and the gate line GL that transmits the (n)th scan 1 signal Sc1(n) are spaced apart from each other on the second gate insulating layer 154, and the second interlayer insulating layer 158 is disposed on the gate line GL that transmits the (n)th scan 4 signal Sc4(n) and the gate line GL that transmits the (n)th scan 1 signal Sc1(n).

[0211] The protruding portion PP of the gate line GL that transmits the (n)th scan 1 signal Sc1(n) overlaps with the bent portion BP of the base line BL that transmits the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1), with a second gate insulating layer 154 and a second buffer layer 150 sandwiched between them, thereby forming a coupling capacitor Cc. The voltage of the (n)th scan 1 signal Sc1(n) is increased due to the coupling of the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1) through the coupling capacitor Cc.

[0212] exist Figure 16 In the display area DA, in each of the first sub-pixels SP1 to the fourth sub-pixels SP4, a first buffer layer 134, a first gate insulating layer 138 and a first interlayer insulating layer 144 are sequentially disposed on the substrate 130, and the base line BL that transmits the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1) and the base line BL that transmits the (n)th scan 1 signal Sc1(n) are spaced apart from each other on the first interlayer insulating layer 144.

[0213] The second buffer layer 150 is disposed on the base line BL for transmitting the (n-1)th odd scan 2 signal Sc2o(n-1) or the (n-1)th even scan 2 signal Sc2e(n-1) and the base line BL for transmitting the (n)th scan 1 signal Sc1(n), and the second semiconductor layer 152 is disposed on the second buffer layer 150.

[0214] The second gate insulating layer 154 is disposed on the second semiconductor layer 152. The gate line GL that transmits the (n) scan 4 signal Sc4(n) and the gate line GL that transmits the (n) scan 1 signal Sc1(n) are spaced apart from each other on the second gate insulating layer 154. The second interlayer insulating layer 158 is disposed on the gate line GL that transmits the (n) scan 4 signal Sc4(n) and the gate line GL that transmits the (n) scan 1 signal Sc1(n).

[0215] The second semiconductor layer 152, the second gate insulating layer 154, and a portion of the gate line GL that transmits the scan 4 signal Sc4(n) constitute a single-gate type sixth transistor T6. A portion of the gate line GL that transmits the scan 4 signal Sc4(n) serves as the top gate electrode of the sixth transistor T6.

[0216] A portion of the base line BL that transmits the (n)th scan 1 signal Sc1(n), the second buffer layer 150, the second semiconductor layer 152, the second gate insulating layer 154, and a portion of the gate line GL that transmits the (n)th scan 1 signal Sc1(n) constitute a dual-gate type second transistor T2. A portion of the base line BL that transmits the (n)th scan 1 signal Sc1(n) and a portion of the gate line GL that transmits the (n)th scan 1 signal Sc1(n) serve as the bottom gate electrode and the top gate electrode of the second transistor T2, respectively.

[0217] In the display device according to the third embodiment of this disclosure, by forming a coupling capacitor Cc between the gate line GL of the scan 1 signal Sc1 and the base line BL of the scan 2 signal Sc2 in each of the first sub-pixels SP1 to the fourth sub-pixels SP4, the voltage of the scan 1 signal increases and the on-state current of the second transistor T2 of the sampling transistor increases. Therefore, the regional threshold voltage difference in the display panel is minimized, preventing degradation such as local brightness deviations, and the display quality is improved.

[0218] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes a display area having a plurality of sub-pixels and a non-display area at the periphery of the display area; The first transistor in each of the plurality of sub-pixels is switched according to the voltage of the second node and is connected to the first node and the third node; The second transistor in each of the plurality of sub-pixels is switched according to the scan 1 signal and connected to the second node and the third node, and the second transistor has a dual-gate type; The third transistor in each of the plurality of sub-pixels is switched according to one of the odd scan 2 signal and the even scan 2 signal and is connected to the data signal and the first node; The fourth transistor in each of the plurality of sub-pixels is switched according to the light emission signal and is connected to the high-level signal and the first node; The fifth transistor in each of the plurality of sub-pixels, the fifth transistor being switched according to the light emission signal and connected to the third node and the fourth node; The sixth transistor in each of the plurality of sub-pixels, the sixth transistor being switched according to scan 4 signal and connected to the initial signal and the second node; The seventh transistor in each of the plurality of sub-pixels, the seventh transistor being switched according to scan 3 signal and connected to the anode reset signal and the fourth node; The eighth transistor in each of the plurality of sub-pixels, the eighth transistor being switched according to the scan 3 signal and connected to the stress signal and the first node; and A light-emitting diode in each of the plurality of sub-pixels, the light-emitting diode being connected to a low-level signal and the fourth node.

2. The display device according to claim 1, wherein, The period of logic high voltage of the scan 1 signal includes the period of logic high voltage of the scan 4 signal.

3. The display device according to claim 2, wherein, During the period of the logic high voltage of the scan 4 signal, the second node is charged to a voltage higher than that of the initial signal.

4. The display device according to claim 3, wherein, The voltage of the initial signal was determined to be a predetermined amount lower than the normal value.

5. The display device according to claim 1 further includes a coupling capacitor connected to one of the odd scan 2 signal and the even scan 2 signal and the scan 1 signal.

6. The display device according to claim 5, further comprising: An output line is located in the non-display area and transmits the scan 1 signal; as well as The carry line, located in the non-display area, transmits one of the odd scan 2 signal and the even scan 2 signal. The output line and the carry line are disposed in overlapping layers in different layers to form the coupling capacitor, wherein at least one insulating layer is positioned between the output line and the carry line.

7. The display device according to claim 6, further comprising: Scan 1 block, which is located in the non-display area, and generate the Scan 1 signal; as well as Two odd-scan blocks and two even-scan blocks are located in the non-display area and respectively generate the odd-scan 2 signal and the even-scan 2 signal. Wherein, the scan 1 block supplies the scan 1 signal to the plurality of sub-pixels through the output line, and The odd-numbered scanning block 2 and the even-numbered scanning block 2 supply the odd-numbered scanning 2 signal and the even-numbered scanning 2 signal to the next stage respectively through the carry line.

8. The display device according to claim 5, further comprising: Scan 1 base line and Scan 1 gate line, which are in each of the plurality of sub-pixels and transmit the Scan 1 signal; Scan 2 base lines, which are in each of the plurality of sub-pixels and send one of the odd scan 2 signal and the even scan 2 signal; as well as Scan 4 gate lines are performed in each of the plurality of sub-pixels, and the scan 4 signal is transmitted. In this embodiment, a portion of the gate line of scan 1 and a portion of the base line of scan 2 are disposed in different layers and overlap to form the coupling capacitor, wherein at least one insulating layer is disposed between the gate line of scan 1 and the base line of scan 2.

9. The display device according to claim 8, wherein, The sixth transistor has a single-gate type.

10. The display device of claim 1, further comprising a storage capacitor in each of the plurality of sub-pixels and connected to the high-level signal and the second node. in, The source electrode of the first transistor, the source electrode of the third transistor, the drain electrode of the fourth transistor, and the source electrode of the eighth transistor constitute the first node. The second node is formed by the gate electrode of the first transistor, the drain electrode of the second transistor, the first capacitor electrode of the storage capacitor, and the drain electrode of the sixth transistor. The drain electrode of the first transistor, the source electrode of the second transistor, and the source electrode of the fifth transistor constitute the third node. The drain electrode of the fifth transistor, the source electrode of the seventh transistor, and the anode of the light-emitting diode constitute the fourth node.

11. The display device according to claim 10, wherein, During the first time period, the light emission signal, the scan 1 signal, the odd scan 2 signal, and the even scan 2 signal have a logic high voltage, while the scan 3 signal and the scan 4 signal have a logic low voltage. During the second time period, the light emission signal, the scan 1 signal, the odd scan 2 signal, the even scan 2 signal, the scan 3 signal, and the scan 4 signal are all at a logic high voltage. During the third time period, the light emission signal, the scan 1 signal, the even-numbered scan 2 signal, and the scan 3 signal have a logic high voltage, while the odd-numbered scan 2 signal and the scan 4 signal have a logic low voltage. During the fourth time period, the light emission signal, the scan 1 signal, the odd scan 2 signal, and the scan 3 signal have a logic high voltage, while the even scan 2 signal and the scan 4 signal have a logic low voltage. During the fifth time period, the light-emitting signal, the odd-numbered scan 2 signal, and the even-numbered scan 2 signal have a logic high voltage, while the scan 1 signal, the scan 3 signal, and the scan 4 signal have a logic low voltage. During the sixth time period, the odd-numbered scan 2 signal, the even-numbered scan 2 signal, and the scan 3 signal have a logic high voltage, while the light-emitting signal, the scan 1 signal, and the scan 4 signal have a logic low voltage.

12. The display device according to claim 10, wherein, Any one of the first to eighth transistors is an oxide semiconductor thin-film transistor, an amorphous silicon thin-film transistor, and a low-temperature polycrystalline silicon thin-film transistor.

13. A display device, comprising: The display panel includes a display area having multiple gate lines and multiple data lines; A timing control circuit is configured to apply gate signals to the plurality of gate lines; Multiple sub-pixels, defined at the intersection of the multiple gate lines and the multiple data lines; Multiple transistors in each of the plurality of sub-pixels; as well as The light-emitting diode in each of the plurality of sub-pixels Wherein, the plurality of transistors in each of the plurality of sub-pixels include: A sampling transistor, which switches according to a first gate signal and is connected to a node, the sampling transistor having a dual-gate type, and An initialization transistor is formed, which switches according to a second gate signal and is connected to the node and the initial signal. Wherein, the period of logic high voltage of the first gate signal includes the period of logic high voltage of the second gate signal, and During the period when the logic high voltage of the second gate signal is applied, the node is charged to a voltage higher than that of the initial signal.

14. The display device according to claim 13, further comprising: A coupling capacitor is disposed in each of the plurality of sub-pixels or in the non-display area of ​​the display panel.

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