Display device

Abstract

This invention provides a technique for improving dynamic image characteristics. A display device includes a plurality of gate lines, a plurality of signal lines, a plurality of pixels, a display gate driver that sequentially scans the plurality of gate lines, and a pre-charging gate line selection unit that uniformly selects the plurality of gate lines. A frame includes: a pre-charging period during which the pre-charging gate line selection unit uniformly selects the plurality of gate lines and writes pre-charging tone signals from the plurality of signal lines to the plurality of pixels; a first period after the pre-charging period where the display gate driver sequentially scans the plurality of gate lines and writes tone signals corresponding to image signals from the plurality of signal lines to the plurality of pixels; and a second period after the first period where no gate line among the plurality of gate lines is selected.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] As an electro-optical device that suppresses the blurring of dynamic images, Japanese Patent Application Publication No. 2010-091967 has been proposed, for example.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2010-091967 Summary of the Invention

[0004] The technical problem that the invention aims to solve To significantly improve the dynamic image characteristics in LCD panels, the following two methods are known: Method 1) High-frequency driving (using an increased frame rate). Method 2) Pulse driving using a flickering backlight (also known as backlight flickering method, which uses pulse-type driving by timing the backlight to turn off in conjunction with the scanning).

[0005] However, since liquid crystal molecules have an upper limit to their response speed, even if the frame rate is increased to a level higher than the response speed of the liquid crystal molecules, it is impossible to improve the dynamic image characteristics, resulting in uneven brightness and degraded image quality.

[0006] The purpose of this invention is to provide a technique that can improve the characteristics of dynamic images.

[0007] Other technical issues and novel features become apparent from the description and accompanying drawings in this specification.

[0008] Means for solving technical problems If we were to briefly summarize the representative aspects of this invention, it would be as follows.

[0009] That is, the display device has: Multiple gate lines extend in a first direction and are arranged side by side in a second direction that intersects the first direction; Multiple signal lines extend in the second direction and are arranged side by side in the first direction; Multiple pixels are arranged in a matrix in the first direction and the second direction; A gate driver for a display sequentially scans the plurality of gate lines; and The pre-charge gate line selection unit selects all of the plurality of gate lines uniformly. One frame contains: During the pre-charging period, the gate line selection unit for pre-charging uniformly selects multiple gate lines and writes a pre-charging tone signal from the multiple signal lines to the multiple pixels. During the first period, after the pre-charging period, the display gate driver sequentially scans the plurality of gate lines, writing tone signals corresponding to the image signals from the plurality of signal lines to the plurality of pixels; and In the second period, after the first period, none of the plurality of gate lines are selected. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating the first driving method of the display device of the comparative example.

[0011] Figure 2 This is a schematic diagram illustrating a display example of image quality degradation.

[0012] Figure 3 This is a diagram illustrating the second driving method of the display device of the comparative example.

[0013] Figure 4 This is a diagram illustrating an example of the configuration of the display device in Embodiment 1.

[0014] Figure 5 This is a diagram illustrating the tone signal supplied to the display device of Embodiment 1.

[0015] Figure 6 This is a timing diagram illustrating the display device of Embodiment 1.

[0016] Figure 7 This is an explanation Figure 4 The diagram shows an example of the circuit configuration of the logic circuits (GL1, GD1).

[0017] Figure 8 This is an explanation Figure 7 The timing diagram of the logic circuits (GL1, GD1).

[0018] Figure 9 This is a diagram showing a configuration example of the display device in Modified Example 1.

[0019] Figure 10 This is a diagram illustrating the timing of the display device in Modified Example 1.

[0020] Figure 11 This is a diagram showing a configuration example of the display device in Modified Example 2.

[0021] Figure 12 This is a top view schematically showing the configuration of the display device of Modified Example 3, as described in Example 1.

[0022] Figure 13This is a top view schematically showing the configuration of the display device of Modified Example 3, as shown in Example 2.

[0023] Figure 14 It is an explanation and Figure 13 The diagram shows the circuit configuration example corresponding to Example 2 of the display device configuration.

[0024] Figure 15 This is a diagram illustrating a configuration example where the unified pre-charge period is divided into two.

[0025] Figure 16 This is a diagram illustrating a configuration example where the unified pre-charge period is divided into three parts.

[0026] Figure 17 This is a diagram illustrating a configuration example where the number of signal systems for the internal reset signal Int-XRST is increased in accordance with the number of segments during the unified precharge period. Detailed Implementation

[0027] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0028] Furthermore, the disclosure is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are of course included within the scope of this invention. Additionally, the accompanying drawings, in order to make the illustration clearer, sometimes schematically show the width, thickness, shape, etc., of various parts compared to the actual form, but this is merely an example and does not limit the interpretation of the invention.

[0029] In addition, in this specification and the figures, the same reference numerals are sometimes used for elements that are the same as those described with respect to the figures that have already appeared, and detailed descriptions are omitted where appropriate.

[0030] In this embodiment, a liquid crystal display device is disclosed as an example of a display device. This liquid crystal display device can be used in various devices such as AR / VR / MR terminals, smartphones, tablet terminals, mobile phone terminals, personal computers, television receivers, in-vehicle devices, and gaming devices.

[0031] "Display device" refers to all display devices that use a display panel to display images. "Display panel" refers to a structure that uses an electro-optic layer to display images. For example, the term "display panel" sometimes refers to a display unit that includes an electro-optic layer, and sometimes refers to a structure in which a semiconductor device with other optical components (such as polarizing components, backlights, touch panels, etc.) and / or driving circuits such as source driver ICs is mounted on the display unit. Here, "electro-optic layer" can include liquid crystal layers, electrochromic (EC) layers, etc., as long as it does not cause technical contradiction. Therefore, in the embodiments described later, a liquid crystal panel including a liquid crystal layer is exemplified as a display panel, but the application of the above-described display panel including other electro-optic layers is not excluded.

[0032] (Implementation Method) First, use Figure 1 , Figure 2 , Figure 3 To explain the technical issues. Figure 1 This is a diagram illustrating the first driving method of the display device of the comparative example. Figure 2 This is a schematic diagram illustrating a display example of image quality degradation. Figure 3 This is a diagram illustrating the second driving method of the display device of the comparative example.

[0033] exist Figure 1 The diagram shows the driving periods in the Nth frame (N frame) and the (N+1)th frame (N+1 frame) following the Nth frame in the display panel. Within each frame, the following periods are shown as driving periods.

[0034] 1) First period T11: The first period T11 is the period during which the gate lines (also called scan lines: G1, G2, G3...) are scanned sequentially and set to the selected state, and the tone signal (tone potential) corresponding to the image signal is written from the signal line to multiple pixels in one line connected to the gate line in the selected state.

[0035] 2) Second period T12: The second period T12 is the response period of the liquid crystal molecules based on the response speed of the liquid crystal molecules of the pixel on which the tone signal has been written.

[0036] 3) Third period T13: The third period T13 is the period during which the backlight is turned on so that the image is displayed based on the tone signal written to all pixels in the display panel.

[0037] Here, because liquid crystal molecules have an upper limit to their response speed, even if the frame rate is increased to a level higher than the response speed of the liquid crystal molecules, it is impossible to improve the dynamic image characteristics, resulting in uneven brightness and degraded image quality.

[0038] exist Figure 2 The diagram schematically illustrates the image quality degradation when the frame rate is driven at a high frequency exceeding the response speed of the liquid crystal molecules. The display panel DISP, for example, includes 2n gate lines G1, G2, G3, ..., G2n-2, G2n-1, G2n, which are scanned sequentially in the order G1, G2, G3, ..., G2n-2, G2n-1, G2n. This example shows N frames displaying a black image (BB) and N+1 frames displaying a white image (WW).

[0039] For example, in region R11 of the display panel, which contains gate lines G1, G2, and G3 that are scanned initially, the liquid crystal molecules have a sufficient response time, thus displaying normal white (WW). On the other hand, in region R12 of the display panel, which contains gate lines G2n-2, G2n-1, and G2n that are scanned later, the liquid crystal molecules have an insufficient response time, thus not displaying normal white (WW), but rather the image is slightly darker (displaying dark white (DW)).

[0040] That is, if the frame rate is increased to a level above the response speed of the liquid crystal molecules, and the response period T12 of the liquid crystal molecules becomes insufficient, the following problem exists: in the region corresponding to the latter half of the gate line scan (the latter half of the display panel: the region of the display panel corresponding to the gate lines in the latter half of the scan sequence), the liquid crystal response is too slow to achieve the desired brightness.

[0041] To solve this technical problem, such as Figure 3 As shown, a known method involves setting a period TPR1 before the first period T11, during which all pixels are uniformly precharged with a tone signal corresponding to an intermediate tone, such as gray. That is, as a countermeasure, a known method involves uniformly precharging the gray potential of all pixels, for example, using the pixel capacitor (Cs) and the liquid crystal capacitor (Clc), so that during subsequent liquid crystal response periods, the liquid crystal response to white, black, and other gray tones is completed quickly. However, in this case, a technical problem exists: a dedicated source driver IC capable of performing this drive is required.

[0042] (Example 1) Next, use Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 This describes the display device of Embodiment 1.

[0043] Figure 4 This is a diagram illustrating an example of the configuration of the display device in Embodiment 1. Figure 5 This is a diagram illustrating the tone signal supplied to the display device of Embodiment 1. Figure 6 This is a timing diagram illustrating the display device of Embodiment 1. Figure 7 This is an explanation Figure 4 The diagram shows an example of the circuit configuration of the logic circuits (GL1, GD1). Figure 8 This is an explanation Figure 7 The timing diagram of the logic circuits (GL1, GD1).

[0044] like Figure 4As shown, the display device 10 includes a display panel (DISP) and a source driver (driver IC) 100. The display panel (DISP) includes an active region (active area / display area) AA, which is provided with multiple gate lines, multiple signal lines, and multiple pixels; a display gate driver 101; and an additional shift register 102 for pre-charging. The active region AA is formed with multiple pixels (PIX) arranged in a matrix (row and column) along a first direction X and a second direction Y intersecting the first direction X. The multiple pixels (PIX) include, for example, multiple pixels (PIX) for red (R), multiple pixels (PIX) for blue (B), and multiple pixels (PIX) for green (G). In this example, as a representative example, a matrix of multiple pixels (PIX) arranged in 2n rows and 4 columns is depicted, that is, 4 pixels in the first direction X (horizontal direction, row direction) and 2n pixels in the second direction Y (vertical direction, column direction) intersecting the first direction X. The additional shift register 102 for precharging can be renamed as a gate line selection unit for precharging, or as part of a gate driver for display.

[0045] The active region AA is configured with multiple gate lines (Gate_1, Gate_2, ..., Gate_2n) extending along a first direction X and arranged side-by-side in a second direction Y. Gate line Gate_1 is connected to multiple pixels in the first row. Similarly, gate lines (Gate_2, ..., Gate_2n) are each connected to multiple pixels in their corresponding rows. Gate lines can be referred to as scan lines.

[0046] Furthermore, the active region AA is configured with multiple signal lines Sig (Sg1, Sg2, Sg3, Sg4) extending along the second direction Y, and arranged side-by-side in the first direction X. Multiple pixels in the first column are connected to signal line Sg1. Similarly, multiple pixels connected to their corresponding columns are connected to signal lines Sg2, Sg3, and Sg4. These signal lines can be referred to as source lines. Figure 4 In this example, four signal lines are disclosed, but other signal lines can also be set horizontally in Sg4.

[0047] Thin-film transistors (TFTs) are used as switching elements Tr disposed in each pixel PIX. Examples of TFTs include bottom-gate transistors and top-gate transistors. A single-gate TFT is exemplified as the switching element Tr, but a dual-gate transistor can also be used. One of the source and drain electrodes of the switching element Tr is connected to signal lines Sig (Sg1, Sg2, Sg3, Sg4), the gate electrode is connected to the gate line Gate_i (i = 1, 2, ..., 2n) which serves as a scan line, and the other of the source and drain electrodes is connected to the pixel electrodes (P1, P2). The pixel electrodes are positioned opposite a common electrode CE across a liquid crystal LC. The common electrode (CE) is connected to a common potential wiring COML. The liquid crystal LC forms a capacitor Clc by treating the pixel electrodes and the common electrode as a pair of capacitor electrodes. Furthermore, a holding capacitor Cs is formed between the pixel electrodes P1, P2 and the common electrode CE, separated by a dielectric such as an insulating film. Additionally, a common voltage VCOM is supplied to the common potential wiring COML from the common potential drive circuit.

[0048] The display gate driver 101 includes multiple shift registers S / R, gate line select circuits GL1-GL2n, and gate line drive circuits GD1-GD2n. The additional shift register 102 includes multiple shift registers S / R_d, set / reset flip-flops SR-FF, and an AND circuit AN. The gate line select circuits GL1-GL2n and the gate line drive circuits GD1-GD2n can each be constructed using NAND circuits.

[0049] The additional shift register 102 is configured to generate a pre-charge timing signal. The first shift register S / R_d has an input terminal for receiving a start pulse STV, a clock terminal for receiving a transmission clock CKV, a reset signal terminal for receiving a reset signal XRST, and an output terminal for receiving a transmission signal trn_d1.

[0050] The second shift register S / R_d to the m-th shift register S / R_d, like the first shift register S / R_d, have input terminals, a clock terminal for receiving the transmission clock CKV, a reset signal terminal for receiving the reset signal XRST, and output terminals for outputting the corresponding transmission signals trn_dn (n = 2, ..., m). The transmission signals trn_dx are supplied from the preceding shift register S / R_d to the input terminals of the second shift register S / R_d to the m-th shift register S / R_d.

[0051] Similar to the first shift register S / R_d, the transfer clock CTV and reset signal XRST are supplied to the second shift register S / R_d through the m-th shift register S / R_d. The transfer signal trn_d1, an output of the first shift register S / R_d, is provided to the second shift register S / R_d. The transfer signal trn_d2, an output of the second shift register S / R_d, is supplied to the third shift register S / R_d. Similarly, the transfer signals trn_d3 through trn_dm-1, outputs of the third shift register S / R_d through the (m-1)-th shift register S / R_d, are supplied to the next-stage shift register S / R_d. The transfer signal trn_dm, an output of the m-th shift register S / R_d, is supplied to the first shift register S / R of the plurality of shift registers S / R within the display gate driver 101.

[0052] When the first shift register S / R_d receives a high-level reset signal XRST, if the start pulse STV changes from low to high and the transmission clock CKV changes from low to high, it generates a transmission signal trn_d1 and supplies it to the second shift register S / R_d.

[0053] When the transmission clock CKV changes from high to low, the second shift register S / R_d generates the transmission signal trn_d2 and supplies it to the third shift register S / R_d. Thus, the transmission signals trn_dx (x = 1, ..., m) are sequentially transmitted to the shift register S / R_d. Any two signals can be used from the start pulse STV and the transmission signal (trn_dx) appended to the shift register S / R_d to generate a signal that defines (identifies) the uniform precharge period.

[0054] exist Figure 4 In the set / reset type flip-flop (SR-FF), a transmission signal trn_d1 is supplied to the set terminal S, and a transmission signal trn_dm-2 is supplied to the reset terminal R, generating an output signal XQ. When the transmission signal trn_d1 goes high, the output signal XQ changes from high to low. When the transmission signal trn_dm-2 goes high, the output signal XQ changes from low to high. The period of the low level of the output signal XQ is a uniform precharge period. Here, uniform means setting all gate lines (Gate_1, ..., Gate2n) to the selected level (high level: H), and uniformly precharging the pixel electrodes (P1, P2) to the desired step-tuning potential.

[0055] The AND circuit AN is supplied with a reset signal XRST and an output signal XQ. It performs a logical product operation on the reset signal XRST and the output signal XQ to generate an internal reset signal Int-XRST. In this example, a low level of the internal reset signal Int-XRST indicates either the discharge period of the pixel electrodes (P1, P2) or a unified pre-charge period for the pixel electrodes (P1, P2). Alternatively, the additional shift register 102 for pre-charge, the set / reset flip-flop (SR-FF), and the AND circuit AN can be collectively referred to as the pre-charge setting circuit.

[0056] The multiple shift registers S / R within the gate driver 101 have a reset terminal supplied with an internal reset signal Int-XRST and a clock terminal supplied with a transmission clock CKV. The first shift register S / R has an input terminal supplied with a transmission signal trn_dm and an output terminal that generates a transmission signal trn_1 and supplies it to the second shift register S / R. Similarly, the second to (n-1)th shift registers S / R have input terminals supplied with transmission signals trn_1-trn_n-2 and output terminals that generate transmission signals trn_2-trn_n-1 and supply them to the corresponding next-stage shift register S / R. The nth shift register S / R has an output terminal that generates and outputs a transmission signal trn_n.

[0057] In the gate line selection circuits GL1-GL2n, gate line selection circuits GL1, GL3, GL5, ..., GL2n-1 have a first input terminal for receiving the first enable signal EN1, and gate line selection circuits GL2, GL4, GL6, ..., GL2n have a first input terminal for receiving the second enable signal EN2. Additionally, gate line selection circuits GL1 and GL2 have a second input terminal for receiving the transmission signal trn_1, and gate line selection circuits GL3 and GL4 have a second input terminal for receiving the transmission signal trn_2. Similarly, gate line selection circuits (GL5, GL6), ..., gate line selection circuits (GL2n-1, GL2n) have second input terminals for receiving transmission signals trn_3, ..., and transmission signal n. The output terminals of each of the gate line selection circuits GL1-GL2n are connected to the second input terminals of each of the gate line drive circuits GD1-GD2n.

[0058] The first input terminals of each of the gate line drive circuits GD1-GD2n are connected to receive the internal reset signal Int-XRST. The output terminals of each of the gate line drive circuits GD1-GD2n are connected to the gate lines (Gate_1, ..., Gate_2n) respectively.

[0059] Multiplexer 110 is disposed between multiple signal lines Sig and source line driver (driver IC) 100. Multiplexer 110 is configured to include: multiple first switches SW1 that are controlled to be turned on or off according to the level of first selection signal MUX1, and multiple second switches SW2 that are controlled to be turned on or off according to the level of second selection signal MUX2.

[0060] The source line driver 100 includes multiple source line terminals S1, S2... for supplying tone signals to multiple signal lines Sig. The multiplexer 110 and the source line driver 100 can be modified into a signal line drive circuit that supplies tone signals to multiple signal lines.

[0061] The first source terminal S1 is connected to signal line Sg1 via the first switch SW1 and to signal line Sg2 via the second switch SW2. The second source terminal S2 is connected to signal line Sg3 via the first switch SW1 and to signal line Sg4 via the second switch SW2. Figure 4 Other source terminals not described herein are also connected to the signal line (Sgm) via the first switch SW1, and to the signal line (Sgm+1) via the second switch SW2.

[0062] exist Figure 4 In the display device 10, by lowering the internal reset signal Int-XRST generated by the additional shift register 102, the gate line drive circuits GD1-GD2n can select all gate lines (Gate_1, ..., Gate_2n). At this time, the source line driver 100 is configured to supply pre-charging tone signals (tone potentials) to multiple signal lines Sig (Sg1, Sg2, Sg3, Sg4, ...), pre-charging the pixel electrodes (P1, P2, ...) of all pixels PIX using the pre-charging tone signals. Here, the pre-charging tone signals can also be referred to as a third tone signal between the first tone signal corresponding to black and the second tone signal corresponding to white. For example, the pre-charging tone signals can be set to tone signals corresponding to gray.

[0063] Therefore, for example, by pre-charging all pixel electrodes (P1, P2, ...) of all pixels into a tone signal corresponding to gray, the liquid crystal response that responds to the tone signal of white, the tone signal of black, or the tone signal corresponding to gray and other tones can be completed quickly during the subsequent liquid crystal response period T12. Thus, a technique that can improve the characteristics of dynamic images can be provided.

[0064] like Figure 5The diagram illustrates the pre-charge and display periods. The signal output specifications of the source line driver 100 are preferably configured as follows: During the pre-charge period, the maximum number of vertical display levels (rows) is twice (2m) the number of levels m of the multiple shift registers S / R_d included in the additional shift register 102. The source line driver 100 is preferably configured to supply pre-charge tone signals to multiple signal lines Sig during this period. Furthermore, during the display period, the number of vertical display levels (rows) is 2n the number of gate lines (Gate_1, ..., Gate_2n). During this period, the source line driver 100 supplies display tone signals to multiple signal lines Sig.

[0065] Therefore, when generating image signals such as moving images in a data processing device, the image signal is set to a vertical 2 (m+n) level quantity. The first 2m levels are set as tone signals for pre-charging, and the subsequent 2n levels are set as image signals of the actual moving images, etc., displayed in the display panel DISP.

[0066] in addition, Figure 4 , Figure 5 This example illustrates two systems with (m+n) shift registers (S / R_d, S / R) and enable signals (EN1 and EN2). With (m+n) shift registers (S / R_d, S / R) and four enable signals, four (m+n) levels of image signal (including tone signals for pre-charging) are required. With (m+n) shift registers (S / R_d, S / R) and one enable signal, (m+n) levels of image signal (including tone signals for pre-charging) are required. However, the specifications of the source line driver 100 do not depend on the number of enable signal systems.

[0067] Next, use Figure 6 Explain the operation of the display device 10. Figure 6 In this context, S<1:x> represents the state of the source line terminals S1, S2, ... . S<1:x>, the start pulse STV, the transmission clock CKV, the reset signal XRST, the first enable signal EN1, the second enable signal EN2, the first selection signal MUX1, and the second selection signal MUX2 are signals supplied from outside the display device 10. Signals other than those mentioned above are internal signals of the display device 10 (display panel DISP). Here, in the display device 10, as... Figure 3 As explained, a frame has a uniform precharge period TPR1, a first period T11, a second period T12, and a third period T13. Figure 6 The main focus is on the unified pre-charge period TPR1 and the first period T11.

[0068] Initially, the reset signal XRST is set low, and the internal reset signal Int-XRST is set low, discharging the pixel electrodes (P1, P2) of all pixels. At this time, the pixel electrodes (P1, P2) are set to ground potential (GND) of 0V in this example. After the discharge is complete, the reset signal XRST and the internal reset signal Int-XRST are set high.

[0069] Then, a start pulse STV, which changes only once in a pulse pattern, is provided to the first shift register S / R_d. Next, the transmission clock CKV is supplied. In addition, the supply of the first enable signal EN1 and the second enable signal EN2 is started.

[0070] Based on the high level of the start pulse STV and the high level of the transmission clock CKV, the first shift register S / R_d generates a high-level transmission signal trn_d1 and supplies it to the second shift register S / R_d. Based on the high level of the transmission signal trn_d1, the output signal XQ of the set / reset flip-flop (SR-FF) is set from high to low, and the internal reset signal Int-XRST is set from high to low, thus initiating the unified precharge period TPR1. The unified precharge period TPR1 can also be referred to as the precharge period TPR1.

[0071] Subsequently, if the transmission clock CKV changes from high to low in a pulse-like manner, the second shift register S / R_d generates the transmission signal trn_d2 and supplies it to the third shift register S / R_d. Thus, the transmission signals trn_dx (x = 1, ..., m) are sequentially transmitted from the first shift register S / R_d to the m-th shift register S / R_d. The transmission signal trn_dm generated from the m-th shift register S / R_d is supplied to the first shift register S / R. Here, when the transmission signal trn_dm-2 is set from low to high, the internal reset signal Int-XRST is set from low to high, thereby ending the precharge cycle TPR1.

[0072] During the unified precharge period TPR1, regardless of the signal levels of the first enable signal EN1 and the second enable signal EN2, all gate lines (Gate_1, ..., Gate_2n) are set to a high-level selection state via the gate line drive circuits GD1-GD2n. At this time, based on the high levels of the first selection signal MUX1 and the second selection signal MUX2, a tone signal corresponding to gray is supplied from all source terminals (S1, S2, ...) of the source line driver 100 to the corresponding signal lines (Sg1, Sg3, Sg2, Sg4, ...). Thus, the pixel electrodes (P1, P2, ...) of all pixels are uniformly precharged to a tone signal corresponding to gray. When the unified precharge period TPR1 ends, based on the high level of the internal reset signal Int-XRST, all gate lines (Gate_1, ..., Gate_2n) are set to a low-level non-selection state via the gate line drive circuits GD1-GD2n.

[0073] Here, the period from the end of the unified precharge period TPR1 to the generation of the transmission signal trn_1 of the first shift register S / R is defined as the reset release period TRR. The reset release period TRR is the period during which all circuitry of the display gate driver 101 is reset simultaneously. Therefore, it is preferable that the reset release period TRR is sufficient in advance, taking into account the time constant of all circuitry of the display gate driver 101.

[0074] After the reset release period (TRR) ends, the gate line scan of the display gate driver 101 begins during period T11. During period T11, tone signals for effective display are written to each pixel.

[0075] During period T11, when the transmission clock CKV changes from low to high, the first shift register S / R, which receives the transmission signal trn_dm, generates the transmission signal trn_1 and supplies it to the second shift register S / R. Subsequently, if the transmission clock CKV changes from high to low, the second shift register S / R generates the transmission signal trn_2 and supplies it to the third shift register S / R. In this way, the transmission signals trn_x (x = 1, ..., n) are sequentially transmitted from the first shift register S / R to the nth shift register S / R.

[0076] When the transmission signal trn_1 is high and the first enable signal EN1 is high, the gate line Gate_1 is set to the selected state. At this time, since the tone signal corresponding to the image signal is supplied to the signal lines Sg1 and Sg3 at a high level with the first selection signal MUX1, the tone signal is written to the pixel electrode P1 of the corresponding pixel (a plurality of pixels connected to the gate line Gate_1 and the signal lines Sg1, Sg3, ...). Furthermore, since the tone signal corresponding to the image signal is supplied to the signal lines Sg2 and Sg4 at a high level with the second selection signal MUX2, the tone signal is written to the pixel electrode P2 of the corresponding pixel (a plurality of pixels connected to the gate line Gate_1 and the signal lines Sg2, Sg4, ...).

[0077] When the transmission signal trn_1 is high and the second enable signal EN2 is high, the gate line Gate_2 is set to a rotating state. At this time, since the tone signal corresponding to the image signal is supplied to the signal lines Sg1 and Sg3 at a high level of the first selection signal MUX1, the tone signal is written to the pixel electrode P1 of the corresponding pixel (a plurality of pixels connected to the gate line Gate_2 and the signal lines Sg1, Sg3, ...). Furthermore, since the tone signal corresponding to the image signal is supplied to the signal lines Sg2 and Sg4 at a high level of the second selection signal MUX2, the tone signal is written to the pixel electrode P2 of the corresponding pixel (a plurality of pixels connected to the gate line Gate_2 and the signal lines Sg2, Sg4, ...).

[0078] When the transmission signal trn_2 is high and the first enable signal EN1 is high, gate line Gate_3 is selected. When the second enable signal EN2 is high, gate line Gate_4 is selected. At this time, since a tone signal corresponding to the image signal is supplied to signal lines Sg1 and Sg3 at a high level with the first selection signal MUX1, this tone signal is written to the pixel electrode P1 of the corresponding pixel (multiple pixels connected to gate line Gate_3 or Gate_4 and signal lines Sg1, Sg3, ...). Furthermore, since a tone signal corresponding to the image signal is supplied to signal lines Sg2 and Sg4 at a high level with the second selection signal MUX2, this tone signal is written to the pixel electrode P2 of the corresponding pixel (multiple pixels connected to gate line Gate_3 or Gate_4 and signal lines Sg2, Sg4, ...).

[0079] Subsequently, when the transmission signals trn_3, ..., trn_n are high, the corresponding gate line is selected based on the first enable signal EN1 and the second enable signal EN2, and the tone signal corresponding to the image signal is supplied to the corresponding signal line based on the first selection signal MUX1 and the second selection signal MUX2. The tone signal is written into the pixel electrode (P1, P2) in the corresponding pixel (multiple pixels connected to the corresponding gate line and the corresponding signal line).

[0080] After writing tone signals to multiple pixels connected to the gate line Gate_2n (after T11 ends), as follows Figure 3 As explained in the document, the periods are set as T12 and T13.

[0081] Therefore, during the pre-charge period TPR1, the tone signal corresponding to gray is uniformly pre-charged to the pixel electrodes (P1, P2, ...) of all pixels. Then, during period T11, the tone signal corresponding to the image signal is written to the pixel electrodes (P1, P2, ...) of all pixels. Then, during the liquid crystal molecule response period T12, the liquid crystal response, which responds to the tone signal of white, the tone signal of black, or the tone signal corresponding to gray and other tones, is rapidly completed. Therefore, a technique that improves dynamic image characteristics can be provided.

[0082] Next, use Figure 7 , Figure 8 The diagram illustrates an example of the circuit configuration of the gate line selection circuit GL (GL1-GL2n) and the gate line drive circuit GD (GD1-GD2n) within the gate driver 101, and demonstrates the operation of the gate driver 101.

[0083] like Figure 7 As shown, the gate line selection circuit GL includes an inverter IV1, a P-channel transistor Q1, an N-channel transistor Q2, and an N-channel transistor Q3.

[0084] The output terminal of the shift register S / R, which outputs the transmission signal trn, is connected to the input terminal of inverter IV1, the gate terminal of transistor Q1, and the gate terminal of transistor Q3. The source terminal of transistor Q1 is connected to receive the internal reset signal Int-XRST. The source-drain paths of transistor Q1 and transistor Q3 are connected in series, and the source terminal of transistor Q3 is connected to a low-potential wiring VGL, which is supplied with a low level to the gate line Gate_i. The source-drain paths of transistor Q2 and transistor Q1 are connected in parallel, and the gate terminal of transistor Q2 is connected to the output terminal of inverter IV1, which outputs the inverted signal xtrn of the transmission signal trn.

[0085] The gate line drive circuit GD includes a P-channel transistor Q4, an N-channel transistor Q5, an N-channel transistor Q6, and a P-channel transistor Q7. The source terminal of transistor Q4 is connected to receive a first enable signal EN1 (or a second enable signal EN2). The drain terminal of transistor Q4 is connected to the gate line Gate_i. The source-drain path of transistor Q4 is connected in series with the source-drain path of transistor Q6. The gate terminal of transistor Q6 is connected to the drain terminal of transistor Q1, and the source terminal of transistor Q6 is connected to a low-potential wiring VGL, which is supplied with a low level to the gate line Gate_i. The source-drain path of transistor Q5 is connected in parallel with the source-drain path of transistor Q4, and the gate terminal of transistor Q5 is connected to the gate terminal of transistor Q1. The gate terminal of transistor Q7 is connected to receive an internal reset signal Int-XRST. The source-drain path of transistor Q7 is connected between the high potential VGH wiring, which is supplied with a high level of gate line Gate_i, and the gate line Gate_i.

[0086] like Figure 8 As shown, the operation of the gate driver 101 is related to... Figure 6 The same applies to the discharge period, the unified precharge period TPR1, the reset release period TRR, and the gate line scan period T11 for performing the display gate driver 101.

[0087] First, when the internal reset signal Int-XRST is set low, it enters the discharge period. During this time, transistor Q7 is turned on, and the gate line Gate_i is set to a high selection state. Additionally, the transmission signal trn is low, and its inversion signal xtrn is high. Therefore, transistors Q1 and Q2 are turned on, transistor Q3 is turned off, signal trnR is low, and transistors Q4, Q5, and Q6 are turned off.

[0088] After the discharge period ends, the internal reset signal Int-XRST is set high. The transmission signal trn is low, and its inversion signal xtrn is high. Therefore, transistors Q1 and Q2 are turned on, transistor Q7 is turned off, the signal trnR is set high, so transistor Q6 is turned on, and the gate line Gate_i is set to a low, non-selected state.

[0089] Then, the unified precharge period TPR1 begins. At this time, the internal reset signal Int-XRST is set low, thus, similar to the discharge period, transistor Q7 is turned on, and the gate line Gate_i is set high. Here, the transmission clock CKV, the first enable signal EN1, and the second enable signal EN2 are provided. At this time, the source line driver 100 supplies tone signals corresponding to gray to all signal lines to perform precharge of all pixels.

[0090] This is followed by the reset release period (TRR). During this time, the internal reset signal Int-XRST is set high. The transmission signal trn is low, and its inversion signal xtrn is high. Similar to the end of the discharge period, the gate line Gate_i is set to a low, non-selected state.

[0091] After the reset release period TRR ends, the gate line scan of the display gate driver 101 begins during period T11. During period T11, tone signals for effective display are written to each pixel. Here, the internal reset signal Int-XRST is high, the transmission signal trn is high, and its inversion signal xtrn is low. Therefore, transistors Q1 and Q2 are off, and transistor Q7 is off. Transistors Q3, Q4, and Q5 are on, and the signal trnR is low, so transistor Q6 is off. Since transistors Q3 and Q4 are on, the gate line Gate_i is set to a high-level selection state based on the high level of the first enable signal EN1 (or the second enable signal EN2).

[0092] (Variation Example 1) exist Figure 4 In the example shown, multiple shift registers S / R within the gate driver 101 are supplied with an internal reset signal Int-XRST. However, the reset of the multiple shift registers S / R can also be achieved using the reset signal XRST. In Modification 1, an example of supplying the reset signal XRST to the multiple shift registers S / R will be described.

[0093] The following uses Figure 9 , Figure 10 Explain the display device of Modified Example 1. Figure 9 This is a diagram showing a configuration example of the display device in Modified Example 1. Figure 10 This is a diagram illustrating the timing of the display device in Modified Example 1.

[0094] Figure 9 The display device 10a and Figure 4 The difference between the display device 10 and the display device 10a is that, in the display device 10a, a reset signal XRST is supplied to a plurality of shift registers S / R. Figure 9Other components of the display device 10a and Figure 4 The other components of the display device 10 are the same, so repeated descriptions are omitted.

[0095] exist Figure 9 In this circuit, wiring L9 is provided to supply the reset signal XRST, which is supplied to one terminal of the AND logic circuit AN, to multiple shift registers S / R.

[0096] For the multiple shift registers S / R within the display gate driver 101, a reset release operation can be performed when the reset signal XRST becomes high.

[0097] The internal reset signal Int-XRST only needs to reset the last logic NAND circuit, namely the gate line drive circuit GD (GD1-GD2n). Therefore, the reset release time (TRR) can be shortened.

[0098] In the layout configuration area of ​​the gate driver 101 for display, a wiring L9 for the reset signal XRST also needs to be formed. Furthermore, it is believed that if the number of wirings L9 is about one, the impact on the layout configuration will be less significant.

[0099] Figure 10 Timing of display device 10a Figure 6 The timing difference of the display device 10 is that, after the discharge period, the reset release (TRR_SR) of multiple shift registers S / R in the display gate driver 101 is set. Figure 10 Other timing of the display device 10a Figure 4 The other timings of the display device 10 are the same, so repeated descriptions are omitted.

[0100] (Variation Example 2) In Embodiment 1, a display device 10 capable of unified precharging by adding an additional shift register 102 is described. Here, if it is possible to select whether to perform unified precharging, then in cases where it is difficult to determine which display panel DISP has the better pixel count and driving frequency during the design phase, it is possible to evaluate after the display panel DISP is manufactured and then decide on a particular one.

[0101] In Modification Example 2, a configuration example of a display device 10b that can select "with uniform precharge / without uniform precharge" based on a control signal is described. Figure 11 This is a diagram showing a configuration example of the display device in Modified Example 2. Figure 11 The display device 10b and Figure 4 The difference between the display device 10 and the display device 10b is that a control circuit CTRC is provided in the display device 10b. Figure 11Other components of the display device 10b and Figure 4 The other components of the display device 10 are the same, so repeated descriptions are omitted.

[0102] The operation of the control circuit CTRC is controlled by the control signal RCTL. When the control signal RCTL is high, the control circuit CTRC is configured to supply the start pulse STV to the first shift register S / R within the display gate driver 101, thus becoming a display device 10b without uniform precharge. On the other hand, when the control signal RCTL is low, the control circuit CTRC is configured to supply the start pulse STV to the first shift register S / R_d of the additional shift register 102, and is configured to supply the transmission signal trn_dm of the output of the m-th shift register S / R_d of the additional shift register 102 to the first shift register S / R within the display gate driver 101, thus becoming a display device 10b with uniform precharge. That is, the control circuit CTRC can be regarded as a control circuit that controls the activation and deactivation of the additional shift register 102.

[0103] The control circuit CTRC includes an inverter IV10, N-channel transistors Q10, Q12, Q14, and Q17, and P-channel transistors Q11, Q15, and Q16.

[0104] The input terminal of inverter IV10 is connected to the wiring of the supplied control signal RCTL, and the output terminal of inverter IV10 is connected to the gate terminals of transistors Q10, Q15, and Q17 respectively. The gate terminals of transistors Q11, Q12, Q14, and Q16 are connected to the wiring of the supplied control signal RCTL.

[0105] The source-drain path of transistor Q10 is connected in parallel with the source-drain path of transistor Q11, and in series with the source-drain path of transistor Q12.

[0106] The source-drain path of transistor Q10 is connected to the wiring supplied with the start pulse STV, and the source-drain path of transistor Q12 is connected to the wiring supplied with a low potential VGL, such as the low level of the gate line Gate. The common connection point of the source-drain paths of transistors Q10 and Q12 is connected to the input terminal of the first shift register S / R_d of the additional shift register 102.

[0107] The source-drain path of transistor Q14 is connected in parallel with the source-drain path of transistor Q15, and in series with the source-drain path of transistor Q16. The source-drain path of transistor Q16 is also connected in parallel with the source-drain path of transistor Q17. The source-drain path of transistor Q14 is connected to the wiring for the supplied start pulse STV, and the source-drain path of transistor Q16 is connected to the wiring for the supplied transmission signal trn_dm. The common connection point of the source-drain paths of transistors Q14 and Q16 is connected to the input terminal of the first shift register S / R within the display gate driver 101.

[0108] When the control signal RCTL is high, transistors Q12, Q14, and Q15 are turned on, while transistors Q10, Q11, Q16, and Q17 are turned off. Consequently, a start pulse STV is supplied to the input terminal of the first shift register S / R within the display gate driver 101, and a low potential VGL is supplied to the input terminal of the first shift register S / R_d of the additional shift register 102. Therefore, the display device 10b is configured without uniform pre-charge.

[0109] When the control signal RCTL is low, transistors Q10, Q11, Q16, and Q17 are turned on, while transistors Q12, Q14, and Q15 are turned off. Consequently, the start pulse STV is supplied to the input terminal of the first shift register S / R_d of the additional shift register 102, and the transmission signal trn_dm output from the m-th shift register S / R_d of the additional shift register 102 is supplied to the input terminal of the first shift register S / R within the display gate driver 101. Therefore, the display device 10b is configured to have a unified precharge.

[0110] (Variation Example 3) Modification 3 examines the configuration in which an additional shift register 102 is provided in the display device 10c (10, 10a, 10b).

[0111] Figure 12 This is a top view schematically showing the configuration of the display device of Modified Example 3, as described in Example 1. Figure 13 This is a top view schematically showing the configuration of the display device of Modified Example 3, as shown in Example 2. Figure 14 It is an explanation and Figure 13 The diagram shows the circuit configuration example corresponding to Example 2 of the display device configuration.

[0112] like Figure 12As shown, when viewed from above, the rectangular active region AA of the display panel DISP is positioned in the central part, and display gate drivers 101 are arranged in the left and right regions of the active region AA. In this example, since there is a surplus configuration in the upper region of the active region AA, additional shift registers 102 are arranged in two locations in the upper region of the active region AA corresponding to the upper side of the display gate driver 101 (on the side opposite to the source line driver 100, based on the display gate driver 101). A multiplexer 110 is arranged in the lower region of the active region AA.

[0113] The display panel (DISP) is provided with pads FPCPAD for connection to a flexible printed circuit board (FPC), and is connected to the FPC. A multiplexer 110 and a source line driver 100 are arranged between the pads FPCPAD and the active area AA. Wiring LL is arranged between the source line driver 100 and the multiplexer 110. Although not shown, wiring is also arranged between the source line driver 100 and the pads FPCPAD.

[0114] Figure 13 The display device 10d and Figure 12 The difference in the display device 10c is that, when viewed from above, the configuration area of ​​the additional shift register 102 is located in two areas corresponding to the lower side of the display gate driver 101 (the same side as the source line driver 100 based on the display gate driver 101). This is in the case where the area above the active region AA is narrow and the area where the additional shift register 102 is configured is not located in the area above the active region AA, such as... Figure 13 As shown, the additional shift register 102 is preferably configured in two regions corresponding to the lower side of the display gate driver 101 (two regions on the lower side of the display panel DISP). Figure 13 Other components of the display device 10d and Figure 12 The other components of the display device 10c are the same, so repeated descriptions are omitted.

[0115] Figure 14 The circuit configuration example corresponding to the configuration example 2 of the display device 10d shown is the same as... Figure 4 The difference in the circuit configuration example of the display device 10 is that the additional shift register 102a is disposed below the display gate driver 101, and the transmission signal trn_dm output by the m-th shift register S / R_d of the additional shift register 102a is supplied to the input terminal of the first shift register S / R in the display gate driver 101 via a relatively long wiring LL14. The additional shift register 102a is disposed below the display gate driver 101. Figure 13 The two areas corresponding to the lower side of the display gate driver 101 ( Figure 13 (The additional shift register 102 portion). Since a relatively long wiring LL14 is used, it is preferable to place a buffer circuit BUF in the middle of the wiring LL14 to amplify the transmitted signal trn_dm and transmit it. Figure 14 Other components of the display device 10d and Figure 4 The other components of the display device 10 are the same, so repeated descriptions are omitted.

[0116] (Variation Example 4) In Variation 4, a configuration is shown that divides the unified precharge period into multiple parts instead of one. Figure 15 This is a diagram illustrating a configuration example where the unified pre-charge period is divided into two. Figure 16 This is a diagram illustrating a configuration example where the unified pre-charge period is divided into three parts. Figure 17 This is a diagram illustrating a configuration example where the number of signal systems for the internal reset signal Int-XRST is increased in accordance with the number of segments during the unified precharge period.

[0117] Even when uniform precharging is performed, if the difference in liquid crystal response between the top and bottom of the screen is not fully filled, it can divide TPR1 during uniform precharging into two segments ( Figure 15 TPR11, TPR12), Triple Division ( Figure 16 Methods for precharging different step-modulation potentials, such as TPR11, TPR12, TPR13, etc.

[0118] In the first unified precharge period (TPR11), similarly to the unified precharge period TPR1, all pixels are precharged to a tone signal corresponding to gray. The tone signal used for precharging can also be referred to as a third tone signal between the first tone signal corresponding to black and the second tone signal corresponding to white. In the second unified precharge period (TPR12), for example, all pixels are precharged to a fourth tone signal between the second and third tone signals. In the third unified precharge period (TPR13), all pixels are precharged to a fifth tone signal between the second and fourth tone signals. Alternatively, in the second unified precharge period TPR12, for example, all pixels are precharged to a fourth tone signal between the first and third tone signals. In the third unified precharge period TPR13, all pixels are precharged to a fifth tone signal between the first and fourth tone signals.

[0119] In this case, such as Figure 17As shown, the number of signal systems for the internal reset signal Int-XRST can be increased to match the number of segments during the unified precharge period, as in the case of the first internal reset signal Int-XRST1, the second internal reset signal Int-XRST2, and the third internal reset signal Int-XRST3.

[0120] If reference Figure 9 The circuit configuration of the display device 10a is easy to understand. For example, it can be configured such that a first internal reset signal Int-XRST1 is supplied to the gate line drive circuits GD1-GD2n, a second internal reset signal Int-XRST2 is supplied to the gate line drive circuits GD1-GD2n, and a third internal reset signal Int-XRST3 is supplied to the gate line drive circuits GD(i+1)-GD1. The gate line drive circuits GD1-GD1 can select a first plurality of gate lines (Gate_1, ..., Gate_2n). The gate line drive circuits GD(i+1)-GD1 can select a second plurality of gate lines (Gate_i+1, ..., Gate_1) from the plurality of gate lines (Gate_1, ..., Gate_2n). The gate line driving circuit GD(l+1)-GD2n can be used to select a third or more gate lines (Gate_l+1, ..., Gate_2n) from a plurality of gate lines (Gate_1, ..., Gate_2n).

[0121] It can prepare three groups of set / reset flip-flops (SR-FF) and logic AND circuits AN. The first group generates the first internal reset signal Int-XRST1, the second group generates the second internal reset signal Int-XRST2, and the third group generates the third internal reset signal Int-XRST3.

[0122] In the first set / reset flip-flop (SR-FF) of the first group, a transmission signal tnr_d1 is supplied to the set terminal S, and a transmission signal trn_di is supplied to the reset terminal R. A first internal reset signal Int-XRST1 is generated from the first logic AND circuit AN of the first group.

[0123] In the second set / reset type flip-flop (SR-FF) of the second group, a transmission signal tnr_d(i+1) is supplied to the set terminal S, and a transmission signal trn_dl is supplied to the reset terminal R. The second internal reset signal Int-XRST2 is generated from the second logic AND circuit AN of the second group.

[0124] In the third set / reset flip-flop (SR-FF) of the third group, a transmission signal tnr_d(l+1) is supplied to the set terminal S, and a transmission signal trn_dm-2 is supplied to the reset terminal R. The third internal reset signal Int-XRST3 is generated from the third logic AND circuit AN of the third group.

[0125] Therefore, by dividing the precharge period into segments and precharging with different tonal potentials in each unified precharge period, the liquid crystal response difference between the top and bottom of the screen can be significantly reduced. This provides a technique that improves dynamic image characteristics.

[0126] As embodiments of this disclosure, all display devices that can be implemented by those skilled in the art based on the above-described display device with appropriate design modifications, as long as they contain the spirit of this invention, fall within the scope of this invention.

[0127] Within the scope of the present invention, those skilled in the art will be able to conceive of various modifications and alterations, which also fall within the scope of the present invention. For example, solutions obtained by appropriately adding, deleting, or designing the constituent elements of the above-described embodiments, or solutions obtained by adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention as long as they possess the spirit of the present invention.

[0128] Furthermore, any other effects resulting from the methods described in this embodiment, effects that are obvious from the description in this specification, or effects that can be reasonably conceived by those skilled in the art, should of course be understood as being brought about by the present invention.

[0129] Furthermore, various inventions can be formed by appropriately combining the multiple constituent elements disclosed in the above embodiments. For example, several constituent elements may be deleted from all the constituent elements shown in the embodiments. Moreover, constituent elements of different embodiments may be appropriately combined.

[0130] Explanation of reference numerals in the attached figures 10, 10a, 10b, 10c, 10d: Display devices; 100: Source driver (driver IC); 101: Gate Driver for Display. 102: Additional shift register for pre-charging (gate line selection unit for pre-charging); Gate_1, Gate_2, ..., Gate_2n: Gate lines (scan lines); Sig, Sg1, Sg2, Sg3, Sg4: Signal lines (source lines); T11: First period; T12: Second period; DISP: Display Panel; AA: Active region; PIX: pixel; X: First direction; Y: Second direction; S / R_d: Shift register; S / R: Shift register; GL1-GL2n: Gate line selection circuit; GD1-GD2n: Gate line drive circuit.

Claims

1. A display device, wherein, have: Multiple gate lines extend in a first direction and are arranged side by side in a second direction that intersects the first direction; Multiple signal lines extend in the second direction and are arranged side by side in the first direction; Multiple pixels are arranged in a matrix in the first direction and the second direction; A gate driver for display sequentially scans the plurality of gate lines; as well as The pre-charge gate line selection unit selects all of the plurality of gate lines uniformly. One frame contains: During the pre-charging period, the gate line selection unit for pre-charging uniformly selects multiple gate lines and writes a pre-charging tone signal from the multiple signal lines to the multiple pixels. During the first period, after the pre-charging period, the display gate driver sequentially scans the plurality of gate lines and writes tone signals corresponding to image signals from the plurality of signal lines to the plurality of pixels. as well as In the second period, following the first period, none of the plurality of gate lines are selected.

2. The display device according to claim 1, wherein, The pre-charging tone signal corresponds to the third tone signal between the first tone signal corresponding to black and the second tone signal corresponding to white.

3. The display device according to claim 2, wherein, The pre-charge period includes a first pre-charge period and a second pre-charge period following the first pre-charge period. During the first pre-charge period, a first plurality of gate lines are selected from the plurality of gate lines, and the third tone signal is written from the plurality of signal lines to all pixels connected to the first plurality of gate lines. During the second pre-charge, a second plurality of gate lines, which are different from the first plurality of gate lines, are selected, and a fourth tone signal between the third tone signal and the second tone signal is written from the plurality of signal lines to all pixels connected to the second plurality of gate lines.

4. The display device according to claim 1, wherein, It has a display panel. The display panel has an active area including the plurality of gate lines, the plurality of signal lines, and the plurality of pixels. When viewed from above, the display panel... The rectangular active region is positioned in the central portion. The display gate driver is configured in the left and right regions of the active region. The pre-charging gate line selection section is disposed in the region corresponding to the upper side of the display gate driver.

5. The display device according to claim 1, wherein, It has a display panel. The display panel has an active area including the plurality of gate lines, the plurality of signal lines, and the plurality of pixels. When viewed from above, the display panel... The rectangular active region is positioned in the central portion. The display gate driver is configured in the left and right regions of the active region. The pre-charging gate line selection section is disposed in the region corresponding to the lower side of the display gate driver.

6. The display device according to claim 1, wherein, It has a source line driver that supplies a step signal to the plurality of signal lines.

7. The display device according to claim 1, wherein, It has a control circuit that controls the activation and deactivation of the gate line selection section for pre-charging.

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