Cholesteric liquid crystal display circuit, driving method thereof and electronic paper

Abstract

The application discloses a cholesteric liquid crystal display circuit, a driving method thereof and electronic paper, and relates to the technical field of cholesteric liquid crystal display. The voltage time sequence of the gate drive circuit, the source drive circuit and the common electrode end is set. In different time periods, when the corresponding pixel is in a liquid crystal torsion state, the gate-source voltage of the switching transistor is the same; when the corresponding pixel is in a liquid crystal non-torsion state, the gate-source voltage of the switching transistor is the same. In different time periods, when the corresponding pixel is in a liquid crystal torsion state, the source electrode voltage of the switching transistor is greater than the common electrode end; when the corresponding pixel is in a liquid crystal non-torsion state, the source electrode voltage of the switching transistor is less than the common electrode end. Not only the size relationship between the source electrode voltage of the switching transistor and the voltage of the common electrode end is switched to prevent liquid crystal polarization, but also the bistable failure, the reflectivity reduction or the state mis-switching of the cholesteric liquid crystal display panel caused by the leakage in the long-time static keeping process can be inhibited, the picture keeping time is prolonged, and the display reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of cholesteric liquid crystal display technology, and more particularly to a cholesteric liquid crystal display circuit, its driving method, and electronic paper. Background Technology

[0002] Cholesteric liquid crystal displays (Ch-LCDs) are bistable display devices that utilize the switching between planar and focal conic states of cholesteric liquid crystal molecules under the influence of an electric field to achieve image display. They can maintain image display without continuous power supply. Frame inversion driving is widely used to avoid ion polarization of the liquid crystal material due to long-term unidirectional voltage driving; this is achieved by alternately refreshing positive and negative frames. Unlike conventional nematic liquid crystal displays, cholesteric liquid crystal panels are bistable display devices that consume power only during image refresh and require no power supply during static image retention. Therefore, the requirements for leakage current in pixel units are extremely stringent. Due to differences in the type and switching characteristics of switching transistors, the leakage current of transistors in one type of refresh frame is usually much greater than that in another type of frame. This leakage current in cholesteric liquid crystal panels can lead to bistable failure during long-term static retention, resulting in problems such as fading of display content, decreased reflectivity, and even incorrect switching between bistable states.

[0003] Therefore, how to reduce the impact of transistor leakage current under specific polarities on the bistable state retention performance in cholesteric liquid crystal display panels is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides a cholesteric liquid crystal display circuit, its driving method, and electronic paper, to at least solve the problem in the related art where frame inversion driving methods cause leakage current in transistors under specific polarities in the cholesteric liquid crystal display panel, which seriously affects the bistable performance.

[0005] To solve the above-mentioned technical problems, the present invention provides a cholesteric liquid crystal display circuit, comprising: multiple pixel units, a gate driving circuit, a source driving circuit, and a common terminal. The pixel unit includes a switching transistor and a pixel capacitor. The gate of the switching transistor is connected to the corresponding gate signal line, the source of the switching transistor is connected to the corresponding data signal line, the drain of the switching transistor is connected to the first terminal of the pixel capacitor, and the second terminal of the pixel capacitor is used to connect to the common terminal. The gate driving circuit is connected to the gate signal line, and the source driving circuit is connected to the data signal line; The gate drive circuit, the source drive circuit, and the common terminal are configured as follows: In the first time period, when the corresponding pixel is in the first color display state, the gate-source voltage of the switching transistor is the first voltage, and the source voltage of the switching transistor is greater than the common terminal. When the corresponding pixel is in the second color display state, the gate-source voltage of the switching transistor is the second voltage. In the second time period that does not overlap with the first time period, when the corresponding pixel is in the first color display state, the gate-source voltage of the switching transistor approaches the first voltage, and the source voltage of the switching transistor is less than the common terminal. When the corresponding pixel is in the second color display state, the gate-source voltage of the switching transistor approaches the second voltage. The first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

[0006] To address the aforementioned technical problems, the present invention also provides an electronic paper comprising the cholesteric liquid crystal display circuit described in any one of the preceding claims.

[0007] To solve the above-mentioned technical problems, the present invention also provides a driving method for a cholesteric liquid crystal display circuit, applied to the cholesteric liquid crystal display circuit described in any one of the above claims, comprising: In the first time period, the voltage timing of the gate driving circuit, the source driving circuit and the common terminal is controlled so that the gate-source voltage of the switching transistor is controlled to be a first voltage and the source voltage of the switching transistor is greater than that of the common terminal so that the corresponding pixel is in a first color display state. The gate-source voltage of the switching transistor is controlled to be a second voltage so that the corresponding pixel is in a second color display state. In the second time period, the voltage timing of the gate driving circuit, the source driving circuit and the common terminal is controlled so that the gate-source voltage of the switching transistor approaches the first voltage and the source voltage of the switching transistor is less than the common terminal, so that the corresponding pixel is in the first color display state, and the gate-source voltage of the switching transistor approaches the second voltage so that the corresponding pixel is in the second color display state. Wherein, the first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

[0008] Through this invention, by setting the voltage timing of the gate driving circuit, the source driving circuit, and the common terminal, the gate-source voltage of the switching transistor tends to converge when the corresponding pixel is in the first color display state, and the gate-source voltage of the switching transistor tends to converge when the corresponding pixel is in the second color display state. The difference is that, in different time periods, when corresponding to the first color display state, the source voltage of the switching transistor is greater than that of the common terminal, and when corresponding to the second color display state, the source voltage of the switching transistor is less than that of the common terminal. The first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state. Compared to the positive and negative frame modes in traditional frame inversion driving schemes, in the first and second time periods of this invention, the relationship between the source voltage of the switching transistor and the voltage at the common terminal is reversed, achieving the effect of preventing liquid crystal polarization in the positive and negative frame modes. At the same time, in the first and second time periods, the gate-source activation voltage of the switching transistor is driven, and the gate-source deactivation voltage also tends to be the same. This can effectively avoid leakage caused by incomplete switching of the switching transistor in one time period compared to the other, suppress bistable failure, decreased reflectivity, or incorrect state switching caused by leakage during long-term static holding of the cholesteric liquid crystal display panel, extend the image holding time, and improve display reliability. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a cholesteric liquid crystal display driving circuit; Figure 2 This is a timing diagram of a traditional frame inversion drive. Figure 3 A schematic diagram of a display circuit provided in an embodiment of the present invention; Figure 4 This invention provides a timing diagram for a frame inversion driver. Figure 5 This is a power supply circuit diagram for a common electrode provided in an embodiment of the present invention. Figure 6 This is a front-end power supply circuit diagram provided for an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0012] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Here, we will first explain some key terms used in the embodiments of the present invention.

[0015] Cholesteric liquid crystal displays (Ch-LCDs) are reflective display devices that utilize the unique helical structure of cholesteric liquid crystal molecules. Unlike conventional nematic liquid crystals, which require continuous power to maintain the image, cholesteric liquid crystals exhibit bistable characteristics: a driving voltage is only required when switching images; once the switching is complete, the image remains stable even when power is completely cut off. Therefore, they are particularly suitable for static display applications such as electronic paper and electronic shelf labels.

[0016] The display principle of cholesteric liquid crystal is as follows: In terms of electrical characteristics, the cholesteric liquid crystal material sandwiched between two electrodes can be equivalent to a parallel plate capacitor, i.e., a pixel capacitor. The arrangement state of the liquid crystal molecules is controlled by the voltage difference across its two ends, and there are mainly two stable states: planar state and focal conic state.

[0017] Planar alignment (bright state): When a voltage pulse of specific amplitude and width is applied, the liquid crystal molecules align in a spiral shape with the spiral axis perpendicular to the substrate. This structure selectively reflects ambient light of specific wavelengths, and the corresponding pixel displays in a bright state. The color of the reflected light is determined by the pitch of the spiral. By adjusting the liquid crystal material, reflections of different colors such as red, green, and blue can be achieved.

[0018] Focused conical alignment state (dark state): When voltage pulses of different amplitudes or waveforms are applied, the helical structure of the liquid crystal molecules is disrupted, forming a disordered structure. At this time, selective reflection no longer occurs, and ambient light is scattered or absorbed by the light-absorbing layer behind it. The corresponding pixel is displayed as dark (usually black or dark).

[0019] Unlike conventional nematic liquid crystals, cholesteric liquid crystals do not require continuous power supply to maintain their state in either planar or focal conic states. Only when switching images is required does a driving voltage need to be applied briefly. By controlling the voltage difference across the pixel capacitor, the liquid crystal is driven to switch between planar and focal conic states or maintain a certain intermediate state, thereby achieving the display of different gray levels or colors.

[0020] In monochrome display applications, cholesteric liquid crystals typically use a white reflective state as the bright state (by adjusting the pitch to reflect broadband white light or by combining it with fluorescent materials), and a focal conic state as the dark state (black). The display of monochrome grayscale is achieved by controlling the switching voltage and timing.

[0021] In color display applications, each complete color pixel is further divided into three sub-pixels: red, green, and blue. Each sub-pixel independently controls the alignment of its cholesteric liquid crystal. For example, when the red sub-pixel is in a planar state (reflecting red light) and the green and blue sub-pixels are in a focal conic state (dark state), the human eye perceives red as a mixture. By independently controlling the three sub-pixels to be in a planar state (reflective), a focal conic state (non-reflective), or an intermediate state between the two, full-color display is achieved. Figure 1 This is a schematic diagram of a cholesteric liquid crystal display driving circuit. Figure 1 As shown, the driving circuit includes multiple gate signal lines (G1, G2, G3, G4...) extending along the row direction and multiple data signal lines (S1, S2, S3...) extending along the column direction. The multiple gate signal lines and multiple data signal lines intersect to define multiple pixel units. Each pixel unit includes a thin-film transistor (TFT) as a switching element and a pixel capacitor (LC). The gate of the TFT is connected to the corresponding gate signal line, the source is connected to the corresponding data signal line, the drain is connected to the first terminal of the pixel capacitor, and the second terminal of the pixel capacitor is used to connect to a common voltage (Vcom).

[0022] Figure 2 This is a timing diagram for a traditional frame inversion driven system. (Example:) Figure 2As shown, in progressive scan driving, the gate driving circuit sequentially outputs high-voltage pulses (as shown by G1, G2, G3, and G4) to each gate signal line to turn on the corresponding thin-film transistors (TFTs) line by line. Simultaneously, the source driving circuit outputs data voltages to the turned-on pixel units through each data signal line. Specifically, to prevent liquid crystal polarization, this driving circuit employs a frame inversion method, alternately performing positive and negative frame refreshes: during a positive frame, the source driving circuit outputs a positive voltage according to the grayscale that the pixel should display (e.g., +17.5V for black, 0V for white); during a negative frame, the source driving circuit outputs a negative voltage (e.g., -17.5V for black, 0V for white), while the common voltage (Vcom) remains at 0V. However, when NMOS transistors are used, the gate-source voltage difference is positive during negative frame refresh, causing the TFTs to not be completely turned off, resulting in leakage current much greater than that during positive frame refresh. Unlike conventional liquid crystal displays (LCDs), cholesteric liquid crystal displays are bistable displays, capable of maintaining static images for weeks or months, placing extremely stringent requirements on the leakage current of pixel units. Due to the aforementioned leakage current differences, the pixel voltage slowly decays over time, causing a gradual decrease in the reflectivity of the planar (bright) state of the cholesteric liquid crystal, and even leading to a mis-switching to the focal conic (dark) state. This manifests as gradual fading of the displayed content, bistable failure, and incorrect image information. Conversely, when PMOS transistors are used in thin-film transistors, the leakage current problem becomes even more severe, similarly leading to a deterioration in the aforementioned bistable retention performance.

[0023] To address this, this invention provides a cholesteric liquid crystal display scheme. By setting the voltage timing of the gate driving circuit, the source driving circuit, and the common terminal, the gate-source voltage of the switching transistor tends to converge when the corresponding pixel is in the first color display state, and the gate-source voltage of the switching transistor tends to converge when the corresponding pixel is in the second color display state. The difference is that, in different time periods, when corresponding to the first color display state, the source voltage of the switching transistor is greater than that of the common terminal, and when corresponding to the second color display state, the source voltage of the switching transistor is less than that of the common terminal. The first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state. Compared to the positive and negative frame modes in traditional frame inversion driving schemes, in the first and second time periods of this invention, the relationship between the source voltage of the switching transistor and the voltage at the common terminal is reversed, achieving the effect of preventing liquid crystal polarization in the positive and negative frame modes. At the same time, in the first and second time periods, the gate-source activation voltage of the switching transistor is driven, and the gate-source deactivation voltage also tends to be the same. This can effectively avoid leakage caused by incomplete switching of the switching transistor in one time period compared to the other, suppress bistable failure, decreased reflectivity, or incorrect state switching caused by leakage during long-term static holding of the cholesteric liquid crystal display panel, extend the image holding time, and improve display reliability.

[0024] Figure 3 This is a schematic diagram of the structure of a cholesteric liquid crystal display circuit provided in an embodiment of the present invention; Figure 4 This is a timing diagram of a frame inversion drive provided in an embodiment of the present invention.

[0025] The cholesteric liquid crystal display circuit provided in this embodiment of the invention may include: multiple pixel units, a gate driving circuit, a source driving circuit, and a common electrode.

[0026] The pixel unit includes a switching transistor and a pixel capacitor. The gate of the switching transistor is connected to the corresponding gate signal line, the source of the switching transistor is connected to the corresponding data signal line, the drain of the switching transistor is connected to the first terminal of the pixel capacitor, and the second terminal of the pixel capacitor is used to connect to the common terminal.

[0027] The gate drive circuit is connected to the gate signal line, and the source drive circuit is connected to the data signal line.

[0028] The gate driving circuit, source driving circuit, and common terminal are configured such that: in the first time period, when the corresponding pixel is in the first color display state, the gate-source voltage of the switching transistor is the first voltage, and the source voltage of the switching transistor is greater than that of the common terminal; when the corresponding pixel is in the second color display state, the gate-source voltage of the switching transistor is the second voltage; in the second time period that does not overlap with the first time period, when the corresponding pixel is in the first color display state, the gate-source voltage of the switching transistor approaches the first voltage, and the source voltage of the switching transistor is less than that of the common terminal; when the corresponding pixel is in the second color display state, the gate-source voltage of the switching transistor approaches the second voltage; the first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

[0029] Taking an NMOS transistor as an example, such as Figure 3 As shown, for Figure 1 At each intersection, the gate of the switching transistor Q is connected to the gate drive circuit, the source is connected to the source drive circuit, the drain is connected to the pixel electrode (Vpixel) of the pixel capacitor, and the common electrode (Vcom) of the pixel electrode is connected to the common electrode.

[0030] The cholesteric liquid crystal display circuit provided in this embodiment of the invention can be applied to black and white display devices or color display devices.

[0031] For monochrome display devices, the bright state (white / light color) corresponds to the planar state (twisted state) of the liquid crystal, and the dark state (black / dark color) corresponds to the focal conic state (non-twisted state). Both the bright and dark states of cholesteric liquid crystals can be stably maintained after power is off. By applying voltage pulses of different amplitudes, pulse widths, or wavenumbers, the liquid crystal is driven to switch between the planar and focal conic states, thus achieving monochrome display. Intermediate gray levels can be achieved through partial switching or mixed states.

[0032] In color display devices, each complete color pixel consists of three sub-pixels, corresponding to red, green, and blue respectively. Each sub-pixel has an independent switching transistor and pixel capacitor, and its driving method is exactly the same as that of a single pixel in a monochrome display device. Its bright state (such as reflecting red light) corresponds to the planar state of the liquid crystal (liquid crystal twisted state), and its dark state (non-reflective) corresponds to the focal cone state of the liquid crystal (liquid crystal non-twisted state). Similarly, any color state needs to be actively written by applying voltage and can be retained after power is turned off.

[0033] Whether it is a monochrome display device or a color display device, the brightness of each pixel (sub-pixel) is determined by controlling whether the cholesteric liquid crystal of each pixel (sub-pixel) is in a planar state (liquid crystal twisted state / bright state) or a focal conic state (liquid crystal non-twisted state / dark state). The frame inversion drive provided in the embodiments of the present invention can be used to prevent liquid crystal polarization and suppress leakage problems under specific polarities.

[0034] In this embodiment of the invention, the first time period and the second time period are respectively used to correspond to the positive frame and the negative frame in the traditional frame inversion drive. That is, in the first time period, the voltage of the pixel electrode (first end) controlling the pixel capacitor is higher than that of the common electrode (second end) when the liquid crystal is in a tortuous state. In the second time period, the voltage of the pixel electrode controlling the pixel capacitor is lower than that of the common electrode when the liquid crystal is in a tortuous state.

[0035] In this embodiment of the invention, "approaching" means that the absolute value of the difference is less than a preset threshold. In some optional embodiments of this invention, during the second time period, when the corresponding pixel is in the first color rendering state, the gate-source voltage of the switching transistor can be equal to the first voltage, and when the corresponding pixel is in the second color rendering state, the gate-source voltage of the switching transistor can be equal to the second voltage.

[0036] In this embodiment of the invention, the switching transistor can be an NMOS transistor or a PMOS transistor, both of which can be referred to. Figure 3 The connection method shown only requires controlling different voltage timings.

[0037] In some optional embodiments of the present invention, the gate driving circuit can be configured to use the same gate activation voltage at any given time period. The source driving circuit and the common terminal are configured such that: in a first time period, the common terminal outputs a third voltage, and the data voltage output by the source driving circuit includes a first data voltage and a second data voltage, wherein the first data voltage is used to set the corresponding pixel to a first color rendering state, and the second data voltage is used to set the corresponding pixel to a second color rendering state; in a second time period, the common terminal outputs a fourth voltage, wherein the data voltage includes the third data voltage and the fourth data voltage, wherein the third data voltage is used to set the corresponding pixel to the first color rendering state, and the fourth data voltage is used to set the corresponding pixel to the second color rendering state; the third voltage is not equal to the fourth voltage.

[0038] In specific implementations, the first data voltage can be set to equal the third data voltage, the second data voltage to equal the fourth data voltage, the third voltage to equal the second data voltage, and the fourth voltage to equal the first data voltage. During any given time period, the gate driving circuit uses the same gate activation voltage and gate deactivation voltage. In the alternating frame inversion drive designed to prevent liquid crystal polarization, in the first time period (positive frame), the source driving circuit uses the first and second data voltages as the activation and deactivation voltages, respectively, while the common terminal uses the third voltage. At this time, under the influence of the first and third data voltages, the corresponding pixel is in a liquid crystal twisted state; under the influence of the second and third data voltages, the corresponding pixel is in a liquid crystal non-twisted state. In the second time period (negative frame), the source driving circuit uses the third and fourth data voltages, while the common terminal uses the fourth voltage. At this time, under the influence of the third and fourth data voltages, the corresponding pixel is in a liquid crystal non-twisted state; under the influence of the fourth data voltage and the fourth voltage, the corresponding pixel is in a liquid crystal twisted state.

[0039] like Figure 4 As shown, in progressive scan driving, the gate driving circuit sequentially outputs high-voltage pulses (as shown by G1, G2, G3, and G4) to each gate signal line to turn on the corresponding thin-film transistors in each row. Simultaneously, the source driving circuit outputs data voltages to the turned-on pixel units through each data signal line. In the first time period, the common terminal outputs a third voltage (e.g., 0V), and the source driving circuit outputs data voltages according to the grayscale displayed for each pixel (e.g., +17.5V for black, 0V for white). In the second time period, the common terminal outputs a fourth voltage (e.g., +17.5V), and the source driving circuit outputs data voltages according to the grayscale displayed for each pixel (e.g., 0V for black, +17.5V for white).

[0040] To achieve Figure 4 The voltage timing shown in this embodiment of the invention provides a power supply control scheme for a common terminal.

[0041] Figure 5 This is a power supply circuit diagram for a common electrode provided in an embodiment of the present invention. For example... Figure 5 As shown, the power supply circuit of the common terminal includes: a first power supply branch and a second power supply branch; the voltage input terminal of the first power supply branch is connected to the first voltage output terminal, the enable terminal of the first power supply branch is connected to the first pin of the display controller MCU, the voltage input terminal of the second power supply branch is connected to the second voltage output terminal, the enable terminal of the second power supply branch is connected to the second pin of the display controller MCU, and the voltage output terminals of the first power supply branch and the second power supply branch are connected to the common terminal.

[0042] In a specific implementation, the first power supply branch may include: a first NPN transistor K1 and a first NMOS transistor Q1; the base of the first NPN transistor K1 is connected to the first pin IO1 of the display controller MCU, the collector of the first NPN transistor K1 is connected to the gate of the first NMOS transistor Q1, the emitter of the first NPN transistor K1 is grounded, the drain of the first NMOS transistor Q1 is connected to the first voltage output terminal POWER1, and the source of the first NMOS transistor Q1 is connected to the common terminal.

[0043] like Figure 4 As shown, the first voltage output terminal POWER1 is connected to the drain of the first NMOS transistor Q1, the source of Q1 is connected to the first pin IO1, the gate of Q1 is connected to the collector of the first NPN transistor K1, the emitter of the first NPN transistor K1 is grounded, and the base of the first NPN transistor K1 is connected to the first pin IO1. This forms a switching path in which the voltage of the first pin IO1 controls the output of the first voltage output terminal POWER1 to the common terminal or to turn it off: when the first pin IO1 is high, the first NPN transistor K1 is turned on, pulling down the gate of the first NMOS transistor Q1 to turn it on, and the voltage of the first voltage output terminal POWER1 is transmitted to the first pin IO1; when the first pin IO1 is low, the first NPN transistor K1 is turned off, and the gate of the first NMOS transistor Q1 is pulled up and turned off.

[0044] The second power supply branch may include: a first PNP transistor K2, a second PNP transistor K3, and a first PMOS transistor Q2; the base of the first PNP transistor K2 is connected to the second pin IO2 of the display controller MCU, the collector of the first PNP transistor K2, the base of the second PNP transistor K3, and the drain of the first PMOS transistor Q2 are connected to the second voltage output terminal POWER2, ​​the emitter of the first PNP transistor K2 is connected to the DC power supply, the collector of the second PNP transistor K3 is connected to the gate of the first PMOS transistor Q2, and the source of the first PMOS transistor Q2 is connected to the common terminal.

[0045] like Figure 4 As shown, the second voltage output terminal POWER2 is connected to the source of the first PMOS transistor Q2, the drain of the first PMOS transistor Q2 is connected to the second pin IO2, and the gate of the first PMOS transistor Q2 is connected to the collector of the first PNP transistor K2. The emitter of the first PNP transistor K2 is grounded, and the base of the first PNP transistor K2 is connected to the second pin IO2. When the second pin IO2 is high, the first PNP transistor K2 is turned on, pulling down the gate of the first PMOS transistor Q2 and turning it on, so the voltage at the second voltage output terminal POWER2 is transmitted to the common terminal; when the second pin IO2 is low, the first PNP transistor K2 is turned off, and the gate of the first PMOS transistor Q2 is pulled high and turned off.

[0046] Additionally, the DC power supply (+3.3V) is connected to the second pin IO2 via a first PNP transistor K2: the emitter of the first PNP transistor K2 is connected to the DC power supply (+3.3V), the collector is connected to the second voltage output terminal POWER2, ​​and the base is connected to the second pin IO2. When the second pin IO2 is low, the first PNP transistor K2 is turned on, and the DC power supply (+3.3V) is output to the second pin IO2 through the first PNP transistor K2, thus clamping or pulling up the first pin IO1 to 3.3V; when the second pin IO2 is high, the first PNP transistor K2 is turned off to prevent backflow.

[0047] Figure 6 This is a front-end power supply circuit diagram provided for an embodiment of the present invention.

[0048] like Figure 6 As shown, the cholesteric liquid crystal display circuit provided in this embodiment of the invention may further include a third power supply branch and a fourth power supply branch; the first end of the third power supply branch is connected to the third pin IO3 of the display controller MCU, and the second end of the third power supply branch is the first voltage output terminal POWER1; the first end of the fourth power supply branch is connected to the fourth pin IO4 of the display controller MCU, and the second end of the fourth power supply branch is the second voltage output terminal POWER2; the third pin IO3 and the fourth pin IO4 are configured to output corresponding duty cycle signals according to preset voltage values.

[0049] In practical implementation, the third and fourth power supply branches can be implemented using the same power management chip. For example, a power chip of model TMI5700 can be used. The input terminal of this chip is connected to a DC power supply, its first control terminal is connected to the third pin IO3 of the display controller MCU, and its second control terminal is connected to the fourth pin IO4 of the display controller MCU. The first output terminal of this power chip serves as the first voltage output terminal POWER1, and the second output terminal serves as the second voltage output terminal POWER2.

[0050] Furthermore, the output of the third power supply branch can also be connected to the fifth pin ADC1 of the display controller MCU, and the output of the fourth power supply branch can also be connected to the sixth pin ADC2 of the display controller MCU, so that the display controller MCU can detect the output voltage of the third power supply branch and the fourth power supply branch.

[0051] During operation, the display controller MCU outputs a first pulse width modulation signal (PWM1) through pin 3 (IO3) and a second pulse width modulation signal (PWM2) through pin 4 (IO4). The duty cycle of PWM1 controls the output voltage of the first voltage output terminal (POWER1), and the duty cycle of PWM2 controls the output voltage of the second voltage output terminal (POWER2). The display controller MCU acquires the actual voltage value of the first voltage output terminal (POWER1) through pin 5 (ADC1) and the actual voltage value of the second voltage output terminal (POWER2) through pin 6 (ADC2).

[0052] The display controller MCU is configured to: scan the duty cycle of pin IO3 from 0% to 100%, while simultaneously reading the voltage value of the corresponding first voltage output terminal POWER1 in real time via pin ADC1; and scan the duty cycle of pin IO4 from 0% to 100%, while simultaneously reading the voltage value of the corresponding second voltage output terminal POWER2 in real time via pin ADC2. When the voltage value acquired at a certain duty cycle matches the preset voltage value, the display controller MCU maintains that duty cycle output, thereby achieving stable output and closed-loop regulation of the required voltage.

[0053] With the above structure, the display controller MCU can independently control the voltage values ​​of the first voltage output terminal POWER1 and the second voltage output terminal POWER2, ​​and use the built-in ADC to perform real-time voltage detection, thereby realizing accurate voltage switching and acquisition functions.

[0054] In some optional embodiments of the present invention, the common terminal may also be configured to maintain the output of a fifth voltage at any time period. The gate driving circuit and the source driving circuit may also be configured as follows: in the first time period, the gate activation voltage output by the gate driving circuit is a sixth voltage, the source driving circuit outputs a seventh voltage when corresponding to the first color rendering state, and the source driving circuit outputs an eighth voltage when corresponding to the second color rendering state, the voltage difference between the sixth voltage and the seventh voltage is the first voltage, and the voltage difference between the sixth voltage and the eighth voltage is the second voltage; in the second time period, the gate activation voltage output by the gate driving circuit is a ninth voltage, the source driving circuit outputs a tenth voltage when corresponding to the first color rendering state, and the source driving circuit outputs an eleventh voltage when corresponding to the second color rendering state, the voltage difference between the ninth voltage and the tenth voltage approaches the first voltage, and the voltage difference between the ninth voltage and the eleventh voltage approaches the second voltage; the seventh voltage is greater than the fifth voltage, and the tenth voltage is less than the fifth voltage.

[0055] In practical implementation, the voltage difference between the ninth and tenth voltages can be set to equal the first voltage, and the voltage difference between the ninth and eleventh voltages can be set to equal the second voltage. During any given time period, the common terminal consistently outputs the sixth voltage. In the alternating frame inversion drive designed to prevent liquid crystal polarization, during the first time period (positive frame), corresponding to the first color display state, the source drive circuit outputs the seventh voltage, which is greater than the fifth voltage. At this time, the gate activation voltage of the gate drive circuit is the sixth voltage. During the second time period (negative frame), corresponding to the first color display state, the source drive circuit outputs the tenth voltage, which is less than the fifth voltage. At this time, the gate activation voltage of the gate drive circuit is the ninth voltage. It can be understood that the ninth voltage is less than the sixth voltage. That is, while keeping the voltage at the common terminal constant, by setting the gate activation voltage to follow the up-and-down changes in the data voltage, the gate-source activation voltage is kept as constant as possible during frame inversion alternation, avoiding leakage in either polarity.

[0056] The various embodiments corresponding to the cholesteric liquid crystal display circuit have been described in detail above. Based on this, the embodiments of the present invention also disclose electronic paper and a driving method for the cholesteric liquid crystal display circuit corresponding to the above-mentioned cholesteric liquid crystal display circuit.

[0057] The electronic paper provided in the embodiments of the present invention may include the cholesteric liquid crystal display circuit provided in any of the above embodiments, and specific implementation methods can be referred to the description of the cholesteric liquid crystal display circuit embodiments above.

[0058] Applied to the cholesteric liquid crystal display circuit provided in any of the above embodiments, the driving method of the cholesteric liquid crystal display circuit provided in this embodiment of the invention may include: in a first time period, controlling the voltage timing of the gate driving circuit, the source driving circuit, and the common terminal, so that the corresponding pixel is in a first color display state by controlling the gate-source voltage of the switching transistor to be a first voltage and the source voltage of the switching transistor to be greater than the common terminal, and the corresponding pixel is in a second color display state by controlling the gate-source voltage of the switching transistor to be a second voltage; in a second time period, controlling the voltage timing of the gate driving circuit, the source driving circuit, and the common terminal, so that the corresponding pixel is in a first color display state by controlling the gate-source voltage of the switching transistor to approach the first voltage and the source voltage of the switching transistor to be less than the common terminal, and the corresponding pixel is in a second color display state by controlling the gate-source voltage of the switching transistor to approach the second voltage; wherein, the first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

[0059] The driving method for the cholesteric liquid crystal display circuit provided in this embodiment of the invention can be applied to the display controller described in the above-described cholesteric liquid crystal display circuit embodiment. For specific implementation details, please refer to the description of the above-described cholesteric liquid crystal display circuit embodiment.

[0060] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0061] The cholesteric liquid crystal display circuit, its driving method, and electronic paper provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A cholesteric liquid crystal display circuit, characterized in that, include: Multiple pixel units, gate driving circuit, source driving circuit, and common terminal; The pixel unit includes a switching transistor and a pixel capacitor. The gate of the switching transistor is connected to the corresponding gate signal line, the source of the switching transistor is connected to the corresponding data signal line, the drain of the switching transistor is connected to the first terminal of the pixel capacitor, and the second terminal of the pixel capacitor is used to connect to the common terminal. The gate driving circuit is connected to the gate signal line, and the source driving circuit is connected to the data signal line; The gate drive circuit, the source drive circuit, and the common terminal are configured as follows: In the first time period, when the corresponding pixel is in the first color display state, the gate-source voltage of the switching transistor is the first voltage, and the source voltage of the switching transistor is greater than the common terminal. When the corresponding pixel is in the second color display state, the gate-source voltage of the switching transistor is the second voltage. In the second time period that does not overlap with the first time period, when the corresponding pixel is in the first color rendering state, the gate-source voltage of the switching transistor is equal to the first voltage, and the source voltage of the switching transistor is less than the common terminal. When the corresponding pixel is in the second color rendering state, the gate-source voltage of the switching transistor is equal to the second voltage. The first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

2. The cholesteric liquid crystal display circuit according to claim 1, characterized in that, The gate drive circuit is configured to use the same gate activation voltage at any given time. The source drive circuit and the common terminal are configured as follows: During the first time period, the common electrode outputs a third voltage, and the data voltage output by the source drive circuit includes a first data voltage and a second data voltage. The first data voltage is used to make the corresponding pixel in the first color rendering state, and the second data voltage is used to make the corresponding pixel in the second color rendering state. During the second time period, the common electrode outputs a fourth voltage, the data voltage including a third data voltage and a fourth data voltage, the third data voltage being used to make the corresponding pixel in the first color rendering state, and the fourth data voltage being used to make the corresponding pixel in the second color rendering state; The third voltage is not equal to the fourth voltage.

3. The cholesteric liquid crystal display circuit according to claim 2, characterized in that, The power supply circuit for the common electrode includes: a first power supply branch and a second power supply branch; The voltage input terminal of the first power supply branch is connected to the first voltage output terminal, the enable terminal of the first power supply branch is connected to the first pin of the display controller, the voltage input terminal of the second power supply branch is connected to the second voltage output terminal, the enable terminal of the second power supply branch is connected to the second pin of the display controller, and the voltage output terminals of the first power supply branch and the second power supply branch are connected to the common terminal.

4. The cholesteric liquid crystal display circuit according to claim 3, characterized in that, The first power supply branch includes: a first NPN transistor and a first NMOS transistor; The base of the first NPN transistor is connected to the first pin of the display controller, the collector of the first NPN transistor is connected to the gate of the first NMOS transistor, the emitter of the first NPN transistor is grounded, the drain of the first NMOS transistor is connected to the first voltage output terminal, and the source of the first NMOS transistor is connected to the common terminal.

5. The cholesteric liquid crystal display circuit according to claim 3, characterized in that, The second power supply branch includes: a first PNP transistor, a second PNP transistor, and a first PMOS transistor; The base of the first PNP transistor is connected to the second pin of the display controller. The collector of the first PNP transistor, the base of the second PNP transistor, and the drain of the first PMOS transistor are connected to the second voltage output terminal. The emitter of the first PNP transistor is connected to a DC power supply. The collector of the second PNP transistor is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the common terminal.

6. The cholesteric liquid crystal display circuit according to claim 3, characterized in that, It also includes the third and fourth power supply branches; The first end of the third power supply branch is connected to the third pin of the display controller, and the second end of the third power supply branch is the first voltage output terminal; The first end of the fourth power supply branch is connected to the fourth pin of the display controller, and the second end of the fourth power supply branch is the second voltage output terminal; The third and fourth pins are configured to output corresponding duty cycle signals according to preset voltage values.

7. The cholesteric liquid crystal display circuit according to claim 6, characterized in that, The output terminal of the third power supply branch is connected to the fifth pin of the display controller, and the fourth power supply branch is connected to the sixth pin of the display controller, so that the display controller can detect the output voltage of the third power supply branch and the fourth power supply branch.

8. The cholesteric liquid crystal display circuit according to claim 1, characterized in that, The common electrode terminal is configured to maintain the output of the fifth voltage at any time. The gate drive circuit and the source drive circuit are configured as follows: During the first time period, the gate activation voltage output by the gate driving circuit is the sixth voltage, the source driving circuit outputs the seventh voltage when the first color rendering state is reached, and the source driving circuit outputs the eighth voltage when the second color rendering state is reached. The voltage difference between the sixth voltage and the seventh voltage is the first voltage, and the voltage difference between the sixth voltage and the eighth voltage is the second voltage. During the second time period, the gate activation voltage output by the gate driving circuit is the ninth voltage, corresponding to the tenth voltage output by the source driving circuit during the first color rendering state, and the eleventh voltage output by the source driving circuit during the second color rendering state. The voltage difference between the ninth voltage and the tenth voltage is equal to the first voltage, and the voltage difference between the ninth voltage and the eleventh voltage is equal to the second voltage. The seventh voltage is greater than the fifth voltage, and the tenth voltage is less than the fifth voltage.

9. An electronic paper, characterized in that, The cholesteric liquid crystal display circuit includes any one of claims 1 to 8.

10. A driving method for a cholesteric liquid crystal display circuit, characterized in that, The cholesteric liquid crystal display circuit according to any one of claims 1 to 8 comprises: In the first time period, the voltage timing of the gate driving circuit, the source driving circuit and the common terminal is controlled so that the gate-source voltage of the switching transistor is controlled to be a first voltage and the source voltage of the switching transistor is greater than that of the common terminal so that the corresponding pixel is in a first color display state. The gate-source voltage of the switching transistor is controlled to be a second voltage so that the corresponding pixel is in a second color display state. In the second time period, the voltage timing of the gate driving circuit, the source driving circuit and the common terminal is controlled so that the gate-source voltage of the switching transistor is equal to the first voltage and the source voltage of the switching transistor is less than the common terminal, so that the corresponding pixel is in the first color display state, and the gate-source voltage of the switching transistor is equal to the second voltage, so that the corresponding pixel is in the second color display state. Wherein, the first color display state corresponds to the liquid crystal twisted state, and the second color display state corresponds to the liquid crystal non-twisted state.

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