Reconfigurable sense amplifier applied to in-memory computing and control method thereof

Abstract

The application discloses a reconfigurable sense amplifier applied to in-memory computing and a control method thereof. The reconfigurable sense amplifier is controlled by a computing enable signal CEN to execute a read mode or a computing mode. In the read mode, a global bit line is connected with a local bit line to amplify and output differential data of a bit line pair. In the computing mode, data of the global bit line is taken as an input value, data of the local bit line is taken as a weight value, and the global bit line and the local bit line are connected with a multiplier to perform multiplication operation on the input value and the weight value and output a computing result. The reconfigurable sense amplifier has a dual-mode reconfigurable architecture, and realizes flexible switching of the read mode and the computing mode without increasing large-scale additional hardware.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a reconfigurable sensitive amplifier and its control method for in-memory computing. Background Technology

[0002] In SRAM-based in-memory computing architectures, the sensitive amplifier is a crucial circuit, primarily responsible for amplifying and outputting the differential data from bit line pairs. Typically, to maintain the storage density of the memory array, a single differential bit line pair can support 64, 128, or even 256 memory cells, resulting in bit line load capacitances of tens or even hundreds of femtofarads (fF). Since SRAM has a relatively low read current, it is difficult to achieve rail-to-rail data output quickly using conventional logic circuits. The sensitive amplifier, however, can effectively solve this problem.

[0003] Traditional, representative sensitive amplifiers are divided into voltage latching and current latching types. The voltage latching sensitive amplifier's topology is similar to that of a 6T-SRAM, using a positive feedback loop composed of cross-coupled inverters. However, its quiescent power consumption is too high, and its input and output share a single pair of ports (OUT and OUTB), making its amplified voltage difference easily susceptible to interference. If the control circuit operates at incorrect timing, it may produce erroneous data output. The current latching sensitive amplifier, on the other hand, does not have this problem because its input and output ports are isolated. However, because its amplification process involves converting a voltage difference to a current difference and then back to a voltage difference, its amplification speed is relatively slow.

[0004] In addition, another type of logic-extended sensitive amplifier implements Boolean logic functions by introducing an additional reference voltage or using an asymmetric differential structure, but these solutions often introduce additional power consumption and symmetry issues. Existing reconfigurable sensitive amplifiers, in computation mode, can only support Boolean logic operations between different rows / columns within the array.

[0005] Overall, the aforementioned types of sensitive amplifiers are highly dependent on precise timing control and have complex peripheral circuits, making them difficult to apply effectively to computational scenarios that rely on large-scale matrix multiplication, such as neural network inference. Summary of the Invention

[0006] Purpose of the invention: The purpose of this invention is to provide a reconfigurable sensitive amplifier and its control method for in-memory computing. Different circuit structures are selected for different modes to improve sensing speed, reduce latency and power consumption, ensure data reliability in read mode, and support efficient large-scale parallel computing in computing mode.

[0007] Technical solution: The present invention provides a reconfigurable sensitive amplifier for in-memory computing, wherein the reconfigurable sensitive amplifier is controlled by a computing enable signal CEN to execute a read mode or a computing mode;

[0008] In read mode, the global bit line is connected to the local bit line to amplify and output the differential data of the bit line pair;

[0009] In computation mode, the data of the global bit line is used as the input value, and the data of the local bit line is used as the weight value. The global bit line and the local bit line are connected to a multiplier to perform multiplication on the input value and the weight value and output the calculation result.

[0010] Furthermore, in readout mode, the reconfigurable sensitive amplifier is equivalent to a current latch-type sensitive amplifier.

[0011] Furthermore, the enable signal CEN is calculated to connect to the gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6;

[0012] The source of P5 is connected to the first local bit line BL, the source of P6 is connected to the second local bit line BLB, and the drains of P5 and P6 are connected to the multiplier; the first global bit line GBL and the second global bit line GBLB are connected to the multiplier.

[0013] When the calculation enable signal CEN is low, P5 and P6 are turned on, the multiplier performs multiplication on the input value and the weight value and outputs the calculation result.

[0014] Furthermore, the enable signal CEN is calculated to connect to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4;

[0015] The source of N3 is connected to the source of P5, and the source of N4 is connected to the source of P6; the drain of N3 is connected to the gate of N5 and connected to the first global bit line GBL, and the drain of N4 is connected to the gate of N6 and connected to the second global bit line GBLB.

[0016] The drains of N5 and N6 are connected to the first and second inverting circuits, respectively. When the enable signal CEN is high, N3 and N4 are turned on, P5 and P6 are turned off, and the first and second inverting circuits output amplified differential data output signals.

[0017] Furthermore, the first reverse circuit includes a first PMOS transistor P1, a third PMOS transistor P3, and a first NMOS transistor N1, and the second reverse circuit includes a second PMOS transistor P2, a fourth PMOS transistor P4, and a second NMOS transistor N2;

[0018] P3 and N1 form the first inverter, the drain of N5 is connected to the source of N1, and the drain of P1 is connected to the output of the first inverter; the first inverter and the second inverter are cross-coupled.

[0019] P4 and N2 form a second inverter, the drain of N6 is connected to the source of N2, and the drain of P2 is connected to the output of the second inverter.

[0020] The gates of P1 and P2 are connected to the enable signal SAEN, which is used to control the switching on and off of the sensitive amplifier.

[0021] Furthermore, the multiplier performs an AND operation or an XNOR operation on the weight value and the input value.

[0022] Furthermore, the multiplier includes the ninth PMOS transistor P9 to the thirteenth PMOS transistor P13, the eighth NMOS transistor N8 to the twelfth NMOS transistor N12, P9, P10, P11, N8 and N9 connected in series to form the first branch, P12, P13, N10 and N11 connected in series to form the second branch, and N12 and N11 connected in parallel.

[0023] The gate connection selection signal SEL of P9 and N11 controls the multiplier to perform an AND operation or an XNOR operation.

[0024] The gate of P10 is connected to the drain of P5, the gates of P12, N9 and N12 are connected to the drain of P6, the gates of P11 and N8 are connected to the first global bit line BGL, and the gates of P13 and N10 are connected to the second global bit line BGLB.

[0025] Furthermore, the sources of N5 and N6 are connected together to the drain of the seventh NMOS transistor N7. The source of N7 is grounded, and the gate of N7 is connected to the enable signal SAEN. The enable signal SAEN is used to control the switching on and off of the sensitive amplifier.

[0026] Furthermore, a pair of cross-coupled PMOS transistors are connected between the drains of P5 and P6.

[0027] The present invention discloses a control method for a reconfigurable sensitive amplifier applied to in-memory computing, which controls the reconfigurable sensitive amplifier to execute a read mode or a calculation mode by calculating an enable signal CEN.

[0028] In read mode, the global bit line is connected to the local bit line to amplify and output the differential data of the bit line pair;

[0029] In computation mode, the data of the global bit line is used as the input value, and the data of the local bit line is used as the weight value. The global bit line and the local bit line are connected to a multiplier to perform multiplication on the input value and the weight value and output the calculation result.

[0030] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) The reconfigurable sensitive amplifier of the present invention has a dual-mode reconfigurable architecture, which realizes flexible switching between reading and calculation modes without adding large-scale additional hardware; (2) The reconfigurable sensitive amplifier of the present invention is based on 6T SRAM cells, which has higher storage density; (3) The reconfigurable sensitive amplifier of the present invention avoids the traditional analog amplification path in calculation mode, and directly uses the digital level signal in the SRAM cell to perform logic operations, which effectively simplifies the peripheral circuit design and improves the amplification speed; (4) The multiplier of the present invention supports AND and XNOR logic operations; (5) The present invention adopts bit line level recovery technology to eliminate static power consumption in calculation logic. Attached Figure Description

[0031] Figure 1 This is a circuit diagram of a reconfigurable sensitive amplifier according to an embodiment of the present invention.

[0032] Figure 2 This is a circuit diagram of a multiplier according to an embodiment of the present invention.

[0033] Figure 3 This is an equivalent circuit diagram of the reconfigurable sensitive amplifier in readout mode according to an embodiment of the present invention.

[0034] Figure 4 This is the equivalent circuit diagram of the reconfigurable sensitive amplifier in computation mode according to an embodiment of the present invention.

[0035] Figure 5 This is a timing diagram of the computing mode in an embodiment of the present invention. Detailed Implementation

[0036] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0037] like Figure 1 As shown, the reconfigurable sensitive amplifier applied to in-memory computing adopts a global bit line readout strategy and includes the first to eighth PMOS transistors P1~P8 and the first to seventh NMOS transistors N1~N7.

[0038] The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the enable signal SAEN, which controls the switching on and off of the sensitive amplifier. The drains of P1 and P2 are connected to the outputs of the first and second inverters, respectively. Both the first and second inverters are composed of one PMOS transistor and one NMOS transistor, and they are cross-coupled. Specifically, the first inverter includes a third PMOS transistor P3 and a first NMOS transistor N1. The drain of P3 is connected to the drain of N1 as the output of the first inverter, and the gate of P3 is connected to the gate of N1 as the input of the first inverter. The input of the first inverter is connected to the output of the second inverter, and the output of the second inverter is connected to the input of the second inverter. Similarly, the second inverter includes a fourth PMOS transistor P4 and a second NMOS transistor N2. The inverted output of the first inverter is used as the first amplified output ROUT, and the inverted output of the second inverter is used as the second amplified output ROUTB.

[0039] The source of N1 is connected to the drain of the fifth NMOS transistor N5, the source of N2 is connected to the drain of the sixth NMOS transistor N6, the sources of N5 and N6 are connected together and connected to the drain of the seventh NMOS transistor N7, the source of N7 is grounded, and the gate of N7 is connected to the enable signal SAEN.

[0040] The calculation enable signal CEN is connected to the gates of the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6. The calculation enable signal CEN is used to control the reconfigurable sensitive amplifier to execute read mode or calculation mode. The source of N3 is connected to the source of P5 and this node is connected to the first local bit line BL. The source of N4 is connected to the source of P6 and this node is connected to the second local bit line BLB. The drain of N3 is connected to the gate of N5 and this node is connected to the first global bit line GBL. The drain of N4 is connected to the gate of N6 and this node is connected to the second global bit line GBLB.

[0041] A pair of cross-coupled PMOS transistors, namely the seventh PMOS transistor P7 and the eighth PMOS transistor P8, are connected between the drains of P5 and P6. The sources of P7 and P8 are both connected to VDD. The drain of P7 is connected to the drain of P6, and the gate of P7 is connected to the drain of P5. The drain of P8 is connected to the drain of P5, and the gate of P8 is connected to the drain of P6. These cross-coupled PMOS transistors are used to restore the bit line level. For example, when BL0=1 and BLB0=0, P8 is turned on, restoring the BL0 level to 1.

[0042] The global bit line pairs (GBL / GBLB) and the drains of P5 and P6 (BL0 / BLB0) are also connected to a multiplier (AND & XNOR). The circuit structure of the multiplier is as follows: Figure 2As shown, the circuit includes PMOS transistors P9 to P13 (ninth to thirteenth), NMOS transistors N8 to N12 (eighth to twelfth), P9, P10, P11, N8, and N9 connected in series to form the first branch, and P12, P13, N10, and N11 connected in series to form the second branch. N12 and N11 are connected in parallel. The gates of P9 and N11 are connected to the selection signal SEL, which controls the multiplier to perform an AND or XNOR operation. The gate of P10 is connected to the drain of P5 (BL0 in the figure, equivalent to being connected to the first local bit line BL), the gates of P12, N9, and N12 are connected to the drain of P6 (BLB0 in the figure, equivalent to being connected to the second local bit line BL), the gates of P11 and N8 are connected to the first global bit line BGL, and the gates of P13 and N10 are connected to the second global bit line BGLB.

[0043] When the computation enable signal CEN is high, N3 and N4 are enabled, and P5 and P6 are disabled. The sensitive amplifier executes read mode. The first global bit line GBL is connected to the first local bit line BL through N3, and the second global bit line GBLB is connected to the second local bit line BLB through N4. The sensitive amplifier is equivalent to a current latching amplifier. Figure 3 The diagram shows the equivalent circuit for the read mode. This embodiment uses the access of a 6T SRAM cell as an example for illustration. WL0 and WL1 in the diagram are both word line signals of one row of the 6T SRAM storage array. This embodiment assumes that row WL0 is accessed.

[0044] The reading process of the sensitive amplifier in readout mode is consistent with that of a traditional current latching sensitive amplifier: after a voltage difference is established between GBL and GBLB, the SAEN signal is activated, and the sensitive amplifier begins to operate. The voltage difference between BL and BLB causes a difference in the gate-source voltage (VGS) of N5 and N6, resulting in a difference in the current flowing through N5 and N6, further creating a current difference between the current paths N1-N5 and N2-N6. This current difference causes different discharge rates at nodes A and B, thus forming a voltage difference between them, which is ultimately amplified through a positive feedback loop to achieve differential voltage rail-to-rail output.

[0045] When the CEN signal is low, the circuit switches to calculation mode. At this time, N3 and N4 are cut off, and P5 and P6 are turned on. The sensitive amplifier then executes the calculation mode. Figure 4 The diagram shows the equivalent circuit for the computation mode. In this configuration, the global bit line GBL / GBLB serves as the input value (IN), while the local bit line BL / BLB serves as the weight value (W). The corresponding computation method (AND or XNOR) can be selected via the SEL signal to perform the multiplication operation. For details of the specific function correspondence, please refer to Table 1.

[0046] When SEL is low, P9 is on and N11 is off. When both the input value GBL and the weight value BL0 are high, their inverted values ​​GBLB and BLB0 are low, P12 and P13 are on, and the output COUT is high. Similarly, when both the input value GBL and the weight value BL0 are low, P10 and P11 are on, and the output COUT is high. At this time, the multiplier implements the XNOR logic function.

[0047] When SEL is high, P9 is off and N11 is on. P10 and P11 are turned off by P9, and N12 is shorted by N11. When both GBL and BL0 are high, P12 and P13 are on, and the output is high. At this time, the multiplier performs the AND logic function.

[0048] Table 1 Truth Table of Multipliers

[0049]

[0050] like Figure 5 The diagram shown is a timing diagram in calculation mode. When WL0 is high, the memory cell is selected and Q0 is output. When SEL is low, an AND operation is performed on the weight value and the input value. When SEL is high, an XNOR operation is performed on the weight value and the input value.

Claims

1. A reconfigurable sensitive amplifier for in-memory computing, characterized in that, The reconfigurable sensitive amplifier is controlled by the computation enable signal CEN to execute either readout mode or computation mode; In read mode, the global bit line is connected to the local bit line to amplify and output the differential data of the bit line pair; In computation mode, the data of the global bit line is used as the input value, the data of the local bit line is used as the weight value, the global bit line and the local bit line are connected to a multiplier, the input value and the weight value are multiplied and the computation result is output; The enable signal CEN is connected to the gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6. The source of P5 is connected to the first local bit line BL, the source of P6 is connected to the second local bit line BLB, and the drains of P5 and P6 are connected to the multiplier. The first global bit line GBL and the second global bit line GBLB connect the multiplier; When the calculation enable signal CEN is low, P5 and P6 are turned on, the multiplier performs multiplication on the input value and the weight value and outputs the calculation result; The enable signal CEN is connected to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4. The source of N3 is connected to the source of P5, and the source of N4 is connected to the source of P6; the drain of N3 is connected to the gate of N5 and connected to the first global bit line GBL, and the drain of N4 is connected to the gate of N6 and connected to the second global bit line GBLB. The drains of N5 and N6 are connected to the first and second inverting circuits, respectively. When the enable signal CEN is high, N3 and N4 are turned on, P5 and P6 are turned off, and the first and second inverting circuits output amplified differential data output signals.

2. The reconfigurable sensitive amplifier for in-memory computing according to claim 1, characterized in that, In read mode, the reconfigurable sensitive amplifier is equivalent to a current latch-type sensitive amplifier.

3. The reconfigurable sensitive amplifier for in-memory computing according to claim 1, characterized in that, The first inverting circuit includes a first PMOS transistor P1, a third PMOS transistor P3, and a first NMOS transistor N1; the second inverting circuit includes a second PMOS transistor P2, a fourth PMOS transistor P4, and a second NMOS transistor N2. P3 and N1 form the first inverter, the drain of N5 is connected to the source of N1, and the drain of P1 is connected to the output of the first inverter; the first inverter and the second inverter are cross-coupled. P4 and N2 form a second inverter, the drain of N6 is connected to the source of N2, and the drain of P2 is connected to the output of the second inverter. The gates of P1 and P2 are connected to the enable signal SAEN, which is used to control the switching on and off of the sensitive amplifier.

4. The reconfigurable sensitive amplifier for in-memory computing according to claim 1, characterized in that, The multiplier performs an AND operation or an XNOR operation on the weight value and the input value.

5. The reconfigurable sensitive amplifier for in-memory computing according to claim 4, characterized in that, The multiplier includes the ninth PMOS transistor P9 to the thirteenth PMOS transistor P13, the eighth NMOS transistor N8 to the twelfth NMOS transistor N12, P9, P10, P11, N8 and N9 connected in series to form the first branch, P12, P13, N10 and N11 connected in series to form the second branch, and N12 and N11 connected in parallel. The gate connection selection signal SEL of P9 and N11 controls the multiplier to perform an AND operation or an XNOR operation. The gate of P10 is connected to the drain of P5, the gates of P12, N9 and N12 are connected to the drain of P6, the gates of P11 and N8 are connected to the first global bit line BGL, and the gates of P13 and N10 are connected to the second global bit line BGLB.

6. The reconfigurable sensitive amplifier for in-memory computing according to claim 1, characterized in that, The sources of N5 and N6 are connected together to the drain of the seventh NMOS transistor N7. The source of N7 is grounded, and the gate of N7 is connected to the enable signal SAEN. The enable signal SAEN is used to control the switching on and off of the sensitive amplifier.

7. The reconfigurable sensitive amplifier for in-memory computing according to claim 1, characterized in that, A pair of cross-coupled PMOS transistors are connected between the drains of P5 and P6.

8. A control method for a reconfigurable sensitive amplifier applied to in-memory computing, characterized in that, The reconfigurable sensitive amplifier is controlled to perform readout mode or calculation mode by calculating the enable signal CEN. In read mode, the global bit line is connected to the local bit line to amplify and output the differential data of the bit line pair; In computation mode, the data of the global bit line is used as the input value, the data of the local bit line is used as the weight value, the global bit line and the local bit line are connected to a multiplier, the input value and the weight value are multiplied and the computation result is output; The enable signal CEN is connected to the gates of the fifth PMOS transistor P5 and the sixth PMOS transistor P6. The source of P5 is connected to the first local bit line BL, the source of P6 is connected to the second local bit line BLB, and the drains of P5 and P6 are connected to the multiplier. The first global bit line GBL and the second global bit line GBLB connect the multiplier; When the calculation enable signal CEN is low, P5 and P6 are turned on, the multiplier performs multiplication on the input value and the weight value and outputs the calculation result; The enable signal CEN is connected to the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4. The source of N3 is connected to the source of P5, and the source of N4 is connected to the source of P6; the drain of N3 is connected to the gate of N5 and connected to the first global bit line GBL, and the drain of N4 is connected to the gate of N6 and connected to the second global bit line GBLB. The drains of N5 and N6 are connected to the first and second inverting circuits, respectively. When the enable signal CEN is high, N3 and N4 are turned on, P5 and P6 are turned off, and the first and second inverting circuits output amplified differential data output signals.

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