Anti-storage unit miswrite circuit, chip, and method
By using the power supply to control the gate and drain of the drive transistor to ensure there is no voltage difference in the circuit preventing accidental writes to memory cells, the problem of accidental flipping caused by leakage in the peripheral circuit is solved, thus improving write reliability and speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU ZHAOXIN SEMICON TECH CO LTD
- Filing Date
- 2026-03-16
- Publication Date
- 2026-06-19
AI Technical Summary
In the prior art, when the leakage current of the peripheral circuit is large, the negative potential charge required for write assistance is easily lost, causing unselected memory cells to be falsely flipped.
By utilizing the power supply terminal to control the absence of a voltage difference between the gate and drain of the drive transistor in the anti-miswrite circuit of the memory cell, negative voltage is prevented from leaking into the unselected memory cell. This includes the coordinated operation of the first drive transistor circuit, the second drive transistor circuit, and the third drive transistor circuit to prevent charge from leaking into the unselected bit line.
It effectively prevents the accidental flipping of unselected memory cells, improves write reliability and speed, and avoids loss due to negative voltage.
Smart Images
Figure CN122245369A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a circuit, chip, and method for preventing accidental writes to memory cells. Background Technology
[0002] Write-assist circuitry enhances write drive capability and accelerates the 1-to-0 toggle speed by applying a negative voltage to the bit lines during the write process, thereby improving write reliability and speed. This technology is widely used in advanced process nodes to optimize power consumption and performance.
[0003] In the prior art, traditional write-assist circuits introduce a negative voltage on a bit line connected in series with the driver transistor to pull the internal node voltage of the selected memory cell to a lower potential, thereby assisting in writing to the memory cell.
[0004] However, in existing technologies, when the leakage current of the peripheral circuit is large, the negative potential charge required for write assistance will leak out, causing the memory cell corresponding to the unselected bit line to flip incorrectly. Therefore, there is an urgent need for a circuit that can prevent charge from leaking into the unselected memory cell to prevent accidental write to the memory cell. Summary of the Invention
[0005] This application provides a circuit, chip, and method for preventing accidental writing to memory cells, in order to solve the problem that when the leakage current of the peripheral circuit is large, the negative potential charge required for write assistance will be lost, causing the memory cell corresponding to the unselected bit line to be accidentally flipped.
[0006] In a first aspect, this application provides a circuit for preventing accidental writing to a memory cell, comprising: a power supply terminal (101), a first driving transistor circuit (102), a second driving transistor circuit (103), a third driving transistor circuit (104), a fourth driving transistor circuit (105), a first bit line (106), and a second bit line (107), wherein the first driving transistor circuit (102) includes a first driving transistor (1021), the second driving transistor circuit (103) includes a seventh driving transistor (1033), and the third driving transistor circuit (104) includes a ninth driving transistor (1041);
[0007] Wherein, one end of the power supply terminal (101) is connected to the first driving transistor circuit (102), the second driving transistor circuit (103), and the third driving transistor circuit (104) respectively; the first driving transistor circuit (102) is connected to the third driving transistor circuit (104); the ninth driving transistor (1041) in the third driving transistor circuit (104) is connected to the second bit line (107); the seventh driving transistor (1033) in the second driving transistor circuit (103) is connected to the first bit line (106); the other end of the power supply terminal (101) is connected to the fourth driving transistor circuit (105).
[0008] The first driving transistor circuit (102) is used to control, via the power supply terminal (101), that there is no voltage difference between the gate and drain of the first driving transistor (1021); and,
[0009] The second driving transistor circuit (102) is used to control the gate and drain of the seventh driving transistor (1033) to have no voltage difference via the power supply terminal (101), so as to prevent negative voltage from leaking to the first bit line (106) and to assist in writing data to the unselected memory cell (20); and,
[0010] The third driving transistor circuit (104) is used to control the gate and drain of the ninth driving transistor (1041) to have no voltage difference through the power supply terminal (101) so as to prevent negative voltage from leaking to the second bit line (107) and assisting in the writing of data to the unselected memory cell (20).
[0011] In one possible design, the first driving transistor circuit (102) includes: a first driving transistor (1021), a second driving transistor (1022), a third driving transistor (1023), and a fourth driving transistor (1024); wherein the source of the first driving transistor (1021) is electrically connected to the power supply terminal (101); the drain of the first driving transistor (1021) is electrically connected to the source of the second driving transistor (1022); the drain of the second driving transistor (1022) is electrically connected to the source of the third driving transistor (1023); the drain of the third driving transistor (1023) is electrically connected to the drain of the fourth driving transistor (1024); and the drain of the fourth driving transistor (1024) is connected to the first driving transistor (1021). The gate of the first driving transistor (102) and the gate of the second driving transistor (1022) are connected in circuit; the source of the fourth driving transistor (1024) is connected in circuit with the power supply terminal (101); the gate of the third driving transistor (1023) and the gate of the fourth driving transistor (1024) are respectively connected in circuit with the drain of the first driving transistor (1021); the source of the first driving transistor circuit (102) is used to determine a first voltage through the power supply terminal (101); the gate of the first driving transistor circuit (102) is used to determine a second voltage that is the same as the first voltage through the drain of the fourth driving transistor (1024), the source of the fourth driving transistor (1024) and the power supply terminal (101), so as to obtain that there is no voltage difference between the gate and the drain of the first driving transistor (1021).
[0012] In one possible design, the second driving transistor circuit (103) includes: a fifth driving transistor (1031), a sixth driving transistor (1032), and a seventh driving transistor (1033); wherein the source of the fifth driving transistor (1031) is electrically connected to the power supply terminal (101); the drain of the fifth driving transistor (1031) is electrically connected to the source of the sixth driving transistor (1032); the drain of the sixth driving transistor (1032) is electrically connected to the gate of the seventh driving transistor (1033); the gate of the fifth driving transistor (1031) is used to receive a control signal; the source of the seventh driving transistor (1033) is connected to the first driving transistor circuit (102). The circuit is connected between the drain of the seventh driving transistor (1033) and the first bit line (106); the gate of the seventh driving transistor (1033) is used to determine the corresponding third voltage through the sixth driving transistor (1032), the fifth driving transistor (1031) and the power supply terminal (101); the source of the seventh driving transistor (1033) is used to determine the fourth voltage that is the same as the third voltage through the first driving transistor circuit (102) and the power supply terminal (101), so that there is no voltage difference between the gate and the drain of the seventh driving transistor (1033) to prevent the negative voltage from leaking to the first bit line (106) and to assist in the writing of data to the unselected memory cell (20).
[0013] In one possible design, the second driving transistor circuit (103) further includes: an eighth driving transistor (1034) and a physical pin (1035); wherein the gate of the eighth driving transistor (1034) is connected to the gate of the sixth driving transistor (1032); the source of the eighth driving transistor (1034) is connected to the drain of the sixth driving transistor (1032); and the drain of the eighth driving transistor (1034) is connected to the physical pin (1035).
[0014] In one possible design, the third driving transistor circuit (104) includes: a ninth driving transistor (1041), a tenth driving transistor (1042), an eleventh driving transistor (1043), a twelfth driving transistor (1044), and a thirteenth driving transistor (1045); wherein the gate of the ninth driving transistor (1041) is connected to the second driving transistor circuit (103); the drain of the ninth driving transistor (1041) is connected to the second bit line (107); the third driving transistor (1042) is connected to the second bit line (1045). The source of the ninth driving transistor (1041) is electrically connected to the drain of the tenth driving transistor (1042), the source of the eleventh driving transistor (1043), the gate of the twelfth driving transistor (1044), and the gate of the thirteenth driving transistor (1045), respectively; the source of the tenth driving transistor (1042) is electrically connected to the power supply terminal (101); the drain of the tenth driving transistor (1042) is electrically connected to the source of the eleventh driving transistor (1043); The drain of the eleventh driving transistor (1043) is electrically connected to the source of the twelfth driving transistor (1044); the drain of the twelfth driving transistor (1044) is electrically connected to the gate of the tenth driving transistor (1042), the gate of the eleventh driving transistor (1043), and the source of the thirteenth driving transistor (1045); the drain of the thirteenth driving transistor (1045) is electrically connected to the power supply terminal (101); the gate of the ninth driving transistor (1041) is electrically connected to the source of the eleventh driving transistor (1044). The gate of the ninth driving transistor (1041) is used to determine the corresponding fifth voltage through the second driving transistor circuit (103) and the power supply terminal (101); the source of the ninth driving transistor (1041) is used to determine the sixth voltage, which is the same as the fifth voltage, through the tenth driving transistor (1042) and the power supply terminal (101), so that there is no voltage difference between the gate and the drain of the ninth driving transistor (1041), so as to prevent the negative voltage from leaking to the second bit line (107) and assisting the writing of data to the unselected memory cell (20).
[0015] In one possible design, the fourth driving transistor circuit (105) includes: a fourteenth driving transistor (1051) and a capacitor (1052); wherein the source of the fourteenth driving transistor (1051) is connected to the power supply terminal (101); one end of the capacitor (1052) is connected to the power supply terminal (101); and the other end of the capacitor (1052) is connected to the second driving transistor circuit (103).
[0016] Secondly, this application provides a chip for preventing accidental writes to memory cells, including the accidental write prevention circuit for memory cells as described in the first aspect.
[0017] Thirdly, this application provides a method for preventing accidental writes to memory cells, applied to the accidental write prevention circuit for memory cells as described in the first aspect, comprising:
[0018] The first driving transistor circuit is used to control the gate and drain of the first driving transistor to have no voltage difference via the power supply terminal; and,
[0019] The second driving transistor circuit is used to control the gate and drain of the seventh driving transistor to have no voltage difference via the power supply terminal, so as to prevent negative voltage from leaking to the first bit line and assisting in writing data to unselected memory cells; and,
[0020] The third driving transistor circuit is used to control the gate and drain of the ninth driving transistor to have no voltage difference through the power supply terminal, so as to prevent negative voltage from leaking to the second bit line and assisting in the writing of data to the unselected memory cell.
[0021] In one possible design, the second driving transistor circuit includes a fifth driving transistor, a sixth driving transistor, and a seventh driving transistor. Correspondingly, the method further includes: the gate of the seventh driving transistor is used to determine a corresponding third voltage through the sixth driving transistor, the fifth driving transistor, and the power supply terminal; the source of the seventh driving transistor is used to determine a fourth voltage identical to the third voltage through the first driving transistor circuit and the power supply terminal, resulting in no voltage difference between the gate and drain of the seventh driving transistor, thus preventing negative voltage leakage to the first bit line and assisting in the writing of data to unselected memory cells.
[0022] In one possible design, the fifth driving transistor is further configured to receive a control signal and be turned on when the control signal is high, both when writing to the selected memory cell begins via the first bit line and the second bit line; the power supply terminal generates a negative voltage after the fifth driving transistor is turned on and when the control signal changes from high to low; the fifth driving transistor transmits the negative voltage to the source of the sixth driving transistor via the control signal; it is turned off when the control signal is low, after transmitting the negative voltage to the source of the sixth driving transistor; after writing to the selected memory cell is completed via the first bit line and the second bit line, the fifth driving transistor is turned on again when the control signal is high; and the source of the sixth driving transistor is updated to a common ground terminal.
[0023] The circuit, chip, and method for preventing accidental writes to memory cells provided in this application include a first driving transistor circuit that, through power supply control, ensures there is no voltage difference between the gate and drain of the first driving transistor; a second driving transistor circuit that, through power supply control, ensures there is no voltage difference between the gate and drain of the seventh driving transistor to prevent negative voltage leakage to the first bit line, thus assisting in writing data to unselected memory cells; and a third driving transistor circuit that, through power supply control, ensures there is no voltage difference between the gate and drain of the ninth driving transistor to prevent negative voltage leakage to the second bit line, thus assisting in writing data to unselected memory cells. Through the cooperation of the power supply, the first driving transistor circuit, the second driving transistor circuit, the third driving transistor circuit, the fourth driving transistor circuit, the first bit line, and the second bit line, the leakage of the negative potential charge required for write assistance can be prevented, thereby avoiding accidental flipping of memory cells corresponding to unselected bit lines. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 Schematic diagram of the anti-miswrite circuit for the memory cell provided in the embodiments of this application Figure 1 ;
[0026] Figure 2 Schematic diagram of the anti-miswrite circuit for the memory cell provided in the embodiments of this application Figure 2 ;
[0027] Figure 3 A flowchart illustrating the method for preventing accidental writes to a storage unit provided in an embodiment of this application;
[0028] Figure 4 This is a schematic diagram of level changes provided for an embodiment of this application. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] Write assist circuits enhance write drive capability and accelerate the 1-to-0 toggle speed by applying a negative voltage to the bit line during the write process, thereby improving write reliability and speed. This technology is widely used in advanced process nodes to optimize power consumption and performance. In existing technologies, traditional write assist circuits introduce a negative voltage on a bit line connected in series with the driver transistor to pull the internal node voltage of the selected memory cell to a lower potential to assist in the write process. However, in existing technologies, when the leakage current in the peripheral circuit is large, the charge required for the negative potential of the write assist circuit will leak out, causing the memory cell corresponding to the unselected bit line to toggle incorrectly. Therefore, there is an urgent need for a circuit that can prevent charge leakage into unselected memory cells to prevent incorrect write operations.
[0031] To address the aforementioned technical problems, this application proposes the following technical concept: Considering a circuit for preventing accidental writes to memory cells comprised of a power supply terminal, a first driving transistor circuit, a second driving transistor circuit, a third driving transistor circuit, a fourth driving transistor circuit, a first bit line, and a second bit line, the inventors, based on the first driving transistor circuit, control the power supply terminal to ensure there is no voltage difference between the gate and drain of the first driving transistor in the first driving transistor circuit; based on the second driving transistor circuit, control the power supply terminal to ensure there is no voltage difference between the gate and drain of the seventh driving transistor in the second driving transistor circuit, thereby preventing negative voltage leakage to the first bit line to assist in writing data to unselected memory cells; and based on the third driving transistor circuit, control the power supply terminal to ensure there is no voltage difference between the gate and drain of the ninth driving transistor in the third driving transistor circuit, thereby preventing negative voltage leakage to the second bit line to assist in writing data to unselected memory cells, thus avoiding accidental flipping of memory cells corresponding to unselected bit lines.
[0032] Figure 1 This is a schematic diagram of the structure of the anti-miswrite circuit for the memory cell provided in the embodiments of this application. Figure 1 .
[0033] like Figure 1 As shown, the anti-miswrite circuit 10 for the memory cell includes: a power supply terminal 101, a first driving transistor circuit 102, a second driving transistor circuit 103, a third driving transistor circuit 104, a fourth driving transistor circuit 105, a first bit line 106, and a second bit line 107. The first driving transistor circuit 102 includes a first driving transistor 1021, the second driving transistor circuit 103 includes a seventh driving transistor 1033, and the third driving transistor circuit 104 includes a ninth driving transistor 1041.
[0034] One end of the power supply terminal 101 is connected to the first driving transistor circuit 102, the second driving transistor circuit 103, and the third driving transistor circuit 104 respectively; the first driving transistor circuit 102 is connected to the third driving transistor circuit 104; the ninth driving transistor 1041 in the third driving transistor circuit 104 is connected to the second bit line 107; the seventh driving transistor 1033 in the second driving transistor circuit 103 is connected to the first bit line 106; and the other end of the power supply terminal 101 is connected to the fourth driving transistor circuit 105.
[0035] The first driving transistor circuit 102 is used to control the gate and drain of the first driving transistor 1021 to have no voltage difference via the power supply terminal 101; and,
[0036] Specifically, the first driving transistor circuit 102 is used to control the gate and drain of the first driving transistor 1021 to have no voltage difference through the power supply terminal 101, so as to prevent the generation of large leakage current and the loss of negative voltage.
[0037] Among them, the first driving transistor 1021 is an NMOS transistor.
[0038] Among them, the NMOS transistor is an N-channel metal-oxide-semiconductor field-effect transistor (N-channel MOSFET). It controls the conductive channel between the source and drain by the gate voltage to realize the switching or signal amplification function of the circuit.
[0039] The statement that there is no voltage difference between the gate and drain of the first driving transistor 1021 means that the voltage difference between the gate and drain is 0.
[0040] Among them, power supply 101 is a specific VWBL power supply.
[0041] The second driving transistor circuit 102 is used to control the gate and drain of the seventh driving transistor 1033 to have no voltage difference via the power supply terminal 101, so as to prevent negative voltage from leaking to the first bit line 106 and assisting in writing data to the unselected memory cell 20; and...
[0042] Specifically, the second driving transistor circuit 102 is used to control the gate and drain of the seventh driving transistor 1033 to have no voltage difference through the power supply terminal 101, so as to prevent the negative voltage from leaking to the first bit line 106 that should not be selected, and to assist the writing of data to the unselected memory cell 20.
[0043] Among them, the seventh driving transistor 1033 is an NMOS transistor.
[0044] Among them, the unselected storage cell 20 is an SRAM storage cell.
[0045] Among them, the SRAM storage cell is the basic storage structure of static random access memory, which is used to stably store one bit of binary data when powered on.
[0046] Among them, the first bit line 106 is the BL bit line; the second bit line 107 is the BLB bit line.
[0047] Among them, the BL bit line is one of the key circuit structures in semiconductor memory, used to transmit data signals in the memory array.
[0048] Among them, the BLB bit line is a complementary bit line in static random access memory. Together with BL, it forms a differential signal transmission pair to improve the anti-interference capability and stability of read and write operations.
[0049] The third driving transistor circuit 104 is used to control the gate and drain of the ninth driving transistor 1041 to have no voltage difference through the power supply terminal 101, so as to prevent the negative voltage from leaking to the second bit line 107 that should not be selected, and to assist the writing of data to the unselected memory cell 20.
[0050] Specifically, the third driving transistor circuit 104 is used to control the gate and drain of the ninth driving transistor 1041 to have no voltage difference through the power supply terminal 101, so as to prevent the negative voltage from leaking to the second bit line 107 and assisting in the writing of data to the unselected memory cell 20.
[0051] In summary, the anti-miswrite circuit for memory cells provided in this embodiment includes a first driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the first driving transistor; a second driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the seventh driving transistor to prevent negative voltage leakage to the first bit line, thus assisting in writing data to unselected memory cells; and a third driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the ninth driving transistor to prevent negative voltage leakage to the second bit line, thus assisting in writing data to unselected memory cells. Through the cooperation of the power supply, the first driving transistor circuit, the second driving transistor circuit, the third driving transistor circuit, the fourth driving transistor circuit, the first bit line, and the second bit line, the leakage of the negative potential charge required for write assistance can be prevented, thereby avoiding the erroneous flipping of memory cells corresponding to unselected bit lines.
[0052] Figure 2 Schematic diagram of the anti-miswrite circuit for the memory cell provided in the embodiments of this application Figure 2 The first driving transistor circuit 102 includes: a first driving transistor 1021, a second driving transistor 1022, a third driving transistor 1023 and a fourth driving transistor 1024.
[0053] In this circuit, the source of the first driving transistor 1021 is connected to the power supply terminal 101; the drain of the first driving transistor 1021 is connected to the source of the second driving transistor 1022; the drain of the second driving transistor 1022 is connected to the source of the third driving transistor 1023; the drain of the third driving transistor 1023 is connected to the drain of the fourth driving transistor 1024; the drain of the fourth driving transistor 1024 is connected to the gates of the first driving transistor 1021 and the second driving transistor 1022, respectively; the source of the fourth driving transistor 1024 is connected to the power supply terminal 101; and the gates of the third driving transistor 1023 and the fourth driving transistor 1024 are connected to the drain of the first driving transistor 1021, respectively.
[0054] Among them, the first driving transistor 1021 is an NMOS transistor; the second driving transistor 1022 is a PMOS transistor; the third driving transistor 1023 is a PMOS transistor; and the fourth driving transistor 1024 is a PMOS transistor.
[0055] PMOS transistors are metal-oxide-semiconductor field-effect transistors that use holes as charge carriers and form a conductive channel when a negative voltage is applied to the gate. They are commonly used in drivers, CMOS logic circuits, and low-power designs.
[0056] The source of the first driving transistor circuit 102 is used to determine the first voltage through the power supply terminal 101.
[0057] The first voltage is a negative voltage.
[0058] The gate of the first driving transistor circuit 102 is used to determine a second voltage that is the same as the first voltage through the drain of the fourth driving transistor 1024, the source of the fourth driving transistor 1024 and the power supply terminal 101, so as to obtain that there is no voltage difference between the gate and drain of the first driving transistor 1021.
[0059] The second voltage is a negative voltage.
[0060] Specifically, after connecting the power supply terminal 101 to the fourth driving transistor 1024 of the latch corresponding to the write driving transistor (first driving transistor circuit 102), the gate of the first driving transistor circuit 102 determines a second voltage that is the same as the first voltage through the drain of the fourth driving transistor 1024, the source of the fourth driving transistor 1024 and the power supply terminal 101, so as to obtain that there is no voltage difference between the gate and drain of the first driving transistor 1021, thus avoiding the generation of large leakage current and the loss of negative voltage.
[0061] In addition, there is a physical pin between the drain of the second driving transistor 1022 and the source of the third driving transistor 1023.
[0062] For example, the physical pin connection is VDD.
[0063] In addition, a device interface board, or DIB, is connected between the gate of the first driving transistor 1021 and the gate of the second driving transistor 1022.
[0064] Continue to refer to Figure 2 The second driving transistor circuit 103 includes: a fifth driving transistor 1031, a sixth driving transistor 1032 and a seventh driving transistor 1033.
[0065] The source of the fifth driving transistor 1031 is connected to the power supply terminal 101; the drain of the fifth driving transistor 1031 is connected to the source of the sixth driving transistor 1032; the drain of the sixth driving transistor 1032 is connected to the gate of the seventh driving transistor 1033; the gate of the fifth driving transistor 1031 is used to receive control signals; the source of the seventh driving transistor 1033 is connected to the first driving transistor circuit 102; and the drain of the seventh driving transistor 1033 is connected to the first bit line 106.
[0066] Among them, the fifth driving transistor 1031 is an NMOS transistor; the sixth driving transistor 1032 is an NMOS transistor.
[0067] The gate of the seventh driving transistor 1033 is used to determine the corresponding third voltage through the sixth driving transistor 1032, the fifth driving transistor 1031 and the power supply terminal 101.
[0068] Specifically, after connecting the power supply terminal 101 to the source of the sixth driving transistor 1032 that generates the address selection signal, the sixth driving transistor 1032 and the fifth driving transistor 1031 configure the gate level of the seventh driving transistor 1033, which is controlled by the address selection signal corresponding to the unselected memory cell, to a third voltage.
[0069] For example, the address selection signal is YSW, which is the signal that controls the selected address of SARM.
[0070] The third voltage is a negative voltage.
[0071] The source of the seventh driving transistor 1033 is used to determine the fourth voltage, which is the same as the third voltage, through the first driving transistor circuit 102 and the power supply terminal 101, so that there is no voltage difference between the gate and drain of the seventh driving transistor 1033, in order to prevent the negative voltage from leaking to the first bit line 106 and to assist in writing data to the unselected memory cell 20.
[0072] The fourth voltage is a negative voltage.
[0073] Among them, the first bit line 106 is an unselected bit line.
[0074] Continue to refer to Figure 2The second driving transistor circuit 103 also includes an eighth driving transistor 1034 and a physical pin 1035.
[0075] The gate of the eighth driving transistor 1034 is connected to the gate of the sixth driving transistor 1032.
[0076] The source of the eighth driving transistor 1034 is connected to the drain of the sixth driving transistor 1032.
[0077] Among them, the eighth driving transistor 1034 is a PMOS transistor.
[0078] The drain of the eighth driver transistor 1034 is connected to the physical pin 1035 via a circuit.
[0079] For example, physical pin 1035 is the VDD pin.
[0080] Continue to refer to Figure 2 The third driving transistor circuit 104 includes: the ninth driving transistor 1041, the tenth driving transistor 1042, the eleventh driving transistor 1043, the twelfth driving transistor 1044, and the thirteenth driving transistor 1045.
[0081] Specifically, the gate of the ninth driving transistor 1041 is connected to the second driving transistor circuit 103; the drain of the ninth driving transistor 1041 is connected to the second bit line 107; the source of the ninth driving transistor 1041 is connected to the drain of the tenth driving transistor 1042, the source of the eleventh driving transistor 1043, the gate of the twelfth driving transistor 1044, and the gate of the thirteenth driving transistor 1045, respectively; and the source of the tenth driving transistor 1042 is connected to the power supply terminal 101. Connections: The drain of the tenth driving transistor 1042 is connected to the source of the eleventh driving transistor 1043; the drain of the eleventh driving transistor 1043 is connected to the source of the twelfth driving transistor 1044; the drain of the twelfth driving transistor 1044 is connected to the gate of the tenth driving transistor 1042, the gate of the eleventh driving transistor 1043, and the source of the thirteenth driving transistor 1045; the drain of the thirteenth driving transistor 1045 is connected to the power supply terminal 101.
[0082] Among them, the ninth driving transistor 1041 is an NMOS transistor; the tenth driving transistor 1042 is an NMOS transistor; the eleventh driving transistor 1043 is a PMOS transistor; the twelfth driving transistor 1044 is a PMOS transistor; and the thirteenth driving transistor 1045 is an NMOS transistor.
[0083] The gate of the ninth driving transistor 1041 is used to determine the corresponding fifth voltage through the second driving transistor circuit 103 and the power supply terminal 101.
[0084] The source of the ninth driving transistor 1041 is used to determine the sixth voltage, which is the same as the fifth voltage, through the tenth driving transistor 1042 and the power supply terminal 101, so that there is no voltage difference between the gate and drain of the ninth driving transistor (1041), so as to prevent the negative voltage from leaking to the second bit line 107 and assisting the writing of data to the unselected memory cell 20.
[0085] In addition, a data input pin, namely DI, is connected between the gate of the tenth driving transistor 1042 and the gate of the eleventh driving transistor 1043.
[0086] In addition, there is a physical pin between the drain of the eleventh driving transistor 1043 and the source of the thirteenth driving transistor 1045.
[0087] Continue to refer to Figure 2 The fourth driving transistor circuit 105 includes: the fourteenth driving transistor 1051 and a capacitor 1052.
[0088] The source of the fourteenth driving transistor 1051 is connected to the power supply terminal 101 via a circuit.
[0089] Among them, the fourteenth driving transistor 1051 is an NMOS transistor.
[0090] In addition, the drain of the fourteenth drive transistor 1051 is the common ground terminal VSS.
[0091] One end of capacitor 1052 is connected to power supply terminal 101 via a circuit.
[0092] Among them, the power supply terminal 101 can be coupled to a negative potential due to the influence of capacitor 1052.
[0093] The other end of capacitor 1052 is connected to the second driving transistor circuit 103.
[0094] In summary, the anti-miswrite circuit for memory cells provided in this embodiment includes a first driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the first driving transistor; a second driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the seventh driving transistor to prevent negative voltage leakage to the first bit line, thus assisting in writing data to unselected memory cells; and a third driving transistor circuit that, through power supply control, ensures no voltage difference between the gate and drain of the ninth driving transistor to prevent negative voltage leakage to the second bit line, thus assisting in writing data to unselected memory cells. Through the cooperation of one or more components among the power supply, the first driving transistor circuit, the second driving transistor circuit, the third driving transistor circuit, the fourth driving transistor circuit, the first bit line, and the second bit line, the leakage of the negative potential charge required for write assistance can be prevented, thereby avoiding erroneous flipping of memory cells corresponding to unselected bit lines.
[0095] Figure 3This is a flowchart illustrating the method for preventing accidental writes to a storage unit provided in this application embodiment. The execution entity in this embodiment can be... Figure 1 The circuit for preventing accidental writes to the memory cell in the illustrated embodiment is not particularly limited in this embodiment. Figure 3 As shown, the method includes:
[0096] S301: First driving transistor circuit, used to control the gate and drain of the first driving transistor to have no voltage difference through the power supply terminal; and,
[0097] S302: The second driver transistor circuit is used to control the gate and drain of the seventh driver transistor to ensure there is no voltage difference, thus preventing negative voltage from leaking to the first bit line and assisting in writing data to unselected memory cells; and...
[0098] In this embodiment, the second driving transistor circuit includes: a fifth driving transistor, a sixth driving transistor, and a seventh driving transistor; correspondingly, the method further includes steps a~b:
[0099] Step a: The gate of the seventh driving transistor is used to determine the corresponding third voltage through the sixth driving transistor, the fifth driving transistor, and the power supply terminal.
[0100] Step b: The source of the seventh driving transistor is used to determine the fourth voltage, which is the same as the third voltage, through the first driving transistor circuit and the power supply terminal. This ensures that there is no voltage difference between the gate and drain of the seventh driving transistor, preventing negative voltage from leaking to the first bit line and assisting in writing data to unselected memory cells.
[0101] In addition, steps c~f are also included:
[0102] Step c: When writing to the selected memory cell via the first bit line and when writing to the selected memory cell via the second bit line, the fifth driver transistor is used to receive the control signal and is turned on when the control signal is high.
[0103] In this embodiment, the negative voltage charge at the power supply terminal is dissipated during the writing process of the selected memory cell, causing the power supply terminal to be pulled back to 0V. If the initial control signal does not become high, the power supply terminal will be raised to a positive potential. Furthermore, when YSW is still connected to the power supply terminal, it may cause the bit line corresponding to the unselected memory cell to conduct with the output of the write driver transistor, thereby causing the memory cell corresponding to the unselected bit line to flip incorrectly. Therefore, a fifth driver transistor controlled by the control signal is added between the power supply terminal and the sixth driver transistor.
[0104] For example, the control signal is the delay signal S0 of boost ctl, where the delay signal is a time delay signal.
[0105] Step d: At the power supply end, after the fifth driving transistor is turned on and the control signal changes from high level to low level, a negative voltage is generated.
[0106] Step e: The fifth driving transistor transmits a negative voltage to the source of the sixth driving transistor via a control signal; when the negative voltage is transmitted to the source of the sixth driving transistor and the control signal is low, it is turned off.
[0107] Specifically, the fifth driving transistor transmits a negative voltage to the source S1 of the sixth driving transistor through a control signal. When the negative voltage is transmitted to the source S1 of the sixth driving transistor and the control signal S0 is low, it is turned off to keep YSW at a negative voltage during the writing process when controlling an unselected memory cell, and prevent it from rising to a positive voltage.
[0108] S0 is further used to represent the gate level of the fifth driving transistor.
[0109] Step f: After writing to the selected memory cell via the first bit line and writing to the selected memory cell via the second bit line, the fifth driver transistor is turned on again when the control signal is high; and the source of the sixth driver transistor is updated to the common ground terminal.
[0110] For example, the source S1 of the sixth driving transistor is updated to the common ground terminal VSS.
[0111] Furthermore, the level changes of the control signal boost ctl, the power supply terminal VWBL, the gate S0 of the fifth driving transistor, and the source S1 of the sixth driving transistor in the above steps, such as Figure 4 The diagram shows the level change.
[0112] S303: The third driving transistor circuit is used to control the gate and drain of the ninth driving transistor to ensure that there is no voltage difference between them through the power supply terminal, so as to prevent negative voltage from leaking to the second bit line and assisting in writing data to unselected memory cells.
[0113] In summary, the method for preventing accidental writes to memory cells provided in this embodiment includes a first driving transistor circuit that controls the gate and drain of the first driving transistor to have no voltage difference via the power supply terminal; a second driving transistor circuit that controls the gate and drain of the seventh driving transistor to have no voltage difference via the power supply terminal to prevent negative voltage from leaking to the first bit line to assist in writing data to unselected memory cells; and a third driving transistor circuit that controls the gate and drain of the ninth driving transistor to have no voltage difference via the power supply terminal to prevent negative voltage from leaking to the second bit line to assist in writing data to unselected memory cells. Through the cooperation of the power supply terminal, the first driving transistor circuit, the second driving transistor circuit, the third driving transistor circuit, the fourth driving transistor circuit, the first bit line, and the second bit line, the leakage of the negative potential charge required for write assistance can be prevented, thus avoiding accidental flipping of memory cells corresponding to unselected bit lines.
[0114] Furthermore, the method for preventing accidental writes to memory cells provided in this embodiment involves the following steps: When writing to a selected memory cell via the first bit line and the second bit line, the fifth driving transistor receives a control signal and is turned on when the control signal is high. At the power supply end, after the fifth driving transistor is turned on and the control signal changes from high to low, a negative voltage is generated. The fifth driving transistor transmits the negative voltage to the source of the sixth driving transistor via the control signal. When the negative voltage is transmitted to the source of the sixth driving transistor and the control signal is low, it is turned off. After writing to the selected memory cell via the first bit line and the second bit line is completed, the fifth driving transistor is turned on again when the control signal is high. Additionally, the source of the sixth driving transistor is updated to a common ground terminal. This ensures that during the writing process, when controlling an unselected memory cell, the voltage remains negative, further preventing accidental flipping of memory cells corresponding to unselected bit lines.
[0115] It should be noted that the anti-miswritten memory cell circuit not only realizes the function of the write auxiliary circuit, but also avoids the accidental flipping of memory cells corresponding to unselected bit lines.
[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A circuit (10) for preventing accidental writes to a memory cell, characterized in that, include: The circuit includes a power supply terminal (101), a first driving transistor circuit (102), a second driving transistor circuit (103), a third driving transistor circuit (104), a fourth driving transistor circuit (105), a first bit line (106), and a second bit line (107), wherein the first driving transistor circuit (102) includes a first driving transistor (1021), the second driving transistor circuit (103) includes a seventh driving transistor (1033), and the third driving transistor circuit (104) includes a ninth driving transistor (1041); Wherein, one end of the power supply terminal (101) is connected to the first driving transistor circuit (102), the second driving transistor circuit (103), and the third driving transistor circuit (104) respectively; the first driving transistor circuit (102) is connected to the third driving transistor circuit (104); the ninth driving transistor (1041) in the third driving transistor circuit (104) is connected to the second bit line (107); the seventh driving transistor (1033) in the second driving transistor circuit (103) is connected to the first bit line (106); the other end of the power supply terminal (101) is connected to the fourth driving transistor circuit (105). The first driving transistor circuit (102) is used to control, via the power supply terminal (101), that there is no voltage difference between the gate and drain of the first driving transistor (1021); and, The second driving transistor circuit (102) is used to control the gate and drain of the seventh driving transistor (1033) to have no voltage difference via the power supply terminal (101), so as to prevent negative voltage from leaking to the first bit line (106) and to assist in writing data to the unselected memory cell (20); and, The third driving transistor circuit (104) is used to control the gate and drain of the ninth driving transistor (1041) to have no voltage difference through the power supply terminal (101) so as to prevent negative voltage from leaking to the second bit line (107) and assisting in the writing of data to the unselected memory cell (20).
2. The anti-miswrite circuit (10) for the storage unit according to claim 1, characterized in that, The first driving transistor circuit (102) includes: a first driving transistor (1021), a second driving transistor (1022), a third driving transistor (1023) and a fourth driving transistor (1024); The source of the first driving transistor (1021) is connected to the power supply terminal (101); the drain of the first driving transistor (1021) is connected to the source of the second driving transistor (1022); the drain of the second driving transistor (1022) is connected to the source of the third driving transistor (1023); the drain of the third driving transistor (1023) is connected to the drain of the fourth driving transistor (1024); the drain of the fourth driving transistor (1024) is connected to the gate of the first driving transistor (1021) and the gate of the second driving transistor (1022); the source of the fourth driving transistor (1024) is connected to the power supply terminal (101); the gates of the third driving transistor (1023) and the fourth driving transistor (1024) are connected to the drain of the first driving transistor (1021). The source of the first driving transistor circuit (102) is used to determine the first voltage through the power supply terminal (101); The gate of the first driving transistor circuit (102) is used to determine a second voltage that is the same as the first voltage through the drain of the fourth driving transistor (1024), the source of the fourth driving transistor (1024) and the power supply terminal (101), so as to obtain that there is no voltage difference between the gate and drain of the first driving transistor (1021).
3. The anti-miswrite circuit (10) for the storage unit according to claim 1, characterized in that, The second driving transistor circuit (103) includes: a fifth driving transistor (1031), a sixth driving transistor (1032) and a seventh driving transistor (1033); The source of the fifth driving transistor (1031) is connected to the power supply terminal (101); the drain of the fifth driving transistor (1031) is connected to the source of the sixth driving transistor (1032); the drain of the sixth driving transistor (1032) is connected to the gate of the seventh driving transistor (1033); the gate of the fifth driving transistor (1031) is used to receive control signals; the source of the seventh driving transistor (1033) is connected to the first driving transistor circuit (102); and the drain of the seventh driving transistor (1033) is connected to the first bit line (106). The gate of the seventh driving transistor (1033) is used to determine the corresponding third voltage through the sixth driving transistor (1032), the fifth driving transistor (1031) and the power supply terminal (101); The source of the seventh driving transistor (1033) is used to determine a fourth voltage that is the same as the third voltage through the first driving transistor circuit (102) and the power supply terminal (101), so that there is no voltage difference between the gate and drain of the seventh driving transistor (1033), so as to prevent the negative voltage from leaking to the first bit line (106) and assisting the writing of data to the unselected memory cell (20).
4. The anti-miswrite circuit (10) for the storage unit according to claim 3, characterized in that, The second driving transistor circuit (103) further includes: an eighth driving transistor (1034) and a physical pin (1035); The gate of the eighth driving transistor (1034) is connected to the gate of the sixth driving transistor (1032). The source of the eighth driving transistor (1034) is connected to the drain of the sixth driving transistor (1032) in a circuit. The drain of the eighth driving transistor (1034) is connected to the physical pin (1035).
5. The anti-miswrite circuit (10) for the storage unit according to claim 1, characterized in that, The third driving transistor circuit (104) includes: a ninth driving transistor (1041), a tenth driving transistor (1042), an eleventh driving transistor (1043), a twelfth driving transistor (1044), and a thirteenth driving transistor (1045). The gate of the ninth driving transistor (1041) is connected to the second driving transistor circuit (103); the drain of the ninth driving transistor (1041) is connected to the second bit line (107); the source of the ninth driving transistor (1041) is connected to the drain of the tenth driving transistor (1042), the source of the eleventh driving transistor (1043), the gate of the twelfth driving transistor (1044), and the gate of the thirteenth driving transistor (1045), respectively; the source of the tenth driving transistor (1042) is connected to the power supply terminal (101). Circuit connections: The drain of the tenth driving transistor (1042) is connected to the source of the eleventh driving transistor (1043); the drain of the eleventh driving transistor (1043) is connected to the source of the twelfth driving transistor (1044); the drain of the twelfth driving transistor (1044) is connected to the gate of the tenth driving transistor (1042), the gate of the eleventh driving transistor (1043), and the source of the thirteenth driving transistor (1045); the drain of the thirteenth driving transistor (1045) is connected to the power supply terminal (101). The gate of the ninth driving transistor (1041) is used to determine the corresponding fifth voltage through the second driving transistor circuit (103) and the power supply terminal (101); The source of the ninth driving transistor (1041) is used to determine a sixth voltage that is the same as the fifth voltage through the tenth driving transistor (1042) and the power supply terminal (101) so that there is no voltage difference between the gate and drain of the ninth driving transistor (1041) to prevent negative voltage from leaking to the second bit line (107) and assisting in the writing of data to the unselected memory cell (20).
6. The anti-miswrite circuit (10) for the storage unit according to claim 4, characterized in that, The fourth driving transistor circuit (105) includes: a fourteenth driving transistor (1051) and a capacitor (1052); The source of the fourteenth driving transistor (1051) is connected to the power supply terminal (101) via a circuit. One end of the capacitor (1052) is connected to the power supply terminal (101) via a circuit. The other end of the capacitor (1052) is connected to the second driving transistor circuit (103).
7. A chip for preventing accidental writes to memory cells, characterized in that, Includes the anti-miswrite circuit for the storage unit as described in any one of claims 1 to 6.
8. A method for preventing accidental writes to a memory cell, characterized in that, The circuit for preventing accidental writes to the memory cell as described in claim 1 includes: The first driving transistor circuit is used to control the gate and drain of the first driving transistor to have no voltage difference via the power supply terminal; and, The second driving transistor circuit is used to control the gate and drain of the seventh driving transistor to have no voltage difference via the power supply terminal, so as to prevent negative voltage from leaking to the first bit line and assisting in writing data to unselected memory cells; and, The third driving transistor circuit is used to control the gate and drain of the ninth driving transistor to have no voltage difference through the power supply terminal, so as to prevent negative voltage from leaking to the second bit line and assisting in the writing of data to the unselected memory cell.
9. The method according to claim 8, characterized in that, The second driving transistor circuit includes: a fifth driving transistor, a sixth driving transistor, and a seventh driving transistor; correspondingly, the method further includes: The gate of the seventh driving transistor is used to determine the corresponding third voltage through the sixth driving transistor, the fifth driving transistor and the power supply terminal; The source of the seventh driving transistor is used to determine a fourth voltage that is the same as the third voltage through the first driving transistor circuit and the power supply terminal, so that there is no voltage difference between the gate and drain of the seventh driving transistor, in order to prevent negative voltage from leaking to the first bit line and to assist in writing data to unselected memory cells.
10. The method according to claim 9, characterized in that, Also includes: When writing to the selected memory cell begins via the first bit line and when writing to the selected memory cell begins via the second bit line, the fifth driving transistor is used to receive control signals and is turned on when the control signal is high. The power supply terminal generates a negative voltage after the fifth driving transistor is turned on and the control signal changes from high level to low level. The fifth driving transistor transmits the negative voltage to the source of the sixth driving transistor via the control signal; when the negative voltage is transmitted to the source of the sixth driving transistor and the control signal is low, it is turned off. After writing to the selected memory cell via the first bit line and writing to the selected memory cell via the second bit line, the fifth driving transistor is turned on again when the control signal is high. Furthermore, the source of the sixth driving transistor is updated to a common ground terminal.