Sram memory array and chip

Abstract

This application provides an SRAM memory array and chip. The SRAM memory array includes at least one column of memory cell arrays, with multiple rows of memory cells. The memory array is used to store data. Multiple read word lines are connected one-to-one with the row direction of the memory cell array to select a target memory cell in the array. The target memory cell is the memory cell to be read. At least one first read bit line is connected one-to-one with the column direction of the memory cell array to transmit a potential signal for a read operation. At least one amplifier is connected one-to-one with the column direction of the memory cell array to identify and amplify the potential signal of the read bit line to output data. At least one second read bit line is connected one-to-one with the first read bit line to deliver charge to the corresponding first read bit line during a read operation. This application can reduce the false read rate of stored data and reduce power consumption.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an SRAM memory array and chip. Background Technology

[0002] In modern high-performance chips, dual-port static random access memory (SRAM) is a core storage component for achieving high-speed parallel data access. It is crucial for improving the data interaction efficiency of on-chip systems and multi-core processors, and ensuring the real-time performance of data processing. Chips need to implement highly reliable read operations to meet the needs of highly integrated, high-speed storage applications, while also taking into account the design requirements of low power consumption and small area.

[0003] In related technologies, pull-up circuits consisting of multiple series-connected PMOS transistors are typically used to compensate for leakage current in dual-port SRAM read lines. However, this series-connected PMOS transistor design leads to complex layout routing, large chip area overhead, and introduces additional signal delay, reducing read operation speed. Summary of the Invention

[0004] This application provides an SRAM storage array and chip to simplify the structure and reduce power consumption.

[0005] In a first aspect, embodiments of this application provide an SRAM memory array and chip, including:

[0006] An array of storage cells with at least one column, the array comprising multiple rows of storage cells; the storage array is used to store data;

[0007] Multiple read lines are connected one-to-one with the rows of the storage cell array to select the target storage cell in the storage cell array; the target storage cell is the storage cell to be read.

[0008] At least one first read bit line is connected one-to-one with the column direction of the memory cell array to transmit the potential signal for the read operation;

[0009] At least one amplifier is connected to each column of the memory cell array to identify and amplify the potential signal of the read bit line in order to output data;

[0010] At least one second read bit line is connected to the first read bit line in a one-to-one correspondence, and is used to deliver charge to the corresponding first read bit line during a read operation.

[0011] In one possible design, a single storage cell in the storage cell array is an 8-tube dual-port storage cell, comprising a 6-tube storage sub-cell and a 2-tube read sub-cell.

[0012] The two-tube read subunit is connected to the six-tube storage subunit, the corresponding read word line, and the corresponding first read bit line, respectively, and is used to establish a read data transmission path between the six-tube storage subunit and the corresponding first read bit line when triggered by the strobe signal of the corresponding read word line.

[0013] In one possible design, one end of the second read bit line is connected to the end of the corresponding first read bit line to enable charge interaction between the second read bit line and the first read bit line.

[0014] In one possible design, the second read bit line has the same length as the corresponding connected first read bit line and is arranged in parallel.

[0015] In one possible design, the first read bit line is connected to all the column-up storage cells of the corresponding connected storage cell array;

[0016] Before the read operation is initiated, the first read bit line and the second read bit line are set to a high potential.

[0017] In one possible design, the read word line is connected one-to-one with the row-oriented memory cells of the memory cell array, and is used to output a high-level strobe signal during a read operation to select all memory cells in the row where the target memory cell is located.

[0018] In one possible design, the amplifier is used to determine the real-time potential of the first read bit line connected to the target memory cell when a read operation is performed on the target memory cell, and compare the real-time potential of the first read bit line with the high potential identification threshold.

[0019] If the real-time potential is greater than the high potential identification threshold, then the first preset data is output;

[0020] If the real-time potential is less than or equal to the high potential identification threshold, then the second preset data is output.

[0021] In one possible design, the 2-transistor read subunit includes two transistors connected in series. The gates of the transistors are connected to the corresponding read word lines and the storage nodes of the 6-transistor storage subunit, respectively. The drains are connected to the corresponding first read bit lines, and the sources are connected to ground.

[0022] In one possible design, the capacitance of the equivalent parasitic capacitance formed by the second read bit line and the first read bit line is positively correlated with the length of the second read bit line.

[0023] Secondly, embodiments of this application provide a chip including the SRAM memory array described in the first aspect and various possible designs of the first aspect.

[0024] The SRAM storage array and chip provided in this embodiment include an SRAM storage array comprising at least one column of storage cells, the storage cell array including multiple rows of storage cells; the storage array is used to store data; multiple read word lines are connected one-to-one with the row direction of the storage cell array to select a target storage cell in the storage cell array; the target storage cell is the storage cell to be read; at least one first read bit line is connected one-to-one with the column direction of the storage cell array to transmit the potential signal of the read operation; at least one amplifier is connected one-to-one with the column direction of the storage cell array to identify and amplify the potential signal of the read bit line to output data; at least one second read bit line is connected one-to-one with the first read bit line to deliver charge to the corresponding first read bit line during the read operation. The SRAM memory array provided in this application embodiment, by configuring second read lines that correspond one-to-one with the first read lines, achieves charge compensation for leakage current during read operations by using the second read lines to deliver charge to the first read lines. This eliminates the DC path formed by the keeper pull-up circuit in related technologies, fundamentally preventing static power consumption during read operations, reducing energy consumption, and lowering the false read rate of stored data. Furthermore, this memory array achieves the compensation function solely through the second read lines with a metal wire structure, eliminating the need for additional semiconductor devices, significantly simplifying the SRAM layout and routing process, reducing chip area overhead, and improving the integration density of the memory array. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0026] Figure 1 A schematic diagram of a read bit line pull-up holding circuit provided for related technologies;

[0027] Figure 2 This is a schematic diagram of the structure of an SRAM storage array provided in an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application.

[0029] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] It should be noted that the SRAM memory array and chip provided in this application can be used in the field of chip technology, or in any field other than the field of chip technology. The application fields of the SRAM memory array and chip provided in this application are not limited.

[0032] The SRAM storage array involved in this application is mainly used in high-performance semiconductor integrated circuits (such as system-on-a-chip SOC, multi-core processors, embedded storage modules, high-speed communication chips, etc.) to solve the leakage current interference problem during the dual-port SRAM read operation.

[0033] In complex, highly integrated storage systems, chips need to achieve high-speed, high-reliability read operations for dual-port SRAMs while also taking into account low power consumption and small area design requirements. For example, in an 8-transistor dual-port SRAM array, the read error rate of read 1 operations must be close to 0, and the read operation clock to output delay must be controlled at the nanosecond level to meet the chip's high-speed data processing needs.

[0034] In related technologies, a series-connected pull-up and hold circuit consisting of multiple series-connected P-type metal-oxide-semiconductor (PMOS) transistors is typically used to compensate for the charge on the read lines of a two-port SRAM, thereby suppressing the potential pull-down effect of leakage current. For example, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the pull-up holding circuit for read bits provided for related technologies. For highly integrated single-ended read-type 8-transistor dual-port SRAM arrays, three PMOS transistors connected in series can be independently configured for each column of read bits. By forming a pull-up path from the power supply to the read bits, the charge is continuously replenished to the read bits, offsetting the effect of superimposed leakage current from unselected 0-state memory cells.

[0035] However, in the above compensation methods, the keeper circuit with series PMOS transistors forms a DC path from power supply to ground during read 0 operations, generating continuous static power consumption and significantly increasing the chip's energy consumption burden, which contradicts the trend of low-power design. At the same time, the keeper circuit configured separately for each column of read bit lines requires additional semiconductor device layout and complex layout routing, which not only significantly increases the chip's area overhead and reduces the integration of the memory array, but also easily causes signal crosstalk due to dense wiring, affecting circuit stability. Furthermore, a fixed number of PMOS transistors will introduce a fixed signal delay, reducing the read operation speed of dual-port SRAM. In addition, the design of the number and size of PMOS transistors makes it difficult to balance the charge compensation effect of read 1 and the potential pull-down efficiency of read 0. In ultra-large-size memory arrays, insufficient compensation can easily lead to read 1 misreading problems. Therefore, the above methods have high power consumption, low integration, and it is difficult to balance the reliability and speed of read operations.

[0036] To address the aforementioned technical problems, the inventors of this application have discovered that by configuring second read lines that correspond one-to-one with the first read lines, and utilizing the equivalent parasitic capacitance formed by the second and first read lines to transfer charge to the first read lines, passive charge compensation for leakage current can be achieved. This replaces the traditional PMOS transistor keeper pull-up circuit, eliminating the need for additional semiconductor devices and allowing the compensation capability to adaptively match the leakage current requirements of the memory array. Based on this, embodiments of this application provide a dual-port SRAM memory array.

[0037] The technical solution of this application will be described in detail below with reference to optional embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0038] Figure 2 This is a schematic diagram of the structure of an SRAM memory array provided in an embodiment of this application. Figure 2 As shown, the SRAM memory array 20 may include:

[0039] A storage cell array 201 with at least one column, comprising multiple rows of storage cells; the storage array is used to store data;

[0040] Multiple read word lines 202 are connected one-to-one with the rows of the storage cell array to select the target storage cell in the storage cell array; the target storage cell is the storage cell to be read.

[0041] At least one first read bit line 203 is connected one-to-one with the column direction of the memory cell array to transmit the potential signal for the read operation;

[0042] At least one amplifier 204 is connected one-to-one with the column of the memory cell array to identify and amplify the potential signal of the read bit line in order to output data;

[0043] At least one second read bit line 205 is connected to the first read bit line in a one-to-one correspondence, and is used to deliver charge to the corresponding first read bit line during the read operation.

[0044] Among them, the storage cell array 201 is the core component of the SRAM storage array. It is formed by arranging multiple rows and columns of storage cells according to rules and is the smallest array unit for realizing physical data storage.

[0045] In this context, the storage unit is the smallest hardware unit in the SRAM storage array that implements the latching and storage of binary data (0 / 1). In this embodiment, it is an 8-transistor dual-port storage unit, comprising a 6-transistor storage subunit and a 2-transistor read subunit, which are responsible for stable data latching and read operation data transmission, respectively.

[0046] Among them, the Read Word Line (RWL) is a control signal line that is connected one-to-one with the row direction of the memory cell array. It selects or turns off all memory cells in the corresponding row by outputting high and low levels, and is the core component for realizing SRAM row selection.

[0047] The target storage unit is the storage unit where data is to be read during the read operation. Its specific location is determined by the row strobe signal of the read word line, and it is the data source unit for the read operation.

[0048] Among them, the first read bit line 203 is a signal transmission line that is connected one-to-one with the column direction of the memory cell array. It is used to transmit the read operation potential signal output by the target memory cell and is the core transmission component connecting the memory cell and the amplifier.

[0049] Among them, amplifier 204 is a sense amplifier (SA), which is the core signal recognition component for SRAM read operation. It can identify and amplify the weak potential changes on the first read bit line and convert the analog potential signal into digital data (0 / 1) output.

[0050] The second read bit line 205 is configured in a one-to-one correspondence with the first read bit line 203. It forms an equivalent parasitic capacitance through electrical connection with the first read bit line, and is the core component for realizing charge compensation during read operation.

[0051] In this embodiment, from Figure 2 As shown, the SRAM memory array contains an m-column memory cell array 201. Each column of the memory cell array consists of n rows of 8-tube dual-port memory cells arranged along the row direction. All memory cells are used to independently latch and store binary data.

[0052] There are n Read Word Lines (RWLs), each connected to a row of the memory cell array. Each read word line is simultaneously connected to the memory cell in the m columns of the corresponding row, thus enabling synchronous selection of the entire row of memory cells.

[0053] There are m first read bit lines 203 (RBL), each of which is connected to a column of the memory cell array. Each first read bit line is simultaneously connected to a memory cell in n rows of the corresponding column, and is used to transmit the read operation potential signal of the corresponding column.

[0054] m amplifiers 204 (SA) are connected one-to-one with a column of the memory cell array and directly electrically connected to the output terminal of the first read bit line of the corresponding column, so as to realize the real-time acquisition, identification and amplification of the potential signal of the first read bit line.

[0055] m second reading lines 205, in Figure 2 In Chinese, it is represented by RBL_BAK (Read Bit Line_Backup). Each second read bit line is configured in one-to-one correspondence with a first read bit line. The two are of equal length, arranged in parallel and electrically connected at their ends. An inherent equivalent parasitic capacitance is formed between the second read bit line and the first read bit line under the chip manufacturing process. The second read bit line achieves charge exchange with the first read bit line through this equivalent parasitic capacitance.

[0056] In the specific work process, let's take reading the digital data "1" stored in the target storage unit of row i and column j as an example.

[0057] Before the read operation is initiated, all m first read bit lines 203 and their corresponding second read bit lines 205 are synchronously precharged through the SRAM precharge unit, so that the potentials of all first read bit lines 203 and second read bit lines 205 are charged to the power supply high potential (Voltage Drain Drain, VDD). At this time, the equivalent parasitic capacitance formed by the second read bit line 205 and the first read bit line 203 completes the charge pre-store, providing a charge source for subsequent charge compensation.

[0058] After the read operation is initiated, the read word line 202 corresponding to the i-th row outputs a high-level strobe signal, while the read word lines 202 of the remaining n-1 rows remain in a low-level off state. The high-level signal of the read word line 202 of the i-th row triggers the read sub-units of all memory cells in the i-th row. Only the target memory cell (the j-th column of the i-th row) establishes a read data transmission path with the first read bit line 203 of the j-th column, while the memory cells of the other columns remain disconnected from the corresponding first read bit line 203.

[0059] The target memory cell stores data as "1", and its read sub-cell is in a turned-off state. The first read bit line 203 of the j-th column should maintain a pre-charged high potential. However, in the j-th column memory cell array, the n-1 rows of unselected memory cells storing data in a 0 state will generate a micro-conduction leakage current. This leakage current will slowly pull down the potential of the first read bit line 203 of the j-th column. At this time, the equivalent parasitic capacitance between the second read bit line 205 and the first read bit line 203 of the j-th column forms a potential difference due to the potential drop of the first read bit line 203. The second read bit line 205 continuously supplies charge to the first read bit line 203 through the equivalent parasitic capacitance, offsetting the potential pull-down effect of the leakage current and maintaining the high potential of the first read bit line 203.

[0060] The amplifier 204 in column j acquires the potential signal of the first read line 203 in real time and compares this potential signal with the high potential recognition threshold inside the amplifier 204. Due to the charge compensation effect of the second read line 205, the potential of the first read line 203 is always higher than the high potential recognition threshold within the preset recognition time window of the amplifier 204. After amplifying the high potential signal, the amplifier 204 outputs the digital data "1", completing this read operation.

[0061] After the read operation is completed, the i-th row read word line 202 returns to the low-level off state, the read data transmission path between the target memory cell and the first read bit line 203 is disconnected, the pre-charge unit is restarted, and all the first read bit lines 203 and the second read bit lines 205 are pre-charged to prepare for the next read operation.

[0062] Where i takes values ​​in the range [0, n-1] and j takes values ​​in the range [0, m-1].

[0063] If the data stored in the target memory cell is "0", its read sub-cell will be turned on after being selected, generating a strong pull-down current that is much greater than the leakage current. This will quickly pull the potential of the first read bit line 203 down to ground potential (Voltage Source, VSS). At this time, the charge transfer speed of the second read bit line 205 is much lower than the potential pull-down speed of the first read bit line 203, and will not affect the amplifier 204's recognition of low-potential signals. The amplifier 204 can accurately output the digital data "0".

[0064] In this embodiment, the equivalent parasitic capacitance formed by the second read bit line 205 and the first read bit line 203 is a passive device. Charge pre-stored only during the pre-charging phase, the charge is transferred to the first read bit line 203 via passive charge release during the read operation, eliminating the need for continuous external power supply (VDD). Furthermore, no DC path is formed when reading "0", thus solving the problem of continuous current loss from power supply to ground in traditional keeper circuits when reading "0", significantly reducing power consumption during the read operation.

[0065] In some embodiments, such as Figure 2 As shown, a single storage cell in the storage cell array 201 is an 8-tube dual-port storage cell, including a 6-tube storage sub-cell and a 2-tube read sub-cell;

[0066] The two-tube read subunit is connected to the six-tube storage subunit, the corresponding read word line 202, and the corresponding first read bit line 203, respectively. It is used to establish a read data transmission path between the six-tube storage subunit and the corresponding first read bit line 203 when triggered by the strobe signal of the corresponding read word line 202.

[0067] For example, during the specific operation, if the target memory cell stores data 1 and the read operation is not started, the i-th row read word line 202 outputs a low level, the first N-type metal-oxide-semiconductor field-effect transistor (NMOS) in the 2-transistor read sub-cell is turned off, the link between the 6-transistor memory sub-cell and the first read bit line is disconnected, and no data is transmitted.

[0068] After the read operation is initiated, the i-th row read word line 202 outputs a high-level strobe signal, triggering the first NMOS transistor to turn on. At this time, the storage node of the 6-transistor storage sub-cell outputs a high-level signal corresponding to the data "1", and the second NMOS transistor remains off due to its high gate potential.

[0069] Although the second NMOS transistor is turned off, the two-transistor read sub-unit has already responded to the read word line 202 selection signal, completing the logical establishment of the read data transmission path. The high-potential data characteristics of the six-transistor memory sub-unit are transmitted to the first read bit line side through this path. The first read bit line maintains a pre-charged high potential, providing a basis for subsequent amplifier identification. At the same time, for memory cells that are not selected, their two-transistor read sub-units remain turned off due to the low level of read word line 202, completely disconnected from the first read bit line.

[0070] In this embodiment, the 8-tube dual-port storage unit adopts a split design of "6-tube storage sub-unit and 2-tube read sub-unit". The 2-tube read sub-unit is a dedicated module for read operations, which is only connected to the read word line and the first read bit line and does not participate in any write operation process. The 6-tube storage sub-unit can interact independently with the write operation link, and the read and write operations do not overlap or interfere with the control link of the storage unit.

[0071] In some embodiments, such as Figure 2 As shown, one end of the second read bit line 205 is connected to the end of the corresponding first read bit line 203 to realize charge interaction between the second read bit line 205 and the first read bit line 203.

[0072] The first reading line 203 and the second reading line 205 are made of the same material. One end of the second reading line 205 is laid out parallel to the first reading line 203 and the end is connected.

[0073] In this embodiment, one end of the second read bit line 205 is connected to the end of the corresponding first read bit line 203. No additional semiconductor devices (PMOS transistors) need to be configured. Compared with the traditional keeper circuit design that requires multiple series PMOS transistors in each column, this solution does not require additional device layout and complex wiring, simplifying the SRAM layout design process.

[0074] In some embodiments, the second read bit line 205 has the same length as the corresponding connected first read bit line 203 and is arranged in parallel.

[0075] Specifically, the equivalent parasitic capacitance formed by the second read bit line 205 and the first read bit line 203 dynamically changes with the length of the first read bit line 203 (i.e., the number of corresponding column memory cells). The larger the memory array size and the stronger the leakage current, the larger the equivalent parasitic capacitance and the stronger the charge transfer capability, thus achieving adaptive matching between leakage current compensation capability and memory array size. Furthermore, without the fixed signal delay introduced by the PMOS transistor in the traditional keeper circuit, the clock-to-output delay of the SRAM read operation is not increased, ensuring the high-speed read operation performance of the dual-port SRAM.

[0076] In this embodiment, the parallel arrangement of the same lengths ensures that the parasitic capacitance between the second read line 205 and the first read line 203 is evenly distributed along the column direction, without any local capacitance being too strong or too weak. This allows for uniform charge compensation at all positions along the column direction of the first read line 203.

[0077] In some embodiments, such as Figure 2 As shown, the first read bit line 203 is connected to all the column-up memory cells of the corresponding memory cell array 201;

[0078] Before the read operation is started, the first read bit line 203 and the second read bit line 205 are set to a high potential.

[0079] In this context, "all storage cells in the column direction are connected" means that a single first read bit line 203 is connected to all storage cells arranged along the row direction in the corresponding column.

[0080] In practical operation, when the SRAM is idle, all read word lines and write word lines output a low level, and there is no data interaction between the memory cell and the external link. At this time, the pre-charge stage is triggered, and the pre-charge unit enters the working state. The output terminal of the pre-charge unit is electrically connected to the first read bit line 203 of all m columns. Since the second read bit line 205 of each column is electrically connected to the end of the first read bit line 203, the pre-charge unit synchronously delivers the charge of the high power supply potential VDD to all the first read bit lines 203 and the corresponding second read bit lines 205 of all m columns, charging them uniformly. After a preset pre-charge time, the potential of all first read bit lines 203 and second read bit lines 205 is charged to the high power supply potential VDD. At this time, the equivalent parasitic capacitance formed by the second read bit line 205 and the first read bit line 203 completes the charge pre-store, providing a sufficient charge source for charge compensation in subsequent read operations. After the first read bit line 203 and the second read bit line 205 are stably set to a high potential, the precharge unit shuts off the charging path and exits the working state. The SRAM completes the precharge stage and enters the read operation state. At this time, the first read bit line 203 and the second read bit line 205 remain at a high potential until the read word line outputs a strobe signal to officially start the read operation.

[0081] In this embodiment, before the read operation is started, the first read bit line 203 and the second read bit line 205 are charged to a high potential, so that the equivalent parasitic capacitance formed by the two completes the charge pre-stored, providing a sufficient charge basis for the second read bit line 205 to transfer charge to the first read bit line 203 during the read operation.

[0082] In some embodiments, such as Figure 2 As shown, the read word line 202 is connected one-to-one with the row-oriented memory cells of the memory cell array 201, and is used to output a high-level strobe signal during the read operation to select all memory cells in the row where the target memory cell is located.

[0083] from Figure 2 As can be seen from the diagram, based on the structure of the n rows of the memory cell array, n independent read word lines (RWL) are configured, numbered sequentially as RWL[0], RWL[1]...RWL[n-1], with the number of read word lines corresponding one-to-one with the number of rows. Each read word line extends along the row direction of the memory cell array, and a single RWL[i] is only connected to the m-column 8-tube dual-port memory cell in the i-th row. The structure of the M columns is configured with m first read bit lines (RBL), numbered sequentially as RBL[0], RBL[1]...RBL[m-1]. At the same time, m second read bit lines are configured, represented by RBL_BAK, numbered sequentially as RBL_BAK[0], RBL_BAK[1]...RBL_BAK[m-1]. There are m amplifiers, numbered sequentially as SA[0], SA[1]...SA[m-1].

[0084] Understandable, Figure 2 The capacitor in the figure is only used to represent the equivalent parasitic capacitance formed by charging the first read bit line 203 and the second read bit line 205 to a high potential, and is an exemplary representation.

[0085] In practical operation, when the SRAM is in read-read state, all n read word lines output a low-level signal (VSS), and the first NMOS transistor of the two-transistor read sub-unit in all rows remains off. The read data transmission path between all memory cells in a row and the first read bit line of the corresponding column is disconnected. When it is necessary to read the target memory cell in row i and column j, the SRAM row control module sends a drive instruction to the RWL[i] corresponding to row i, controlling RWL[i] to switch from low level to power supply high level (VDD) strobe signal. The read word lines of the remaining n-1 rows remain low level, realizing precise row-direction addressing. The high-level strobe signal output by RWL[i] is transmitted to the gate of the two-transistor read sub-unit of all memory cells in row i and column m, triggering the two-transistor read sub-units of all memory cells in the row to enter the standby state. At this time, the two-transistor read sub-unit of each memory cell in the row prepares to establish a read data transmission path with the first read bit line of the corresponding column according to the state of its stored data. Only the first read bit line of column j cooperates to complete the subsequent data transmission.

[0086] In this embodiment, the read word lines are connected one-to-one with the row-oriented storage units, so that the strobe signal of a single read word line only acts on the storage unit of the corresponding row, and the read word lines of other rows always remain at a low level, so that cross-row storage units will not be accidentally triggered.

[0087] In some embodiments, amplifier 204 is used to determine the real-time potential of the first read bit line 203 connected to the target memory cell when a read operation is performed on the target memory cell, and compare the real-time potential of the first read bit line 203 with a high potential identification threshold.

[0088] If the real-time potential is greater than the high potential recognition threshold, the first preset data is output.

[0089] If the real-time potential is less than or equal to the high potential recognition threshold, then the second preset data is output.

[0090] Optionally, the high potential identification threshold refers to a fixed potential threshold preset inside the amplifier, which varies depending on the circuit and can be set independently according to requirements. This embodiment does not impose any limitations on this threshold.

[0091] The first preset data is 1. The second preset data is 0. Both the first and second preset data are binary data.

[0092] Among them, real-time potential refers to the dynamic potential value of the first read bit line connected to the target memory cell throughout the entire process of the read operation of the target memory cell.

[0093] For example, assume the target memory cell is 1, located in row i and column j. After a read operation is initiated, the read word line in row i outputs a high-level strobe signal. The two-transistor read sub-cell of the target memory cell remains off due to the stored data 1. The potential of the first read bit line 203 in column j decreases slowly due to the pull-down effect of the leakage current of the unselected memory cell, but under the charge compensation effect of the second read bit line 205, its potential is always maintained above the high-potential recognition threshold. The amplifier 204 in column j acquires the dynamic potential of the first read bit line 203 in real time and continuously compares the real-time potential with the internally preset high-potential recognition threshold. The result is determined to be that the real-time potential is greater than the high-potential recognition threshold. Based on the comparison result, the amplifier 204 immediately outputs the first preset data (digit 1) and transmits the digital data to the subsequent data output circuit of the SRAM, completing the reading of data 1. After the read operation is completed, the amplifier stops potential acquisition, and the output returns to a high-impedance state, waiting for the next read operation to be triggered.

[0094] In this embodiment, the high potential recognition threshold of the amplifier is matched with the charge compensation capability of the second reading line. The second reading line 205 stabilizes the real-time potential of the first reading line above the threshold through charge compensation, so that the amplifier can accurately determine and output the digital 1, reducing the probability of misreading the read 1 operation.

[0095] In some embodiments, such as Figure 2 As shown, the 2-transistor read subunit includes two transistors connected in series. The gates of the transistors are connected to the corresponding read word line 202 and the storage node of the 6-transistor storage subunit, respectively. The drains are connected to the corresponding first read bit line 203, and the sources are connected to ground.

[0096] Specifically, the 2-transistor read subunit includes two transistors connected in series, and the gates of the two transistors are respectively connected to the memory nodes of the corresponding read word line 202 and the 6-transistor memory subunit.

[0097] from Figure 2 As can be seen, the 2-transistor read sub-unit is composed of N-type Metal-Oxide-Semiconductor Field-Effect Transistors (NMOS). The gate of one NMOS transistor is connected to the read word line 202 (RWL[i]) corresponding to the i-th row, receiving the row selection high / low level control signal output by the read word line, providing row selection logic control for the read data transmission path. The gate of the other NMOS transistor is connected to the storage node of the 6-transistor storage sub-unit (…). Figure 2 The electrical connection marked Q receives the potential signal (VDD, high potential for storage 1, VSS, low potential for storage 0) output by the storage node, providing storage data logic control for the read data transmission path.

[0098] In some embodiments, the capacitance of the equivalent parasitic capacitance formed by the second read bit line 205 and the first read bit line 203 is positively correlated with the length of the second read bit line 205.

[0099] Among them, the equivalent parasitic capacitance refers to the metal coupling parasitic capacitance formed by the parallel and close wiring of the second read bit line 205 and the first read bit line 203 under the semiconductor chip manufacturing process. It is a passive capacitor and does not require additional capacitor design. It is the charge storage carrier for the second read bit line 205 to transfer charge to the first read bit line 203. Its capacitance value determines the charge storage capacity and compensation capacity.

[0100] Specifically, when the physical length of the second read bit line 205 increases, the capacitance of the equivalent parasitic capacitance increases accordingly. When the physical length of the second read bit line 205 decreases, the capacitance of the equivalent parasitic capacitance decreases accordingly.

[0101] In this embodiment, the positive correlation between capacitance and length allows the charge storage capacity of the second read line 205 to increase synchronously with the increase of the number of columns and rows and the increase of leakage current. Without the need to adjust the device parameters or add compensation circuits, it can adapt to the leakage current compensation requirements of memory arrays of different sizes.

[0102] This application also provides a chip, including an SRAM storage array as described in the above embodiments.

[0103] The chip provided in this application embodiment, by configuring second read lines that correspond one-to-one with the first read lines, achieves charge compensation for leakage current during read operations by using the second read lines to deliver charge to the first read lines. This eliminates the DC path formed by the keeper pull-up circuit in related technologies, fundamentally preventing static power consumption during read operations and reducing energy consumption. Furthermore, this memory array achieves the compensation function solely through the second read lines with a metal wire structure, eliminating the need for additional semiconductor devices. This significantly simplifies the SRAM layout and routing process, reduces chip area overhead, and improves the integration of the memory array.

[0104] Figure 3 A schematic diagram of the structure of the electronic device provided in this application. Figure 3 As shown, the electronic device 30 provided in this embodiment includes at least one processor 301 and a memory 302. Optionally, the electronic device 30 further includes a communication component 303. The processor 301, memory 302, and communication component 303 are connected via a bus. The processor 301 includes an SRAM storage array as described in the above embodiment.

[0105] In the specific implementation process, at least one processor 301 executes computer execution instructions stored in memory 302, causing at least one processor 301 to execute the corresponding method.

[0106] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0107] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0108] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0109] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0112] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0113] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0114] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. An SRAM memory array, characterized in that, include: An array of storage cells with at least one column, the array of storage cells comprising multiple rows of storage cells; The storage array is used to store data; Multiple read lines are connected one-to-one with the rows of the storage cell array to select the target storage cell in the storage cell array; the target storage cell is the storage cell to be read. At least one first read bit line is connected one-to-one with the column direction of the memory cell array to transmit the potential signal for the read operation; At least one amplifier is connected to each column of the memory cell array to identify and amplify the potential signal of the read bit line in order to output data; At least one second read bit line is connected to the first read bit line in a one-to-one correspondence, and is used to deliver charge to the corresponding first read bit line during a read operation.

2. The SRAM storage array according to claim 1, characterized in that, A single storage cell in the storage cell array is an 8-tube dual-port storage cell, including a 6-tube storage sub-cell and a 2-tube read sub-cell; The two-tube read subunit is connected to the six-tube storage subunit, the corresponding read word line, and the corresponding first read bit line, respectively, and is used to establish a read data transmission path between the six-tube storage subunit and the corresponding first read bit line when triggered by the strobe signal of the corresponding read word line.

3. The SRAM storage array according to claim 1, characterized in that, One end of the second read bit line is connected to the end of the corresponding first read bit line to realize charge interaction between the second read bit line and the first read bit line.

4. The SRAM storage array according to claim 3, characterized in that, The second read bit line has the same length as the corresponding connected first read bit line and is arranged in parallel.

5. The SRAM storage array according to claim 4, characterized in that, The first read bit line is connected to all the column-oriented memory cells of the corresponding memory cell array; Before the read operation is initiated, the first read bit line and the second read bit line are set to a high potential.

6. The SRAM storage array according to claim 4, characterized in that, The read word line is connected one-to-one with the row-oriented storage cells of the storage cell array, and is used to output a high-level strobe signal during a read operation to select all storage cells in the row where the target storage cell is located.

7. The SRAM storage array according to claim 2, characterized in that, The amplifier is used to determine the real-time potential of the first read bit line connected to the target memory unit when the target memory unit is performing a read operation, and compare the real-time potential of the first read bit line with a high potential identification threshold. If the real-time potential is greater than the high potential identification threshold, then the first preset data is output; If the real-time potential is less than or equal to the high potential identification threshold, then the second preset data is output.

8. The SRAM storage array according to claim 2, characterized in that, The 2-transistor read subunit includes two transistors connected in series. The gates of the transistors are connected to the corresponding read word lines and the storage nodes of the 6-transistor storage subunit, respectively. The drains are connected to the corresponding first read bit lines, and the sources are connected to ground.

9. The SRAM storage array according to claim 1, characterized in that, The capacitance of the equivalent parasitic capacitance formed by the second read bit line and the first read bit line is positively correlated with the length of the second read bit line.

10. A chip, characterized in that, Including the SRAM memory array as described in any one of claims 1 to 9.

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