Sram write assist circuit, method, and chip

CN122245372APending Publication Date: 2026-06-19SUZHOU ZHAOXIN SEMICON TECH CO LTD

Patent Information

Authority / Receiving Office: CN · China
Patent Type: Applications(China)
Current Assignee / Owner: SUZHOU ZHAOXIN SEMICON TECH CO LTD
Filing Date: 2026-03-16
Publication Date: 2026-06-19

AI Technical Summary

Technical Problem

The existing technology has problems with adding overdrive circuits to SRAM memory, which leads to complex control logic and increased chip area overhead.

Method used

By designing a time-sequential collaborative control mechanism between the pre-charge control terminal and the target control terminal, and utilizing the parasitic coupling capacitance between the bit line and the word line, precise timing coordination between the auxiliary bit line pre-charge coupling and the target cell data writing is achieved, avoiding the need for additional overdrive boost circuitry.

Benefits of technology

It simplifies the control logic, reduces circuit design and manufacturing costs, avoids data write interference and timing conflicts, and ensures the accuracy and efficiency of SRAM data writing.

✦ Generated by Eureka AI based on patent content.

Smart Images

Figure CN122245372A_ABST

Patent Text Reader

Abstract

This application provides an SRAM write auxiliary circuit, method, and chip. The circuit includes an SRAM memory array, word lines, complementary bit lines, a bit line precharge module, a target control terminal, and a write driver module. The SRAM memory array includes a target memory cell and multiple unselected memory cells. Both the target memory cell and the multiple unselected memory cells are connected to word lines. The target memory cell and each unselected memory cell are respectively connected to their corresponding complementary bit lines. The bit line precharge module includes a precharge control terminal. The target memory cell and each unselected memory cell are respectively connected to their corresponding bit line precharge modules. The complementary bit lines corresponding to the target memory cell and each unselected memory cell are connected to their corresponding bit line precharge modules. The target control terminal controls the connection and disconnection between the target memory cell and the write driver module. The complementary bit lines of the target memory cell are connected to the output terminal of the write driver module through the target control terminal. This circuit improves the success rate of memory cell writes.

Need to check novelty before this filing date? Find Prior Art