Data erasing method and electronic device

Abstract

This application discloses a data erasure method and electronic device, relating to the field of data processing technology. The method includes: the processor only allows the write protection shutdown and data erasure process to be initiated when the management board is in a secondary return-to-board type, thus avoiding accidental erasure operations in non-target scenarios such as initial production or maintenance from the source. Furthermore, the write protection function is disabled through direct hardware pin linkage, reducing the risk of accidental triggering or vulnerabilities at the software level. Therefore, the data erasure method provided in this application improves the security of data erasure processing within the target address range.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data erasure method and electronic device. Background Technology

[0002] Electrically Erasable Programmable Read-Only Memory (EEPROM) is a storage device used in the board management controller to store non-volatile data. During the secondary board production process of the board management controller, it is necessary to erase some of the data stored in the EEPROM.

[0003] In related technologies, data erasure can be performed on a portion of the data stored in an EEPROM using software commands. Specifically, a data erasure instruction can be triggered in the EEPROM via software commands. This instruction instructs the EEPROM to erase data within a target address range. Upon receiving the data erasure instruction, the EEPROM erases the data within the target address range, obtaining the erased data within that range.

[0004] However, the above method erases data within the target address range at the software level, resulting in lower security when erasing data within the target address range. Summary of the Invention

[0005] This application provides a data erasure method and electronic device to improve the security of erasing data within a target address range.

[0006] This application provides a data erasure method applied to a processor of a baseboard management controller. The baseboard management controller includes a memory, and the processor is equipped with data protection pins and a return-to-board detection pin, including:

[0007] The type of management board where the processor is located is determined by the return-to-board detection pin; the type of management board is either the first production type or the second return-to-board type.

[0008] When the management board is of the secondary return type, the write protection function of the memory is turned off through the data protection pin; the data protection pin is connected to the write protection pin of the memory, and the write protection function is used to protect the data in the memory from being erased;

[0009] The data erase request is received through the data protection pin. The data erase request is used to request the erasure of data in the target address range in the memory.

[0010] The data at the target address range is erased according to the data erasure request, resulting in the erased data at the target address range.

[0011] This application provides a data erasure method applied to the erasure verification module of a substrate management controller. The substrate management controller includes a processor and includes:

[0012] Receive the erase end command sent by the processor. The erase end command is used to indicate that the erasure process of the data in the target address range has ended.

[0013] Determine the data within the target address range after erasure; the data within the target address range after erasure is obtained by erasing the data within the target address range.

[0014] The data in the target address range after erasure is verified to determine the erasure result; the erasure result is either successful or unsuccessful.

[0015] This application also provides a data erasure device, comprising:

[0016] The first determination module is used to determine the type of the management board where the processor is located by the return board detection pin; the type of the management board is either the first production type or the second return type.

[0017] The write protection disable module is used to disable the write protection function of the memory via the data protection pin when the management board is of the secondary return type. The data protection pin is connected to the write protection pin of the memory, and the write protection function is used to protect the data in the memory from being erased.

[0018] The first receiving module is used to receive a data erase request through a data protection pin. The data erase request is used to request the erasure of data in a target address range in the memory.

[0019] The data erasure module is used to perform data erasure processing on the data in the target address range according to the data erasure request, and obtain the data in the target address range after erasure.

[0020] This application also provides a data erasure device, comprising:

[0021] The second receiving module is used to receive the erase end command sent by the processor. The erase end command is used to indicate that the erasure process of the data in the target address range has ended.

[0022] The second determining module is used to determine the data of the target address range after erasure; the data of the target address range after erasure is obtained by erasing the data of the target address range.

[0023] The verification module is used to verify the data in the target address range after erasure and determine the erasure result of the data in the target address range; the erasure result is either successful or unsuccessful.

[0024] The first sending module is used to send the erasure result to the processor.

[0025] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above-described data erasure method.

[0026] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described data erasure method.

[0027] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described data erasure method.

[0028] The data erasure method and electronic device provided in this application only allow the processor to initiate the write protection shutdown and data erasure process when the management board is a secondary return type, thus avoiding accidental erasure operations in non-target scenarios such as initial production and maintenance from the source. Furthermore, the write protection function relies on direct hardware pin linkage to disable, reducing the risk of accidental triggering or vulnerabilities at the software level. Therefore, the data erasure method provided in this application improves the security of data erasure processing within the target address range. Attached Figure Description

[0029] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram illustrating an application scenario provided in the embodiments of this application;

[0031] Figure 2 A flowchart illustrating a data erasure method provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of a storage area in a memory provided in an embodiment of this application;

[0033] Figure 4 This application provides a schematic diagram of a data erasure process for data within a target address range, as illustrated in an embodiment of the present application.

[0034] Figure 5 A flowchart illustrating the process of determining data erasure parameters provided in this application embodiment;

[0035] Figure 6 A flowchart illustrating the process of determining the type of management board provided in this application embodiment;

[0036] Figure 7 A schematic diagram of a management board provided in an embodiment of this application;

[0037] Figure 8 A schematic flowchart illustrating the process of determining the erasure result provided in an embodiment of this application;

[0038] Figure 9 This is a schematic diagram of the structure of a data erasure device provided in an embodiment of this application;

[0039] Figure 10 A schematic diagram of another data erasure device provided in an embodiment of this application;

[0040] Figure 11 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0042] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0043] First, the technical terms used in this application will be explained:

[0044] Baseboard Management Controller: In electronic devices such as servers and industrial control equipment, the baseboard management controller is the core embedded control unit of the electronic device, used to realize functions such as hardware status monitoring, configuration management and remote maintenance of electronic devices.

[0045] EEPROM: It is a supporting storage device for the baseboard management controller, used to store various non-volatile data configured during the production process of electronic devices. Exemplarily, EEPROM is used to store interface identification index (logo index), the number of redundant power supplies, fan single / double rotor mode, hardware configuration parameters, and production line calibration data, etc. It should be noted that these data are written during the first production of the electronic device to ensure that the electronic device can be properly adapted to the preset operating scenarios after leaving the factory.

[0046] With the increasing demand for flexible production in the electronic manufacturing industry, core components such as the baseboard management controller and motherboard of electronic devices can be re-produced through secondary board return. Secondary board return production refers to recycling, refurbishing or repairing the baseboard management controller or motherboard and then putting it back into production. Taking the baseboard management controller as an example, since various non-volatile data have been stored in the EEPROM during the first production process of the baseboard management controller, and some of these non-volatile data do not match the requirements of secondary board return production, so this part of the non-volatile data needs to be erased during the secondary board return process. Otherwise, it will cause problems such as production line detection equipment reporting errors and configuration information conflicts, which will further lead to abnormal product functions after secondary board return.

[0047] In some embodiments, a processor and an EEPROM are deployed on the management board of the baseboard management controller, and the processor and the EEPROM are connected through a Serial Peripheral Interface (SPI) or an Inter-Integrated Circuit (I2C) bus. And a write protection pin is deployed in the EEPROM to protect the data in the EEPROM from being erased.

[0048] In the related art, the non-volatile data stored in the EEPROM can be erased through software commands. Specifically, the processor receives a data erasure request sent by the front-end device. The data erasure request is used to request data erasure processing for the data in the target address range of the EEPROM. After receiving the data erasure request, the processor sends an erasure instruction to the EEPROM through the SPI or I2C bus. The erasure instruction is used to instruct the EEPROM to erase the data in the target address range. After receiving the erasure instruction, the EEPROM performs data erasure processing on the data in the target address range to obtain the data in the erased target address range.

[0049] However, the above method, which performs data erasure processing on the target address range at the software level, relies solely on human intervention to determine whether to erase the data within that range. If erasure is confirmed, a data erasure request is sent to the processor via the front-end device. This raises concerns that staff may mistakenly send data erasure requests to the processor during maintenance. Furthermore, software vulnerabilities could lead to accidental erasure of the target address range, resulting in low security for this method.

[0050] Furthermore, different types of EEPROMs have different data erasure parameters. When erasing data in the target address range using the above method, it is necessary to determine the corresponding data erasure code based on the type of memory, which increases the cost of erasing data in the target address range and results in lower efficiency.

[0051] Furthermore, after the memory performs data erasure on the target address range, there may be instances where the erasure process fails. Even in cases of data erasure failure on the target address range, issues such as management board configuration conflicts may still arise.

[0052] Based on this, this application provides a data erasure method in which the processor only allows the write protection shutdown and data erasure process to be initiated when the management board is in a secondary return-to-board type, thus avoiding accidental erasure operations in non-target scenarios such as initial production and maintenance from the source. Furthermore, the write protection function is disabled through direct hardware pin linkage, reducing the risk of accidental triggering or vulnerabilities at the software level. Therefore, the data erasure method provided in this application improves the security of data erasure processing within the target address range.

[0053] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] This section describes the specific application environment architecture or hardware architecture upon which the data erasure method depends. (References) Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. For example... Figure 1 As shown, the front-end device 11 and the management board 12 are configured, wherein the management board 12 is equipped with a first processor 13 and a memory 14, and the memory 14 stores non-volatile data. The first processor 13 and the memory 14 are connected via an SPI or I2C bus.

[0055] In practical applications, the front-end device 11 can communicate with the first processor 13. Specifically, when it is necessary to erase non-volatile data in the memory 14, the front-end device 11 can send a data erase request to the first processor 13. The data erase request requests data to be erased within a target address range. After receiving the data erase request, the first processor 13 sends an erase command to the memory 14 via the SPI or I2C bus. The erase command instructs the memory 14 to erase the data within the target address range. After receiving the erase command, the memory 14 erases the data within the target address range.

[0056] It should be noted that the execution subject in each embodiment of this application can be a processor, microprocessor, or a device integrating the aforementioned processor or microprocessor, such as a terminal device. The specific execution subject in each embodiment of this application is not limited and can be selected and set according to actual needs. In the following embodiments, a terminal device integrating the aforementioned processor or microprocessor is used as an example for description, which does not constitute a limitation on the actual execution subject.

[0057] It should be noted that, Figure 1 This is merely an example to illustrate one application scenario, and is not intended to limit the application scenario.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0059] Figure 2 This is a flowchart illustrating a data erasure method provided in an embodiment of this application. Figure 2 As shown, the method may include the following steps:

[0060] S201. Determine the type of management board where the processor is located by the return board detection pin; the type of management board is either the first production type or the second return board type.

[0061] A management board is a circuit board in a baseboard management controller that houses core components such as the processor and memory. The management board implements hardware control and data storage functions for the baseboard management controller. In some embodiments, the management board supports both initial production and re-production, with the management board type indicating whether it is an initial or re-production.

[0062] Specifically, the management board type is either first-time production type or second-time return type. If the management board type is first-time production type, it means the management board is being produced for the first time. If the management board type is second-time return type, it means the management board is being produced for the second time.

[0063] In some embodiments, the type of management board is used to determine whether data erasure of the memory on the management board is required. If the type of management board indicates that the management board is a first-time production type, it is determined that data erasure of the memory on the management board is not required; if the type of management board indicates that the management board is a second-time return type, it is determined that data erasure of the memory on the management board is required.

[0064] The board management controller is a core embedded control unit in electronic devices such as servers, undertaking critical functions such as hardware status monitoring, configuration management, and remote maintenance. The board management controller contains a processor and memory. The processor has data protection pins and return-to-board detection pins. The data protection pins are used to unlock the write protection function of the memory, while the return-to-board detection pins are used to identify the type of management board.

[0065] In some embodiments, when the management board is produced for the first time, the return detection pin is in a high-level state; when the management board is produced for the second time, the return detection pin is in a low-level state.

[0066] Therefore, the processor can determine the type of management board by detecting the voltage level of the return board detection pin. Specifically, when the voltage level of the return board detection pin is high, the processor determines that the management board is of the first production type; when the voltage level of the return board detection pin is low, the processor determines that the management board is of the second return type.

[0067] S202. When the management board is of the secondary return type, disable the write protection function of the memory through the data protection pin; the data protection pin is connected to the write protection pin of the memory, and the write protection function is used to protect the data in the memory from being erased.

[0068] When the management board is a secondary return type, it indicates that data erasure of the data in the memory is required. Therefore, the processor can disable the write protection function of the memory via the data protection pin to enable subsequent data erasure of the data in the memory. The memory is used to store non-volatile data, and the memory can be, for example, an EEPROM.

[0069] In some embodiments, the processor may disable the write protection function of the memory via the data protection pin as follows: receiving a first erase instruction via the data protection pin, the first erase instruction indicating permission to erase data in the memory; sending an unlock signal to the memory via the data protection pin and the write protection pin; the unlock signal indicating that the memory has disabled the write protection function; and receiving a response signal from the memory via the data protection pin and the write protection pin, the response signal indicating that the memory has disabled the write protection function.

[0070] The first erase command is a hardware authorization command sent by the front-end device to the data protection pin. It should be noted that the first erase command is not a software-level command, but rather implemented through hardware signals.

[0071] For example, assuming the data protection pin is in a low-level state, the front-end device can control the data protection pin to be in a high-level state, and control the high-level state of the data protection pin to last for a duration greater than or equal to a preset duration. When the processor detects that the data protection pin is in a high-level state and the high-level state of the data protection pin lasts for a duration greater than or equal to the preset duration, it determines that it has received a first erase command from the front-end device.

[0072] The write-protect pin is a hardware pin in the memory used to control the write protection function, and the write-protect pin is connected to the data protection pin via an SPI or I2C bus.

[0073] The unlock signal is a voltage level signal sent by the processor through the data protection pin to the write protection pin to indicate that write protection is disabled. The response signal is a voltage level signal sent by the memory through the write protection pin to the data protection pin to indicate that write protection has been successfully disabled.

[0074] In some embodiments, after receiving a first erase command, the processor can send a low-level signal to the write-protect pin via the data protection pin. Upon receiving the low-level signal via the write-protect pin, the memory disables write protection. Then, the memory sends a low-level signal to the data protection pin via the write-protect pin. Upon receiving the low-level signal via the data protection pin, the processor determines that the memory has successfully disabled write protection.

[0075] S203. Receive a data erase request through the data protection pin. The data erase request is used to request the erasure of data in the target address range in the memory.

[0076] A data erase request is a control command sent by the front-end device to the data protection pin, and it is the direct trigger signal to initiate the data erase process. The target address range indicates the memory address of the data to be erased.

[0077] When a front-end device needs to erase at least one piece of data in the memory, it can determine the storage address of each piece of data in the memory, determine the target address range, and send a data erase request to the processor through the data protection pin.

[0078] S204. Perform data erasure processing on the data in the target address range according to the data erasure request, and obtain the data in the target address range after erasure.

[0079] In some embodiments, after receiving a data erase request, the processor may verify the target address range indicated by the data erase request to determine whether the target address range is within the address range in memory where data erasure is permitted. If the target address range is within the address range in memory where data erasure is permitted, an erase instruction is sent to the memory according to the target address range. Upon receiving the erase instruction, the memory performs data erasure on the data in the target address range.

[0080] exist Figure 2 In the illustrated embodiment, the processor only allows the write protection shutdown and data erasure process to be initiated when the management board is a secondary return type, thus avoiding accidental erasure operations in non-target scenarios such as initial production and maintenance from the source. Furthermore, the write protection function relies on direct hardware pin linkage to disable, reducing the risk of accidental triggering or vulnerabilities at the software level. Therefore, the data erasure method provided in this application improves the security of data erasure processing within the target address range.

[0081] exist Figure 2 Based on the illustrated embodiment, the memory includes a configuration data storage area and a firmware data storage area; wherein, the configuration data storage area is used to store data that is allowed to be erased, and the firmware data storage area is used to store data that is not allowed to be erased. Specifically, it can be combined with... Figure 3 To understand, Figure 3 This is a schematic diagram of a storage region in a memory provided in an embodiment of this application. Figure 3 As shown, the memory includes a configuration data storage area and a firmware data storage area.

[0082] The configuration data storage area is an independent physical address segment partitioned by the memory through hardware circuitry, used to store data adapted to a specific production batch. For example, the configuration data storage area can store data that allows for data erasure, such as the number of redundant power supplies, fan single / dual rotor modes, and hardware configuration parameters.

[0083] The firmware data storage area is a separate address segment in the memory, physically isolated from the configuration data storage area. It is used to store critical data that ensures the operation of the device's core functions. For example, the firmware data storage area can store hardware drivers, core operating parameters, and other data that cannot be erased.

[0084] It should be noted that the configuration data storage area and the firmware data storage area are isolated at the hardware level. This physically prevents the possibility of accidental erasure of data in the firmware data storage area, further improving the security of data erasure processing within the target address range.

[0085] The following is combined Figure 4 This application further explains the method of performing data erasure processing on data within a target address range according to a data erasure request to obtain the erased data within the target address range.

[0086] Figure 4 This is a schematic diagram illustrating a data erasure process for data within a target address range, provided as an embodiment of this application. Figure 4 As shown, the process may include the following steps:

[0087] S401. Determine the storage area where the target address range is located based on the configuration data storage area and the firmware data storage area.

[0088] In some embodiments, the processor determines the storage area where the target address range is located in the following way: the target address range is sent to the address verification module through a hardware connection circuit, the address verification module is used to verify the storage area where the target address range is located; the address verification module includes the address range of the configuration data storage area and the address range of the firmware data storage area; the processor receives the storage area where the target address range is located sent by the address verification module through a hardware connection circuit.

[0089] The address verification module is a hardware module in the baseboard management controller used to verify the memory region to which the target address range belongs.

[0090] After receiving a data erase request, the processor can send the target address range to the address verification module via hardware connection circuitry. Upon receiving the target address range, the address verification module compares it with the address ranges of both the configuration data storage area and the firmware data storage area to determine whether the target address range falls within the address range of the configuration data storage area or the firmware data storage area.

[0091] If the target address is within the address range of the configuration data storage area, the address verification module determines that the storage area containing the target address range is the configuration data storage area; if the target address is within the address range of the firmware data storage area, the address verification module determines that the storage area containing the target address range is the firmware data storage area.

[0092] After determining the storage area where the target address range is located, the address verification module sends the storage area where the target address range is located to the processor through the hardware connection circuit.

[0093] S402. If the target address range is located in a memory region that is a configuration data storage region, determine the data erasure parameters adapted to the memory.

[0094] If the memory region containing the target address range is a configuration data storage region, then the data within the target address range is data in the memory that is allowed to be erased. Therefore, data erasure can be performed on the data within the target address range.

[0095] Data erase parameters are hardware adaptation and control parameters used by the memory to perform data erase operations. For example, data erase parameters may include parameters such as erase pulse width and total clock frequency.

[0096] Specifically, it can be combined with Figure 5 As shown, Figure 5 This is a schematic flowchart illustrating the process of determining data erasure parameters, provided as an embodiment of this application. Figure 5 As shown, the process may include the following steps:

[0097] S501, Obtain memory information from the memory.

[0098] In some embodiments, the memory includes memory information. This memory information may include, for example, the memory's product identifier and model information. The processor may send an information retrieval request to the memory, which requests the retrieval of the memory's information. Upon receiving the information retrieval request, the memory sends the memory information to the processor.

[0099] S502. Determine the data erasure parameters based on the mapping relationship between memory information and data erasure parameters, and the memory information.

[0100] For example, assume that the mapping relationship between stored information and data erasure parameters is as shown in Table 1.

[0101] Table 1

[0102]

[0103] Assuming the product identifier of the memory is XXX1 and the model information is NNN, the data erasure parameters of the memory are determined to be: an erasure pulse width of 10ms and a total clock frequency of 100KHz.

[0104] In some embodiments, if the memory does not have storage information in the mapping relationship between memory information and data erase parameters, the processor determines that the data erase parameters of the memory are preset data erase parameters.

[0105] S403. Based on the data erase parameters and the target address range, a second erase instruction is sent to the memory through the data protection pin and the write protection pin. The second erase instruction is used to instruct the memory to perform data erase processing on the data in the target address range according to the data erase parameters.

[0106] For example, assuming the target address range is 0x0000-0xFFFF, and the data erasure parameters include an erase pulse width of 10ms and a total clock frequency of 100kHz, then the second erase instruction is used to instruct the memory to perform data erasure processing on the data in the address range 0x0000-0xFFFF with an erase pulse width of 10ms and a total clock frequency of 100kHz.

[0107] S404: Receive erase response sent by the memory via the data protection pin and write protection pin. The erase response is used to indicate that the memory has completed the data erase process for the target address range.

[0108] An erase response is a hardware level signal sent by the memory to the processor to indicate that the data erasure process has been completed. For example, an erase response can be a low-level signal.

[0109] After receiving the second erase instruction, the memory performs data erasure on the data within the target address range according to the data erasure parameters indicated by the second erase instruction. After completing the data erasure process, the memory sends a low-level signal to the data protection pin via the write-protect pin. Upon receiving the low-level signal via the data protection pin, the processor confirms that the memory has completed the data erasure process.

[0110] In some embodiments, the processor is equipped with a hardware status register to store the status of the data erasure process. The data erasure process status includes: not executed, executed, successful erasure, and failed erasure. This allows the baseboard management controller to record each stage of the data erasure process, enabling timely feedback to the front-end devices regarding their queries about the data erasure status. Furthermore, if the data erasure status is "failed," operators can promptly determine the failure and quickly pinpoint the cause.

[0111] exist Figure 4 In the illustrated embodiment, the processor determines the storage region to which the target address range belongs through the address verification module, reducing the possibility of accidental erasure of data in the firmware data storage region from a hardware perspective and improving data security in the firmware data storage region. Furthermore, the compatibility of the data erasure parameters is determined, matching the hardware characteristics of different memory models, improving the compatibility and success rate of data erasure operations, and reducing the probability of erasure failure due to mismatched data erasure parameters.

[0112] Based on the above embodiments, the following, in conjunction with Figure 6 The method for determining the type of management board in this application will be further explained.

[0113] Figure 6 This is a flowchart illustrating a method for determining the type of management board, as provided in an embodiment of this application. Figure 6 As shown, the process may include the following steps:

[0114] S601. The conductive circuit status of the return board identification hole is determined by the return board detection pin. The conductive circuit status is either in a conducting state or a non-conducting state. The conductive circuit status is used to indicate whether a screw has been installed at the return board identification hole.

[0115] The management board includes a return board identification hole, which is used to install screws and is connected to the return board detection pin.

[0116] The return plate identification hole is a pre-set screw mounting hole on the management board. It should be noted that the inner wall or periphery of the return plate identification hole has a conductive plating layer. During the initial production of the management board, no screws are installed in the return plate identification hole, and at this time, the conductive plating layer of the return plate identification hole does not form a complete current path. After the initial production of the management board is completed, screws will be installed in the return plate identification hole, at which point the conductive plating layer of the return plate identification hole will form a complete current path. It should be noted that even if the screws on the return plate identification hole are removed, a complete current path still exists in the conductive plating layer of the return plate identification hole.

[0117] Specifically, it can be combined with Figure 7 To understand, Figure 7 This is a schematic diagram of a management board provided in an embodiment of this application. Figure 7 As shown, the management board is equipped with a processor, memory, and a return-to-board identification hole. The processor's return-to-board detection pin is connected to the return-to-board identification hole, and the processor's data protection pin is connected to the memory's write-protection pin.

[0118] The conductive circuit status indicates the physical state of whether the conductive plating at the return plate identification hole has formed a complete current path. Specifically, a conductive circuit in a "conductive" state indicates that the conductive plating at the return plate identification hole has formed a complete current path, meaning that a screw has been installed at the return plate identification hole. Conversely, a non-conductive circuit indicates that the conductive plating at the return plate identification hole has not formed a complete current path, meaning that a screw has not been installed at the return plate identification hole.

[0119] In some embodiments, the conductive loop state can control the voltage level of the return-to-board detection pin. Specifically, when the conductive loop state is on, the voltage level of the return-to-board detection pin is high; when the conductive loop state is off, the voltage level of the return-to-board detection pin is low.

[0120] Therefore, the processor can determine the state of the conductive loop by detecting the voltage level of the return-to-board detection pin. Specifically, if the processor detects a high voltage level on the return-to-board detection pin, it determines that the conductive loop is in a conducting state. If the processor detects a low voltage level on the return-to-board detection pin, it determines that the conductive loop is in a non-conducting state.

[0121] S602. Determine the type of management board based on the state of the conductive circuit.

[0122] In some embodiments, the processor determines the type of management board based on the conductive circuit state as follows: when the conductive circuit state is non-conductive, the management board type is determined to be the first production type; when the conductive circuit state is conductive, the management board type is determined to be the second return type.

[0123] If the conductive circuit is in a non-conductive state, it indicates that the conductive plating at the return board identification hole has not formed a complete current path, meaning that no screws have been installed at the return board identification hole. Therefore, the processor determines that the management board is a first-time production type.

[0124] If the conductive circuit is in a conductive state, it indicates that the conductive plating at the return board identification hole has formed a complete current path, meaning that a screw has been installed at the return board identification hole. Therefore, the processor determines that the management board type is a secondary return board type.

[0125] exist Figure 6In the illustrated embodiment, the return board identification hole, formed by the mounting screws, creates a conductive circuit and is directly associated with the return board detection pin. This allows the conductive circuit status to serve as a direct indicator of the management board type, automatically distinguishing between the initial production state and the secondary return board state without manual intervention. This reduces the cost of manual judgment on the production line, minimizes operational errors caused by human misjudgment, and further enhances the security of data erasure operations on the target address range.

[0126] The above embodiments describe the process of erasing data within a target address range using the data erasure method provided in this application. In some embodiments, after obtaining the erased data within the target address range, the processor can further verify the erased data to determine the erasure result. Specifically, this can be combined with... Figure 8 To understand.

[0127] Figure 8 This is a schematic flowchart illustrating a method for determining the erasure result, as provided in an embodiment of this application. Figure 8 As shown, the process may include the following steps:

[0128] S801. Send an erasure end command to the erasure verification module. The erasure end command is used to indicate that the data erasure process of the data in the target address range has been completed. The erasure verification module is used to determine the erasure result of the data erasure process of the data in the target address range. The erasure result is either erasure successful or erasure failed.

[0129] The erase verification module is a dedicated hardware module in the baseboard management controller used to verify the results of data erase processing. In some embodiments, the erase verification module can determine whether the data in the target address range has been completely erased based on preset verification logic.

[0130] The erase end instruction is a hardware signal sent by the processor to the erase verification module after the data erase process is completed.

[0131] In some embodiments, the erase verification module can receive an erase end instruction sent by the processor, which indicates that the erase process of the data in the target address range has ended; determine the data in the target address range after erasure; the data in the target address range after erasure is obtained after erasing the data in the target address range; verify the data in the target address range after erasure to determine the erase result of the erase process of the data in the target address range; the erase result is either erase successful or erase failed.

[0132] After receiving the erase end command from the processor, the erase verification module can send a data retrieval request to the memory. This request retrieves the data within the erased target address range from the memory. Upon receiving the data retrieval request, the memory sends the erased target address range data to the erase verification module.

[0133] Then, the erase verification module verifies the data in the erased target address range to determine the erase result. Specifically, the erase verification module determines the erase result as follows: It verifies the data in the erased target address range according to the Cyclic Redundancy Check (CRC) algorithm to determine the verification result, which is either successful or unsuccessful. If the verification result is successful, it compares the data in the erased target address range with preset data to determine the comparison result, which is either successful or unsuccessful. If the comparison result is successful, the erase result is determined to be successful. If the verification result is unsuccessful, or the comparison result is unsuccessful, the erase result is determined to be unsuccessful.

[0134] Cyclic Redundancy Check (CRC) is a hardware-level data verification algorithm used to check the accuracy of data erasure within a target address range. The verification result is the conclusion drawn from the CRC check of the erased data within the target address range.

[0135] In some embodiments, the verification result is either verification success or verification failure. Verification success indicates that the verification value calculated by the Cyclic Redundancy Check (CRC) algorithm is the same as the preset verification value, meaning that the data in the target address range did not encounter errors during transmission or erasure, and the data status meets the verification standard. Verification failure indicates that the verification value calculated by the CRC algorithm is different from the preset verification value, meaning that the data in the target address range contains errors, has experienced transmission abnormalities, or has not been effectively erased.

[0136] The preset data is reference data for blank values ​​that is pre-stored in the erase verification module. In some embodiments, for each piece of data in the data of the erased target address range, if the data is the same as the preset data, it means that the data is a blank value, that is, the data at that storage address has been successfully erased. If the data is different from the preset data, it means that the data is not a blank value, that is, the data at that storage address has not been successfully erased.

[0137] The comparison result indicates whether the data in the erased target address range is the same as the preset data. A successful comparison means that all data in the erased target address range is the same as the preset data, indicating that the data in the target address range has been completely erased. A failed comparison means that at least one piece of data in the erased target address range differs from the preset data, indicating that the data in the target address range has not been completely erased.

[0138] In some embodiments, the erasure verification module can perform polynomial operations on the data in the erased target address range using a cyclic redundancy check algorithm to generate a fixed-length verification value. Then, this verification value is compared with a preset verification value. If the verification value is the same as the preset verification value, the erasure verification module determines the verification result as successful; if the verification value is different from the preset verification value, the erasure verification module determines the verification result as unsuccessful.

[0139] In some embodiments, if the verification result is a verification failure, the erase verification module can determine that the erase result is an erase failure.

[0140] In some embodiments, if the verification result is successful, the erasure verification can compare each piece of data in the erased target address range with preset data. If all data in the erased target address range is the same as the preset data, the comparison result is determined to be successful. If at least one piece of data in the erased target address range is different from the preset data, the comparison result is determined to be unsuccessful.

[0141] In some embodiments, if the comparison result is successful, the erase verification module determines that the erase result is successful. If the comparison result is unsuccessful, the erase verification module determines that the erase result is unsuccessful.

[0142] In some embodiments, the erase verification module is connected to the front-end device via a general purpose input / output (GPIO) pin. After determining the erase result, the erase verification module can send the erase result to the front-end device via the GPIO pin. For example, if the erase result is successful, the erase verification module can send a high-level signal to the front-end device via the GPIO pin; if the erase result is unsuccessful, the erase verification module can send a low-level signal to the front-end device via the GPIO pin.

[0143] In some embodiments, after receiving the erasure result sent by the erasure verification module, if the erasure result is an erasure failure, the front-end device can send a prompt message to the client. The prompt message is used to indicate that the data erasure process for the target address range was unsuccessful.

[0144] S802, Receive the erasure result sent by the erasure verification module.

[0145] In some embodiments, after determining the erasure result, the erasure verification module may send the erasure result to the processor.

[0146] In some embodiments, if the erasure result is an erasure failure, the processor may repeatedly initiate data erasure processing on the data in the target address range after receiving the erasure result, until the erasure result is an erasure success, and / or the number of data erasure processes is greater than or equal to a preset threshold.

[0147] exist Figure 8 In the illustrated embodiment, the erasure verification module is independent of the processor and memory. It directly reads and verifies the data within the target address range through hardware circuitry, unaffected by software interference, thus improving the objectivity and reliability of the erasure result determination. Furthermore, through a dual verification mechanism of cyclic redundancy algorithm and preset data comparison, it not only detects the completeness and correctness of the data erasure process within the target address range but also confirms whether the data within the target address range has been completely erased to blank values ​​through preset data comparison. This reduces the possibility of undetected data residue and improves the quality of the management board in the secondary production run. Simultaneously, after determining the erasure result, the erasure verification module feeds it back to the front-end equipment, allowing the production line to quickly determine the subsequent process flow without manual data analysis, thereby improving production efficiency.

[0148] Figure 9 This is a schematic diagram of a data erasure device provided in an embodiment of this application. Figure 9 As shown, this application embodiment provides a data erasure device 90, which includes a first determining module 91, a write protection disabling module 92, a first receiving module 93, and a data erasure module 94, wherein:

[0149] The first determination module 91 is used to determine the type of the management board where the processor is located by the return board detection pin; the type of the management board is either the first production type or the second return board type.

[0150] Write protection shutdown module 92 is used to disable the write protection function of the memory via the data protection pin when the management board is of the secondary return type; the data protection pin is connected to the write protection pin of the memory, and the write protection function is used to protect the data in the memory from being erased;

[0151] The first receiving module 93 is used to receive a data erase request through a data protection pin. The data erase request is used to request the erasure of data in a target address range in the memory.

[0152] The data erasure module 94 is used to perform data erasure processing on the data in the target address range according to the data erasure request, and obtain the data in the target address range after erasure.

[0153] In one possible implementation, the write protection shutdown module 92 is specifically used for:

[0154] The first erase command is received through the data protection pin. The first erase command is used to indicate that the data in the memory can be erased.

[0155] An unlock signal is sent to the memory via the data protection pin and the write protection pin; the unlock signal is used to instruct the memory to disable write protection.

[0156] The system receives response signals from the memory via the data protection pin and write protection pin. These response signals indicate that the memory has disabled write protection.

[0157] In one possible implementation, the memory includes a configuration data storage area and a firmware data storage area; wherein the configuration data storage area is used to store data that is allowed to be erased, and the firmware data storage area is used to store data that is not allowed to be erased; the data erasure module 94 is specifically used for:

[0158] Based on the configured data storage area and the firmware data storage area, determine the storage area where the target address range is located;

[0159] If the target address range is located in a memory region that is a configuration data storage region, determine the data erasure parameters adapted to the memory.

[0160] Based on the data erase parameters and the target address range, a second erase instruction is sent to the memory through the data protection pin and the write protection pin. The second erase instruction is used to instruct the memory to perform data erase processing on the data in the target address range according to the data erase parameters.

[0161] The erase response sent by the memory is received through the data protection pin and write protection pin. The erase response is used to indicate that the memory has completed the data erase process.

[0162] In one possible implementation, the data erasure module 94 is specifically used for:

[0163] The target address range is sent to the address verification module via a hardware connection circuit. The address verification module is used to verify the storage area where the target address range is located. The address verification module includes the address range of the configuration data storage area and the address range of the firmware data storage area.

[0164] The hardware connection circuit receives the storage area containing the target address range sent by the address verification module.

[0165] In one possible implementation, the management board includes a return board identification hole for mounting screws, and the return board identification hole is connected to a return board detection pin; the first determining module 91 is specifically used for:

[0166] The conductive circuit status of the return board identification hole is determined by the return board detection pin. The conductive circuit status is either in a conductive state or a non-conductive state. The conductive circuit status is used to indicate whether a screw has been installed at the return board identification hole.

[0167] The type of management board is determined based on the state of the conductive circuit.

[0168] In one possible implementation, the first determining module 91 is specifically used for:

[0169] If the conductive circuit is in a non-conductive state, the type of the management board is determined to be the first production type;

[0170] When the conductive circuit is in the on state, the type of the management board is determined to be a secondary return board type.

[0171] In one possible implementation, the data erasure device 90 further includes a second transmitting module, which is specifically used for:

[0172] An erasure completion command is sent to the erasure verification module. The erasure completion command indicates that the data erasure process for the target address range has ended. The erasure verification module is used to determine the erasure result of the data erasure process for the target address range. The erasure result is either erasure successful or erasure failed.

[0173] Receive the erasure result sent by the erasure verification module.

[0174] For a description of the features in the embodiment corresponding to the data erasure device 90, please refer to the relevant description of the embodiment corresponding to the data erasure method with the processor as the execution subject, which will not be repeated here.

[0175] Figure 10 This is a schematic diagram of another data erasure device provided in an embodiment of this application. Figure 10 As shown in the figure, this application embodiment also provides a data erasure device 100, which includes a second receiving module 101, a second determining module 102, a verification module 103, and a first sending module 104, wherein:

[0176] The second receiving module 101 is used to receive the erase end command sent by the processor. The erase end command is used to indicate that the erasure process of the data in the target address range has ended.

[0177] The second determining module 102 is used to determine the data of the target address range after erasure; the data of the target address range after erasure is obtained by erasing the data of the target address range.

[0178] Verification module 103 is used to verify the data in the target address range after erasure and determine the erasure result of the data in the target address range; the erasure result is either successful or unsuccessful.

[0179] The first sending module 104 is used to send the erasure result to the processor.

[0180] In one possible implementation, the verification module 103 is specifically used for:

[0181] The data in the target address range after erasure is verified according to the cyclic redundancy check algorithm to determine the verification result, which is either verification success or verification failure.

[0182] If the verification result is successful, the data of the erased target address range is compared with the preset data to determine the comparison result, which is either a successful comparison or a failed comparison.

[0183] If the comparison result is successful, the erasure result is determined to be successful.

[0184] If the verification result is a verification failure, or the comparison result is a comparison failure, then the erasure result is determined to be an erasure failure.

[0185] For a description of the features in the embodiment corresponding to the data erasure device 100, please refer to the relevant description of the embodiment corresponding to the data erasure method with the erasure verification module as the execution subject, which will not be repeated here.

[0186] Figure 11 A schematic diagram of the structure of the electronic device provided in this application. Figure 11 As shown, the electronic device 110 provided in this embodiment includes at least one second processor 1101 and a memory 1102. Optionally, the electronic device 110 further includes a communication component 1103. The second processor 1101, the memory 1102, and the communication component 1103 are connected via a bus.

[0187] In a specific implementation, at least one second processor 1101 executes computer execution instructions stored in memory 1102, causing at least one second processor 1101 to execute the above-described data erasure method embodiment.

[0188] The specific implementation process of the data erasure method executed by the second processor 1101 can be found in the above method embodiment. Its implementation principle and technical effect are similar, and will not be repeated here.

[0189] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0190] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0191] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0192] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described data erasure method embodiments when running.

[0193] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0194] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described data erasure method embodiments.

[0195] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described data erasure method embodiments.

[0196] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0197] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0198] The data erasure method and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data erasure method, characterized in that, A processor for a substrate management controller, the substrate management controller including a memory, the processor having data protection pins and a return-to-board detection pin, the method comprising: The type of the management board where the processor is located is determined by the return board detection pin; the type of the management board is either the first production type or the second return type. When the management board is of the secondary return board type, the write protection function of the memory is disabled through the data protection pin; the data protection pin is connected to the write protection pin of the memory, and the write protection function is used to protect the data in the memory from being erased; The data erase request is received through the data protection pin, and the data erase request is used to request the erasure of data in the target address range in the memory; The data in the target address range is erased according to the data erasure request to obtain the erased data in the target address range.

2. The method according to claim 1, characterized in that, The step of disabling the write protection function of the memory via the data protection pin includes: The first erase command is received through the data protection pin, and the first erase command is used to indicate that the data in the memory can be erased. An unlock signal is sent to the memory via the data protection pin and the write protection pin; the unlock signal is used to instruct the memory to disable the write protection function. The system receives a response signal from the memory via the data protection pin and the write protection pin. The response signal indicates that the memory has disabled the write protection function.

3. The method according to claim 1 or 2, characterized in that, The memory includes a configuration data storage area and a firmware data storage area; wherein, the configuration data storage area is used to store data that allows the data erasure process, and the firmware data storage area is used to store data that does not allow the data erasure process. The step of performing data erasure processing on the data in the target address range according to the data erasure request to obtain the erased data in the target address range includes: Based on the configuration data storage area and the firmware data storage area, determine the storage area where the target address range is located; If the storage area containing the target address range is the configured data storage area, determine the data erasure parameters adapted to the memory; According to the data erasure parameters and the target address range, a second erase instruction is sent to the memory through the data protection pin and the write protection pin. The second erase instruction is used to instruct the memory to perform the data erasure process on the data in the target address range according to the data erasure parameters. The erase response sent by the memory is received through the data protection pin and the write protection pin. The erase response is used to indicate that the memory has completed the data erase process for the data in the target address range.

4. The method according to claim 3, characterized in that, The step of determining the storage area containing the target address range based on the configured data storage area and the firmware data storage area includes: The target address range is sent to the address verification module via a hardware connection circuit. The address verification module is used to verify the storage area where the target address range is located. The address verification module includes the address range of the configuration data storage area and the address range of the firmware data storage area. The hardware connection circuit receives the storage area containing the target address range sent by the address verification module.

5. The method according to claim 1 or 2, characterized in that, The management board includes a return board identification hole for mounting screws, and the return board identification hole is connected to the return board detection pin. The step of determining the type of management board where the processor resides via the return-to-board detection pin includes: The conductive circuit state of the return board identification hole is determined by the return board detection pin, and the conductive circuit state is either in a conductive state or a non-conductive state; the conductive circuit state is used to indicate whether the screw has been installed at the return board identification hole. The type of the management board is determined based on the state of the conductive circuit.

6. The method according to claim 5, characterized in that, Determining the type of the management board based on the state of the conductive circuit includes: If the conductive circuit is in the non-conductive state, the type of the management board is determined to be the first production type; When the conductive circuit is in the on state, the type of the management board is determined to be the secondary return board type.

7. The method according to claim 1 or 2, characterized in that, After obtaining the erased target address range data, the method further includes: An erasure completion command is sent to the erasure verification module, the erasure completion command indicating that the data erasure process for the target address range has ended; the erasure verification module is used to determine the erasure result of the data erasure process for the target address range; the erasure result is either erasure successful or erasure failed; Receive the erasure result sent by the erasure verification module.

8. A data erasure method, characterized in that, An erasure verification module for a substrate management controller, wherein the substrate management controller includes a processor, the method comprising: Receive an erase end command sent by the processor, the erase end command being used to indicate that the erasure process of data in the target address range has ended; The data of the target address range after erasure is determined; the data of the target address range after erasure is obtained by erasing the data of the target address range. The data in the target address range after erasure is verified to determine the erasure result of the data erasure process in the target address range; the erasure result is either successful erasure or failed erasure. The erasure result is sent to the processor.

9. The method according to claim 8, characterized in that, The step of verifying the data in the erased target address range to determine the erasure result of the data erasure process in the target address range includes: The data in the erased target address range is verified according to the cyclic redundancy check algorithm to determine the verification result, which is either verification success or verification failure. If the verification result is successful, the data of the erased target address range is compared with the preset data to determine the comparison result, which is either a successful comparison or a failed comparison. If the comparison result indicates that the comparison was successful, the erasure result is determined to be successful. If the verification result is a verification failure, or the comparison result is a comparison failure, then the erasure result is determined to be an erasure failure.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data erasure method as described in any one of claims 1 to 9 when executing the computer program.

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