Trim adjustment test method, device, apparatus and storage medium

Abstract

This invention discloses a TRIM tuning test method, apparatus, device, and computer-readable storage medium for MRAM chips. The TRIM tuning test method for MRAM chips includes configuring multiple different alternative tuning parameters sequentially on the MRAM chip under set high and low temperature conditions, and performing read / write function tests to obtain a first tuning parameter set and a second tuning parameter set. The intersection of the tuning parameters between the first and second tuning parameter sets is then obtained. If the intersection is empty, the MRAM chip is determined to be a failed chip; if it is not empty, the average value of the tuning parameters in the intersection is taken as the fixed tuning value of the MRAM chip. The fixed tuning value determined in this application enables the MRAM chip to be read and written normally under extreme temperature environments, ensuring the accuracy and reliability of the tuning parameters and the good working performance of the MRAM chip.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing technology, and in particular to a TRIM tuning test method, apparatus, device, and computer-readable storage medium for MRAM chips. Background Technology

[0002] MRAM (Magnetoresistive Random Access Memory) is a non-volatile magnetic random access memory that uses the magnetoresistive effect to store data. Due to the influence of manufacturing processes, the parameters of different MRAM chips may vary slightly, resulting in performance deviations for each chip. During CP and FT testing, key parameters such as VREF and RINT of MRAM chips need to be adjusted using TRIM to ensure that the parameters of each MRAM chip reach their optimal values. Ensuring the accuracy and reliability of the TRIM adjustment results is crucial to guaranteeing the good working performance of MRAM chips. Summary of the Invention

[0003] The purpose of this invention is to provide a method, apparatus, device, and computer-readable storage medium for TRIM tuning testing of MRAM chips, which can improve the accuracy and reliability of TRIM tuning results of MRAM chips.

[0004] To address the aforementioned technical problems, this invention provides a TRIM tuning test method for MRAM chips, comprising:

[0005] Under set high temperature conditions, multiple different alternative adjustment parameters are sequentially configured for the MRAM chip, and the read and write function test is performed on the MRAM chip so that the alternative adjustment parameters of the read and write function test are used as the first adjustment parameters to obtain the first adjustment parameter set.

[0006] Under set low temperature conditions, multiple different alternative tuning parameters are sequentially configured for the MRAM chip, and read / write function tests are performed on the MRAM chip so that the alternative tuning parameters that pass the read / write function test are used as the second tuning parameters to obtain the second tuning parameter set.

[0007] Perform an intersection operation on the first set of adjustment parameters and the second set of adjustment parameters to obtain the intersection of adjustment parameters;

[0008] Determine whether the intersection of the adjustment parameters is an empty set. If it is, then the MRAM chip is determined to be a failed chip. If not, then the average value of each adjustment parameter in the intersection of the adjustment parameters is taken as the fixed adjustment value of the MRAM chip.

[0009] In one optional embodiment of this application, under a set high-temperature condition, multiple different alternative tuning parameters are sequentially configured for the MRAM chip, and read / write function tests are performed on the MRAM chip, so that the MRAM chip uses the alternative tuning parameters obtained from the read / write function test as the first tuning parameters to obtain a first tuning parameter set, including:

[0010] Under the set high temperature condition, the first alternative adjustment parameter within the set adjustment parameter range is used as the current adjustment parameter to configure the MRAM chip;

[0011] Perform read and write operations on the MRAM chip;

[0012] Determine whether the read data and write data corresponding to the MRAM chip are consistent;

[0013] If so, the current adjustment parameter is used as the first adjustment parameter of the MRAM chip;

[0014] If not, then the current adjustment parameter is the parameter for which the MRAM chip failed the read / write test;

[0015] Determine whether there are any unconfigured alternative adjustment parameters within the set adjustment parameter range. If so, select a new current adjustment parameter from among the unconfigured alternative adjustment parameters and repeat the operation of configuring the current adjustment parameter for the MRAM chip.

[0016] If not, then the first adjustment parameter is used as the set element to obtain the first adjustment parameter set.

[0017] In an optional embodiment of this application, after obtaining the first set of adjustment parameters, the method further includes:

[0018] Determine whether the first set of adjustment parameters is an empty set;

[0019] If so, then the MRAM chip is a faulty chip;

[0020] If not, then when there are at least two first adjustment parameters in the first adjustment parameter set, determine whether each first adjustment parameter is sequentially continuous.

[0021] If not, then the MRAM chip is determined to be a faulty chip;

[0022] After obtaining the second set of tuning parameters, the following is also included:

[0023] Determine whether the second set of adjustment parameters is an empty set;

[0024] If so, then the MRAM chip is a faulty chip;

[0025] If not, then when there are at least two second adjustment parameters in the second adjustment parameters, determine whether each second adjustment parameter is consecutive.

[0026] If not, then the MRAM chip is determined to be a faulty chip.

[0027] In an optional embodiment of this application, when the intersection of the adjustment parameters is not an empty set, the method further includes:

[0028] The MRAM chips are classified into different levels based on the number of adjustment parameters in the intersection of the adjustment parameters; wherein, the level of the MRAM chip is positively correlated with the number of available adjustment parameters in the intersection of the adjustment parameters.

[0029] In an optional embodiment of this application, the TRIM tuning test method for the MRAM chip further includes, before sequentially configuring multiple different alternative tuning parameters for the MRAM chip:

[0030] Under normal temperature conditions, multiple different theoretical adjustment parameters were sequentially configured for the MRAM chip, and the read and write functions of the MRAM chip were tested.

[0031] The alternative adjustment parameters are determined based on the theoretical adjustment parameters obtained from the read / write function test of the MRAM chip.

[0032] In one optional embodiment of this application, the alternative adjustment parameter is a parameter of any type either VREF parameter or RINT parameter;

[0033] The set high temperature is no lower than 80°C, and the set low temperature is no higher than -35°C.

[0034] A TRIM tuning test apparatus for an MRAM chip, comprising:

[0035] The first test module is used to configure multiple different alternative adjustment parameters for the MRAM chip under a set high temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative adjustment parameters of the read and write function test as the first adjustment parameter to obtain the first adjustment parameter set.

[0036] The second test module is used to configure multiple different alternative tuning parameters for the MRAM chip in sequence under a set low temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative tuning parameters of the read and write function test as the second tuning parameters to obtain the second tuning parameter set.

[0037] The intersection operation module is used to perform an intersection operation on the first set of adjustment parameters and the second set of adjustment parameters to obtain the intersection of adjustment parameters.

[0038] The judgment and calculation module is used to determine whether the intersection of the adjustment parameters is an empty set. If it is, the MRAM chip is determined to be a failed chip; if not, the average value of each adjustment parameter in the intersection of the adjustment parameters is taken as the fixed adjustment value of the MRAM chip.

[0039] In an optional embodiment of this application, the TRIM trimming test of the MRAM chip further includes a grading module, used to grade the MRAM chip according to the number of trimming parameters in the intersection of the trimming parameters when the intersection of the trimming parameters is not an empty set; wherein, the grade of the MRAM chip is positively correlated with the number of available trimming parameters in the intersection of the trimming parameters.

[0040] A TRIM tuning test apparatus for MRAM chips includes:

[0041] Memory, used to store computer programs;

[0042] A processor for executing the computer program to implement the steps of the TRIM tuning test method for an MRAM chip as described in any of the preceding claims.

[0043] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the TRIM tuning test method for an MRAM chip as described in any of the preceding claims.

[0044] This invention provides a TRIM tuning test method, apparatus, device, and computer-readable storage medium for MRAM chips. The TRIM tuning test method for MRAM chips includes: under a set high-temperature condition, sequentially configuring multiple different alternative tuning parameters for the MRAM chip and performing read / write function tests on the MRAM chip, so that the MRAM chip uses the alternative tuning parameters from the read / write function test as first tuning parameters to obtain a first tuning parameter set; under a set low-temperature condition, sequentially configuring multiple different alternative tuning parameters for the MRAM chip and performing read / write function tests on the MRAM chip, so that the MRAM chip uses the alternative tuning parameters from the read / write function test as second tuning parameters to obtain a second tuning parameter set; performing an intersection operation on the first and second tuning parameter sets to obtain a tuning parameter intersection; determining whether the tuning parameter intersection is an empty set; if so, determining that the MRAM chip is a failed chip; if so, using the average value among the tuning parameters in the tuning parameter intersection as the fixed tuning value of the MRAM chip.

[0045] In this application, during the TRIM tuning test of the MRAM chip, multiple different alternative tuning parameters are sequentially configured for the MRAM chip under both set high and low temperature conditions. Read and write function tests are then performed on the MRAM chip with each of these alternative tuning parameters. This process selects a first set of tuning parameters that enables the MRAM chip to pass the read and write function test under the set high temperature condition, and a second set that enables it to pass the test under the set low temperature condition. The tuning parameters in the intersection of the first and second sets are clearly parameters that simultaneously ensure good read and write functionality for the MRAM chip in both high and low temperature environments. Therefore, the average value of all tuning parameters in the intersection is used as the fixed tuning value for the MRAM chip. This ensures that the MRAM chip maintains normal and good read and write operations under different extreme temperature environments, thus guaranteeing the accuracy and reliability of the MRAM chip's tuning parameters and consequently ensuring good performance of the MRAM chip. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic flowchart of the TRIM tuning test method for an MRAM chip provided in this application embodiment;

[0048] Figure 2 A schematic diagram of the process for obtaining the first set of adjustment parameters provided in an embodiment of this application;

[0049] Figure 3 This is a structural block diagram of the TRIM adjustment and testing device for an MRAM chip provided in an embodiment of the present invention. Detailed Implementation

[0050] In mass production testing of MRAM chips using CP and FT methods, TRIM tuning tests are typically performed at room temperature to determine the tuning parameters that enable read and write operations under these conditions. However, these tuning parameters may cause the MRAM chip to fail and become unusable under extreme conditions such as high or low temperatures. In other words, tuning parameters determined by testing at room temperature are unreliable.

[0051] Therefore, in order to ensure the reliability of the adjustment parameters, this application conducts adjustment tests at two different extreme temperatures, namely a set high temperature and a set low temperature. Finally, based on the adjustment parameters that enable the MRAM chip to achieve normal read and write operations at both extreme temperatures, more accurate and reliable adjustment parameters are determined, which is conducive to ensuring the good and reliable working performance of the MRAM chip.

[0052] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] like Figure 1 As shown, Figure 1 This is a schematic flowchart of the TRIM tuning test method for an MRAM chip provided in an embodiment of this application.

[0054] In an optional embodiment of this application, the TRIM tuning test method for the MRAM chip may include:

[0055] S10: Under the set high temperature conditions, configure multiple different alternative adjustment parameters for the MRAM chip in sequence, and perform read and write function tests on the MRAM chip so that the alternative adjustment parameters of the read and write function test are used as the first adjustment parameters to obtain the first adjustment parameter set.

[0056] In practical applications, the set high temperature can be no less than 80 degrees Celsius, for example, the set high temperature can be 85 degrees Celsius, specifically based on the actual working process of the MRAM chip.

[0057] Furthermore, the adjustment parameters involved in this embodiment can be any type of parameter such as VREF or RINT.

[0058] Based on this, while maintaining the MRAM chip in the set high-temperature environment, multiple different alternative tuning parameters were configured for the MRAM chip in sequence. Read and write function tests were then performed on each MRAM chip with each alternative tuning parameter configured separately. That is, while maintaining the set high temperature, read and write function tests were performed on the MRAM chip corresponding to multiple different alternative tuning parameters. For each alternative tuning parameter, if it allows the MRAM chip to pass the read and write function test, then that alternative tuning parameter can be used as the first tuning parameter. Thus, a set of first tuning parameters can be obtained.

[0059] Optionally, such as Figure 2 As shown, the actual process of obtaining the first adjustment parameter may include:

[0060] S11: Under the set high temperature condition, the first alternative adjustment parameter within the set adjustment parameter range is used as the current adjustment parameter to configure the current adjustment parameter for the MRAM chip;

[0061] S12: Perform read and write operations on the MRAM chip;

[0062] S13: Determine whether the read data and write data corresponding to the MRAM chip are consistent; if yes, proceed to S14; otherwise, proceed to S15.

[0063] S14: Use the current trimming parameter as the first trimming parameter of the MRAM chip, and proceed to S16;

[0064] S15: The current adjustment parameter is the parameter for which the MRAM chip failed the read / write test;

[0065] S16: Determine whether there are any unconfigured alternative adjustment parameters within the set adjustment parameter range. If yes, proceed to S17; otherwise, proceed to S18.

[0066] S17: Select a new current adjustment parameter from the unconfigured alternative adjustment parameters and proceed to S12;

[0067] S18: Using the first tuning parameter as the set element, obtain the first tuning parameter set.

[0068] It should be noted that the alternative adjustment parameters set in this embodiment are generally multiple continuously changing parameters. Taking the VREF (reference voltage) parameter as an example, theoretically, the VREF parameter of the MRAM chip should be within the range of 1.2V ± 2%. The alternative adjustment values ​​can be: 1.17V, 1.18V, 1.19V, 1.20V, 1.21V, 1.22V, 1.23V, and 1.24V, which are eight linearly continuously changing parameters. When actually testing the MRAM chip, each alternative adjustment parameter within the range of 1.17V to 1.24V should be tested completely to obtain more comprehensive test results. After configuring each alternative parameter for the MRAM chip, the MRAM chip may not be able to complete read and write operations normally when configuring the alternative adjustment parameters. In this case, only the alternative adjustment parameters that enable the MRAM chip to complete normal read and write operations are selected as the first adjustment parameters, and the set of all the first adjustment parameters is also called the first adjustment parameter set.

[0069] Furthermore, this embodiment only describes the situation where the MRAM chip fails the test because the read and write data results are inconsistent. However, it is understood that in actual testing, if the MRAM chip can only complete the read operation after being configured with the current adjustment parameters, but cannot complete the write operation, or if the MRAM chip cannot perform the read operation, then there is no need to perform a further write operation. In this case, the current adjustment parameters of the MRAM chip can also be considered as failing the read and write operation.

[0070] S20: Under the set low temperature conditions, configure multiple different alternative adjustment parameters for the MRAM chip in sequence, and perform read and write function tests on the MRAM chip so that the alternative adjustment parameters of the MRAM chip that pass the read and write function test are used as the second adjustment parameters to obtain the second adjustment parameter set.

[0071] In this embodiment, the set low temperature can be below -35°C, for example, -40°C. Specifically, it can be set based on the actual working environment of the MRAM chip and its operational requirements.

[0072] Furthermore, it is obvious that configuring alternative adjustment parameters for the MRAM chip under low temperature conditions, and performing read / write function tests when the MRAM chip is configured with different adjustment parameters, are exactly the same as the read / write function tests performed under high temperature conditions. They can also be implemented in a similar manner to steps S11 to S18. Therefore, this embodiment will not repeat the details.

[0073] Based on the above discussion, and considering MRAM chips, their performance often faces greater challenges under extreme high and low temperature environments. Therefore, the tuning parameters configured for the MRAM chip must ensure normal read and write operations under extreme high and low temperature conditions, and generally also enable read and write operations at room temperature. Accordingly, this embodiment specifically focuses on selecting tuning parameters that ensure normal read and write operations for the MRAM chip under extreme high and low temperature environments.

[0074] However, further considering that when configuring each alternative adjustment parameter for the MRAM chip, switching between high and low temperatures would take too long, which would not only make the entire testing process too time-consuming but also significantly increase the testing cost; therefore, in this embodiment, during the actual testing process, the read and write functions of the MRAM chip are tested by polling each alternative adjustment parameter under both the set high temperature condition and the set low temperature condition. In the entire testing process, only one switch between high and low temperature conditions is required, which greatly improves the testing efficiency and reduces the testing cost.

[0075] Furthermore, in actual testing, the MRAM chip can be placed in a high-temperature environment first, and each alternative tuning parameter can be configured sequentially to perform read and write function tests. Then, the MRAM chip can be placed in a low-temperature environment, and each alternative tuning parameter can be configured sequentially to perform read and write function tests. However, this application does not exclude the possibility of first placing the MRAM chip in a low-temperature environment to configure each alternative tuning parameter and perform read and write function tests, and then placing the MRAM chip in a high-temperature environment to configure each alternative tuning parameter and perform read and write function tests. In short, as long as it is ensured that the MRAM chip can be configured with multiple alternative tuning parameters and perform corresponding read and write function tests in both high-temperature and low-temperature environments, it is acceptable.

[0076] Furthermore, in an optional implementation of this embodiment, after obtaining the first set of adjustment parameters, the following may be further included:

[0077] Determine whether the first set of adjustment parameters is empty;

[0078] If so, then the MRAM chip is a faulty chip;

[0079] If not, then when there are at least two first adjustment parameters in the first adjustment parameter set, determine whether each first adjustment parameter is sequentially continuous.

[0080] If not, then the MRAM chip is determined to be a faulty chip.

[0081] Similarly, after obtaining the second set of tuning parameters, it can further include:

[0082] Determine whether the second set of adjustment parameters is empty;

[0083] If so, then the MRAM chip is a faulty chip;

[0084] If not, then when there are at least two second adjustment parameters, determine whether the second adjustment parameters are consecutive.

[0085] If not, then the MRAM chip is determined to be a faulty chip.

[0086] It is understandable that the first set of adjustment parameters in the first adjustment parameter set are those that enable the MRAM chip to perform normal read and write operations under a set high temperature condition, while the second set of adjustment parameters are those that enable the MRAM chip to perform normal read and write operations under a set low temperature condition. Therefore, when the first set of adjustment parameters is empty, it means that none of the above-mentioned alternative adjustment parameters can enable the MRAM chip to perform normal read and write operations; at this time, the MRAM chip can be considered a failed chip, that is, the adjustment test has failed.

[0087] Based on this, as described above, in this embodiment, the alternative adjustment parameters change linearly and continuously within the set adjustment parameter range; under normal circumstances, the first adjustment parameters in the first adjustment parameter set and the second adjustment parameters in the second adjustment parameter set should change sequentially and continuously. Taking the VREF parameter as being within the range of 3V to 8V, the corresponding alternative adjustment parameters can be eight linearly and continuously changing parameters: 1.17V, 1.18V, 1.19V, 1.20V, 1.21V, 1.22V, 1.23V, and 1.24V. If the first adjustment parameters determined by the read / write test are 1.17V, 1.18V, 1.19V, and 1.20V respectively, then the first adjustment parameters in the first adjustment parameter set can be considered to be sequentially continuous. However, if the first adjustment parameters determined by the read / write test are 1.17V, 1.20V, 1.21V, and 1.24V, then the first adjustment parameters in the first adjustment parameter set are considered to be discontinuous. Obviously, this is not consistent with the normal operating characteristics of the MRAM chip, so the MRAM chip can also be considered a faulty chip. Similarly, the method for determining whether the second adjustment parameters in the second adjustment parameter set are sequentially continuous is the same as the method for determining whether the first adjustment parameters are sequentially continuous. When the second adjustment parameters are not sequentially continuous, the MRAM chip is also considered a faulty chip. This will not be repeated here.

[0088] S30: Perform an intersection operation on the first and second adjustment parameter sets to obtain the intersection of adjustment parameters.

[0089] As described above, each first adjustment parameter in the first adjustment parameter set is an adjustment parameter that can satisfy the normal read and write operation of the MRAM chip under the set high temperature condition, while each second adjustment parameter in the second adjustment parameter set is an adjustment parameter that can satisfy the normal read and write operation of the MRAM chip under the set low temperature condition. Therefore, by performing an intersection operation on the first adjustment parameter set and the second adjustment parameter set, each adjustment parameter in the resulting adjustment parameter intersection set can achieve normal read and write operation of the MRAM chip under both the set high temperature condition and the set low temperature condition.

[0090] S40: Determine whether the intersection of the adjustment parameters is an empty set. If it is, then determine that the MRAM chip is a failed chip. If not, then take the average value of each adjustment parameter in the intersection of the adjustment parameters as the fixed adjustment value of the MRAM chip.

[0091] As described above, each adjustment parameter in the intersection of adjustment parameters in this embodiment can enable normal read and write operations of the MRAM chip under both set high temperature and set low temperature conditions.

[0092] Therefore, if the intersection of the adjustment parameters is an empty set, it means that there is no adjustment parameter among the candidate adjustment parameters that can satisfy both the normal read and write of the MRAM chip at the set high temperature and the normal read and write of the MRAM chip at the set low temperature. At this time, it can be considered that the MRAM chip adjustment test has failed and the MRAM chip itself is a failed chip.

[0093] Conversely, when the intersection of the adjustment parameters is not an empty set, the optimal adjustment parameters corresponding to the MRAM chip can be determined by comprehensively considering all the adjustment parameters in the intersection of the adjustment parameters, and this can be used as the fixed adjustment value of the MRAM chip.

[0094] In this embodiment, the average value of each adjustment parameter in the intersection of adjustment parameters is used as the fixed adjustment value. In practical applications, there may only be one adjustment parameter in the intersection of adjustment parameters, in which case the adjustment parameter can be directly used as the fixed adjustment value.

[0095] Furthermore, based on the fundamental characteristics of MRAM chips, a larger range of adjustment parameters that can satisfy the normal read and write operations of an MRAM chip generally indicates better performance of the MRAM chip. Therefore, when the intersection of adjustment parameters is not an empty set, it can further include:

[0096] MRAM chips are classified into different grades based on the number of adjustment parameters in the intersection of adjustment parameters; the grade of an MRAM chip is positively correlated with the number of available adjustment parameters in the intersection of adjustment parameters.

[0097] In practical applications, MRAM chips can be divided into two or three levels. Taking the division of MRAM chips into three levels as an example: if the number of adjustment parameters in the intersection of adjustment parameters is no more than two, the MRAM chip is classified as the third level; if the number of adjustment parameters in the intersection of adjustment parameters is greater than 2 and less than or equal to 5, the MRAM chip is classified as the second level; and if the number of adjustment parameters in the intersection of adjustment parameters is greater than 5, the MRAM chip is classified as the first level.

[0098] It is understandable that other methods can be used to classify MRAM chips in practical applications, which will not be listed in this embodiment.

[0099] In summary, during the TRIM tuning test of the MRAM chip in this application, multiple different alternative tuning parameters are sequentially configured for the MRAM chip under both set high-temperature and set low-temperature conditions. Read and write function tests are then performed on the MRAM chip with each of these alternative tuning parameters. This process selects a first set of tuning parameters that enables the MRAM chip to pass the read and write function test under the set high-temperature condition, and a second set that enables it to pass the test under the set low-temperature condition. The tuning parameters in the intersection of the first and second sets are clearly parameters that simultaneously ensure good read and write functionality for the MRAM chip in both high-temperature and low-temperature environments. Therefore, the average value of all tuning parameters in the intersection is used as the fixed tuning value for the MRAM chip. This ensures that the MRAM chip maintains normal and good read and write operations under different extreme temperature environments, thus guaranteeing the accuracy and reliability of the MRAM chip's tuning parameters and ultimately ensuring good performance of the MRAM chip.

[0100] Based on any of the above embodiments, in an optional embodiment of this application, the TRIM tuning test method for MRAM chips may include:

[0101] 1) During the high-temperature testing phase of CP or FT, the MRAM chip is first adjusted to obtain the first adjustment range A;

[0102] 2) Save the first adjustment range A and the chip DEVICE ID into an EXCEL or TXT document in the test machine software system for easy retrieval during the next adjustment test.

[0103] 3) During the low-temperature testing phase of CP or FT, the MRAM chip is adjusted a second time to obtain the second adjustment range B;

[0104] 4) The first adjustment range A corresponding to the chip DEVICE ID of the current MRAM chip being tested will be read from the EXCEL or TXT document of the test machine;

[0105] 5) Compare the first adjustment range A and the second adjustment range B for the same DEVICE ID to obtain the common adjustment range A∩B that is consistent under both high and low temperatures;

[0106] If A∩B=0, it means that the current MRAM chip under test has failed to obtain the adjustment value that simultaneously meets the requirements of high and low temperature testing; the chip is determined to be a failed chip.

[0107] If A∩B>0, it means that the current MRAM chip being tested has obtained a trim value that simultaneously meets the requirements of high and low temperature testing. At this time, the average value of the trim value range of A∩B≠0 is selected as the final default trim value and written into EFUSE for solidification, and graded according to the A∩B window size.

[0108] Based on any of the above embodiments, this application further considers that, in order to more accurately determine the range of alternative adjustment parameters for the MRAM chip in the high-temperature and low-temperature stages, before performing adjustment tests on the MRAM chip in the high-temperature and low-temperature stages, the following may be further included:

[0109] Under normal temperature conditions, multiple different theoretical adjustment parameters were sequentially configured for the MRAM chip, and the read and write functions of the MRAM chip were tested.

[0110] Based on the theoretical adjustment parameters of the MRAM chip after passing the read and write function test, the alternative adjustment parameters are determined.

[0111] In this embodiment, the set room temperature can be the current actual ambient temperature; in addition, the number of theoretical adjustment parameters configured in this embodiment does not need to be too large.

[0112] For example, based on historical test data of the MRAM chip's tuning parameters, the maximum and minimum boundary values ​​of the theoretical tuning parameter range of the MRAM chip can be determined. These maximum and minimum boundary values ​​can be used as the first and second theoretical tuning parameters, respectively. The first and second theoretical tuning parameters can then be sequentially configured to the MRAM chip, and read / write function tests can be performed on them. If both theoretical tuning parameters enable the MRAM chip to pass the read / write function test, then the maximum and minimum boundary values ​​can be used as the range of candidate tuning parameters. Within this range, several tuning parameters can be selected at equal intervals as candidate tuning parameters.

[0113] Furthermore, if either the first or second theoretical adjustment parameter fails to enable the MRAM chip to pass the read / write function test, taking the failure of the first theoretical adjustment parameter as an example, the average of the first and second theoretical adjustment parameters is used as the third theoretical adjustment parameter. The read / write function test is then performed on the MRAM chip configured with this third theoretical adjustment parameter. If the MRAM chip passes the read / write function test, a fourth theoretical adjustment parameter is selected between the third and first theoretical adjustment parameters and configured for the MRAM chip, ultimately determining the maximum value of a more accurate adjustment parameter range.

[0114] Based on this, when it is necessary to perform VREF parameter adjustment tests on the MRAM chip, if both the maximum and minimum boundary values ​​of the theoretical adjustment parameter range corresponding to the RINT parameter can enable the MRAM chip to pass the read and write function test, then the average value between the maximum and minimum boundary values ​​of the theoretical adjustment parameter range corresponding to the RINT parameter is taken as the current RINT parameter of the MRAM chip, and the VREF parameter adjustment test is performed on the MRAM chip according to the above TRIM adjustment test method.

[0115] The TRIM adjustment test apparatus for MRAM chips provided in the embodiments of the present invention will be described below. The TRIM adjustment test apparatus for MRAM chips described below can be referred to in correspondence with the TRIM adjustment test method for MRAM chips described above.

[0116] Figure 3 The structural block diagram of the TRIM trimming test device for MRAM chips provided in the embodiments of the present invention is shown below. Figure 3 The TRIM tuning test apparatus for MRAM chips may include:

[0117] The first test module 100 is used to configure multiple different alternative adjustment parameters for the MRAM chip under a set high temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative adjustment parameters of the read and write function test as the first adjustment parameter to obtain the first adjustment parameter set.

[0118] The second test module 200 is used to configure multiple different alternative adjustment parameters for the MRAM chip in sequence under a set low temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative adjustment parameters of the read and write function test as the second adjustment parameters to obtain the second adjustment parameter set.

[0119] The intersection operation module 300 is used to perform an intersection operation on the first set of adjustment parameters and the second set of adjustment parameters to obtain the intersection of adjustment parameters.

[0120] The judgment and calculation module 400 is used to determine whether the intersection of the adjustment parameters is an empty set. If it is, the MRAM chip is determined to be a failed chip. If not, the average value of each adjustment parameter in the intersection of the adjustment parameters is taken as the fixed adjustment value of the MRAM chip.

[0121] In an optional embodiment of this application, the first test module 100 is specifically configured to: under the set high temperature condition, use the first alternative adjustment parameter within the set adjustment parameter range as the current adjustment parameter to configure the MRAM chip with the current adjustment parameter; perform read and write operations on the MRAM chip; determine whether the read data and write data corresponding to the MRAM chip are consistent; if yes, use the current adjustment parameter as the first adjustment parameter of the MRAM chip; if no, the current adjustment parameter is the parameter for which the MRAM chip failed the read / write test; determine whether there are any unconfigured alternative adjustment parameters within the set adjustment parameter range; if yes, select a new current adjustment parameter from the unconfigured alternative adjustment parameters and repeat the operation of configuring the current adjustment parameter for the MRAM chip; if no, use the first adjustment parameter as a set element to obtain the first adjustment parameter set.

[0122] In an optional embodiment of this application, a failure determination module is further included, which is used to determine whether the first adjustment parameter set is an empty set after obtaining the first adjustment parameter set; if yes, the MRAM chip is a failed chip; if no, when there are not less than two first adjustment parameters in the first adjustment parameter set, it is determined whether each first adjustment parameter is sequentially consecutive; if no, the MRAM chip is determined to be a failed chip.

[0123] The failure determination module is also used to determine whether the second adjustment parameter set is an empty set after obtaining the second adjustment parameter set; if yes, the MRAM chip is a failed chip; if no, when there are at least two second adjustment parameters in the second adjustment parameters, determine whether each second adjustment parameter is sequentially consecutive; if no, determine that the MRAM chip is a failed chip.

[0124] In an optional embodiment of this application, a level classification module is further included, which is used to classify the MRAM chip according to the number of adjustment parameters in the intersection of the adjustment parameters when the intersection of the adjustment parameters is not an empty set; wherein, the level of the MRAM chip is positively correlated with the number of available adjustment parameters in the intersection of the adjustment parameters.

[0125] In an optional embodiment of this application, the third arithmetic module is configured to configure multiple different theoretical adjustment parameters for the MRAM chip under a set normal temperature condition before configuring multiple different alternative adjustment parameters for the MRAM chip in sequence, and to perform read and write function tests on the MRAM chip; and to determine the alternative adjustment parameters based on the theoretical adjustment parameters obtained by the MRAM chip through the read and write function tests.

[0126] In one optional embodiment of this application, the alternative adjustment parameter is any one of the VREF parameter or the RINT parameter; the set high temperature is not lower than 80°C, and the set low temperature is not higher than -35°C.

[0127] The TRIM trimming test apparatus for MRAM chips in this embodiment is used to implement the aforementioned TRIM trimming test method for MRAM chips. Therefore, the specific implementation of the TRIM trimming test apparatus for MRAM chips can be found in the embodiment section of the TRIM trimming test method for MRAM chips above. The specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0128] This application also provides an embodiment of a TRIM tuning test apparatus for an MRAM chip, which may include:

[0129] Memory, used to store computer programs;

[0130] A processor for executing the computer program to implement the steps of the TRIM tuning test method for an MRAM chip as described in any of the preceding claims.

[0131] The TRIM tuning test method for the MRAM chip executed by the processor in this embodiment may include: under a set high temperature condition, sequentially configuring multiple different alternative tuning parameters for the MRAM chip, and performing read / write function tests on the MRAM chip, so that the MRAM chip uses the alternative tuning parameters from the read / write function test as the first tuning parameter to obtain a first tuning parameter set; under a set low temperature condition, sequentially configuring multiple different alternative tuning parameters for the MRAM chip, and performing read / write function tests on the MRAM chip, so that the MRAM chip uses the alternative tuning parameters from the read / write function test as the second tuning parameter to obtain a second tuning parameter set; performing an intersection operation on the first tuning parameter set and the second tuning parameter set to obtain a tuning parameter intersection; determining whether the tuning parameter intersection is an empty set; if so, determining that the MRAM chip is a failed chip; if not, using the average value among the tuning parameters in the tuning parameter intersection as the fixed tuning value of the MRAM chip.

[0132] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the TRIM tuning test method for an MRAM chip as described in any of the preceding claims.

[0133] The computer-readable storage medium may be random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0134] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0135] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for TRIM trim test of an MRAM chip, characterized in that, include: Under set high temperature conditions, multiple different alternative adjustment parameters are sequentially configured for the MRAM chip, and the read and write function test is performed on the MRAM chip so that the alternative adjustment parameters of the read and write function test are used as the first adjustment parameters to obtain the first adjustment parameter set. Under set low temperature conditions, multiple different alternative tuning parameters are sequentially configured for the MRAM chip, and read / write function tests are performed on the MRAM chip so that the alternative tuning parameters that pass the read / write function test are used as the second tuning parameters to obtain the second tuning parameter set. Perform an intersection operation on the first set of adjustment parameters and the second set of adjustment parameters to obtain the intersection of adjustment parameters; Determine whether the intersection of the adjustment parameters is an empty set. If it is, then the MRAM chip is determined to be a failed chip. If not, then the average value of each adjustment parameter in the intersection of the adjustment parameters is taken as the fixed adjustment value of the MRAM chip.

2. The TRIM tuning test method for MRAM chips as described in claim 1, characterized in that, Under set high-temperature conditions, multiple different alternative tuning parameters are sequentially configured for the MRAM chip, and read / write function tests are performed on the MRAM chip. The alternative tuning parameters that pass the read / write function test are used as the first tuning parameters to obtain a first tuning parameter set, including: Under the set high temperature condition, the first alternative adjustment parameter within the set adjustment parameter range is used as the current adjustment parameter to configure the MRAM chip; Perform read and write operations on the MRAM chip; Determine whether the read data and write data corresponding to the MRAM chip are consistent; If so, the current adjustment parameter is used as the first adjustment parameter of the MRAM chip; If not, then the current adjustment parameter is the parameter for which the MRAM chip failed the read / write test; Determine whether there are any unconfigured alternative adjustment parameters within the set adjustment parameter range. If so, select a new current adjustment parameter from among the unconfigured alternative adjustment parameters and repeat the operation of configuring the current adjustment parameter for the MRAM chip. If not, then the first adjustment parameter is used as the set element to obtain the first adjustment parameter set.

3. The TRIM tuning test method for MRAM chips as described in claim 1, characterized in that, After obtaining the first set of adjustment parameters, the process also includes: Determine whether the first set of adjustment parameters is an empty set; If so, then the MRAM chip is a faulty chip; If not, then when there are at least two first adjustment parameters in the first adjustment parameter set, determine whether each first adjustment parameter is sequentially continuous. If not, then the MRAM chip is determined to be a faulty chip; After obtaining the second set of tuning parameters, the following is also included: Determine whether the second set of adjustment parameters is an empty set; If so, then the MRAM chip is a faulty chip; If not, then when there are at least two second adjustment parameters in the second adjustment parameters, determine whether each second adjustment parameter is consecutive. If not, then the MRAM chip is determined to be a faulty chip.

4. The TRIM adjustment test method for MRAM chips as described in any one of claims 1 to 3, characterized in that, When the intersection of the adjustment parameters is not an empty set, it also includes: The MRAM chips are classified into different levels based on the number of adjustment parameters in the intersection of the adjustment parameters; wherein, the level of the MRAM chip is positively correlated with the number of available adjustment parameters in the intersection of the adjustment parameters.

5. The TRIM tuning test method for MRAM chips as described in claim 1, characterized in that, Before configuring multiple different alternative tuning parameters for the MRAM chip in sequence, the process also includes: Under normal temperature conditions, multiple different theoretical adjustment parameters were sequentially configured for the MRAM chip, and the read and write functions of the MRAM chip were tested. The alternative adjustment parameters are determined based on the theoretical adjustment parameters obtained from the read / write function test of the MRAM chip.

6. The TRIM tuning test method for MRAM chips as described in claim 1, characterized in that, The alternative adjustment parameters are either VREF parameters or RINT parameters of any type. The set high temperature is no lower than 80°C, and the set low temperature is no higher than -35°C.

7. A TRIM adjustment and testing device for an MRAM chip, characterized in that, include: The first test module is used to configure multiple different alternative adjustment parameters for the MRAM chip under a set high temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative adjustment parameters of the read and write function test as the first adjustment parameter to obtain the first adjustment parameter set. The second test module is used to configure multiple different alternative tuning parameters for the MRAM chip in sequence under a set low temperature condition, and to perform read and write function tests on the MRAM chip, so that the MRAM chip can use the alternative tuning parameters of the read and write function test as the second tuning parameters to obtain the second tuning parameter set. The intersection operation module is used to perform an intersection operation on the first set of adjustment parameters and the second set of adjustment parameters to obtain the intersection of adjustment parameters. The judgment and calculation module is used to determine whether the intersection of the adjustment parameters is an empty set. If it is, the MRAM chip is determined to be a failed chip; if not, the average value of each adjustment parameter in the intersection of the adjustment parameters is taken as the fixed adjustment value of the MRAM chip.

8. The TRIM adjustment and testing apparatus for MRAM chips as described in claim 7, characterized in that, It also includes a grading module, which is used to grade the MRAM chip according to the number of trimming parameters in the intersection of the trimming parameters when the intersection of the trimming parameters is not an empty set; wherein, the grade of the MRAM chip is positively correlated with the number of available trimming parameters in the intersection of the trimming parameters.

9. A TRIM adjustment and testing device for MRAM chips, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the TRIM tuning test method for an MRAM chip as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the TRIM tuning test method for an MRAM chip as described in any one of claims 1 to 6.

Images