Dual power automatic switching circuit and switching method
By combining a power signal transmission circuit and a control circuit composed of a voltage regulator chip and a MOSFET, along with an energy storage capacitor array, the problems of high cost, slow response speed, and arc wear in existing dual power switching technologies are solved, achieving flexible power switching and fast, uninterrupted power switching.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LONGCHEER ELECTRONICS HUIZHOU
- Filing Date
- 2026-03-19
- Publication Date
- 2026-06-19
Smart Images
Figure CN122246980A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power management technology, and in particular to a dual-power automatic switching circuit and switching method. Background Technology
[0002] In the field of electronic products, especially in electronic devices with multiple power sources, such as when both the battery and the charging power supply are in an effective power supply state at the same time, the backend usually needs to give priority to the charging power supply, or in other scenarios with dual power supplies, automatic power switching needs to be implemented.
[0003] Currently, the traditional dual power switching design methods mainly include the following: The first approach is to use a dedicated dual-power switching chip to achieve main and backup power switching. However, this approach suffers from high costs and the voltage range is limited by the chip specifications, resulting in insufficient application flexibility.
[0004] The second option is to use relay control. This option uses mechanical contact switching, which has a slow response speed, is prone to arcing and wear, has a limited lifespan, and has a slight power interruption gap during switching, which may cause the backend system to reset or malfunction.
[0005] The third approach is a diode switching circuit, using two high-power Schottky diodes and a filter circuit. The drawbacks of this approach are: the diodes exhibit significant conduction losses and generate substantial heat under high current conditions; it cannot provide reverse cutoff protection; and it is only applicable to power supplies of the same voltage level, limiting its application range. Summary of the Invention
[0006] This invention provides a dual-power automatic switching circuit and switching method, which aims to achieve seamless switching between dual power supplies, enabling the dual-power automatic switching circuit to adapt to various power supply application scenarios.
[0007] This invention provides a dual-power automatic switching circuit, the circuit comprising: a voltage regulator chip, a first power supply, a second power supply, a first power supply signal transmission circuit, a second power supply signal transmission circuit, a control circuit, and a power switching circuit; The first power supply is connected to the voltage regulator chip through the first power signal transmission circuit; the second power supply is connected to the voltage regulator chip through the second power signal transmission circuit. If the first power supply is in an effective power supply state, the first power supply supplies power to the voltage regulator chip through the first power signal transmission circuit; the control circuit is used to control the power switching circuit to disconnect the second power signal transmission circuit. If the first power supply is in an ineffective power supply state, the control circuit is used to control the power switching circuit to turn on the second power signal transmission circuit, and the second power supply supplies power to the voltage regulator chip through the second power signal transmission circuit. The power supply signal output by the voltage regulator chip is input to the terminal through the energy storage capacitor array.
[0008] Furthermore, the first power signal transmission circuit includes: a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The gate of the first NMOS transistor is connected to the first power supply, the source is grounded, and the drain is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The source of the first PMOS transistor is connected to the first power supply, the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is connected to the power input terminal of the voltage regulator chip and the power pin of the voltage regulator chip.
[0009] Furthermore, the first power signal transmission circuit also includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first resistor is connected to the first power supply, and the other end is connected to one end of the second resistor, one end of the first capacitor, and the gate of the first NMOS transistor. The other end of the second resistor and the other end of the first capacitor are grounded. One end of the third resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the gate of the first PMOS transistor, one end of the second capacitor, one end of the fourth resistor, and the gate of the second PMOS transistor. The other end of the second capacitor is connected between the drain of the first PMOS transistor and the other end of the fourth resistor, and the other end of the fourth resistor is connected between the other end of the second capacitor and the drain of the second PMOS transistor.
[0010] Furthermore, the control circuit includes a second NMOS transistor; The gate of the second NMOS transistor is connected to the first power supply, the source is grounded, and the drain is connected to the second power supply. The control terminal of the power switching circuit is connected between the second power supply and the drain of the second NMOS transistor.
[0011] Furthermore, the control circuit also includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; One end of the fifth resistor is connected to the first power supply, and the other end is connected to one end of the sixth resistor and the gate of the second NMOS transistor; the other end of the sixth resistor is grounded. One end of the seventh resistor is connected to the second power supply, and the other end is connected to the drain of the second NMOS transistor; One end of the eighth resistor is connected between the drain of the second NMOS transistor and the other end of the seventh resistor, and the other end of the eighth resistor is connected to the control terminal of the power switching circuit.
[0012] Furthermore, the power switching circuit includes: a third NMOS transistor; The gate of the third NMOS transistor is connected between the drain of the second NMOS transistor and the second power supply, the source is grounded, and the drain is connected to the input terminal of the second power supply signal transmission circuit.
[0013] Furthermore, the power switching circuit also includes a third capacitor; One end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end is grounded.
[0014] Furthermore, the second power signal transmission circuit includes a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of the third NMOS transistor. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the third PMOS transistor is connected to the second power supply. The drain of the fourth PMOS transistor is connected to the power input terminal of the voltage regulator chip.
[0015] Furthermore, the second power signal transmission circuit also includes: a fourth capacitor, a fifth capacitor, and a ninth resistor; One end of the fourth capacitor is connected between the second power supply and the drain of the third PMOS transistor, and the other end is connected to the gate of the third PMOS transistor. One end of the fifth capacitor is connected between one end of the ninth resistor and the source of the fourth PMOS transistor, and the other end is connected to the gate of the fourth PMOS transistor. One end of the ninth resistor is also connected to the source of the third PMOS transistor; The other end of the ninth resistor is connected to the gate of the third PMOS transistor, the other end of the fifth capacitor, and the drain of the third NMOS transistor.
[0016] On the other hand, the present invention also discloses a method for automatic switching between dual power supplies, the method comprising: The first power supply is connected to the voltage regulator chip through a first power supply signal transmission circuit; the second power supply is connected to the voltage regulator chip through a second power supply signal transmission circuit. If the first power supply is in an effective power supply state, the first power supply supplies power to the voltage regulator chip through the first power signal transmission circuit; the control circuit controls the power switching circuit to disconnect the second power signal transmission circuit. If the first power supply is in an ineffective power supply state, the control circuit controls the power switching circuit to turn on the second power signal transmission circuit, and the second power supply supplies power to the voltage regulator chip through the second power signal transmission circuit. The power supply signal output by the voltage regulator chip is input to the terminal through the energy storage capacitor array.
[0017] Compared with the prior art, the present invention has at least the following technical effects: By setting up the above circuit and circuit control, the power supply is prioritized whenever the first power supply is in an effective power supply state, regardless of whether the second power supply is powered or not. When the first power supply is powered on after the second power supply is in an effective power supply state, the system can switch without power failure and the operation is not affected. When the first power supply is not in an effective power supply state and it is necessary to switch to the second power supply, a large-capacity energy storage capacitor array is set at the output of the voltage regulator chip to maintain the power supply to the downstream load at the moment of switching, thereby meeting the power demand during the switching process. This prevents the system from resetting or malfunctioning due to instantaneous power loss, and ultimately achieves fast and uninterrupted switching between the two power supplies. This allows the dual power supply automatic switching circuit to adapt to various power supply application scenarios. Attached Figure Description
[0018] Figure 1 This is a simplified schematic diagram of the power supply section in the dual-power automatic switching circuit of the present invention (Embodiment 1). Figure 2 This is a simplified schematic diagram of the control section in a dual-power automatic switching circuit according to an embodiment of the present invention; Figure 3 This is a simplified flowchart illustrating the automatic switching method for dual power supplies in Embodiment 2 of the present invention. Detailed Implementation
[0019] The following description, with reference to schematic diagrams, illustrates a dual-power automatic switching circuit and switching method according to the present invention, which represents a preferred embodiment of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0020] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.
[0021] Example 1 Please refer to Figure 1 This embodiment discloses a dual power supply automatic switching circuit, which includes: a voltage regulator chip U202, a first power supply VBUS, a second power supply VDD_SYS, a first power supply signal transmission circuit 1, a second power supply signal transmission circuit 4, a control circuit 2, and a power switching circuit 3. The first power supply VBUS is connected to the voltage regulator chip U202 through the first power signal transmission circuit 1; the second power supply VDD_SYS is connected to the voltage regulator chip U202 through the second power signal transmission circuit 4. If the first power supply VBUS is in an effective power supply state, the first power supply VBUS supplies power to the voltage regulator chip U202 through the first power signal transmission circuit 1; the control circuit 2 is used to control the power switching circuit 3 to disconnect the second power signal transmission circuit 4. If the first power supply VBUS is in an ineffective power supply state, the control circuit 2 is used to control the power switching circuit 3 to turn on the second power signal transmission circuit 4, and the second power supply VDD_SYS supplies power to the voltage regulator chip U202 through the second power signal transmission circuit 4. The power supply signal output by the voltage regulator chip U202 is input to the terminal through the energy storage capacitor array 5.
[0022] In this embodiment, by setting the above-mentioned circuit and circuit control, the VBUS power supply is used preferentially as long as the first power supply VBUS is in an effective power supply state, regardless of whether the second power supply VDD_SYS is powered or not, it does not affect the VBUS power supply; when the first power supply VBUS is powered on after the second power supply VDD_SYS is in an effective power supply state, it can meet the requirement of switching without power failure, and the system operation is not affected; when the first power supply VBUS is in an ineffective power supply state and needs to switch to the second power supply VDD_SYS, by setting a large-capacity energy storage capacitor array 5 at the output terminal of the voltage regulator chip U202, the power supply to the back-end load can be maintained at the moment of switching, thereby meeting the power demand during the switching process, so that the system will not reset or malfunction due to instantaneous power failure, and finally realize the fast and uninterrupted switching of dual power supplies, so that the dual power supply automatic switching circuit can adapt to various power supply application scenarios.
[0023] In this embodiment, being in an effective power supply state means that the power supply is in a normal power supply state, that is, the power supply is connected and the output voltage reaches the usable operating level (usually higher than the threshold voltage Vth of the NMOS transistor), which can provide effective power to the system; while being in an "ineffective power supply state" means that the power supply is not connected, has been disconnected, or the output voltage is lower than the effective operating level, which cannot provide sufficient power to the system.
[0024] In this embodiment, the first power supply VBUS is the priority power supply, which is usually provided by an external adapter or charger; the second power supply VDD_SYS is the secondary power supply or backup power supply, which is usually a battery power supply.
[0025] In this embodiment, the voltage regulator chip U202 is preferably an LDO chip (Low Dropout Regulator), and the specific model can be AS9113-33S5RN or other LDO chips with the same function. The voltage regulator chip U202 regulates the input voltage and outputs it to the back-end load system.
[0026] In this embodiment, the first power signal transmission circuit 1 includes: a first PMOS transistor Q705, a second PMOS transistor Q710, and a first NMOS transistor Q706.
[0027] In this configuration, the gate of the first NMOS transistor Q706 is connected to the first power supply VBUS, the source is grounded, and the drain is connected to the gate of the first PMOS transistor Q705 and the gate of the second PMOS transistor Q710. The source of the first PMOS transistor Q705 is connected to the first power supply VBUS, and the drain of the first PMOS transistor Q705 is connected to the drain of the second PMOS transistor Q710. The source of the second PMOS transistor Q710 is connected to the power input terminal LDO_IN of the voltage regulator chip U202 and the power pin VIN of the voltage regulator chip U202.
[0028] In this embodiment, the first power signal transmission circuit 1 adopts a back-to-back PMOS transistor structure (Q705 and Q710), with the drains of the two PMOS transistors connected and their gates jointly controlled. Power conduction control uses PMOS switching transistors, whose on-resistance is in the milliohm range (typically 30-50mΩ). Under high current operating conditions, conduction losses are extremely low, and no significant heat generation is observed, offering a significant advantage over traditional Schottky diode solutions (on-state voltage drop 0.5-0.7V). Simultaneously, the back-to-back PMOS transistor structure utilizes the unidirectional conductivity of the internal body diode of the PMOS transistor. When both the first PMOS transistor Q705 and the second PMOS transistor Q710 are turned off, even if the second power supply VDD_SYS voltage is higher than the first power supply VBUS voltage, current cannot flow in reverse from the output LDO_IN node of the second power signal transmission circuit 4 to the first power supply VBUS, achieving effective reverse current protection and protecting the first power supply VBUS from reverse current surges.
[0029] Furthermore, in this embodiment, the first power signal transmission circuit 1 further includes: a first capacitor C1142, a second capacitor C1141, a first resistor R1157, a second resistor R1156, a third resistor R1154, and a fourth resistor R1155.
[0030] In this configuration, one end of the first resistor R1157 is connected to the first power supply VBUS, and the other end is connected to one end of the second resistor R1156, one end of the first capacitor C1142, and the gate of the first NMOS transistor Q706. The other end of the second resistor R1156 and the other end of the first capacitor C1142 are grounded.
[0031] One end of the third resistor R1154 is connected to the drain of the first NMOS transistor Q706, and the other end is connected to the gate of the first PMOS transistor Q705, one end of the second capacitor C1141, one end of the fourth resistor R1155, and the gate of the second PMOS transistor Q710.
[0032] The other end of the second capacitor C1141 is connected between the drain of the first PMOS transistor Q705 and the other end of the fourth resistor R1155. The other end of the fourth resistor R1155 is connected between the other end of the second capacitor C1141 and the drain of the second PMOS transistor Q710.
[0033] In this embodiment, the first resistor R1157 and the second resistor R1156 form a voltage divider circuit to divide the voltage of the first power supply VBUS and provide it to the gate of the first NMOS transistor Q706, preventing the gate voltage from being too high and damaging the device. The first capacitor C1142 is connected in parallel with the second resistor R1156 to filter out high-frequency noise and transient interference on the first power supply VBUS, improving detection stability. The third resistor R1154 acts as a current-limiting resistor to prevent the drain current of the first NMOS transistor Q706 from being too large. The fourth resistor R1155 and the second capacitor C1141 form an RC filter network, wherein the second capacitor C1141 is connected in parallel between the gate and drain of the first PMOS transistor Q705 and the second PMOS transistor Q710, for filtering and stabilizing the gate voltage, suppressing oscillations and interference during the switching process, and ensuring the reliability of the PMOS transistor switching operation.
[0034] Furthermore, in this embodiment, the control circuit 2 includes a second NMOS transistor Q709.
[0035] The gate of the second NMOS transistor Q709 is connected to the first power supply VBUS, the source is grounded, and the drain is connected to the second power supply VDD_SYS. The control terminal of the power switching circuit 3 is connected between the second power supply VDD_SYS and the drain of the second NMOS transistor Q709.
[0036] Furthermore, in this embodiment, the control circuit 2 further includes: a fifth resistor R1160, a sixth resistor R1161, a seventh resistor R1159, and an eighth resistor R1162.
[0037] One end of the fifth resistor R1160 is connected to the first power supply VBUS, and the other end is connected to one end of the sixth resistor R1161 and the gate of the second NMOS transistor Q709; the other end of the sixth resistor R1161 is grounded.
[0038] One end of the seventh resistor R1159 is connected to the second power supply VDD_SYS, and the other end is connected to the drain of the second NMOS transistor Q709.
[0039] One end of the eighth resistor R1162 is connected between the drain of the second NMOS transistor Q709 and the other end of the seventh resistor R1159, and the other end of the eighth resistor R1162 is connected to the control terminal of the power switching circuit 3.
[0040] In this embodiment, the fifth resistor R1160 and the sixth resistor R1161 form a voltage divider circuit, which divides the voltage of the first power supply VBUS and provides it to the gate of the second NMOS transistor Q709. This prevents the gate voltage from exceeding the maximum rated value of the device and provides a suitable gate drive voltage, enabling the second NMOS transistor Q709 to reliably turn on or off according to the effective power supply state of VBUS. The seventh resistor R1159 acts as a pull-up resistor. When the second NMOS transistor Q709 is turned off, the drain voltage of its drain is pulled up to the level of the second power supply VDD_SYS through the seventh resistor R1159, providing a clear high-level control signal for the power switching circuit 3. The eighth resistor R1162 acts as a signal transmission resistor, transmitting the control signal from the drain of the second NMOS transistor Q709 to the gate of the third NMOS transistor Q702 in the power switching circuit 3, while also providing some current limiting protection and signal isolation.
[0041] Furthermore, in this embodiment, the power switching circuit 3 includes a third NMOS transistor Q702.
[0042] The gate of the third NMOS transistor Q702 is connected between the drain of the second NMOS transistor Q709 and the second power supply VDD_SYS, the source is grounded, and the drain is connected to the input terminal of the second power signal transmission circuit 4.
[0043] In this embodiment, after the power switching circuit 3 and the control circuit 2 are combined, the specific control logic is as follows: When the first power supply VBUS is in an active power supply state (i.e., VBUS is high), the gate voltage of the second NMOS transistor Q709 is high, and the second NMOS transistor Q709 is turned on, pulling its drain voltage down to near ground. At this time, the control terminal of the power switching circuit 3 receives a low-level signal, controlling the second power signal transmission circuit 4 to disconnect, so that the second power supply VDD_SYS is not connected to the input terminal LDO_IN of the voltage regulator chip U202.
[0044] When the first power supply VBUS is in an inactive state (i.e., VBUS is off, or the power supply is at a low level), the gate voltage of the second NMOS transistor Q709 is low, and the second NMOS transistor Q709 is cut off. The drain of the second NMOS transistor is pulled high to the VDD_SYS level through its connection with the second power supply VDD_SYS. At this time, the control terminal of the power switching circuit 3 receives a high-level signal, controlling the second power signal transmission circuit 4 to conduct, so that the second power supply VDD_SYS is connected to the power input terminal LDO_IN of the voltage regulator chip U202, realizing backup power supply.
[0045] It is understandable that the control signal detection and transmission of both control circuit 2 and power switching circuit 3 are implemented using NMOS switches. Whether the NMOS transistor is turned on or off depends only on whether its gate-source voltage VGS exceeds the threshold voltage Vth (usually 1-3V), and is unrelated to the absolute voltage value of the power supply. Therefore, the voltage levels of the first power supply VBUS and the second power supply VDD_SYS can be different, as long as their respective voltages meet the operating range of the power input terminal LDO_IN of the voltage regulator chip U202.
[0046] For example, the first power supply VBUS can be a 5V charger power supply, while the second power supply VDD_SYS can be a 12V battery power supply, or the first power supply VBUS can be a 12V adapter power supply, and the second power supply VDD_SYS can be a 19V battery power supply; the circuit can still function normally in both cases. In practical applications, NMOS transistors with different VGS threshold voltage ranges can be flexibly selected based on the specific voltage levels of the first power supply VBUS and the second power supply VDD_SYS. For example, for a 5V power supply system, an NMOS transistor with a Vth of approximately 2V can be selected; for a 12V or higher voltage system, an NMOS transistor with a Vth of approximately 4V can be selected. This flexibility makes circuit debugging convenient and highly adaptable. It avoids awkward problems such as switching failures or system malfunctions caused by power supply voltage mismatch or excessive voltage difference, thus broadening the application range of this circuit.
[0047] Furthermore, the power switching circuit 3 also includes a third capacitor C1151; one end of the third capacitor C1151 is connected to the gate of the third NMOS transistor Q702, and the other end is grounded.
[0048] In this embodiment, the third capacitor C1151 is used for filtering and stabilizing the gate voltage, filtering out high-frequency noise and transient interference in the control signal, and preventing the third NMOS transistor Q702 from malfunctioning due to gate voltage fluctuations.
[0049] Furthermore, in this embodiment, the second power signal transmission circuit 4 includes a third PMOS transistor Q707 and a fourth PMOS transistor Q704.
[0050] The gate of the third PMOS transistor Q707 is connected to the gate of the fourth PMOS transistor Q704 and the drain of the third NMOS transistor Q702. The source of the third PMOS transistor Q707 is connected to the source of the fourth PMOS transistor Q704. The drain of the third PMOS transistor Q707 is connected to the second power supply VDD_SYS. The drain of the fourth PMOS transistor Q704 is connected to the power input terminal LDO_IN of the voltage regulator chip U202.
[0051] In this embodiment, the second power signal transmission circuit 4 also adopts a back-to-back PMOS transistor structure (Q707 and Q704), with the sources of the two PMOS transistors connected and their gates jointly controlled. Similar to the first power signal transmission circuit 1, the power on-state control uses a PMOS switching transistor with a milliohm-level on-resistance and extremely low conduction loss, resulting in no significant heat generation. The back-to-back PMOS transistor structure achieves bidirectional blocking functionality: when both the third PMOS transistor Q707 and the fourth PMOS transistor Q704 are turned off, regardless of whether the second power supply VDD_SYS voltage is higher than the LDO_IN voltage, or the LDO_IN voltage (powered by the first power supply VBUS) is higher than the VDD_SYS voltage, current cannot flow in reverse through the body diode of the PMOS transistor, effectively preventing reverse flow between the two power supplies and improving the safety and reliability of power switching.
[0052] Furthermore, in this embodiment, the second power signal transmission circuit 4 further includes: a fourth capacitor C1152, a fifth capacitor C1150, and a ninth resistor R1158.
[0053] One end of the fourth capacitor C1152 is connected between the second power supply VDD_SYS and the drain of the third PMOS transistor Q707, and the other end is connected to the gate of the third PMOS transistor Q707; one end of the fifth capacitor C1150 is connected between one end of the ninth resistor R1158 and the source of the fourth PMOS transistor Q704, and the other end is connected to the gate of the fourth PMOS transistor Q704; one end of the ninth resistor R1158 is also connected to the source of the third PMOS transistor Q707; the other end of the ninth resistor R1158 is connected to the gate of the third PMOS transistor Q707, the other end of the fifth capacitor C1150, and the drain of the third NMOS transistor Q702.
[0054] In this embodiment, the fourth capacitor C1152 serves as the input filter capacitor for the second power supply VDD_SYS, connected in parallel between the input terminal of the second power supply VDD_SYS and the source of the third PMOS transistor Q707. It filters out high-frequency noise and ripple at the power input, improving power quality and providing a stable input voltage for the second power signal transmission circuit 4. The ninth resistor R1158 acts as the gate control resistor, transmitting the control signal from the drain of the third NMOS transistor Q702 to the common gate of the third PMOS transistor Q707 and the fourth PMOS transistor Q704. It also limits current, preventing excessive instantaneous gate current. The fifth capacitor C1150 is connected in parallel between the gate and source of the fourth PMOS transistor Q704, forming an RC filter network with the ninth resistor R1158. This network filters and shapes the gate control signal, suppressing oscillations and high-frequency interference during switching, and improving the stability and reliability of the PMOS transistor's switching action.
[0055] Preferably, in this embodiment, an input signal protection circuit is also included, which is connected to the output terminal of the first power signal transmission circuit 1 and the output terminal of the second power signal transmission circuit 4.
[0056] The input signal protection circuit includes a sixth capacitor C1149, a seventh capacitor C615, an eighth capacitor C612, and a tenth resistor R605.
[0057] Wherein, one end of the sixth capacitor C1149 is connected to the output terminals of the first power signal transmission circuit 1 and the second power signal transmission circuit 4, and the other end is grounded; one end of the seventh capacitor C615 is connected to one end of the sixth capacitor C1149, and the other end is grounded; one end of the tenth resistor R605 is connected to one end of C615 and the power input terminal of the voltage regulator chip U202, and the other end is connected to one end of the eighth capacitor C612 and the enable terminal of the voltage regulator chip U202, and the other end of the eighth capacitor C612 is grounded.
[0058] In a further preferred embodiment, the energy storage capacitor array 5 includes a capacitor array consisting of a ninth capacitor C1143, a tenth capacitor C1144, an eleventh capacitor C1145, a twelfth capacitor C1146, a thirteenth capacitor C1147, and a fourteenth capacitor C1148, disposed at the output terminal VOUT of the voltage regulator chip U202. The other end of each capacitor is grounded. The output terminal VOUT outputs a power signal to the power rail VDD_3V3 through the energy storage capacitor array 5.
[0059] It is understandable that the number of capacitors in the above-mentioned energy storage capacitor array 5 can be selected according to the actual situation, and no specific restrictions are imposed here.
[0060] In this embodiment, these parallel capacitors can maintain power supply to the back-end load during power switching (such as when switching from VBUS to VDD_SYS), so that the system will not reset due to momentary power loss. At the same time, the multi-capacitor parallel structure provides a larger total capacity and a lower equivalent series resistance.
[0061] The circuit disclosed in this embodiment uses three NMOS transistors, four PMOS transistors, and several matching resistors, capacitors, and other discrete components to construct a complete dual-power automatic switching system. Compared to dedicated integrated dual-power switching IC chip solutions, MOS transistors, as standardized and general-purpose discrete components, have a much lower unit price than integrated chips.
[0062] Example 2 Based on the same inventive concept, this embodiment discloses a method for automatic switching between dual power supplies, the method comprising: S1. The first power supply VBUS is connected to the voltage regulator chip U202 through the first power signal transmission circuit 1; the second power supply is connected to the voltage regulator chip U202 through the second power signal transmission circuit 4. S2. If the first power supply VBUS is in an effective power supply state, the first power supply VBUS supplies power to the voltage regulator chip U202 through the first power signal transmission circuit 1; the control circuit 2 controls the power switching circuit 3 to disconnect the second power signal transmission circuit 4. S3. If the first power supply VBUS is in an ineffective power supply state, the control circuit 2 controls the power switching circuit 3 to turn on the second power signal transmission circuit 4, and the second power supply VDD_SYS supplies power to the voltage regulator chip U202 through the second power signal transmission circuit 4. S4. The power supply signal output by the voltage regulator chip U202 is input to the terminal through the energy storage capacitor array.
[0063] In this embodiment, VBUS is used preferentially whenever the first power supply VBUS is in an effective power supply state, regardless of whether the second power supply VDD_SYS is powered or not. When the first power supply VBUS is powered on after the second power supply VDD_SYS is in an effective power supply state, the system can switch without power loss and the operation is not affected, allowing the automatic switching circuit of the dual power supply to adapt to various power supply application scenarios. When the first power supply VBUS is in an ineffective power supply state and needs to switch to the second power supply VDD_SYS, the large-capacity energy storage capacitor array 5 set at the output of the voltage regulator chip U202 maintains the power supply to the back-end load at the moment of switching, meeting the power demand during the switching process, so that the system will not reset or malfunction due to instantaneous power loss, thereby realizing fast and uninterrupted switching between the dual power supplies.
[0064] Using the circuit disclosed in Embodiment 1, the following seven operating scenarios can be achieved: Scenario 1: The first power supply VBUS is in an active power supply state: When the first power supply VBUS is in an effective power supply state, the second NMOS transistor Q709 is turned on, causing the third NMOS transistor Q702 to be turned off, and the third PMOS transistor Q707 and the fourth PMOS transistor Q704 to be turned off, thus disconnecting the second power supply signal transmission circuit 4; the first NMOS transistor Q706 is turned on, causing the first PMOS transistor Q705 and the second PMOS transistor Q710 to be turned on, and the first power supply VBUS supplies power to the power input terminal LDO_IN of the voltage regulator chip U202 through the first power supply signal transmission circuit 1.
[0065] Scenario 2: Single secondary power supply VDD_SYS is in an active power supply state: When the first power supply VBUS is in an inactive power supply state, the second NMOS transistor Q709 is turned off, the third NMOS transistor Q702 is turned on, causing the third PMOS transistor Q707 and the fourth PMOS transistor Q704 to turn on, and the second power supply VDD_SYS supplies power to the power input terminal LDO_IN of the voltage regulator chip U202 through the second power signal transmission circuit 4; when the first NMOS transistor Q706 is turned off, the first PMOS transistor Q705 and the second PMOS transistor Q710 are turned off, and the first power signal transmission circuit 1 is disconnected.
[0066] Scenario 3: Both power supplies are in effective power supply state at the same time: The second NMOS transistor Q709 turns on, causing the third NMOS transistor Q702 to turn off, and the second power supply signal transmission circuit 4 is disconnected; the first NMOS transistor Q706 turns on, causing the first PMOS transistor Q705 and the second PMOS transistor Q710 to turn on, the first power supply VBUS supplies power to the system, and the second power supply VDD_SYS is in standby mode.
[0067] Scenario 4: Both power supplies are in a valid power supply state, but the second power supply VDD_SYS is powered down.
[0068] The second NMOS transistor Q709 remains on, the third NMOS transistor Q702 remains off, and the second power signal transmission circuit 4 remains disconnected; the first power supply VBUS continues to supply power, and the system operation is unaffected.
[0069] Scenario 5: Both power supplies are in active power supply state, but the first power supply VBUS loses power: After the first power supply VBUS is de-energized, the second NMOS transistor Q709 is turned off, causing the third NMOS transistor Q702 to turn on. The third PMOS transistor Q707 and the fourth PMOS transistor Q704 are also turned on, and the second power supply VDD_SYS begins to supply power to the power input terminal LDO_IN of the voltage regulator chip U202. The first NMOS transistor Q706 is turned off, causing the first PMOS transistor Q705 and the second PMOS transistor Q710 to turn off, and the first power signal transmission circuit 1 is disconnected.
[0070] During the switching interval, the energy storage capacitor array 5 at the output terminal VOUT of the voltage regulator chip U202 maintains the power supply to the back-end system and prevents the system from resetting.
[0071] Scenario 6: The first power supply VBUS is in an active power supply state, and the second power supply VDD_SYS is powered on: The second NMOS transistor Q709 remains on, the third NMOS transistor Q702 remains off, and the second power supply signal transmission circuit 4 remains disconnected; the first power supply VBUS continues to supply power, and the power-on of the second power supply VDD_SYS does not affect the operation of the system.
[0072] Scenario 7: The second power supply VDD_SYS is in an active power supply state, and the first power supply VBUS is powered on: After the first power supply VBUS is powered on, the second NMOS transistor Q709 turns on, causing the third NMOS transistor Q702 to turn off, and the third PMOS transistor Q707 and the fourth PMOS transistor Q704 to turn off, thus disconnecting the second power supply signal transmission circuit 4. The first NMOS transistor Q706 then turns on, causing the first PMOS transistor Q705 and the second PMOS transistor Q710 to turn on, and the first power supply VBUS begins supplying power. Because the power-on process of the first power supply VBUS is gradual, the second power supply VDD_SYS continues to supply power during its voltage rise, achieving a seamless "on-then-off" switching, and the system operation is unaffected.
[0073] The above seven typical scenarios fully demonstrate the working mechanism and reliability of the dual power supply automatic switching circuit of the present invention under various power state changes.
[0074] Various modifications and variations are possible without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.
Claims
1. A dual-power automatic switching circuit, characterized in that, The circuit includes: a voltage regulator chip, a first power supply, a second power supply, a first power supply signal transmission circuit, a second power supply signal transmission circuit, a control circuit, and a power switching circuit. The first power supply is connected to the voltage regulator chip through the first power signal transmission circuit; the second power supply is connected to the voltage regulator chip through the second power signal transmission circuit. If the first power supply is in an effective power supply state, the first power supply supplies power to the voltage regulator chip through the first power signal transmission circuit; the control circuit is used to control the power switching circuit to disconnect the second power signal transmission circuit. If the first power supply is in an ineffective power supply state, the control circuit is used to control the power switching circuit to turn on the second power signal transmission circuit, and the second power supply supplies power to the voltage regulator chip through the second power signal transmission circuit. The power supply signal output by the voltage regulator chip is input to the terminal through the energy storage capacitor array.
2. The dual-power automatic switching circuit as described in claim 1, characterized in that, The first power signal transmission circuit includes: a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The gate of the first NMOS transistor is connected to the first power supply, the source is grounded, and the drain is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The source of the first PMOS transistor is connected to the first power supply, the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the source of the second PMOS transistor is connected to the power input terminal of the voltage regulator chip and the power pin of the voltage regulator chip.
3. The dual-power automatic switching circuit as described in claim 2, characterized in that, The first power signal transmission circuit further includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first resistor is connected to the first power supply, and the other end is connected to one end of the second resistor, one end of the first capacitor, and the gate of the first NMOS transistor. The other end of the second resistor and the other end of the first capacitor are grounded. One end of the third resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the gate of the first PMOS transistor, one end of the second capacitor, one end of the fourth resistor, and the gate of the second PMOS transistor. The other end of the second capacitor is connected between the drain of the first PMOS transistor and the other end of the fourth resistor, and the other end of the fourth resistor is connected between the other end of the second capacitor and the drain of the second PMOS transistor.
4. The dual-power automatic switching circuit as described in claim 1, characterized in that, The control circuit includes a second NMOS transistor; The gate of the second NMOS transistor is connected to the first power supply, the source is grounded, and the drain is connected to the second power supply. The control terminal of the power switching circuit is connected between the second power supply and the drain of the second NMOS transistor.
5. The dual-power automatic switching circuit as described in claim 4, characterized in that, The control circuit further includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; One end of the fifth resistor is connected to the first power supply, and the other end is connected to one end of the sixth resistor and the gate of the second NMOS transistor; the other end of the sixth resistor is grounded. One end of the seventh resistor is connected to the second power supply, and the other end is connected to the drain of the second NMOS transistor; One end of the eighth resistor is connected between the drain of the second NMOS transistor and the other end of the seventh resistor, and the other end of the eighth resistor is connected to the control terminal of the power switching circuit.
6. The dual-power automatic switching circuit as described in claim 4, characterized in that, The power switching circuit includes: a third NMOS transistor; The gate of the third NMOS transistor is connected between the drain of the second NMOS transistor and the second power supply, the source is grounded, and the drain is connected to the input terminal of the second power supply signal transmission circuit.
7. The dual-power automatic switching circuit as described in claim 5, characterized in that, The power switching circuit also includes a third capacitor; One end of the third capacitor is connected to the gate of the third NMOS transistor, and the other end is grounded.
8. The dual-power automatic switching circuit as described in claim 1, characterized in that, The second power signal transmission circuit includes a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and the drain of the third NMOS transistor. The source of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the third PMOS transistor is connected to the second power supply. The drain of the fourth PMOS transistor is connected to the power input terminal of the voltage regulator chip.
9. The dual-power automatic switching circuit as described in claim 7, characterized in that, The second power signal transmission circuit also includes: a fourth capacitor, a fifth capacitor, and a ninth resistor; One end of the fourth capacitor is connected between the second power supply and the drain of the third PMOS transistor, and the other end is connected to the gate of the third PMOS transistor. One end of the fifth capacitor is connected between one end of the ninth resistor and the source of the fourth PMOS transistor, and the other end is connected to the gate of the fourth PMOS transistor. One end of the ninth resistor is also connected to the source of the third PMOS transistor; The other end of the ninth resistor is connected to the gate of the third PMOS transistor, the other end of the fifth capacitor, and the drain of the third NMOS transistor.
10. A method for automatic switching between dual power supplies, characterized in that, The method includes: The first power supply is connected to the voltage regulator chip through a first power supply signal transmission circuit; the second power supply is connected to the voltage regulator chip through a second power supply signal transmission circuit. If the first power supply is in an effective power supply state, the first power supply supplies power to the voltage regulator chip through the first power signal transmission circuit; the control circuit controls the power switching circuit to disconnect the second power signal transmission circuit. If the first power supply is in an ineffective power supply state, the control circuit controls the power switching circuit to turn on the second power signal transmission circuit, and the second power supply supplies power to the voltage regulator chip through the second power signal transmission circuit. The power supply signal output by the voltage regulator chip is input to the terminal through the energy storage capacitor array.