General design method for multiple-input cooperative flip-around synchronous switched-capacitor collection

Abstract

This invention discloses a general design method for multi-input cooperative switching synchronous switched capacitor harvesting, comprising the following steps: Step 1, constructing a basic topology, which includes M piezoelectric transducers, N flying capacitors, and 4N + 5 power switches; Step 2, deriving analytical expressions for the voltage switching efficiency and output power of the basic topology based on the principle of charge conservation; Step 3, constructing an optimization model for the basic topology, with the maximum output power boost ratio (MOPIR) as the objective function and the number of piezoelectric transducers (M), the number of flying capacitors (N), and the value of the N flying capacitors as optimization parameters; Step 4, solving the basic topology optimization model using an optimization algorithm to determine the optimal values ​​of M, N, and the N flying capacitors; Step 5, adjusting the optimization parameters when the basic topology has input phase asynchrony or inherent capacitor mismatch. This invention achieves efficient design of a multi-transducer energy harvesting system by establishing a theoretical framework and optimization model, and ensures the robustness of the circuit under non-ideal conditions.

Description

Technical Field

[0001] This invention relates to the field of piezoelectric energy harvesting technology, and in particular to a general design method and electronic device for multi-input coordinated flip-synchrotron capacitor harvesting. Background Technology

[0002] With the development of Internet of Things (IoT) technology, powering miniature wireless sensor nodes (WSNs) has become a critical issue in practical applications. These wireless sensor nodes are typically deployed in environments where battery replacement is inconvenient, such as structural health monitoring systems or environmental monitoring stations. Traditional battery-powered methods face challenges such as difficult maintenance and high operating costs. Piezoelectric energy harvesting (PEH) technology offers an effective way to solve this problem by converting environmental mechanical vibration energy into electrical energy.

[0003] In piezoelectric energy harvesting interface circuits, traditional full-bridge rectifiers (FBRs) are widely used due to their simple structure and high stability, but their interface efficiency is limited. To improve performance, several advanced technologies have been developed: (1) Inductive synchronous switching harvesting (SSHI) technology, which utilizes the inductance of the piezoelectric current ( (1) Reverse the voltage across the piezoelectric element at zero crossover moment to reduce charge loss on the inherent capacitor; (2) Synchronous charge extraction (SECE) technology extracts accumulated charge when the voltage of the piezoelectric transducer (PT) reaches its maximum value, thus decoupling the piezoelectric element from the load; (3) Capacitor synchronous switch collection (SSHC) technology uses a capacitor instead of an inductor to reverse the voltage, which has advantages in miniaturization, cost and implementation.

[0004] In practical applications, many IoT devices require multiple piezoelectric transducers to meet power demands, such as in multi-node sensor networks or distributed vibration source scenarios. However, when traditional single-transducer interface technology is applied to multi-transducer configurations, the equivalent capacitance increases proportionally with the number of transducers, while the flip-flop capacitance... Or, if the inductance L remains constant, the switching efficiency will decrease significantly. For example, such as Figure 1 As shown, the efficiency of a traditional SSHC circuit is 33% with a single transducer, but drops to 10% with eight transducers in parallel. While existing technologies have proposed cooperative flip-flop SSHC (CF-SSHC) circuits for three-input six-stage configurations, these implementations are limited to specific fixed topologies. They lack a theoretical framework for analyzing and designing multi-input SSHC circuits applicable to arbitrary numbers of inputs and stages, and there is no systematic method to guide designers in determining the optimal topology for any number of transducers.

[0005] In summary, this invention aims to propose a general design method for multi-input cooperative switching synchronous switched capacitor harvesting. By establishing a theoretical framework and optimization strategy applicable to any M-input N-level configuration, it solves the problem that the efficiency of traditional multi-input SSHC circuits decreases with the increase of the number of transducers. At the same time, it takes into account the robustness of the circuit under non-ideal conditions, providing a systematic and quantifiable design scheme for multi-transducer energy harvesting systems, and meeting the actual needs of scenarios such as power supply for multiple sensors in the Internet of Things. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a general design method and electronic device for multi-input cooperative switching synchronous capacitor harvesting. This general design method and electronic device for multi-input cooperative switching synchronous capacitor harvesting achieves efficient design of multi-transducer energy harvesting systems by establishing a theoretical framework and optimization model, while ensuring the robustness of the circuit under non-ideal conditions.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A general design method for multi-input cooperative flip-sync capacitor harvesting includes the following steps.

[0009] Step 1: Construct the basic topology, which includes M piezoelectric transducers, N-stage SSHC circuits, a full-bridge rectifier, and an output capacitor. .

[0010] M piezoelectric transducers are connected in parallel at the input of an N-stage SSHC circuit.

[0011] The N-class SSHC circuit includes N flying capacitors and 4N + 5 power switches.

[0012] A full-bridge rectifier can rectify the AC output from an N-stage SSHC circuit into AC output current for the output capacitor. The power supply is direct current.

[0013] During the non-zero crossover period, M piezoelectric transducers operate in parallel to harvest energy.

[0014] piezoelectric current At the zero-crossing moment, the M intrinsic capacitances of the M piezoelectric transducers and the N flying capacitors share charge sequentially. After the reset phase, the charge sharing sequence is reversed, and the voltage polarity of each piezoelectric transducer is completely reversed through 2MN + 1 flipping phases.

[0015] Step 2: Based on the principle of charge conservation, derive the voltage reversal efficiency k and output power of the basic topology. The analytical expression for is given by ; where k is a function of M intrinsic capacitors and N flying capacitors; and Positive correlation.

[0016] Step 3: Construct a basic topology optimization model, with the maximum output power ratio (MOPIR) as the objective function, and the number of piezoelectric transducers (M), the number of flying capacitors (N), and the values ​​of the N flying capacitors as the parameters. To optimize parameters.

[0017] Step 4: Solve the basic topology optimization model using optimization algorithms to determine the optimal values ​​of M, N, and N flying capacitors.

[0018] In step 1, the working cycle of the basic topology includes a charging cycle, a clearing cycle, and a recharging cycle; for a dual-transducer single-stage topology, M=2, N=1, the charging cycle includes... , Two phases, the clearing cycle includes Phase, recharge cycle includes , There are two phases, with a total of 5 flip-flop stages; for a dual-transducer N-stage topology, both the charging cycle and the recharging cycle contain 2N phases, and the clearing cycle contains 1 phase, for a total of 4N + 1 flip-flop stages.

[0019] In step 2, when M=2, N=1, and the inherent capacitances of the two piezoelectric transducers are equal and both are... At that time, the analytical expression for the voltage switching efficiency k is:

[0020] (1)

[0021] In the formula, This is the value of the flying capacitance.

[0022] In step 2, when M=2, N=1, and the inherent capacitances of the two piezoelectric transducers are equal and both are... At that time, output power The parsing expression is:

[0023] (2)

[0024] In the formula, f is the excitation frequency. This is the open-circuit voltage of the piezoelectric transducer. This is the rectified voltage.

[0025] In step 4, the optimization algorithm solves the basic topology optimization model in two stages: initialization and main loop. In the initialization stage, the number of iterations T, the maximum number of flying capacitors max_N, and the number of transducers M are set, and the voltage reversal efficiency matrix and flying capacitor voltage vector are initialized. In the main loop stage, the maximum output power boost ratio MOPIR of different combination circuits is solved by simulating charge sharing operations.

[0026] Step 4, the main loop, includes the following steps:

[0027] Step 4-1, Reset: Set the inherent capacitance voltage of the M piezoelectric transducers. Where P is a 1×M dimensional vector.

[0028] Step 4-2, Forward charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (3). :

[0029] (3)

[0030] In the formula, Let be the voltage across the intrinsic capacitance of the k-th piezoelectric transducer during the (i-1)th iteration. It is the voltage before the j-th flying capacitor is shared. The voltage after the j-th flying capacitor is shared. The capacitance value of the j-th flying capacitor , Let be the intrinsic capacitance value of the k-th piezoelectric transducer.

[0031] After forward charging is complete, Updated to:

[0032] (4)

[0033] Step 4-3, Clear: Set the clear reset voltage for M inherent capacitors. Remove residual charge from the inherent capacitance of the piezoelectric transducer.

[0034] Step 4-4, Reverse charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (5). :

[0035] (5)

[0036] After reverse charging is complete, Updated to:

[0037] (6)

[0038] Steps 4-5: Calculate the equivalent voltage in parallel: Calculate the equivalent voltage after parallel connection of the inherent capacitance of the piezoelectric transducer according to the following formula (7). Specifically:

[0039] Steps 4-6: Calculate the flipping efficiency: Calculate the flipping efficiency under the current optimized parameter combination according to the following formula (8). Specifically:

[0040] (8)

[0041] In the formula, This is the rectified voltage.

[0042] Steps 4-7: Iterative Update: Use the current flying capacitor voltage as the initial value for the next iteration.

[0043] It also includes step 5, adjusting optimization parameters: when the basic topology has input phase asynchrony or inherent capacitance mismatch, the optimization parameters solved in step 4 need to be adjusted to ensure the robustness of the basic topology circuit.

[0044] Step 5, the method for adjusting the optimization parameters is as follows:

[0045] A. To address input phase asynchrony, one end of the piezoelectric transducer is fixed to a vibration table, and the other end is fixed to a mass block. This ensures the phase consistency of all piezoelectric transducers under vibration excitation, thus suppressing phase asynchrony from a physical structure perspective. Simultaneously, a phase synchronization verification mechanism is introduced into the optimization algorithm to monitor the phase state of each transducer in real time. If a phase deviation is detected to exceed a threshold, the charge sharing timing is automatically adjusted to further improve the circuit's adaptability to phase asynchrony.

[0046] B. To address inherent capacitance mismatch, by maintaining the total capacitance of M inherent capacitors constant, the inherent capacitance of a single piezoelectric transducer is allowed to fluctuate within the range of 11-33nF.

[0047] In step 1, the inherent capacitance of each of the M piezoelectric transducers is... The capacitance values ​​of the N flying capacitors are... 1 to 5 times.

[0048] An electronic device includes a storage medium storing a computer program that, when run, executes the general design method of multi-input cooperative flip-synchrotron capacitor collection described above.

[0049] This invention offers the following advantages: The universal design method for multi-input cooperative switching synchronous switched capacitor harvesting establishes a CF-SSHC circuit theoretical framework applicable to any M-input N-stage configuration. It derives closed-form expressions for voltage switching efficiency and output power, revealing the intrinsic relationship between the number of transducers, stages, and energy harvesting efficiency. This achieves a systematic and quantifiable design, overcoming the limitations of traditional empirical topology exploration. The proposed optimization algorithm automatically determines the optimal number of transducers, stages, and flying capacitor parameters. In an 8-stage configuration, as the number of transducers increases from 1 to 60, the maximum output power improvement ratio expands from 3.8 to 9. The dual-transducer single-stage topology achieves a 7.4% power improvement compared to traditional SSHC, and the dual-transducer 8-stage topology achieves a 32.2% power improvement, significantly outperforming traditional technologies. Furthermore, robust design addresses non-ideal factors such as phase asynchrony and capacitor mismatch in practical applications. When the inherent capacitance of a single piezoelectric transducer deviates from the ideal value by 10%, robust design is implemented. At the same time, the output power drops by only 0.58%, which reduces the stringent requirements for component matching and improves the feasibility and reliability of the system in mass production and long-term operation. Moreover, this design method does not rely on large-size inductors and uses capacitors to achieve voltage switching, which is in line with the development trend of miniaturization and low cost of energy harvesting circuits and is suitable for various application scenarios such as power supply of multiple sensors in the Internet of Things. Attached Figure Description

[0050] Figure 1 shows the relationship between a traditional multi-input single-stage SSHC circuit and its switching efficiency.

[0051] Figure 2(a) shows the basic topology of the dual transducer single-stage CF-SSHC of the present invention.

[0052] Figure 2 (b) shows the flip-flop phase of the dual transducer single-stage CF-SSHC of the present invention.

[0053] Figure 2 (c) shows the key waveforms of the dual-transducer single-stage CF-SSHC of the present invention.

[0054] Figure 3 shows the switching efficiency versus capacitance ratio of the dual-transducer single-stage CF-SSHC of the present invention. Relationship curve graph.

[0055] Figure 4 shows the output power of the dual-transducer single-stage CF-SSHC of the present invention and the conventional SSHC. With rectified voltage Comparison chart of changes.

[0056] Figure 5 shows the topology and a schematic diagram of the flip-phase of the dual transducer N-stage CF-SSHC of the present invention.

[0057] Figure 6 shows the output power of the dual-transducer 8-stage CF-SSHC of the present invention compared with that of a conventional SSHC. With rectified voltage Comparison chart of changes.

[0058] Figure 7 shows the topology and working principle of the general M-input N-level CF-SSHC of the present invention.

[0059] Figure 8 shows the relationship between MOPIR and PT number (M) of the M-input 8-level CF-SSHC of the present invention.

[0060] Figure 9 shows the effect of inherent capacitor mismatch on output power in this invention. Detailed Implementation

[0061] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0062] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0063] A general design method for multi-input cooperative flip-over synchronous switched capacitor harvesting includes the following steps.

[0064] Step 1: Construct the basic topology of the multi-input collaborative flip-sync synchronous capacitor harvesting circuit. The basic topology is the core architecture of the entire energy harvesting system, and its design rationality directly determines the subsequent energy harvesting efficiency and stability.

[0065] like Figure 2 As shown in (a), the basic topology includes M piezoelectric transducers (PTs), an N-stage SSHC circuit, a full-bridge rectifier (FBR), and an output capacitor. The values ​​of M and N can be flexibly adjusted according to the power requirements of the actual application scenario.

[0066] M piezoelectric transducers are connected in parallel at the input of an N-stage SSHC circuit.

[0067] The N-class SSHC circuit includes N flying capacitors and 4N + 5 power switches.

[0068] A full-bridge rectifier can rectify the AC output from an N-stage SSHC circuit into AC output current for the output capacitor. The power supply is direct current.

[0069] like Figure 2 (c) Figure 5 and Figure 7 As shown, during the non-zero crossover period, M piezoelectric transducers operate in parallel to harvest energy. This connection method can combine the energy collected by multiple transducers to maximize the total energy harvested and ensure that the system can make full use of the mechanical vibration energy in the environment.

[0070] piezoelectric current At the zero-crossing moment, the circuit enters the voltage reversal phase, at which point the M inherent capacitances of the M piezoelectric transducers... With N flying capacitors Charge sharing is performed sequentially, preparing for voltage polarity reversal through charge transfer and redistribution. After a brief reset phase, the charge sharing sequence is reversed, ultimately achieving complete voltage polarity reversal for each piezoelectric transducer through 2MN+1 flipping phases. This process effectively reduces charge waste on inherent capacitance and improves energy utilization efficiency.

[0071] like Figure 2 As shown in (b), the working cycle of the basic topology is strictly divided into three parts: the charging cycle, the clearing cycle, and the recharging cycle. The cycle division varies for different topologies.

[0072] For a dual-transducer single-stage topology:

[0073] The charging cycle includes , Two phases are used to achieve charge sharing between the two transducers and the flying capacitor, respectively.

[0074] The cleanup cycle includes Phase, used to short-circuit the transducer to clear residual charge.

[0075] Recharge cycles include , Two phases are used to complete the reverse reconstruction of the transducer voltage, and the entire working cycle consists of 5 flip-flop phases.

[0076] For the dual-transducer N-stage topology, both the charging cycle and the recharging cycle contain 2N phases, which correspond to the alternating charge sharing between the N flying capacitors and the two transducers. The clearing cycle still contains 1 phase. The entire operating cycle has a total of 4N+1 switching stages. By increasing the number of phases, more precise charge transfer control is achieved, further improving the switching efficiency.

[0077] Step 2: Based on the principle of charge conservation, derive the voltage reversal efficiency k and output power of the basic topology. The analytical expression for is given by ; where k is a function of M intrinsic capacitors and N flying capacitors; and Positive correlation.

[0078] Voltage reversal efficiency and output power are core indicators for evaluating the performance of energy harvesting systems, and accurately deriving their analytical expressions is crucial for achieving optimal system design. In this invention, voltage reversal efficiency k is defined as the reconstructed voltage... With rectified voltage The ratio of the two values, as defined, directly reflects the degree of energy loss during the voltage reversal process and the output power. It is positively correlated with the switching efficiency k, that is, the higher the switching efficiency, the greater the output power.

[0079] When M=2, N=1, and the parameters of the two piezoelectric transducers are consistent Based on the principle of charge conservation, and through detailed analysis of the charge transfer process in each switching stage, the analytical expression for the voltage switching efficiency k is derived as follows:

[0080] (1)

[0081] In the formula, Let be the value of the flying capacitor. This expression clearly reveals the mathematical relationship between the flying capacitor value and the switching efficiency, providing a theoretical basis for the parameter optimization of the flying capacitor.

[0082] Simultaneously, based on the energy conversion characteristics of the piezoelectric transducer, the output power is derived. The parsing expression is:

[0083] (2)

[0084] in, Let f be the inherent capacitance of a single piezoelectric transducer, and f be the excitation frequency. This represents the open-circuit voltage of the piezoelectric transducer. This expression comprehensively considers the influence of multiple key parameters, such as inherent capacitance, rectified voltage, excitation frequency, open-circuit voltage, and switching efficiency, on the output power, providing comprehensive theoretical support for system performance evaluation and parameter optimization.

[0085] To verify the accuracy of the analytical expression, the dual-transducer single-stage CF-SSHC circuit was simulated using Cadence Virtuoso. The simulation parameters were set as follows: Figure 3 and Figure 4 As shown, the inherent capacitance of the piezoelectric transducer =22nF, excitation current Amplitude 35µA, excitation frequency f=250Hz, open circuit voltage =2V, flying capacitor =22nF, the full-bridge rectifier adopts an ideal diode model (diode voltage drop) =0V). Simulation results show that the reconstructed voltage after zero-crossing flip is 0V. =0.3 Substituting the relevant parameters into the analytical expression for the switching efficiency, the calculated switching efficiency is consistent with the simulation results. At the same time, the error between the simulated value and the calculated value of the output power is within 3%, verifying the accuracy and reliability of the analytical expression.

[0086] Step 3: Construct a basic topology optimization model. To adapt to different application scenarios, a general topology optimization model needs to be established, with the maximum output power ratio (MOPIR) as the objective function, and the values ​​of the piezoelectric transducers (M), the number of flying capacitors (N), and the values ​​of the N flying capacitors as the parameters. To optimize parameters, this metric comprehensively reflects the performance improvement of the optimized system compared to the traditional system, and is a core indicator for evaluating the optimization effect. The design variables of the optimization model include the number of transducers M, the number of stages N, and the flying capacitor value. These variables directly affect the system's energy harvesting efficiency and circuit complexity.

[0087] Flying capacitor The value range needs to be related to the inherent capacitance of the piezoelectric transducer. A match was found, and after extensive simulation verification and engineering practice, it was determined that... The value of is equal to Or The value should be within the range of 1 to 5 times. If the flying capacitor value is too small, the charge transfer capability will be insufficient, affecting the switching efficiency. If the flying capacitor value is too large, although it can improve the switching efficiency to a certain extent, it will increase the chip area, increase the cost, and introduce greater parasitic effects, which is not conducive to the miniaturization and low-cost design of the circuit. Therefore, this value range can achieve a good balance between performance and practicality.

[0088] When establishing an optimization model, constraints in practical applications must also be considered, including circuit complexity constraints, cost constraints, and parasitic parameter constraints. Circuit complexity constraints require that the number of transducers and stages not be excessive, otherwise it will lead to a surge in the number of power switches, increasing the difficulty of circuit design and control complexity. Cost constraints require that the optimized topology minimize the number of components and cost while meeting performance requirements. Parasitic parameter constraints require that the impact of parasitic resistance and capacitance on circuit performance be fully considered when selecting parameters to ensure the practicality and reliability of the model.

[0089] Step 4: Solve the basic topology optimization model using optimization algorithms to determine the optimal values ​​of M, N, and N flying capacitors.

[0090] Solving the basic topology optimization model using optimization algorithms includes two stages: initialization and main loop.

[0091] Table 1

[0092]

[0093] As shown in Table 1 above, during the initialization phase, the iteration count T, the maximum number of flying capacitors max_N, and the number of transducers M need to be set according to the requirements of the actual application scenario. The voltage reversal efficiency matrix and the flying capacitor voltage vector are also initialized. The iteration count T needs to balance optimization accuracy and computational efficiency, and is usually set to 50-100 times. This ensures that a relatively optimal solution is found without excessive computation time due to too many iterations. The maximum number of flying capacitors max_N is determined based on circuit miniaturization and performance requirements, and is generally set to 8-12 levels. Exceeding this range will not significantly improve performance and will significantly increase circuit complexity. The number of transducers M is determined based on actual power requirements and can be flexibly selected between 1 and 60.

[0094] During the main loop phase, the maximum output power boost ratio (MOPIR) of different optimized parameter combinations is solved by simulating charge sharing operations.

[0095] The main loop described above preferably includes the following steps.

[0096] Step 4-1, Reset: Set the inherent capacitance voltage of the M piezoelectric transducers. Where P is a 1×M dimensional vector. This ensures that the initial state is consistent in each iteration, thereby improving the accuracy of the evaluation results.

[0097] Step 4-2, Forward charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (3). :

[0098] (3)

[0099] In the formula, Let be the voltage across the intrinsic capacitance of the k-th piezoelectric transducer during the (i-1)th iteration. It is the voltage before the j-th flying capacitor is shared. The voltage after the j-th flying capacitor is shared. The capacitance value of the j-th flying capacitor , Let be the intrinsic capacitance value of the k-th piezoelectric transducer.

[0100] After forward charging is complete, Updated to: (4)

[0101] Step 4-3, Clear: Set the clear reset voltage for M inherent capacitors. (1×M-dimensional vector) to remove residual charge on the inherent capacitance of the piezoelectric transducer, in preparation for reverse charging.

[0102] Step 4-4, Reverse charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (5). :

[0103] (5)

[0104] After reverse charging is complete, Updated to:

[0105] (6)

[0106] This step simulates the process of a flying capacitor charging the transducer in reverse, thus reversing the voltage polarity.

[0107] Steps 4-5: Calculate the equivalent voltage in parallel: Calculate the equivalent voltage after parallel connection of the inherent capacitance of the piezoelectric transducer according to the following formula (7). This equivalent voltage can reflect the overall voltage state of all transducers, specifically:

[0108] Steps 4-6: Calculate the flipping efficiency: Calculate the flipping efficiency under the current optimized parameter combination according to the following formula (8). This efficiency value is a key indicator for evaluating circuit performance, specifically:

[0109] (8)

[0110] In the formula, This is the rectified voltage.

[0111] Steps 4-7, Iterative Update: Settings The current flying capacitor voltage is used as the initial value for the next iteration to ensure the continuity of the iteration process.

[0112] By iteratively evaluating different parameter combinations using the aforementioned optimization algorithm, the optimal values ​​of M and N, along with the corresponding flying capacitor parameters, are ultimately determined. For example, in a power supply scenario for an IoT sensor, the optimization algorithm finds that when M=4 and N=4, the MOPIR reaches its optimal value. At this point, the circuit can meet the sensor's power requirements while maintaining low circuit complexity and cost, achieving a good balance between performance and practicality.

[0113] Step 5: Adjust optimization parameters: When the basic topology has input phase asynchrony or inherent capacitance mismatch, the optimization parameters obtained in step 4 need to be adjusted to ensure the robustness of the basic topology circuit.

[0114] Step 5: Adjust and optimize parameters to ensure circuit robustness. In actual application environments, there are many non-ideal factors, such as asynchronous input phase and inherent capacitor mismatch. These factors will affect the performance stability of the circuit. Therefore, it is necessary to adjust and optimize parameters to ensure the robustness of the circuit.

[0115] Input phase asynchrony is mainly caused by factors such as differences in the material properties of piezoelectric transducers, uneven structural stress distribution, and environmental interference. This leads to misalignment of the energy harvesting cycles of each transducer, disrupting the timing synchronization of charge sharing and reducing energy harvesting efficiency. To address this issue, the physical mounting method of the transducers is adjusted. One end of each piezoelectric transducer is fixed to a vibration table, and the other end is fixed to the same mass block. This ensures that the vibration phase of all piezoelectric transducers is consistent under vibration excitation, thus suppressing phase asynchrony from a physical structural perspective. Simultaneously, a phase synchronization verification mechanism is introduced into the optimization algorithm to monitor the phase state of each transducer in real time. If a phase deviation exceeds a threshold, the charge sharing timing is automatically adjusted, further improving the circuit's adaptability to phase asynchrony.

[0116] Inherent capacitance mismatch is mainly caused by manufacturing tolerances, differences in material properties, and environmental factors, leading to problems such as uneven voltage output, resonant frequency shift, and decreased charge transfer efficiency. To address this issue, a constant total capacitance constraint is set in the optimization model, allowing the inherent capacitance of a single piezoelectric transducer to fluctuate within the range of 11~33nF. By adjusting the inherent capacitance or flying capacitance parameters of other transducers, the total capacitance is kept constant, ensuring the overall circuit performance stability. Simulation verification shows that... Figure 9 As shown, when the inherent capacitance of a single transducer deviates from the ideal value by 10%, the output power only decreases by 0.58%, verifying the circuit's strong robustness to capacitor mismatch.

[0117] In addition, the impact of environmental factors such as temperature and humidity changes on circuit performance must be considered. Environmental adaptability constraints should be introduced during parameter optimization, and component parameters with small temperature coefficients and high stability should be selected to ensure that the circuit can work stably under different environmental conditions.

[0118] like Figure 6 As shown, in this invention, when M=2 and N=8, the maximum output power of the CF-SSHC circuit reaches 108.77μW, which is 32.2% higher than the 82.3μW of the traditional SSHC circuit, fully verifying the superiority of the design method of this invention. This method, through establishing a general topology, deriving analytical expressions, optimizing parameter combinations, and enhancing robustness design, achieves the efficient design of a multi-input cooperative switching synchronous switched capacitor harvesting system. It can be widely applied in various scenarios such as IoT multi-sensor power supply, structural health monitoring, and environmental monitoring, providing a complete solution for the engineering application of piezoelectric energy harvesting technology.

[0119] The present invention also provides a storage medium, wherein the computer program stored in the storage medium executes the above-mentioned multi-input cooperative flip capacitor synchronous switch piezoelectric energy harvesting method when running (that is, controlling the switch network to switch in a preset time sequence between the energy harvesting stage, the charging stage, the zeroing stage and the recharging stage, so as to realize the cooperative flipping and extraction of charge).

[0120] The present invention also provides an electronic device (such as an Internet of Things sensor node, a piezoelectric energy management chip, or an energy harvesting module containing a microcontroller), characterized in that: it includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-described multi-input cooperative flip-capacitor synchronous switching piezoelectric energy harvesting method through the computer program.

[0121] The sequence numbers of the above embodiments of the present invention are merely for description and do not represent the superiority or inferiority of the embodiments. In the above embodiments of the present invention, the descriptions of each embodiment have their own emphasis; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units can be a logical functional division, and in actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces; the indirect coupling or communication connection of units or modules can be electrical or other forms. The units described as separate components may or may not be physically separated; the components shown as units may or may not be physical units, that is, they can be located in one place or distributed across multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of this embodiment. Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, optical disks, and other media capable of storing program code.

[0122] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A general design method for multiple-input cooperative flip-around synchronous switched-capacitor collection, characterized by: Includes the following steps: Step 1, Constructing the base topology, which includes M piezoelectric transducers, N stages of SSHC circuits, full-bridge rectifier, and output capacitor ; M piezoelectric transducers are connected in parallel at the input of the N-stage SSHC circuit; An N-class SSHC circuit includes N flying capacitors and 4N + 5 power switches; A full-bridge rectifier can rectify the AC output from an N-stage SSHC circuit into AC output current for the output capacitor. Direct current (DC) power supply; During the non-zero crossover period, M piezoelectric transducers operate in parallel to harvest energy; piezoelectric current At the zero-crossing moment, the M intrinsic capacitances of the M piezoelectric transducers and the N flying capacitors share charge sequentially. After the reset phase, the charge sharing sequence is reversed, and the voltage polarity of each piezoelectric transducer is completely reversed through 2MN + 1 flipping phases. Step 2: Based on the principle of charge conservation, derive the voltage reversal efficiency k and output power of the basic topology. The analytical expression for ; where k is a function of M intrinsic capacitors and N flying capacitors; and Positive correlation; Step 3: Construct a basic topology optimization model, with the maximum output power ratio (MOPIR) as the objective function, and the number of piezoelectric transducers (M), the number of flying capacitors (N), and the values ​​of the N flying capacitors as the parameters. To optimize parameters; Step 4: Solve the basic topology optimization model using optimization algorithms to determine the optimal values ​​of M, N, and N flying capacitors.

2. The general design method for multi-input cooperative flip-sync capacitor harvesting according to claim 1, characterized in that: In step 1, the working cycle of the basic topology includes a charging cycle, a clearing cycle, and a recharging cycle; for a dual-transducer single-stage topology, M=2, N=1, the charging cycle includes... , Two phases, the clearing cycle includes Phase, recharge cycle includes , There are two phases, with a total of 5 flip-flop stages; for a dual-transducer N-stage topology, both the charging cycle and the recharging cycle contain 2N phases, and the clearing cycle contains 1 phase, for a total of 4N + 1 flip-flop stages.

3. The general design method for multi-input cooperative flip-sync synchronous switched capacitor harvesting according to claim 1, characterized in that: In step 2, when M=2, N=1, and the inherent capacitances of the two piezoelectric transducers are equal and both are... At that time, the analytical expression for the voltage switching efficiency k is: （1）; In the formula, This is the value of the flying capacitance.

4. The general design method for multi-input cooperative flip-sync synchronous switched capacitor harvesting according to claim 3, characterized in that: In step 2, when M=2, N=1, and the inherent capacitances of the two piezoelectric transducers are equal and both are... At that time, output power The parsing expression is: （2）; In the formula, f is the excitation frequency. This is the open-circuit voltage of the piezoelectric transducer. This is the rectified voltage.

5. The general design method for multi-input cooperative flip-sync synchronous switched capacitor harvesting according to claim 1, characterized in that: In step 4, the optimization algorithm solves the basic topology optimization model in two stages: initialization and main loop. In the initialization stage, the number of iterations T, the maximum number of flying capacitors max_N, and the number of transducers M are set, and the voltage reversal efficiency matrix and flying capacitor voltage vector are initialized. In the main loop stage, the maximum output power boost ratio MOPIR of different combination circuits is solved by simulating charge sharing operations.

6. The general design method for multi-input cooperative flip-sync synchronous switched capacitor harvesting according to claim 5, characterized in that: Step 4, the main loop, includes the following steps: Step 4-1, Reset: Set the inherent capacitance voltage of the M piezoelectric transducers. Where P is a 1×M dimensional vector; Step 4-2, Forward charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (3). : （3）; In the formula, Let be the voltage across the intrinsic capacitance of the k-th piezoelectric transducer during the (i-1)th iteration. It is the voltage before the j-th flying capacitor is shared. The voltage shared by the j-th flying capacitor. The capacitance value of the j-th flying capacitor , This represents the inherent capacitance value of the k-th piezoelectric transducer; After forward charging is complete, Updated to: （4）; Step 4-3, Clear: Set the clear reset voltage for M inherent capacitors. Remove residual charge from the inherent capacitance of the piezoelectric transducer; Step 4-4, Reverse charging: Calculate the voltage of the j-th flying capacitor in the i-th iteration according to the following formula (5). : （5）; After reverse charging is complete, Updated to: （6）; Steps 4-5: Calculate the equivalent voltage in parallel: Calculate the equivalent voltage after parallel connection of the inherent capacitance of the piezoelectric transducer according to the following formula (7). Specifically: ; Steps 4-6: Calculate the flipping efficiency: Calculate the flipping efficiency under the current optimized parameter combination according to the following formula (8). Specifically: （8）; In the formula, This is the rectified voltage; Steps 4-7: Iterative Update: Use the current flying capacitor voltage as the initial value for the next iteration.

7. The general design method for multi-input cooperative flip-sync capacitor harvesting according to claim 1, characterized in that: It also includes step 5, adjusting optimization parameters: when the basic topology has input phase asynchrony or inherent capacitance mismatch, the optimization parameters solved in step 4 need to be adjusted to ensure the robustness of the basic topology circuit.

8. The general design method for multi-input cooperative flip-sync synchronous switched capacitor harvesting according to claim 7, characterized in that: Step 5, the method for adjusting the optimization parameters is as follows: A. To address input phase asynchrony, one end of the piezoelectric transducer is fixed to a vibration table, and the other end is fixed to a mass block. This ensures the phase consistency of all piezoelectric transducers under vibration excitation, thus suppressing phase asynchrony from a physical structure perspective. Simultaneously, a phase synchronization verification mechanism is introduced into the optimization algorithm to monitor the phase state of each transducer in real time. If a phase deviation is detected to exceed a threshold, the charge sharing timing is automatically adjusted to further improve the circuit's adaptability to phase asynchrony. B. To address inherent capacitance mismatch, by maintaining the total capacitance of M inherent capacitors constant, the inherent capacitance of a single piezoelectric transducer is allowed to fluctuate within the range of 11-33nF.

9. The general design method for multi-input cooperative flip-sync capacitor harvesting according to claim 1, characterized in that: In step 1, the inherent capacitance of each of the M piezoelectric transducers is... Then the capacitance of the N flying capacitors takes the value of 1 to 5 times.

10. An electronic device, characterized in that: It includes a storage medium, wherein the computer program stored in the storage medium, when run, executes the general design method for multi-input cooperative flip-over synchronous switched capacitor collection as described in any one of claims 1-9.

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