A topology for inverters and a modulation method thereof

Abstract

This invention relates to the field of power electronics technology, specifically to an inverter topology and its modulation method. The topology of this invention is named 1P-2L-NNPC, where one arm is two-level and the other arm is an NNPC four-level. Compared to a single-phase four-level topology, this topology reduces two capacitors, four IGBTs, and two diodes; compared to a single-phase T-type three-level inverter, it only adds two diodes without increasing control complexity. For the proposed 1P-2L-NNPC topology, this invention also proposes a set of corresponding modulation techniques. The space voltage vector diagram of 1P-2L-NNPC is analyzed, and different three-segment sequences are selected according to different sectors. The output current is... i a As a feedback signal, the obtained modulation signal can be used to perform simple calculations to obtain the sector where the reference voltage is located and the duty cycle. Finally, simulations demonstrate the advantages of the proposed topology and modulation technique in terms of the number of output voltage levels and the number of switching operations.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to an inverter topology and its modulation method. Background Technology

[0002] Single-phase photovoltaic inverters are mostly used in residential distributed power generation. Currently, common topologies include two-level and three-level inverters. Three-level inverters have a lower output voltage dv / dt, resulting in higher output current quality, and are therefore more widely used.

[0003] Compared to three-level inverters, four-level inverters can provide more output voltage levels, thus resulting in higher output current quality. However, four-level inverters have a larger number of switches and capacitors in their topology, leading to higher costs and limiting their widespread adoption.

[0004] Nested Neutral Point Clamped Inverter (NNPC) is a common four-level topology. Each phase of this topology contains two floating capacitors, two reverse diodes, and six fully controlled switches. This topology does not require controlling the neutral point voltage balance; it only needs to balance the floating capacitor voltages. However, compared to a T-type three-level inverter, each arm of the NNPC contains two floating capacitors. For a single-phase NNPC topology, the NNPC needs to control the voltages of four floating capacitors, while the T-type three-level inverter only needs to control the voltages of two DC-side capacitors. Furthermore, a single-phase NNPC four-level inverter contains a total of 12 fully controlled devices and four diodes, while a single-phase T-type three-level inverter contains only eight fully controlled devices. Therefore, whether in terms of control complexity or the number of capacitors and switches, the single-phase NNPC four-level inverter has no advantage over the single-phase T-type inverter. In conclusion, although the single-phase NNPC four-level inverter can improve output current quality, its high hardware and software costs significantly limit the widespread application of four-level topologies and also restrict the improvement of output current quality.

[0005] To address the aforementioned issues, this invention proposes a novel single-phase four-level topology. This structure comprises a two-level topology for phase a and an NNPC topology for phase b, named the Single-Phase Nested Midpoint Clamping-Two-Level Hybrid Four-Level Inverter (1P-2L-NNPC). The 1P-2L-NNPC contains a total of 8 fully controlled devices, 2 diodes, and 2 floating capacitors. This is 4 fewer fully controlled devices, 2 fewer diodes, and 2 fewer floating capacitors than the single-phase NNPC four-level inverter, and only 2 more diodes than the single-phase T-type three-level inverter. The diodes only increase hardware costs slightly and require no additional control in the software. Regarding control complexity, the single-phase T-type three-level inverter requires balancing the voltages of the two DC-side capacitors, while the 1P-2L-NNPC designed in this invention only requires balancing the voltages of the two floating capacitors in the phase b NNPC. Therefore, the two topologies have the same control cost. However, the 1P-2L-NNPC proposed in this invention can achieve a seven-level output voltage, while a single-phase T-type inverter can only output a maximum of a five-level voltage.

[0006] Based on the proposed 1P-2L-NNPC topology, this invention also includes a modulation technique to ensure its proper functioning. Summary of the Invention

[0007] In order to overcome the shortcomings of the prior art and achieve the above-mentioned functions, the present invention provides an inverter topology and its modulation method.

[0008] This invention is achieved through the following technical solution: An inverter topology includes a DC-side power supply, an a-phase bridge arm, a b-phase bridge arm, a filter inductor, and a load; the input voltage of the DC-side power supply is... u dc The midpoint of the DC-side power supply is defined as the reference point. o The reference point o Will u dc Divide equally; The a-phase bridge arm is a two-level topology, consisting of two insulated-gate bipolar transistors S. a1 S a2 Series connection, S a1 One end is connected to the positive bus of the DC power supply, S a2 One end is connected to the negative bus of the DC power supply, S a1 With S a2 The connection point is the output terminal of phase a, S a1 With S a2 Operating in complementary mode, the output voltage of phase a bridge arm is + u dc / 2 or - u dc / 2; The b-phase bridge arm is a nested midpoint clamped four-level topology, consisting of six insulated-gate bipolar transistors (SMTs). b1 S b2 S b3 S b4 S b5 S b6 It consists of two floating capacitors C1 and C2 and two clamping diodes D1 and D2 connected in series; S b1 To S b6 Sequentially connected, S b1 The other end is connected to the positive bus of the DC power supply, S b6 The other end is connected to the DC side power supply negative bus; S b1 With S b6 Complementary conduction, S b2 With S b4 Complementary conduction, S b3 With S b5 Complementary conduction; The anode of the clamping diode D1 is connected to the cathode of D2, forming a common connection point; one end of C1 is connected to S. b1 With S b2 The connection point is C1, and the other end of C1 is connected to the common connection point; one end of C2 is connected to the common connection point, and the other end of C2 is connected to S. b5 With S b6 The connection point; The output voltage of the b-phase bridge arm is + u dc / 2、- u dc / 2、+ u dc / 6 or - u dc / 6; The output terminal of phase a is connected to the output terminal of phase b in sequence through the load and the filter inductor to form a closed loop; The output voltage of phase a bridge arm is superimposed with the output voltage of phase b bridge arm. Through the combination of two-level output of phase a and four-level output of phase b, the inverter output includes + u dc / 2、- u dc / 2、+2 u dc / 3、-2 u dc / 3、+ u dc / 3、- u dc The seven levels of / 3 and 0.

[0009] Furthermore, the switching state of the a-phase bridge arm satisfies: when Sa1 On, S a2 At cutoff, the output voltage of phase a bridge arm is + u dc / 2, corresponding to switch state 3; when S a1 Deadline, S a2 When the circuit is on, the output voltage of phase a bridge arm is - u dc / 2 corresponds to switch state 0.

[0010] Furthermore, the switching state of the b-phase bridge arm satisfies: Switch state 3: S b1 S b2 S b3 On, S b4 S b5 S b6 At the cutoff, the output voltage of phase b bridge arm is + u dc / 2; Switch state 2: Includes two redundant conduction combinations, combination one is S b1 S b3 On, S b2 S b4 S b5 S b6 Deadline; Combination 2 is S b2 S b3 On, S b1 S b4 S b5 S b6 Cut-off; Under both combinations, the output voltage of phase b bridge arm is + u dc / 6; Switch state 1: Includes two redundant conduction combinations, combination one is S b3 S b6 On, S b1 S b2 S b4 S b5 Deadline; Combination 2 is S b1 S b4 S b5 S b6 On, S b2 S b3 Cut-off; both combinations output voltage of phase b bridge arm - u dc / 6; Switch state 0: S b4 S b5 S b6 On, S b1 S b2 Sb3 At cutoff, the output voltage of phase b bridge arm is - u dc / 2.

[0011] Furthermore, the S of the a-phase bridge arm a1 S with phase b bridge arm b1 The S phase of the a-phase bridge arm is connected to the positive busbar of the DC power supply. a2 S with phase b bridge arm b6 It is connected to the negative busbar of the DC power supply.

[0012] A modulation method suitable for the topology of the inverter includes the following steps: 1) Collect the output current of the inverter i a ,Will i a The current deviation signal is obtained by subtracting the current from the preset reference current; 2) The current deviation signal is input into the proportional-integral controller, and the modulation signal is obtained after parameter tuning. m a The m a The amplitude range is -1 to 1; 3) To m a Amplitude adjustment is performed, and the result is calculated. m a * =3× m a The m a * The amplitude range is -3 to 3; 4) According to m a * The numerical range of the reference voltage is determined by sector S, and the specific determination rule is as follows: When 2≤ m a * When ≤3, the sector S is determined to be S3; When 1≤ m a * When <2, sector S = S2; When 0≤ m a * When <1, sector S = S1 is determined; When -1 < m a * When ≤0, sector S is determined to be S4; When -2 <m a * When ≤-1, sector S is determined to be S5; When -3≤ m a * When ≤-2, sector S is determined to be S6; 5) Select the corresponding three-segment switching sequence according to sector S. The three-segment switching sequence has a "V0-V1-V0" structure, where V0 is the voltage vector at the beginning and end of the sequence, and V1 is the voltage vector in the middle of the sequence. The switching sequence corresponding to each sector is as follows: Sector S1: 30-31-30; Sector S2: 31-32-31; Sector S3: 32-33-32; Sector S4: 00-01-00; Sector S5: 01-02-01; Sector S6: 02-03-02; 6) Calculate the duty cycle of voltage vector V0. d Duty cycle of V0 and V1 d 1. The calculation formula is: , where floor() is the floor function; 7) By switching the two redundant combinations of switch state 1 or the two redundant combinations of switch state 2 in phase b bridge arm, the voltages of floating capacitors C1 and C2 are balanced. 8) Based on the switching sequence, duty cycle, and capacitor voltage balance result, generate a pulse width modulation drive signal to control the conduction and cutoff of each insulated gate bipolar transistor, thereby achieving stable output of the inverter.

[0013] Furthermore, when sector S is S1, S2, or S3, phase a bridge arm remains in switch state 3, and the output voltage is + u dc / 2; When sector S is S4, S5, or S6, phase a bridge arm remains in switch state 0, and the output voltage is - u dc / 2, the operating frequency of the a-phase bridge arm is 50Hz.

[0014] The beneficial effects of this invention are: This invention proposes a new single-phase four-level topology: 1P-2L-NNPC, which reduces 6 fully controlled devices, 2 floating capacitors, and 2 diodes compared to the single-phase NNPC; and only adds 2 diodes compared to the single-phase T-type three-level structure.

[0015] The present invention proposes that the 1P-2L-NNPC output voltage has a maximum of 7 levels, which is two more levels than a single-phase three-level inverter, and the voltage dv / dt is smaller.

[0016] The modulation technique proposed in this invention, suitable for 1P-2L-NNPC, can effectively reduce switching losses. The two-level bridge arms operate at the base frequency, and the switching losses are almost zero, thus making it more efficient than a single-phase NNPC four-level inverter. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the 1P-2L-NNPC topology of the present invention; Figure 2 This is a space voltage vector diagram of the 1P-2L-NNPC topology of the present invention; Figure 3 This is a flowchart illustrating the implementation of the present invention; Figure 4 The simulation results of the output voltage and current of this invention are given when the modulation index is 0.4. Figure 5 The simulation results of the output voltage and current of this invention are given when the modulation index is 0.8. Figure 6 The simulation results for the number of switch switching operations are shown in the figure. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] Specifically, the steps include the following: S1: Topology of the 1P-2L-NNPC inverter.

[0021] like Figure 1 The diagram shows the topology of a 1P-2L-NNPC. The output load is... R The filter inductor is L Output current i a And its positive direction is shown in the figure. The DC side input voltage is u dc.definition u dc The midpoint is o , o Divide the DC side voltage equally.

[0022] Figure 1 Phase a consists of two insulated-gate bipolar transistors (IGBTs) connected in series, with the output of phase a located between the two IGBTs. Output current. i a After passing through the load and filter inductor, the fluid flows into phase b. Phase b has an NNPC four-level topology, with the following order from top to bottom: S... b1 S b2 S b3 S b4 S b5 S b6 Six IGBTs are strung together between the DC positive bus and the DC negative bus, with the topmost S... b1 Connected to the DC positive bus, the lowest S b6 Connected to the DC negative bus. This invention connects the S of phase a... a1 S with phase b b1 Connect, connect phase S of phase a a2 and b phase S b6 Connected. Phase b contains two floating capacitors, with the upper end of C1 connected to S. b1 With S b2 The lower end of C1 is connected to the node between them. b2 With S b3 S b4 With S b5 The midpoint of the series diodes between them; similarly, the upper end of C2 is also connected to this point, and the lower end of C2 is connected to S. b5 With S b6 Between. For phase a, S a1 With S a2 Working in a complementary state; for phase b, S b1 and S b6 Complementary, S b2 and S b4 Complementary, S b3 and S b5 Complementary.

[0023] o It is a reference point. The so-called four-level output level refers to the output point being relative to the reference point. o The number of voltage levels between points. Figure 1 In the middle, the b-phase output is a four-level signal, that is... u bo The maximum number of voltage levels is four, with phase a output having two voltage levels. u ao It has two voltage levels. Therefore, phase a can output ±u dc / 2 has two voltage levels; the b phase can output ± u dc / 2, ± u dc / 6 A total of four levels. Definition - u dc / 2 and + u dc / 2 corresponds to switch states 0 and 3, - u dc / 6 and + u dc The switch states corresponding to / 6 are 1 and 2.

[0024] The relationship between phases ab, switches, and output voltage is shown in Tables 1 and 2. It should be noted that the NNPC of phase b contains redundant switch combinations in both 0 and 1 states, which can be used to balance the voltages of C1 and C2.

[0025] From Tables 1 and 2, it can be seen that the b-phase NNPC can output four switching states: 0, 1, 2, and 3, while the two levels of the a-phase can output two switching states: 0 and 3. Therefore, the space voltage vector diagram of the 1P-2L-NNPC is as follows: Figure 2 As shown, the 1P-2L-NNPC contains a total of 8 voltage vectors, which divide the space vector diagram into six sectors, and can output a maximum of ± u dc / 2、±2 / 3 u dc ±1 / 3 u dc There are seven levels, including 0.

[0026] The symmetrical three-segment sequence formed by the candidate vectors of each sector is shown in Table 3. It can be observed that when the output level is greater than 0, the two-level structure of phase a always outputs switch state 3, i.e. u ao Always + u dc 2; When the output level is less than 0, the two-level structure of phase a always outputs a switch state of 0, that is... u ao Always for - u dc / 2. Therefore, the two-level structure of phase a operates at the power frequency, i.e., 50Hz, resulting in very few switching operations and significantly reducing switching losses. For phase b, the switching state changes only twice in the three-segment sequence of each sector.

[0027] S2: 1P-2L-NNPC inverter modulation technology.

[0028] Output current is i a ,Will i a The difference between the input and reference current is fed into a proportional-integral (PR) controller to achieve current tracking. The signal output from the PR is defined as follows: m a , m a Essentially, it's a modulated signal; after setting the PR controller parameters... m a The amplitude is between -1 and 1.

[0029] This invention proposes a method based on m a The method for determining the sector where the reference voltage is located based on the amplitude. First, m a Multiply by 3 to get m a * ,at this time m a * The amplitude is between -3 and 3. m a * The calculation formula is as follows: (1); and then Figure 2 And sector S in Table 3 can be determined by the following formula: (2); Based on the sector obtained from Formula 2, and combined with the three-segment sequence in Table 3, it can be determined which sequence should be used to track the reference current.

[0030] The three-segment sequence in Table 3 is uniformly defined as V0-V1-V0, where V0 represents the first and third vectors in the three-segment sequence, and V1 represents the middle vector. The duty cycle of V0 is defined as follows: d 0, V1 duty cycle is d 1. Then d 0 and d 1 can be obtained through the following formula (3); In phase b, the four-level NNPC contains two floating capacitors, C1 and C2. Since the four-level NNPC is a well-studied four-level topology, conventional strategies have shown that the balance of C1 and C2 can be achieved by switching the redundant switch combinations in states 1 and 2, i.e., 1a and 1b, 2a and 2b in Table 2, which will not be elaborated here.

[0031] The duty cycle obtained by Formula 3 is allocated to the three-segment sequence in Table 3. Then, a suitable switch combination is selected to balance the floating capacitor voltage of phase b. Finally, the corresponding PWM signals generated by Tables 1 and 2 drive the IGBTs to operate, enabling the 1P-2L-NNPC inverter to function normally. It can be seen that the calculation process for the duty cycle and sector determination in this invention is simple. The flowchart of the modulation technology suitable for 1P-2L-NNPC proposed in this invention is as follows: Figure 3 As shown.

[0032] This embodiment was verified in simulation. Simulation parameters: DC input voltage 200V, filter inductor... L 6mH, load R The impedance is 24Ω, and the sampling period is 100μs. Simulations were performed at modulation indices of 0.4 and 0.8, and the results are as follows. Figure 4 and Figure 5 As shown. Furthermore, the average number of switching operations was statistically analyzed under different modulation indices (0.4, 0.5, 0.6, 0.7, 0.8, 0.9) for single-phase NNPC four-level and single-phase T-type three-level circuits, and the results are as follows. Figure 6 As shown.

[0033] like Figure 4 As shown, at a modulation index of 0.4, phase a has a two-level waveform with a period of the fundamental frequency, while phase b has a high-frequency changing four-level waveform. Within each half-cycle of the fundamental frequency, phase b outputs a three-level waveform. At this time, the output voltage of 1P-2L-NNPC exhibits a five-level waveform, and the output current THD is 2.88%. Figure 5 As shown, when the modulation index is 0.8, phase a still exhibits a two-level waveform with the fundamental frequency as its period, while phase b is a high-frequency changing four-level waveform. Within each half-cycle of the fundamental frequency, phase b outputs a four-level waveform. At this time, the output voltage of the 1P-2L-NNPC presents a seven-level waveform, and the output current THD is 1.67%. Simulation results show that the 1P-2L-NNPC inverter and modulation strategy designed in this invention can achieve two-level operation of phase a and four-level operation of phase b, and the two-level operation is based on the fundamental frequency.

[0034] like Figure 6 As shown, the 1P-2L-NNPC has the fewest switching operations, which helps to reduce the number of switching operations and thus reduce switching losses.

[0035] In summary, the topology designed in this invention and its supporting modulation technology enable the 1P-2L-NNPC to operate normally, and can reduce switching losses and improve system efficiency.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Any other modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention, as long as they do not depart from the spirit and scope of the technical solutions of the present invention, should be covered within the scope of the claims of the present invention.

Claims

1. A topology for an inverter, characterized in that, It includes a DC-side power supply, phase a bridge arm, phase b bridge arm, filter inductor, and load; the input voltage of the DC-side power supply is... u dc The midpoint of the DC-side power supply is defined as the reference point. o The reference point o Will u dc Divide equally; The a-phase bridge arm is a two-level topology, consisting of two insulated-gate bipolar transistors S. a1 S a2 Series connection, S a1 One end is connected to the positive bus of the DC power supply, S a2 One end is connected to the negative bus of the DC power supply, S a1 With S a2 The connection point is the output terminal of phase a, S a1 With S a2 Operating in complementary mode, the output voltage of phase a bridge arm is + u dc / 2 or - u dc / 2; The b-phase bridge arm is a nested midpoint clamped four-level topology, consisting of six insulated-gate bipolar transistors (SMTs). b1 S b2 S b3 S b4 S b5 S b6 It consists of two floating capacitors C1 and C2 and two clamping diodes D1 and D2 connected in series; S b1 To S b6 Sequentially connected, S b1 The other end is connected to the positive bus of the DC power supply, S b6 The other end is connected to the DC side power supply negative bus; S b1 With S b6 Complementary conduction, S b2 With S b4 Complementary conduction, S b3 With S b5 Complementary conduction; The anode of the clamping diode D1 is connected to the cathode of D2, forming a common connection point; one end of C1 is connected to S. b1 With S b2 The connection point is C1, and the other end of C1 is connected to the common connection point; one end of C2 is connected to the common connection point, and the other end of C2 is connected to S. b5 With S b6 The connection point; The output voltage of the b-phase bridge arm is + u dc / 2、- u dc / 2、+ u dc / 6 or - u dc / 6; The output terminal of phase a is connected to the output terminal of phase b in sequence through the load and the filter inductor to form a closed loop; The output voltage of phase a bridge arm is superimposed with the output voltage of phase b bridge arm. Through the combination of two-level output of phase a and four-level output of phase b, the inverter output includes + u dc / 2、- u dc / 2、+2 u dc / 3、-2 u dc / 3、+ u dc / 3、- u dc The seven levels of / 3 and 0.

2. The inverter topology according to claim 1, characterized in that, The switching state of phase a bridge arm satisfies: when S a1 On, S a2 At cutoff, the output voltage of phase a bridge arm is + u dc / 2, corresponding to switch state 3; when S a1 Deadline, S a2 When the circuit is on, the output voltage of phase a bridge arm is - u dc / 2 corresponds to switch state 0.

3. The inverter topology according to claim 1, characterized in that, The switching state of the b-phase bridge arm satisfies: Switch state 3: S b1 S b2 S b3 On, S b4 S b5 S b6 At the cutoff, the output voltage of phase b bridge arm is + u dc / 2; Switch state 2: Includes two redundant conduction combinations, combination one is S b1 S b3 On, S b2 S b4 S b5 S b6 Deadline; Combination 2 is S b2 S b3 On, S b1 S b4 S b5 S b6 Cut-off; Under both combinations, the output voltage of phase b bridge arm is + u dc / 6; Switch state 1: Includes two redundant conduction combinations, combination one is S b3 S b6 On, S b1 S b2 S b4 S b5 Deadline; Combination 2 is S b1 S b4 S b5 S b6 On, S b2 S b3 Cut-off; both combinations output voltage of phase b bridge arm - u dc / 6; Switch state 0: S b4 S b5 S b6 On, S b1 S b2 S b3 At cutoff, the output voltage of phase b bridge arm is - u dc / 2.

4. The inverter topology according to claim 1, characterized in that, The S of phase a bridge arm a1 S with phase b bridge arm b1 The S phase of the a-phase bridge arm is connected to the positive busbar of the DC power supply. a2 S with phase b bridge arm b6 It is connected to the negative busbar of the DC power supply.

5. A modulation method applicable to the topology of the inverter according to any one of claims 1 to 4, characterized in that, Includes the following steps: 1) Collect the output current of the inverter i a ,Will i a The difference between the current and the preset reference current is used to obtain the current deviation signal; 2) The current deviation signal is input into the proportional-integral controller, and the modulation signal is obtained after parameter tuning. m a The m a The amplitude range is -1 to 1; 3) To m a Amplitude adjustment is performed, and the result is calculated. m a * =3× m a The m a * The amplitude range is -3 to 3; 4) According to m a * The numerical range of the reference voltage is determined by sector S, and the specific determination rule is as follows: When 2≤ m a * When ≤3, the sector S is determined to be S3; When 1≤ m a * When <2, sector S = S2; When 0≤ m a * When <1, sector S = S1 is determined; When -1 < m a * When ≤0, sector S is determined to be S4; When -2 < m a * When ≤-1, sector S is determined to be S5; When -3≤ m a * When ≤-2, sector S is determined to be S6; 5) Select the corresponding three-segment switching sequence according to sector S. The three-segment switching sequence has a "V0-V1-V0" structure, where V0 is the voltage vector at the beginning and end of the sequence, and V1 is the voltage vector in the middle of the sequence. The switching sequence corresponding to each sector is as follows: Sector S1: 30-31-30; Sector S2: 31-32-31; Sector S3: 32-33-32; Sector S4: 00-01-00; Sector S5: 01-02-01; Sector S6: 02-03-02; 6) Calculate the duty cycle of voltage vector V0. d Duty cycle of V0 and V1 d 1. The calculation formula is: , where floor() is the floor function; 7) By switching the two redundant combinations of switch state 1 or the two redundant combinations of switch state 2 in phase b bridge arm, the voltages of floating capacitors C1 and C2 are balanced. 8) Based on the switching sequence, duty cycle, and capacitor voltage balance result, generate a pulse width modulation drive signal to control the conduction and cutoff of each insulated gate bipolar transistor, thereby achieving stable output of the inverter.

6. The modulation method according to claim 5, characterized in that, When sector S is S1, S2, or S3, phase a bridge arm remains in switch state 3, and the output voltage is + u dc / 2; When sector S is S4, S5, or S6, phase a bridge arm remains in switch state 0, and the output voltage is - u dc / 2, the operating frequency of the a-phase bridge arm is 50Hz.

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