Signal processing method and apparatus, device, and storage medium

Abstract

This application provides a signal processing method, apparatus, device, and storage medium, which can be applied to the field of signal processing technology. The method includes: determining the glitch probability of each candidate circuit unit based on the signal transmission conditions corresponding to each candidate circuit unit; determining a target circuit unit from multiple candidate circuit units based on the glitch probability of each candidate circuit unit; electrically connecting multiple suppression circuits to the target circuit unit to obtain multiple circuit combination units; determining the glitch probability of each circuit combination unit based on the signal transmission conditions corresponding to each circuit combination unit; determining multiple candidate suppression circuits from the multiple suppression circuits based on the glitch probability of each circuit combination unit; and determining a target suppression circuit from the multiple candidate suppression circuits based on the complexity of each candidate suppression circuit, so as to process the output signal of the target circuit unit through the target suppression circuit.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and more specifically to a signal processing method, apparatus, device, and storage medium. Background Technology

[0002] Signal glitches refer to brief, unexpected voltage pulses or logic jumps that occur in a circuit. They manifest as instantaneous erroneous changes in a signal between stable states and often lead to problems such as logic errors and system failures.

[0003] Most related technologies suppress signal glitches through fixed parameter design or circuit design, without considering the actual application scenarios and working conditions of the circuit, making it difficult to cope with the risk of sudden signal glitches. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a signal processing method, apparatus, device, and medium.

[0005] According to a first aspect of this application, a signal processing method is provided, applied to a circuit including multiple candidate circuit units. The method includes: determining the glitch probability of each candidate circuit unit based on the signal transmission conditions corresponding to each candidate circuit unit; determining a target circuit unit from the multiple candidate circuit units based on the glitch probability of each candidate circuit unit; electrically connecting multiple suppression circuits to the target circuit unit to obtain multiple circuit combination units, wherein the suppression circuits are used to perform glitch suppression processing on the output signal of the target circuit unit; determining the glitch probability of each circuit combination unit based on the signal transmission conditions corresponding to each circuit combination unit; determining multiple candidate suppression circuits from the multiple suppression circuits based on the glitch probability of each circuit combination unit; and determining a target suppression circuit from the multiple candidate suppression circuits based on the complexity of each candidate suppression circuit, so as to process the output signal of the target circuit unit through the target suppression circuit, wherein the complexity characterizes the circuit size of the corresponding candidate suppression circuit.

[0006] According to an embodiment of this application, a first difference between the reception time of the output signal of any candidate circuit unit and a reference time is determined; if the first difference is greater than a preset error threshold, the first difference is processed based on the deviation adjustment degree indicated by a preset time control parameter to obtain a first adjustment signal; and a delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the first adjustment signal.

[0007] According to an embodiment of this application, the time control parameters include a proportional gain coefficient, an integral gain coefficient, and a derivative gain coefficient. Processing the first difference based on the preset time control parameters to obtain a first adjustment signal includes: obtaining a first adjustment amount based on the proportional gain coefficient and the first difference, where the proportional gain coefficient indicates the amplification degree of the first difference; obtaining a second adjustment amount based on the integral gain coefficient and the first difference, where the integral gain coefficient indicates the degree of elimination of the accumulated deviation in the first difference; obtaining a third adjustment amount based on the derivative gain coefficient and the first difference, where the derivative gain coefficient indicates the degree of suppression of the changing trend of the first difference; and obtaining the first adjustment signal based on the first adjustment amount, the second adjustment amount, and the third adjustment amount.

[0008] According to an embodiment of this application, a second adjustment signal is obtained based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit; a delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the second adjustment signal.

[0009] According to an embodiment of this application, a second adjustment signal is obtained based on a second difference between the real-time temperature and a reference temperature of any candidate circuit unit and a third difference between the real-time voltage and a reference voltage of any candidate circuit unit. This includes: obtaining an initial adjustment signal based on the second difference, a temperature delay coefficient matched with the second difference, a third difference, a voltage delay coefficient matched with the third difference, and a temperature-voltage coupling coefficient matched with the second and third differences. The temperature delay coefficient indicates the degree of influence of temperature change on the arrival time of the output signal of any candidate circuit unit, the voltage delay coefficient indicates the degree of influence of voltage change on the arrival time of the output signal of any candidate circuit unit, and the temperature-voltage coupling coefficient indicates the degree of influence of temperature change and voltage change on the arrival time of the output signal of any candidate circuit unit. A second adjustment signal is obtained based on a temperature adaptive gain coefficient and the initial adjustment signal. The temperature adaptive gain coefficient characterizes the safety level of any candidate circuit unit at the real-time temperature.

[0010] According to an embodiment of this application, obtaining a second adjustment signal based on a temperature-adaptive gain coefficient and an initial adjustment signal includes: obtaining a temperature-adaptive gain coefficient based on a real-time temperature, a critical temperature, and a response steepness coefficient, wherein the response steepness coefficient indicates the intensity of change in the initial adjustment signal; and obtaining a second adjustment signal based on the product of the temperature-adaptive gain coefficient and the initial adjustment signal.

[0011] According to an embodiment of this application, a second adjustment signal is obtained based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit; a delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the first adjustment signal and the second adjustment signal.

[0012] According to a second aspect of this application, an apparatus for signal processing of a circuit is provided, applied to the circuit including a plurality of candidate circuit units. The apparatus includes: a prediction module for determining the probability of glitch occurrence of each candidate circuit unit based on the signal transmission conditions corresponding to each candidate circuit unit; a first determination module for determining a target circuit unit from the plurality of candidate circuit units based on the probability of glitch occurrence of each candidate circuit unit; a combination module for electrically connecting a plurality of suppression circuits to the target circuit unit to obtain a plurality of circuit combination units, wherein the suppression circuits are used to perform glitch suppression processing on the output signal of the target circuit unit; a second determination module for determining the probability of glitch occurrence of each circuit combination unit based on the signal transmission conditions corresponding to each circuit combination unit; a screening module for determining a plurality of candidate suppression circuits from the plurality of suppression circuits based on the probability of glitch occurrence of each circuit combination unit; and a suppression module for determining a target suppression circuit from the plurality of candidate suppression circuits based on the complexity of each candidate suppression circuit, so as to process the output signal of the target circuit unit through the target suppression circuit, wherein the complexity characterizes the circuit size of the corresponding candidate suppression circuit.

[0013] According to a third aspect of this application, an electronic device is provided, comprising: one or more processors; and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method described above.

[0014] According to a fourth aspect of this application, a computer-readable storage medium is also provided, on which a computer program or instructions are stored, wherein the computer program or instructions, when executed by a processor, implement the steps of the above-described method.

[0015] The signal processing method provided according to the embodiments of this application has at least the following advantages compared with related technologies:

[0016] The probability of glitches is predicted by utilizing signal transmission conditions. The probability of glitches is used to determine the target circuit unit that needs to be inserted into the suppression circuit. Then, based on the real-time operating status of the circuit, possible sudden signal glitches in the circuit are suppressed to improve the success rate of signal glitches suppression. Combining the probability of glitches and complexity, the target suppression circuit is selected for use. While reducing the probability of glitches, the complexity of the suppression circuit is minimized to avoid resource waste caused by circuit redundancy. Attached Figure Description

[0017] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0018] Figure 1 The diagram illustrates application scenarios of signal processing methods, apparatus, devices, and media according to embodiments of this application.

[0019] Figure 2 A flowchart illustrating a signal processing method according to an embodiment of this application is shown schematically.

[0020] Figure 3 A flowchart illustrating the acquisition of a first adjustment signal according to this application is shown schematically;

[0021] Figure 4 A detailed flowchart illustrating the acquisition of a first adjustment signal according to an embodiment of this application is shown schematically;

[0022] Figure 5 A detailed flowchart illustrating the acquisition of the second adjustment signal according to an embodiment of this application is shown schematically;

[0023] Figure 6 A schematic block diagram of a signal processing apparatus according to an embodiment of this application is shown.

[0024] Figure 7 A block diagram schematically illustrates an electronic device suitable for implementing a signal processing method according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0028] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0029] In circuits, signal glitches are a common problem that causes logic errors and system failures. To suppress signal glitches, related technologies employ optimization designs using methods such as redundancy term methods, Gray code encoding, and fixed delay matching.

[0030] Redundancy methods can refer to eliminating race conditions by adding spare logic gates or circuits using Karnaugh maps or Boolean algebra. Gray code encoding can refer to reducing glitches in multi-bit flip scenarios such as counters using unit transition encoding. Fixed delay matching can refer to inserting buffers in the critical path of the circuit to balance signal delays.

[0031] In the redundancy method, the number of spare logic gates or circuits inserted, as well as the preset compensation value in fixed delay matching, are fixed values ​​determined based on engineer experience. Fixed insertion numbers and compensation values ​​are insufficient to address the risk of sudden signal glitches in actual application scenarios and operating states, and are inadequate to offset dynamic timing deviations caused by temperature / voltage drift during circuit operation. Furthermore, to ensure effective glitch suppression, excessive insertion numbers lead to redundant design, increasing circuit footprint and power consumption. Gray code encoding is only applicable to sequential transition scenarios and is ineffective for asynchronous multipath signals, thus limiting its application scenarios.

[0032] To address at least one of the aforementioned problems, embodiments of this application provide a signal processing method. This method predicts the probability of glitches occurring in candidate circuit units based on signal transmission conditions, and then uses this probability to select target circuit units from the candidate units into which a suppression circuit needs to be inserted. The insertion of the suppression circuit is then implemented based on the actual operating state of the circuit, addressing potential and possibly sudden signal glitches. By combining the probability of glitches and complexity to determine the final target suppression circuit, the risk of signal glitches is suppressed while avoiding resource waste.

[0033] Figure 1 The diagram illustrates an application scenario of the signal processing method according to an embodiment of this application. For example... Figure 1As shown, application scenario 100 according to an embodiment of this application may include a processor 101 and a circuit 102. The processor 101 may be an electronic device such as a server or a personal computer. The circuit 102 may include a plurality of candidate circuit units and a delay compensation unit.

[0034] It should be noted that the signal processing method provided in this application embodiment can generally be executed by the processor 101. Correspondingly, the signal processing device provided in this application embodiment can generally be disposed in the processor 101. Then, a target circuit unit that needs to be processed for output signal is determined from a plurality of candidate circuit units in the circuit 102. Alternatively, a delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of the candidate circuit unit.

[0035] It should be understood that Figure 1 The number of processors 101 and circuits 102 shown is merely illustrative. Any number of processors 101 and circuits 102 can be used depending on implementation requirements.

[0036] Figure 2 A flowchart illustrating a signal processing method according to an embodiment of this application is shown schematically.

[0037] like Figure 2 As shown, the signal processing method 200 according to an embodiment of this application is applied to a circuit, and the method may include steps S210 to S260.

[0038] In step S210, the probability of glitch occurrence for each candidate circuit unit is obtained based on the signal transmission conditions corresponding to each candidate circuit unit.

[0039] According to embodiments of this application, multiple candidate circuit units can be components of a circuit.

[0040] Furthermore, based on the pre-trained prediction model, multiple signal transmission conditions are processed to obtain the probability of glitches occurring for each candidate circuit unit.

[0041] For example, the circuit can be a digital circuit. Candidate circuit units can include at least one of a logic node and a signal path in the digital circuit. A logic node can refer to a node in the circuit that has a defined logical state or function. A logical state can refer to the behavior of the node in the circuit, such as a stable state (high or low level), transient state, high impedance state, etc. A function can refer to the function that the node performs in the circuit, such as reset, enable, etc. Logic nodes include, for example, connection nodes in signal transmission, gate circuit input / output terminals, and data ports of memory units. A signal path can refer to the complete physical and logical path through which a signal is transmitted from a source (such as an input port, clock source, register) to a target (such as an output port, another register).

[0042] Signal transmission conditions may include at least one of the following: signal arrival time difference between candidate circuit units and critical competing paths, power supply voltage noise amplitude, and signal transition mode.

[0043] A critical contention path refers to a signal path that starts from the same input terminal as a candidate circuit cell and transmits the same signal to the same node. It has a timing competition relationship with the candidate circuit cell. The signal arrival time difference between a candidate circuit cell and the critical contention path refers to the time difference between their arrival at the same node, starting from the same input terminal. For example, the arrival time difference between different input signals of a multi-input logic gate.

[0044] There can be one or more critical contention paths. When there is only one critical contention path, the signal arrival time difference between a candidate circuit element and the critical contention path refers to the time difference between them starting from the same input terminal, transmitting the same signal, and arriving at the same node. When there are multiple critical contention paths, the signal arrival time difference between a candidate circuit element and the critical contention path refers to the minimum absolute value of multiple time differences among them, starting from the same input terminal, transmitting the same signal, and arriving at the same node.

[0045] Power supply voltage noise amplitude can characterize the voltage fluctuations of the power supply, which may cause signal propagation delays. For example, gate circuit delay is inversely proportional to the power supply voltage, and a decrease in power supply voltage will reduce the drive current, making the signal edges slower and exacerbating crosstalk and timing uncertainties.

[0046] Signal transition patterns refer to the way voltage changes over time during a signal transition from 0 to 1 or 1 to 0, i.e., the slope and shape of the voltage curve during the transition. This slope affects crosstalk, delay, power consumption, determines signal integrity, and influences the waveform quality of local signals.

[0047] The prediction model can be a logistic regression model, such as a single-layer perceptron. Before executing step S210, a training set is constructed using the collected signal transmission condition data of the digital circuit during operation or simulation to train the prediction model.

[0048] Based on this, the probability of glitches is predicted by utilizing the signal transmission conditions of the circuit in the actual operating environment, so that the prediction results can fully reflect the current operating conditions of the circuit and improve the accuracy of the prediction.

[0049] In step S220, the target circuit unit is determined from multiple candidate circuit units based on the probability of glitch occurrence of each candidate circuit unit.

[0050] For example, candidate circuit units with a glitch occurrence probability greater than a preset safety threshold are selected as target circuit units. Here, the number of target circuit units can be one or more.

[0051] In step S230, multiple suppression circuits are electrically connected to the target circuit unit respectively to obtain multiple circuit combination units.

[0052] According to embodiments of this application, a suppression circuit is used to suppress glitches in the output signal of a target circuit unit. Any suppression circuit may include at least one backup logic gate or backup circuit. The circuit combination unit includes the target circuit unit and the suppression circuit electrically connected to the target circuit unit.

[0053] For example, multiple backup logic gates or backup circuits are selected from a pre-configured circuit library, and at least one of the multiple backup logic gates or backup circuits is combined to obtain multiple suppression circuits. This provides multiple options for the subsequent screening of candidate suppression circuits.

[0054] Here, the electrical connection between the suppression circuit and the target circuit unit can refer to the connection in circuit simulation software.

[0055] In step S240, the probability of glitches occurring in each circuit combination unit is determined based on the signal transmission conditions corresponding to each circuit combination unit.

[0056] For example, based on the aforementioned prediction model, the signal transmission conditions corresponding to each circuit combination unit are processed to obtain the probability of glitch occurrence for each circuit combination unit.

[0057] When the suppression circuit and the target circuit unit are electrically connected in circuit simulation software, the signal transmission conditions can be obtained by simulating multiple circuit combination units in the software. Alternatively, during actual testing, the signal transmission conditions corresponding to each circuit combination unit can be collected sequentially by connecting the input terminals of multiple suppression circuits to the output terminals of the target circuit unit.

[0058] In step S250, multiple candidate suppression circuits are determined from multiple suppression circuits based on the glitch occurrence probability of each circuit combination unit.

[0059] For example, suppression circuits in circuit combination units with a glitch occurrence probability less than or equal to a preset safety threshold are selected as candidate suppression circuits to ensure that the suppression circuits used for further screening can reduce the glitch occurrence probability of the target circuit unit to less than or equal to the preset safety threshold.

[0060] Step S260: Based on the complexity of each candidate suppression circuit, a target suppression circuit is determined from multiple candidate suppression circuits, so as to process the output signal of the target circuit unit through the target suppression circuit.

[0061] According to embodiments of this application, complexity characterizes the circuit size of the corresponding candidate suppression circuit. For example, the number of logic gates and the area occupied by the candidate suppression circuit.

[0062] Taking the number of logic gates in the candidate suppression circuit as an example to illustrate the complexity, step S260 will be further explained. For example, for multiple candidate suppression circuits, the total number of logic gates contained in the multiple candidate suppression circuits is used as the complexity. The candidate suppression circuit with the lowest complexity is selected as the target suppression circuit for processing the output signal of the target circuit unit.

[0063] The output of the target circuit unit can be connected to the input of the target suppression circuit. The target suppression circuit, after being connected to the target circuit unit, can be used as a new component in the circuit.

[0064] In the case of multiple target circuit units, for each target circuit unit, steps S230 to S260 are executed sequentially until the target suppression circuits corresponding to each of the multiple target circuit units are obtained.

[0065] In the embodiments of this application, the probability of glitch occurrence is predicted using signal transmission conditions. The prediction process fully considers the actual operating conditions of the circuit, improving the accuracy of glitch probability prediction. The probability of glitch occurrence is used to determine the circuit units that require the insertion of suppression circuits. Combining the probability of glitch occurrence and complexity, the suppression circuit with the lowest complexity that meets the signal glitch suppression requirements is selected. This minimizes resource overhead and avoids resource waste while reducing the probability of glitch occurrence; it is applicable to digital circuits under different signal transmission conditions.

[0066] In some embodiments, determining the target suppression circuit from multiple candidate suppression circuits based on the complexity of each candidate suppression circuit may include: performing iterative optimization under preset constraints with the objective function of minimizing complexity to obtain the target suppression circuit.

[0067] For example, the objective function is expressed as:

[0068] ;

[0069] In the formula, X represents the decision variable vector, that is, the combination of backup logic gates or backup circuits in the candidate suppression circuit, X=( ), m represents the number of spare logic gates or spare circuits, Let represent a binary decision variable, indicating whether to choose the _____. A spare logic gate or spare circuit, if This indicates the selection to insert the j-th spare logic gate or spare circuit. This indicates that the j-th spare logic gate or spare circuit is not selected for insertion. Indicate complexity, Indicates the selection of the first The complexity (e.g., number, resource overhead) of a spare logic gate or spare circuit is also known as hardware cost. "Subject to" indicates a constraint. This indicates the probability of a glitches occurring in the target circuit unit after inserting a selected spare logic gate or spare circuit. This represents the safety threshold. `min` indicates minimization.

[0070] If the goal is solely the number of spare logic gates or spare circuits, then In other words, the objective function simplifies to minimizing the number of spare logic gates or spare circuits inserted. .

[0071] Based on this, the selection of the target suppression circuit is transformed into a target optimization problem, thereby further improving the screening efficiency.

[0072] For example, the probability of burr occurrence It can be represented as:

[0073] ;

[0074] In the formula, This represents the Sigmoid activation function, which maps the result of the linear weighted summation within the parentheses to the probability interval (0,1). The weights represent the weights of the i-th signal transmission condition. These weights are learned through a large amount of data during the model training phase and reflect the importance of each signal transmission condition in predicting the probability of glitch occurrence. This represents the i-th feature extraction function, which can extract or calculate feature values ​​related to the probability of glitch occurrence from signal transmission conditions; △t path This represents the signal arrival time difference between the target circuit unit and the critical competitive path, and the unit can be seconds or nanoseconds. This indicates the power supply voltage noise amplitude, measured in volts, and can be obtained through measurement. This represents a vector or code that describes the transition pattern of a signal; for example, it represents a binary bitmask with multiple bit flips.

[0075] Here, the probability of punctures occurring ranges from 0 (no risk) to 1 (extremely high risk).

[0076] Figure 3 A flowchart illustrating the acquisition of a first adjustment signal according to this application is shown schematically.

[0077] Signal path delay error refers to the deviation between the actual time a signal takes to travel from the transmitter to the receiver in the signal path and the expected or theoretically designed time. This deviation can cause the signal to fail to arrive at the receiver at the correct time, resulting in signal glitches. Circuit aging effects, signal integrity issues, or manufacturing process variations can all contribute to signal path delay error.

[0078] To fundamentally suppress signal path delay errors, the following steps will be taken in conjunction with... Figure 3 The method for compensating for signal path delay errors is further explained. In some embodiments, the method further includes:

[0079] First, determine a first difference 302 between the receiving time 304 of the output signal of any candidate circuit unit and the reference time 301 of the output signal of any candidate circuit unit.

[0080] According to embodiments of this application, any candidate circuit unit can refer to any signal path in the circuit. The reception time 304 of the output signal of any candidate circuit unit can refer to the actual arrival time of the signal at the output terminal in any signal path. The reference time 301 of the output signal of any candidate circuit unit can refer to the reference arrival time of the signal at the output terminal in any signal path, and can be a preset value or an empirical value.

[0081] For example, the first difference 302 is represented as:

[0082] ;

[0083] In the formula, This indicates the first difference is 302. Indicates reference arrival time. Indicates the actual arrival time.

[0084] Then, if the first difference is greater than the preset error threshold, the first difference is processed based on the degree of deviation adjustment indicated by the preset time control parameter to obtain the first adjustment signal 303.

[0085] For example, the time control parameters may include the proportional gain coefficient, the integral gain coefficient, and the derivative gain coefficient. For instance, the time control parameters may be preset values ​​or empirical values ​​in a proportional-integral-derivative (PID) control algorithm.

[0086] Then, the delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the first adjustment signal.

[0087] According to an embodiment of this application, a delay compensation unit connected to any candidate circuit unit can compensate the output signal of any candidate circuit unit based on a time adjustment amount indicated by a first adjustment signal.

[0088] For example, the delay compensation unit may include at least one of a buffer chain or a voltage-controlled delay line. A buffer chain can consist of multiple buffers connected in series, allowing the selection of the number of buffers to adjust the delay as needed; it is suitable for digital and discrete delay adjustments, with a fixed adjustment step size, simple structure, and easy integration. A voltage-controlled delay line can continuously change the delay time by adjusting the control voltage, suitable for analog and continuous delay adjustments, with fast response speed and high adjustment accuracy, suitable for high-frequency or high-precision scenarios.

[0089] For example, the first compensation signal is transmitted to the control interface of the delay compensation unit to control the delay compensation unit to adjust the number of connected buffers or adjust the control voltage based on the time adjustment amount indicated by the first compensation signal to compensate for the signal path delay error.

[0090] Based on this, time delay compensation is performed by using the real-time difference between the receiving time of the output signal and the reference time to reduce delay and fundamentally prevent the generation of signal glitches.

[0091] Figure 4 A detailed flowchart illustrating the acquisition of a first adjustment signal according to an embodiment of this application is shown schematically.

[0092] Next, combined Figure 4 The detailed process of obtaining the first adjustment signal is further explained below. In some embodiments, processing the first difference based on preset time control parameters to obtain the first adjustment signal includes the following steps:

[0093] First, based on the proportional gain coefficient 401 and the first difference, the first adjustment amount 402 is obtained.

[0094] According to an embodiment of this application, the proportional gain coefficient 401 indicates the degree of amplification for the first difference.

[0095] For example, the first adjustment amount 402 is represented as:

[0096] ;

[0097] In the formula, This indicates the first adjustment amount is 402. This indicates a proportional gain coefficient of 401. It can determine the strength of the proportional-integral-derivative controller's response to the current deviation. The larger the value, the stronger and faster the corrective action on the current deviation, but... An excessively large value may cause system oscillation.

[0098] Secondly, based on the integral gain coefficient 403 and the first difference, the second adjustment amount 404 is obtained.

[0099] According to an embodiment of this application, the integral gain coefficient 403 indicates the degree of elimination of the first difference deviation.

[0100] For example, the second adjustment amount 404 is represented as:

[0101] ;

[0102] In the formula, This indicates the second adjustment amount is 404. Represents the integral gain coefficient. Indicates time.

[0103] Here, The strength of the proportional-integral-derivative (PID) controller's response to accumulated errors over a period of time is determined. The first difference between a certain time in the past and the current time. The integral (cumulative sum).

[0104] Then, based on the difference between the differential gain coefficient 405 and the first value, the third adjustment amount 406 is obtained.

[0105] According to an embodiment of this application, the differential gain coefficient 405 indicates the degree of suppression against the first difference change trend.

[0106] For example, the third adjustment amount 406 is represented as:

[0107] ;

[0108] In the formula, This indicates the third adjustment amount is 406. This represents the differential gain coefficient.

[0109] Here, The strength of the proportional-integral-derivative (PID) controller's response to changes in error trends is determined. Indicates the first difference The rate of change over time (i.e., the speed at which the error changes). The term has predictive properties, can suppress the oscillating trend of the system, and improve stability. Excessive size may amplify the effects of noise.

[0110] Then, based on the first adjustment amount 402, the second adjustment amount 404 and the third adjustment amount 406, the first adjustment signal is obtained.

[0111] For example, the first adjustment signal Represented as:

[0112] .

[0113] In the embodiments of this application, the first difference is processed using the proportional gain coefficient, integral gain coefficient, and differential gain coefficient, which can comprehensively consider the error change rate, accumulation degree, and actual value, and output the first adjustment signal quickly, smoothly, and accurately.

[0114] Temperature drift and voltage fluctuations can also cause signal path delay errors in circuits. Increased temperature reduces carrier mobility and increases interconnect resistance in the circuit. Decreased voltage directly weakens transistor driving capability. More complexly, temperature and voltage are coupled; for example, the effect of voltage fluctuations on delay is amplified at high temperatures.

[0115] In related technologies, a fixed compensation coefficient is used to compensate for signal path delay errors caused by the above reasons. However, in application scenarios such as automotive electronics, servers, and 5G base stations (dynamic voltage regulation), the compensation coefficient cannot adapt to the nonlinear changes between temperature and / or voltage and signal path delay errors, affecting the compensation effect.

[0116] To accurately compensate for signal path delay errors caused by environmental changes, the improved signal path delay error compensation method will be further described below. In some embodiments, the method further includes:

[0117] First, a second adjustment signal is obtained based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit.

[0118] According to embodiments of this application, the second difference characterizes the degree of deviation between the real-time temperature of any candidate circuit unit and the reference temperature. The third difference characterizes the degree of deviation between the real-time voltage of any candidate circuit unit and the reference voltage.

[0119] For example, firstly, the second difference between the real-time temperature and the reference temperature of any candidate circuit unit and the third difference between the real-time voltage and the reference voltage of any candidate circuit unit are substituted into the environment-delay mapping model characterizing the multiple regression relationship between the initial adjustment signal and the second and third differences to obtain the initial adjustment signal. Then, the second adjustment signal is obtained based on the product of the temperature adaptive gain coefficient and the initial adjustment signal.

[0120] Then, the delay compensation unit connected to any candidate circuit unit compensates the output signal of any candidate circuit unit based on the time adjustment amount indicated by the second adjustment signal.

[0121] For example, the first compensation signal is transmitted to the control interface of the delay compensation unit to control the delay compensation unit to adjust the number of connected buffers or adjust the control voltage based on the time adjustment amount indicated by the second compensation signal to compensate for the signal path delay error.

[0122] In the embodiments of this application, the real-time environmental information of any candidate circuit unit is used to determine its corresponding second adjustment signal for environmental compensation, thereby accurately compensating for the delay error caused by environmental changes and solving the nonlinear distortion problem under extreme operating conditions.

[0123] Figure 5 A detailed flowchart illustrating the acquisition of the second adjustment signal according to an embodiment of this application is shown schematically.

[0124] Next, combined Figure 5 The detailed acquisition process of the second adjustment signal is further described below. In some embodiments, obtaining the second adjustment signal based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit may include the following steps:

[0125] First, an initial adjustment signal 506 is obtained based on the second difference 501, the temperature delay coefficient 503 matched with the second difference 501, the third difference 502, the voltage delay coefficient 504 matched with the third difference 502, and the temperature-voltage coupling coefficient 505 matched with the second difference 501 and the third difference 502.

[0126] According to embodiments of this application, the temperature delay factor 503 indicates the degree of influence of temperature change on the arrival time of the output signal of any candidate circuit unit. The voltage delay factor 504 indicates the degree of influence of voltage change on the arrival time of the output signal of any candidate circuit unit. The temperature-voltage coupling factor 505 indicates the degree of influence of both temperature change and voltage change on the arrival time of the output signal of any candidate circuit unit.

[0127] For example, the initial adjustment signal 506 is represented as:

[0128] ;

[0129] In the formula, This indicates the initial adjustment signal is 506. This represents the temperature retardation factor of 503, which can be expressed in ns / ℃ and can be a constant. It represents the real-time temperature, in °C, and can be detected in real time by a temperature sensor. This represents the reference temperature and can be a constant. This represents a voltage delay factor of 504, which can be expressed in ns / V and can be a constant. This represents the real-time voltage, measured in volts (V), and can be monitored in real time using a voltage sensor. The reference voltage can be a constant. This represents the temperature-pressure coupling coefficient of 505, which can be expressed in ns / ℃·V and can be a constant.

[0130] It is understandable that the above formula is the aforementioned environment-delay mapping model. The temperature delay coefficient 503 can represent the linear effect of a 1°C change in temperature on the signal path delay. The voltage delay coefficient 504 can represent the linear effect of a 1V change in voltage on the signal path delay. The temperature-voltage coupling coefficient 505 can represent the nonlinear effect of the interaction between temperature and voltage on the delay, such as the coupling effect between high temperature and low voltage.

[0131] The aforementioned coefficients can be obtained through multiple regression calculations using experimental data from the digital circuit testing phase. Here, the digital circuit testing phase can refer to the testing phase of chips with deployed digital circuits.

[0132] Based on this, the impact of temperature and voltage changes on the circuit is quantified, thereby improving the accuracy of compensation.

[0133] Then, based on the product of the temperature adaptive gain coefficient 507 and the initial adjustment signal 506, the second adjustment signal 508 is obtained.

[0134] According to an embodiment of this application, the temperature adaptive gain coefficient 507 characterizes the safety level of any candidate circuit unit at the real-time temperature, and the compensation intensity of the output signal is controlled by the temperature adaptive gain coefficient 507.

[0135] In the embodiments of this application, the second adjustment signal is calculated by using the temperature adaptive gain coefficient representing the real-time operating conditions and the degree of influence of voltage and temperature changes on signal transmission, which can improve the calculation accuracy of the second adjustment signal.

[0136] In some embodiments, obtaining the second adjustment signal 508 based on the temperature adaptive gain coefficient 507 and the initial adjustment signal 506 may include the following steps:

[0137] First, based on the real-time temperature, critical temperature, and response steepness coefficient, the temperature adaptive gain coefficient 507 is obtained.

[0138] According to an embodiment of this application, the response steepness coefficient indicates the intensity of the change in the initial adjustment signal.

[0139] For example, the temperature adaptive gain coefficient 507 is expressed as:

[0140] ;

[0141] In the formula, This indicates a temperature-adaptive gain coefficient of 507. This represents the natural exponential function with base e. This indicates the critical temperature, and the unit can be °C. It can be provided by the manufacturer. This represents the steepness coefficient of the response, which controls the steepness of the formula, i.e. how quickly the compensation intensity changes with temperature variations; The larger the value, the steeper the change of the function near the critical temperature, and the more drastic the change in the compensation strength; The value is usually chosen between 0.1 and 0.5 depending on the actual needs.

[0142] Based on this, a temperature-adaptive gain coefficient is calculated using real-time temperature and response steepness coefficient. When the temperature approaches the process limit, the compensation intensity is automatically increased, which can improve the calculation accuracy of the second adjustment signal.

[0143] Then, based on the product of the temperature adaptive gain coefficient 507 and the initial adjustment signal 506, the second adjustment signal 503 is obtained.

[0144] For example, the second adjustment signal 503 is represented as:

[0145] ;

[0146] In the formula, This indicates the second adjustment signal.

[0147] In some embodiments, the method further includes: obtaining a second adjustment signal based on a second difference between the real-time temperature of any candidate circuit unit and a reference temperature, and a third difference between the real-time voltage of any candidate circuit unit and a reference voltage. A delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on a time adjustment amount indicated by the first and second adjustment signals.

[0148] For example, the time adjustment amount is based on the indication of the first adjustment signal and the second adjustment signal. Represented as:

[0149] .

[0150] In the embodiments of this application, the first compensation signal and the second compensation signal are superimposed and then subjected to delay compensation, which can compensate for signal path timing errors caused by process deviations, aging effects or signal integrity problems in real time and respond quickly to sudden environmental changes; at the same time, it compensates for delay errors caused by process deviations and environmental changes and suppresses signal glitches.

[0151] Based on the above signal processing method, embodiments of this application also provide a signal processing apparatus. The following will be combined with... Figure 6The device is described in detail.

[0152] Figure 6 A schematic block diagram of a signal processing apparatus according to an embodiment of this application is shown.

[0153] like Figure 6 As shown, the signal processing device 600 of this embodiment is applied to a circuit, which includes multiple candidate circuit units. The device includes a prediction module 610, a first determination module 620, a combination module 630, a second determination module 640, a screening module 650, and a suppression module 660.

[0154] The prediction module 610 is used to determine the probability of glitches occurring in each candidate circuit unit based on the signal transmission conditions corresponding to each candidate circuit unit. In one embodiment, the prediction module 610 can be used to perform step S210 described above, which will not be repeated here.

[0155] The first determining module 620 is used to determine the target circuit unit from multiple candidate circuit units based on the probability of glitch occurrence of each candidate circuit unit. In one embodiment, the first determining module 620 can be used to perform step S220 described above, which will not be repeated here.

[0156] The combination module 630 is used to electrically connect multiple suppression circuits to the target circuit unit to obtain multiple circuit combination units. The suppression circuits are used to perform glitch suppression processing on the output signal of the target circuit unit. In one embodiment, the combination module 630 can be used to perform step S230 described above, which will not be repeated here.

[0157] The second determining module 640 is used to determine the probability of glitch occurrence for each circuit combination unit based on the signal transmission conditions corresponding to each circuit combination unit. In one embodiment, the second determining module 640 can be used to execute step S240 described above, which will not be repeated here.

[0158] The screening module 650 is used to determine multiple candidate suppression circuits from multiple suppression circuits based on the glitch occurrence probability of each circuit combination unit. In one embodiment, the screening module 650 can be used to perform step S250 described above, which will not be repeated here.

[0159] The suppression module 660 is used to determine a target suppression circuit from multiple candidate suppression circuits based on the complexity of each candidate suppression circuit, so as to process the output signal of the target circuit unit through the target suppression circuit. The complexity characterizes the circuit size of the corresponding candidate suppression circuit. In one embodiment, the suppression module 660 can be used to perform step S260 described above, which will not be repeated here.

[0160] According to an embodiment of this application, the device further includes a first compensation module, which is used to determine a first difference between the reception time of the output signal of any candidate circuit unit and a reference time; when the first difference is greater than a preset error threshold, the first difference is processed based on the deviation adjustment degree indicated by a preset time control parameter to obtain a first adjustment signal; and the delay compensation unit connected to any candidate circuit unit is controlled to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the first adjustment signal.

[0161] According to an embodiment of this application, the first compensation module includes a processing unit, which is used to obtain a first adjustment amount based on a proportional gain coefficient and a first difference, wherein the proportional gain coefficient indicates the amplification degree of the first difference; obtain a second adjustment amount based on an integral gain coefficient and the first difference, wherein the integral gain coefficient indicates the degree of elimination of the cumulative deviation in the first difference; obtain a third adjustment amount based on a differential gain coefficient and the first difference, wherein the differential gain coefficient indicates the degree of suppression of the changing trend of the first difference; and obtain a first adjustment signal based on the first adjustment amount, the second adjustment amount, and the third adjustment amount.

[0162] According to an embodiment of this application, the device further includes a second compensation module, which is used to obtain a second adjustment signal based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit; and to control a delay compensation unit connected to any candidate circuit unit to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the second adjustment signal.

[0163] According to an embodiment of this application, the second compensation module includes an acquisition unit. The acquisition unit is used to obtain an initial adjustment signal based on a second difference, a temperature delay coefficient matching the second difference, a third difference, a voltage delay coefficient matching the third difference, and a temperature-voltage coupling coefficient matching the second and third differences. The temperature delay coefficient indicates the degree of influence of temperature change on the arrival time of the output signal of any candidate circuit unit, the voltage delay coefficient indicates the degree of influence of voltage change on the arrival time of the output signal of any candidate circuit unit, and the temperature-voltage coupling coefficient indicates the degree of influence of temperature change and voltage change on the arrival time of the output signal of any candidate circuit unit. Based on the temperature adaptive gain coefficient and the initial adjustment signal, a second adjustment signal is obtained. The temperature adaptive gain coefficient characterizes the safety level of the chip at the real-time temperature.

[0164] According to an embodiment of this application, the acquisition unit is specifically used to obtain a temperature adaptive gain coefficient based on the real-time temperature, the critical temperature, and the response steepness coefficient, wherein the response steepness coefficient indicates the intensity of the change in the initial adjustment signal; and to obtain a second adjustment signal based on the product of the temperature adaptive gain coefficient and the initial adjustment signal.

[0165] According to an embodiment of this application, the device further includes a third acquisition module, which is used to obtain a second adjustment signal based on a second difference between the real-time temperature and the reference temperature of any candidate circuit unit and a third difference between the real-time voltage and the reference voltage of any candidate circuit unit; and to control a delay compensation unit connected to any candidate circuit unit to compensate the output signal of any candidate circuit unit based on the time adjustment amount indicated by the first adjustment signal and the second adjustment signal.

[0166] According to embodiments of this application, any multiple modules among the prediction module 610, the first determination module 620, the combination module 630, the second determination module 640, the screening module 650, and the suppression module 660 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this application, at least one of the prediction module 610, the first determination module 620, the combination module 630, the second determination module 640, the screening module 650, and the suppression module 660 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array, a programmable logic array, a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit, or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in any one of the three implementation methods of software, hardware, and firmware, or in a suitable combination of any of these. Alternatively, at least one of the prediction module 610, the first determination module 620, the combination module 630, the second determination module 640, the screening module 650, and the suppression module 660 may be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0167] Figure 7 A block diagram schematically illustrates an electronic device suitable for implementing a signal processing method according to an embodiment of this application.

[0168] like Figure 7 As shown, an electronic device 700 according to an embodiment of this application includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory 702 or a program loaded from a storage portion 708 into a random access memory 703. The processor 701 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a dedicated microprocessor. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for executing different steps of the method flow according to an embodiment of this application.

[0169] Random access memory 703 stores various programs and data required for the operation of electronic device 700. Processor 701, read-only memory 702, and random access memory 703 are interconnected via bus 704. Processor 701 executes various steps of the method flow according to embodiments of this application by executing programs in read-only memory 702 and / or random access memory 703. It should be noted that the programs may also be stored in one or more memories other than read-only memory 702 and random access memory 703. Processor 701 may also execute various steps of the method flow according to embodiments of this application by executing programs stored in said one or more memories.

[0170] According to embodiments of this application, the electronic device 700 may further include an input / output interface 705, which is also connected to a bus 704. The electronic device 700 may also include one or more of the following components connected to the input / output interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube, liquid crystal display, etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card, such as a local area network card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the input / output interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0171] Embodiments of this application also provide a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0172] According to embodiments of this application, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including but not limited to: portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this application, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this application, the computer-readable storage medium may include the read-only memory 702, and / or random access memory 703, and / or one or more memories other than read-only memory 702 and random access memory 703 described above.

[0173] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 709, and / or installed from a removable medium 711. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0174] In embodiments of this application, the computer program can be downloaded and installed from a network via communication section 709, and / or installed from removable medium 711. When the computer program is executed by processor 701, it performs the functions defined in the system of embodiments of this application. According to embodiments of this application, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0175] According to embodiments of this application, program code for executing the computer programs provided in the embodiments of this application can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0176] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer programs according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0177] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. A signal processing method, characterized by, Applied to a circuit, the circuit including multiple candidate circuit units, the method includes: Based on the signal transmission conditions corresponding to each candidate circuit unit, the probability of glitch occurrence for each candidate circuit unit is determined. Based on the glitch occurrence probability of each candidate circuit unit, the target circuit unit is determined from the plurality of candidate circuit units; Multiple suppression circuits are electrically connected to the target circuit unit to obtain multiple circuit combination units. The suppression circuits are used to perform glitch suppression processing on the output signal of the target circuit unit. Based on the signal transmission conditions corresponding to each of the circuit combination units, the probability of glitch occurrence for each of the circuit combination units is determined. Multiple candidate suppression circuits are determined from the plurality of suppression circuits based on the glitch occurrence probability of each of the circuit combination units; Based on the complexity of each of the candidate suppression circuits, a target suppression circuit is determined from the plurality of candidate suppression circuits to process the output signal of the target circuit unit through the target suppression circuit, wherein the complexity characterizes the circuit size of the corresponding candidate suppression circuit.

2. The signal processing method of claim 1, wherein, The method further includes: Determine the first difference between the reception time of the output signal of any candidate circuit unit and the reference time; If the first difference is greater than a preset error threshold, the first difference is processed based on the degree of deviation adjustment indicated by a preset time control parameter to obtain a first adjustment signal. The delay compensation unit connected to any of the candidate circuit units is controlled to compensate the output signal of any of the candidate circuit units based on the time adjustment amount indicated by the first adjustment signal.

3. The signal processing method according to claim 2, characterized in that, The time control parameters include a proportional gain coefficient, an integral gain coefficient, and a derivative gain coefficient. The process of processing the first difference based on the preset time control parameters to obtain the first adjustment signal includes: Based on the proportional gain coefficient and the first difference, a first adjustment amount is obtained, wherein the proportional gain coefficient indicates the degree of amplification for the first difference; Based on the integral gain coefficient and the first difference, a second adjustment amount is obtained, wherein the integral gain coefficient indicates the degree of elimination of the cumulative deviation in the first difference; Based on the differential gain coefficient and the first difference, a third adjustment amount is obtained, wherein the differential gain coefficient indicates the degree of suppression of the changing trend of the first difference; A first adjustment signal is obtained based on the first adjustment amount, the second adjustment amount, and the third adjustment amount.

4. The signal processing method according to claim 1, characterized in that, The method further includes: A second adjustment signal is obtained based on the second difference between the real-time temperature and the reference temperature of any candidate circuit unit and the third difference between the real-time voltage and the reference voltage of any candidate circuit unit. The delay compensation unit connected to any of the candidate circuit units compensates for the output signal of any of the candidate circuit units based on the time adjustment amount indicated by the second adjustment signal.

5. The signal processing method according to claim 4, characterized in that, The second adjustment signal is obtained based on the second difference between the real-time temperature and the reference temperature of any candidate circuit unit and the third difference between the real-time voltage and the reference voltage of any candidate circuit unit, including: An initial adjustment signal is obtained based on the second difference, a temperature delay coefficient matching the second difference, the third difference, a voltage delay coefficient matching the third difference, and a temperature-voltage coupling coefficient matching the second difference and the third difference. The temperature delay coefficient indicates the degree of influence of temperature change on the arrival time of the output signal of any candidate circuit unit, the voltage delay coefficient indicates the degree of influence of voltage change on the arrival time of the output signal of any candidate circuit unit, and the temperature-voltage coupling coefficient indicates the degree of influence of temperature change and voltage change on the arrival time of the output signal of any candidate circuit unit. The second adjustment signal is obtained based on the temperature-adaptive gain coefficient and the initial adjustment signal, wherein the temperature-adaptive gain coefficient characterizes the safety level of any candidate circuit unit at the real-time temperature.

6. The signal processing method according to claim 5, characterized in that, The process of obtaining the second adjustment signal based on the temperature adaptive gain coefficient and the initial adjustment signal includes: Based on the real-time temperature, critical temperature, and response steepness coefficient, the temperature adaptive gain coefficient is obtained, wherein the response steepness coefficient indicates the intensity of change in the initial adjustment signal; The second adjustment signal is obtained by multiplying the temperature adaptive gain coefficient and the initial adjustment signal.

7. The signal processing method according to claim 2, characterized in that, The method further includes: A second adjustment signal is obtained based on the second difference between the real-time temperature and the reference temperature of any candidate circuit unit and the third difference between the real-time voltage and the reference voltage of any candidate circuit unit. The delay compensation unit connected to any of the candidate circuit units compensates for the output signal of any of the candidate circuit units based on the time adjustment amount indicated by the first adjustment signal and the second adjustment signal.

8. A signal processing apparatus, characterized in that, Applied to a circuit, the circuit including a plurality of candidate circuit units, the device includes: The prediction module is used to determine the probability of glitches occurring in each of the candidate circuit units based on the signal transmission conditions corresponding to each candidate circuit unit. The first determining module is used to determine the target circuit unit from the plurality of candidate circuit units based on the probability of glitch occurrence of each candidate circuit unit. A combination module is used to electrically connect multiple suppression circuits to the target circuit unit to obtain multiple circuit combination units. The suppression circuit is used to perform glitch suppression processing on the output signal of the target circuit unit. The second determining module is used to determine the probability of glitch occurrence of each circuit combination unit based on the signal transmission conditions corresponding to each circuit combination unit. A screening module is used to determine multiple candidate suppression circuits from the multiple suppression circuits based on the glitch occurrence probability of each of the circuit combination units; A suppression module is used to determine a target suppression circuit from the plurality of candidate suppression circuits based on the complexity of each candidate suppression circuit, so as to process the output signal of the target circuit unit through the target suppression circuit, wherein the complexity characterizes the circuit size of the corresponding candidate suppression circuit.

9. An electronic device, comprising: One or more processors; Memory, used to store one or more computer programs. The characteristic feature is that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the steps of the method according to any one of claims 1 to 7.

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