Power-on reset circuit for low battery voltage

Abstract

An integrated circuit includes a power-on reset circuit that activates other portions of the integrated circuit based on an external power supply voltage provided at a power supply pin of the integrated circuit. The power-on reset circuit includes a fine power-on reset detector and a low-dropout regulator. The fine power-on reset detector is configured to compare the external power supply voltage with a bandgap reference voltage generated by a bandgap module of the integrated circuit to detect when the external power supply voltage rises above a power-on reset threshold voltage, thereby resetting the integrated circuit upon power-on. The low-dropout regulator provides an intermediate power supply voltage to an internal module of the integrated circuit that is susceptible to damage from a higher damage voltage, which is lower than the maximum voltage of the external power supply at the power supply pin.

Description

Technical Field

[0001] The present invention relates to an integrated circuit with a power-on reset circuit that activates other parts of the integrated circuit based on an external power supply voltage provided at the power supply pin of the integrated circuit. Background Technology

[0002] In today's world, many products, especially those in the Internet of Things (IoT) field, are powered by rechargeable batteries. As device sizes shrink, battery voltages also decrease; in many products, button cells with voltages as low as 2.7V are common. Meanwhile, charging the battery via a standard USB port is mandatory. A typical USB port operates at 5V. Therefore, the operating voltages required for the integrated circuits in such products must span a wide range. The minimum voltage of the external battery powering the product is set by the minimum supply voltage Vbat,min required to activate the product's integrated circuits, and the maximum supply voltage Vbat,max is set by the maximum voltage of the USB port.

[0003] Inside an integrated circuit, the module responsible for activation is called the power-on reset circuit. Its threshold voltage, Vpor,thld, determines the battery voltage at which the system starts up or remains off. Due to variations in manufacturing processes and temperature, this threshold voltage also varies by a certain amount, ∆Vpor,thld. For the main analog modules of the integrated circuit to operate correctly, a minimum intermediate power supply voltage, AVDD,min, is required. Therefore, as... Figure 1 As shown in (A), AVDD,min and ∆Vpor,thld together determine the minimum power supply voltage Vbat,min for the integrated circuit to function properly. The maximum power supply voltage Vbat,max is provided by the 5V from the USB during charging. If the internal modules of the integrated circuit are directly connected to the external power supply voltage of the battery, the maximum intermediate power supply voltage AVDD,max is equal to the maximum power supply voltage Vbat,max, and all transistors must be able to withstand this voltage.

[0004] In standard deep submicron processes (e.g., <130nm technology), only dedicated, bulky, and typically degraded high-voltage HV-MOS transistors can be directly connected to a 5V USB power supply. Therefore, circuit design using these transistors is challenging, and most analog modules are implemented using so-called IO-MOS transistors with a maximum withstand voltage of 3.6V. Consequently, in these processes, the analog intermediate supply voltage AVDD is typically generated internally by a low-dropout regulator, which requires a desired voltage Vldo between its input and output to provide the intermediate supply voltage AVDD. For the minimum operating voltage of such integrated circuits, the required voltage Vldo, added to the minimum intermediate supply voltage AVDD,min and the threshold voltage change ∆Vpor,thld, increases the minimum supply voltage Vbat,min, as shown below. Figure 1 As shown in (B).

[0005] The following example illustrates the problems with existing power-on reset circuits: AVDD,min=2.25V (=2.5V-10%), Vldo,max=0.25V, ∆Vpor,thld=0.5V, then Vbat,min=3V.

[0006] For lower minimum power supply voltages Vbat,min, the minimum analog power supply voltage AVDD,min cannot be maintained, and the functionality of the analog module cannot be guaranteed.

[0007] To reduce the minimum supply voltage Vbat,min, enabling integrated circuits to operate with an external small battery at a given minimum analog supply voltage AVDD,min, the following methods can currently be used:

[0008] • By adopting a larger process node and directly connecting the analog module to the external power supply voltage Vbat, the low-dropout regulator can be eliminated, thus avoiding the maximum required voltage Vldo,max between the input and output of the low-dropout regulator. However, this contradicts the requirement for high integration density.

[0009] • Reduce the threshold voltage change ∆Vpor,thld.

[0010] The following challenging requirements make designing a power-on reset circuit with low threshold voltage variation ∆Vpor,thld quite difficult:

[0011] • Low current consumption: The power-on reset circuit must remain operational even when the battery voltage is below the minimum supply voltage Vbat,min. Therefore, its current consumption directly affects the cutoff current of the integrated circuit and related battery life.

[0012] • Low threshold voltage variation ∆Vpor,thld requires any type of precise reference (e.g., a bandgap reference). A simple power-on reset circuit essentially uses the transistor's threshold voltage (MOS threshold voltage) as a reference, but this voltage varies significantly with process and temperature.

[0013] • Because the power-on reset circuit detects the external battery power supply of the integrated circuit, it must withstand voltages up to 5V from the USB. In deep submicron processes, this requires the use of high-voltage HV-MOS transistors, making it impossible to employ complex circuitry to achieve low threshold variation ∆Vpor,thld (e.g., a bandgap reference directly connected to the external power supply voltage Vbat).

[0014] Therefore, existing implementations require trade-offs between parameters such as cutoff current consumption, minimum battery voltage for activation, and the availability of MOS devices in the target technology. For example, in technologies supporting standard MOS transistors at 5V (e.g., >130nm processes), a bandgap reference can be designed that is directly powered by a battery and has low current consumption in the microampere range. Thus, the power-on reset circuit can obtain a precise reference to limit the low threshold voltage variation ∆Vpor,thld.

[0015] Similarly, in deep submicron technologies where standard MOS devices supporting 5V are not available, the standard approach is to use high-voltage HV-MOS transistors in a diode configuration to implement a simple, low-current, directly battery-powered power-on reset circuit. This topology uses the transistor's threshold voltage as a reference, but this reference is highly susceptible to temperature and process variations. This results in a large threshold voltage variation ∆Vpor,thld, which in turn increases the minimum power supply voltage Vbat,min required for activation.

[0016] Similarly, in deep submicron technology, a precise bandgap reference can be achieved using a 3.6V IO-MOS transistor with microamp-level current consumption, powered by an internal low-dropout regulator. As mentioned above, power generation requires a certain desired voltage Vldo between its input and output, which again limits the minimum power supply voltage Vbat,min required to activate the integrated circuit. Summary of the Invention

[0017] The purpose of this invention is to provide an integrated circuit with a power-on reset circuit that has precise threshold detection capability to achieve a low minimum operating voltage, especially suitable for (but not limited to) deep submicron processes.

[0018] This objective is achieved by the integrated circuit described in claim 1.

[0019] The power-on reset circuit of the present invention is configured such that, in the first switching mode, before power-on reset, during the external power supply voltage boosting process, the internal module and the bandgap module are connected to the power supply pins, and they are disconnected from the intermediate power supply voltage. For example... Figure 1 As shown in (A), this direct connection between the internal modules and the external power supply voltage achieves a low minimum power supply voltage Vbat,min. Furthermore, the switch is configured such that, in a second switching mode, after power-on reset, the internal modules are connected to the intermediate power supply voltage and disconnected from the power supply pins. This ensures the internal modules are protected from excessively high voltages that could damage them, and, due to the precise bandgap reference voltage of the bandgap modules powered by the intermediate power supply voltage, the threshold voltage variation ∆Vpor,thld is minimized.

[0020] In a preferred embodiment, the power-on reset circuit includes a coarse power-on reset detector (POR detector) constructed using a high-voltage-supporting MOS transistor. This detector compares the external power supply voltage Vbat with the MOS threshold voltage Vpor_coarse,thld and provides a coarse power-on reset signal when the external power supply voltage Vbat exceeds the MOS threshold voltage Vpor_coarse,thld during the boost process. A switch enable module is configured to activate a first switching mode upon detecting the coarse power-on reset signal. This ensures that an intermediate power supply voltage AVDD is not generated during periods when the external power supply voltage Vbat is below the MOS threshold voltage Vpor_coarse,thld, thereby reducing current consumption and the minimum power supply voltage Vbat,min. Figure 1 The comparison between (A) and (B) is shown.

[0021] This invention is specifically designed for (but not limited to) deep submicron technology (<130nm), based on the premise that the analog intermediate power supply voltage AVDD is typically generated internally by a low-dropout regulator, and provides a method that breaks the trade-offs of the aforementioned prior art solutions through the following novel concept:

[0022] 1. The two-step threshold detection mechanism described above: For an external power supply voltage Vbat below the coarse power-on reset threshold, a simple direct battery-powered module (current consumption in the microamp range) is operational. This module is triggered based on a MOS threshold voltage reference Vpor_coarse,thld used as the power-on reset threshold. The coarse power-on reset detector activates a fine power-on reset detector, which uses a bandgap reference, consumes slightly more current (approximately 1 microamp), and has a precise power-on reset threshold for final chip startup. The final change in threshold voltage ∆Vpor,thld is only approximately 100mV.

[0023] 2. During the lower voltage range of the external power supply voltage Vbat during the boost process, the intermediate analog power supply voltage AVDD is short-circuited to the battery power supply via a switch. This eliminates the dropout voltage of the low-dropout regulator and allows for a higher minimum power supply voltage Vbat,min to be used in the design of a fine power-on reset detector.

[0024] In another preferred embodiment, the switch is connected to a large external decoupling capacitor, which is connected to the integrated circuit via pins of the integrated circuit. In its first switching mode, the switch is configured to pre-charge the decoupling capacitor using a boosted external power supply voltage Vbat, which helps to accelerate the charging speed of the decoupling capacitor.

[0025] These and other aspects of the invention will become apparent and illustrated by the embodiments described below. Those skilled in the art will understand that various embodiments can be combined. Attached Figure Description

[0026] Figure 1 (A) and (B) show voltage level diagrams of the minimum supply voltage Vbat,min for integrated circuits with and without low-dropout regulators for providing intermediate supply voltages. Figure 2 A block diagram of a first embodiment of the power-on reset circuit according to the present invention is shown. Figure 3 It shows according to Figure 2 The voltage level diagram of the power-on reset circuit. Figure 4 It shows according to Figure 2 Timing diagram of the power-on reset circuit during the external power supply voltage Vbat boost process. Detailed Implementation Plan

[0027] Figure 2A first embodiment of integrated circuit 1 is shown, which has a power-on reset circuit 2 for activating other modules of integrated circuit 1 based on an external power supply voltage Vbat provided at power supply pin 3 of integrated circuit 1. Most of integrated circuit 1 is fabricated using standard deep submicron processes (e.g., <130nm), for example, the internal analog module 4 is implemented using so-called IO-MOS transistors with a maximum withstand voltage of 3.6V. Only a few dedicated, bulkier, and generally degraded high-voltage HV-MOS transistors in integrated circuit 1 are directly connected to a 5V USB power supply. These high-voltage HV-MOS transistors are used to construct a coarse power-on reset detector 5, which compares the external power supply voltage Vbat with a MOS threshold voltage Vpor_coarse,thld, and provides a coarse power-on reset signal 6 when the external power supply voltage Vbat exceeds the MOS threshold voltage Vpor_coarse,thld during the boost process. This MOS threshold voltage Vpor_coarse,thld is derived from the MOS threshold voltage and therefore has a relatively large change ΔVpor_coarse,thld of approximately 0.5V. The quiescent current of the coarse power-on reset detector 5 during operation is approximately 100nA.

[0028] The power-on reset circuit 2 also includes a fine power-on reset detector 7, which is configured to compare the external power supply voltage Vbat with a precise bandgap reference voltage Vref_bg generated by the bandgap module 8 of the fine power-on reset detector 7 to detect when the external power supply voltage Vbat rises above the power-on reset threshold voltage Vpor_fine,thld. A high-ohm voltage divider 9 is used to proportionally reduce the external power supply voltage Vbat to provide it as a second input to the comparator 10. The fine power-on reset detector 7 is enabled by the coarse power-on reset signal 6 of the coarse power-on reset detector 5. All modules of the fine power-on reset detector 7 are designed for low current consumption. The output signal of the fine power-on reset detector 7 is a fine power-on reset signal 11, which goes high when the external power supply voltage Vbat exceeds the precise fine power-on reset threshold Vpor_fine,thld. This fine power-on reset signal 11 ultimately controls the startup of the integrated circuit 1.

[0029] Integrated circuit 1 also includes a low-dropout regulator 13, which provides an intermediate power supply voltage AVDD to the internal analog modules 4 of integrated circuit 1. These internal analog modules 4 are susceptible to damage from higher failure voltages, which are lower than the maximum voltage Vbat,max of the external power supply at power pin 3. This intermediate power supply voltage AVDD allows the use of IO-MOS transistors with a maximum terminal voltage of 3.6V. The intermediate power supply voltage AVDD also powers the bandgap module 8 of the fine power-on reset detector 7.

[0030] Integrated circuit 1 also includes a switch 14, configured to, in a first switching mode, connect the internal analog module 4 and the bandgap module 8 to the power supply pin 3 and disconnect them from the intermediate power supply voltage AVDD during the external power supply voltage boosting process before power-on reset. Figure 2 In the preferred embodiment shown, the switch enable module 15 is configured to activate a first switch mode upon detection of a coarse power-on reset signal 6 by activating switch 14. The switch enable module 15 is configured as a logic gate whose second input is connected to a fine power-on reset signal 11. When the fine power-on reset signal 11 is logic high, switch 14 is disabled again, thus activating the second switch mode. After power-on reset, the internal analog module 4 is connected to the intermediate power supply voltage AVDD and disconnected from the power supply pin 3, as shown. Figure 4 As shown.

[0031] The low-dropout regulator 13 requires a desired voltage Vldo between its input and output. Its input is connected to an external power supply voltage Vbat provided at power supply pin 3, and the output of the low-dropout regulator 13 is connected to the output of switch 14. Since in the first switching mode, switch 14 directly connects its input power supply pin 3 to the output of the low-dropout regulator 13, both the input and output of the low-dropout regulator 13 are connected to the external power supply voltage Vbat, which disables the low-dropout regulator 13. Therefore, switch 14 is configured to disable the generation of the intermediate power supply voltage AVDD in the first switching mode and to activate the generation of the intermediate power supply voltage AVDD in the second switching mode (when the desired voltage Vldo exists between the input and output of the low-dropout regulator 13). In this example, switch 14 is implemented using a PMOS transistor. However, other implementations are also possible. By short-circuiting the low-dropout regulator 13, the loss of power margin is avoided, which helps the fine power-on reset detector 7 operate within a lower external power supply voltage Vbat range, thereby allowing for a lower external power supply voltage Vbat chip activation threshold.

[0032] Integrated circuit 1 also includes an output pin 16, to which a large external decoupling capacitor 17 is connected. Switch 14 is connected to the large external decoupling capacitor 17 via the output pin 16, and in its first switching mode, switch 14 is configured to precharge the decoupling capacitor 17 using a boosted external power supply voltage Vbat, which speeds up the power-up process of the product containing integrated circuit 1.

[0033] Figure 3 It shows according to Figure 2 The voltage level diagram of power-on reset circuit 2. Figure 4 It shows according to Figure 2 The timing diagram shows the behavior of the power-on reset circuit 2 during the external power supply voltage Vbat boost process. As a possible example, the following values ​​can be assumed:

[0034] The required voltage for the low dropout regulator 13 is Vldo,max = 0.25V;

[0035] Minimum intermediate power supply voltage AVDD,min = 2.25V (2.5V – 10%).

[0036] The change in the MOS threshold voltage reference, ∆Vpor_coarse,thld = 0.5V;

[0037] The change in voltage ∆Vpor_fine,thld = 0.1V is achieved by the fine power-on reset detector 7.

[0038] like Figure 3 As shown on the right, the coarse power-on reset detector 5 is activated once the external power supply voltage Vbat is boosted, while the fine power-on reset detector 7 is activated only when the coarse power-on reset threshold is exceeded.

[0039] from Figure 3 The graph clearly shows that the minimum battery voltage (“activation mode”) Vbat,min for operation is obtained by adding the minimum analog voltage AVDD,min required for operation of analog module 4, the maximum voltage drop VLDO,max on low dropout regulator 13, and the maximum change ∆Vpor_fine,thld of the fine power-on reset detector, resulting in 2.6V.

[0040] The advantage of using switch 14 lies in the minimum power supply voltage for fine power-on reset detector 7: Figure 3 In the case of ("POR fine,min with switch 14"), it is equal to Vbat,min minus the change in coarse power-on reset detector 5 ∆Vpor_coarse,thld, resulting in 2.1V. Without switch 14 ( Figure 3 The POR without switch 14 (fine,min) is reduced by the voltage Vldo,max required to activate the low dropout regulator 13, resulting in only 1.85V.

[0041] Several other different embodiments of controlling the switch 14 are possible:

[0042] • In another embodiment, switch 14 can be enabled only during the initial boost of the external power supply voltage Vbat to the triggering of the coarse power-on reset detector 5. Since direct connection is prohibited during the activation phase of the fine power-on reset detector 7, this detector must be able to operate normally within a lower operating range. However, in this embodiment, switch 14 helps to accelerate the boost rate of the intermediate power supply voltage AVDD.

[0043] • In yet another embodiment, switch 14 can be enabled as described above, but remains enabled during subsequent startup processes and even in active mode, as long as the external power supply voltage Vbat is below the maximum permissible operating voltage of the IO-MOS transistor (i.e., 3.6V). A separate voltage monitor is then required to disable switch 14 if the external power supply voltage Vbat rises further (e.g., by connecting the integrated circuit to a USB port).

[0044] The aforementioned power-on reset circuit 2 can be implemented in integrated circuit 1, which also includes a wireless data interface. As a specific example, the wireless data interface can be implemented as an NFC interface conforming to the ISO 18.092 standard.

Claims

1. An integrated circuit having a power-on reset circuit, the power-on reset circuit activating other parts of the integrated circuit based on an external power supply voltage provided at a power supply pin of the integrated circuit, the power-on reset circuit comprising: A fine power-on reset detector is configured to compare the external power supply voltage with a bandgap reference voltage generated by the bandgap module of the integrated circuit to detect when the external power supply voltage rises above the power-on reset threshold voltage, thereby resetting the integrated circuit upon power-on. as well as A low-dropout regulator is used to provide an intermediate power supply voltage to the internal modules of the integrated circuit, which are susceptible to damage from higher damage voltages, the damage voltages being lower than the maximum voltage of the external power supply at the power supply pin; The power-on reset circuit includes: The switch is configured such that, in a first switching mode, it can connect the internal module and the bandgap module to the power supply pin during the external power supply voltage boosting process before power-on reset and disconnect them from the intermediate power supply voltage; and in a second switching mode, it can connect the internal module to the intermediate power supply voltage and disconnect them from the power supply pin after power-on reset.

2. The integrated circuit of claim 1, wherein the power-on reset circuit further comprises a coarse power-on reset detector, the coarse power-on reset detector being constructed of a high-voltage-supporting MOS transistor, for comparing the external power supply voltage with a MOS threshold voltage, and providing a coarse power-on reset signal when the external power supply voltage exceeds the MOS threshold voltage during the boosting process, wherein the switch enable module is configured to activate the first switch mode when the coarse power-on reset signal is detected.

3. The integrated circuit according to claim 1, wherein the switch is configured to disable the generation of the intermediate power supply voltage in the first switching mode and activate the generation of the intermediate power supply voltage in the second switching mode.

4. The integrated circuit of claim 1, wherein the switch is connected to a large external decoupling capacitor connected to the integrated circuit via a pin of the integrated circuit, and wherein the switch is configured in its first switching mode to precharge the decoupling capacitor using a boosted external power supply voltage.

5. The integrated circuit of claim 1, further comprising a wireless data interface, wherein the wireless data interface includes an NFC interface conforming to the ISO 18.092 standard.

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