A complementary low-phase-noise frequency synthesizer and its usage method

Abstract

A complementary low-phase-noise frequency synthesizer and its usage method are disclosed. The synthesizer includes a frequency multiplier module, an adjustment module, and a low-noise PLL module. The low-noise PLL module includes a crystal oscillator, a third mixer, a PID circuit, and a third power divider. The adjustment module includes a second mixer and a DDS chip. The frequency multiplier module includes a first power divider. In application, the frequency multiplier module and the adjustment module first output a second phase reference signal. Then, the crystal oscillator, the third mixer, and the PID circuit form a closed-loop lock to achieve selective phase tracking. The loop bandwidth of the PID circuit is then adjusted to output signals with low near-end and low far-end phase noise. The adjustment frequency modulation resolution of the DDS chip meets the requirements of practical use. Therefore, the output signal of this design has low near-end and low far-end phase noise.

Description

Technical Field

[0001] This invention relates to a frequency synthesizer, belonging to the field of frequency synthesis and time-frequency control technology, and particularly to a complementary low-phase-noise frequency synthesizer and its usage method. Background Technology

[0002] Phase-tunable frequency synthesizers can provide reference signals with precisely adjustable phase and frequency, and are therefore widely used in many fields such as atomic frequency standards, radar, guidance, navigation and remote sensing. In these applications, phase noise is the ceiling that limits the frequency stability and adjustment accuracy of the signal, directly determines the spectral purity of the output signal, and thus limits the key performance of the terminal system.

[0003] Chinese patent application number 201410717244.1, filed on December 2, 2014, discloses a frequency synthesizer that drives a phase-locked loop after up-conversion using a DDS chip. It includes a DDS chip circuit and a phase-locked loop circuit. The output of a high-stability crystal oscillator is connected to the input of a first 3dB power divider. The output of the first 3dB power divider is connected to the inputs of a first direct frequency multiplier circuit and a second direct frequency multiplier circuit. The outputs of the first direct frequency multiplier circuit and the FPGA control circuit are connected to the input of the DDS chip circuit. The outputs of the second direct frequency multiplier circuit and the DDS chip circuit are connected to the input of a mixer-filter circuit. The output of the mixer-filter circuit is connected to the input of the phase-locked loop circuit. Although this design improves the phase noise of the output signal by increasing the phase detection frequency and reducing the frequency multiplication factor, it still has the following drawbacks:

[0004] In this design, only a single 100MHz high-stability crystal oscillator is used as the source reference signal. Although a signal with low far-end noise can be obtained, the near-end noise of the signal is high, which will limit the application of the frequency synthesizer in radar, communication and other systems.

[0005] The information disclosed in this background section is intended only to enhance understanding of the overall background of this application and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to overcome the defects and problems of high near-end noise of the output signal in the prior art, and to provide a complementary low phase noise frequency synthesizer with low near-end phase noise and low far-end phase noise of the output signal and its usage method.

[0007] To achieve the above objectives, the technical solution of the present invention is:

[0008] A complementary low-phase-noise frequency synthesizer, the synthesizer comprising a frequency multiplication module, an adjustment module, and a low-noise PLL module;

[0009] The low-noise PLL module includes a crystal oscillator, a third mixer, and a PID circuit. The output of the crystal oscillator is connected to the input of the third power divider. One output of the third power divider is connected to one input of the third mixer. The output of the third mixer is connected to the input of the PID circuit. The output of the PID circuit is connected to the voltage control terminal of the crystal oscillator. The other output of the third power divider outputs the final output signal. The other input of the third mixer is connected to the output of the second mixer of the adjustment module.

[0010] One input terminal of the second mixer is connected to the output terminal of the DDS chip, and the input terminal of the DDS chip is connected to one output terminal of the first power divider of the frequency multiplier module; the other input terminal of the second mixer is connected to the other output terminal of the first power divider; the input terminal of the first power divider receives the frequency multiplied signal of the reference signal.

[0011] One output terminal of the third power divider is connected to the input terminal of the third comparator. The output terminal of the third comparator is connected to the input terminal of the third buffer. The output terminal of the third buffer is connected to the input terminal of the third bandpass filter amplifier. The output terminal of the third bandpass filter amplifier is connected to one input terminal of the third mixer.

[0012] The other output terminal of the third power divider is connected to the input terminal of the third low-pass filter, and the output terminal of the third low-pass filter outputs a signal.

[0013] The third bandpass filter amplifier includes a third first bandpass filter, a third first amplifier, a third second bandpass filter, a third second amplifier, a third third bandpass filter, and a third third amplifier;

[0014] The output terminal of the third bandpass filter is connected to the input terminal of the third amplifier. The output terminal of the third amplifier is connected to the input terminal of the third bandpass filter. The output terminal of the third bandpass filter is connected to the input terminal of the third amplifier. The output terminal of the third amplifier is connected to the input terminal of the third bandpass filter. The output terminal of the third bandpass filter is connected to the input terminal of the third amplifier.

[0015] The center frequency of the third bandpass filter is 230MHz, the center frequency of the third bandpass filter is 230MHz, and the center frequency of the third bandpass filter is 230MHz.

[0016] The cutoff frequency of the third low-pass filter is 10MHz.

[0017] The output terminal of the DDS chip is connected to the input terminal of the second low-pass filter, and the output terminal of the second low-pass filter is connected to one input terminal of the second mixer.

[0018] The cutoff frequency of the second low-pass filter is 50MHz.

[0019] The input terminal of the first power divider is connected to the output terminal of the first bandpass filter amplifier. The input terminal of the first bandpass filter amplifier is connected to the output terminal of the first buffer. The input terminal of the first buffer is connected to the output terminal of the first comparator. The input terminal of the first comparator is connected to the output terminal of the first low-pass filter. The input terminal of the first low-pass filter receives a reference signal.

[0020] The first bandpass filter amplifier includes a first bandpass filter, a first amplifier, a first second bandpass filter, a first second amplifier, a first third bandpass filter, and a first third amplifier;

[0021] The output terminal of the first bandpass filter is connected to the input terminal of the first amplifier. The output terminal of the first amplifier is connected to the input terminal of the first second bandpass filter. The output terminal of the first second bandpass filter is connected to the input terminal of the first second amplifier. The output terminal of the first second amplifier is connected to the input terminal of the first third bandpass filter. The output terminal of the first third bandpass filter is connected to the input terminal of the first third amplifier.

[0022] The center frequency of the first bandpass filter is 250MHz, the center frequency of the first second bandpass filter is 250MHz, and the center frequency of the first third bandpass filter is 250MHz.

[0023] The cutoff frequency of the first low-pass filter is 10MHz.

[0024] The frequency multiplier module is connected to the power supply module via signal, the adjustment module is connected to the power supply module via signal, and the low-noise PLL module is connected to the power supply module via signal.

[0025] The power module includes multiple power rails and multiple ground lines. Each power rail is connected to its corresponding ground line. The power rails are isolated from each other using LDOs / filters and ferrite beads. The multiple ground lines are partitioned and shielded in an analog / RF / digital manner.

[0026] A method of using a complementary low-phase-noise frequency synthesizer, the method comprising the following steps:

[0027] Step 1: First, input the first reference signal to the first power divider, and then the first power divider outputs the same first signal and second signal;

[0028] Step 2: First, write the frequency control word and phase control word into the DDS chip. At the same time, the first signal is input to the DDS chip. Then, the DDS chip outputs the digitally controlled intermediate frequency signal according to the frequency control word and phase control word. Then, the digitally controlled intermediate frequency signal and the second signal enter the second mixer for mixing. Then, the second mixer outputs the second phase reference signal with lower near-end phase noise.

[0029] Step 3: First, the crystal oscillator outputs a third reference signal with low phase noise at the far end. Then, the third power divider outputs the third and fourth signals based on the third reference signal. The third signal and the second reference signal then enter the third mixer for mixing. The third mixer outputs a phase error signal. The PID circuit generates a control signal based on the phase error signal. The crystal oscillator then forms a closed-loop lock based on the control signal to make the phase of the third reference signal track the phase of the second phase reference signal.

[0030] Step 4: The fourth signal output from the third power divider is the final output signal of the synthesizer;

[0031] Step 5: When the near-end phase noise of the final output signal is low, narrow the loop bandwidth of the PID circuit; when the far-end phase noise of the final output signal is low, widen the loop bandwidth of the PID circuit; when the phase noise of the final output signal is low at both the near and far ends, adjust the loop bandwidth of the PID circuit to the offset frequency of the intersection of the phase noise curves of the first and third reference signals.

[0032] One input terminal of the DDS chip is connected to the output terminal of the MCU chip, and the input terminal of the MCU chip is connected to the output terminal of the host computer; the input terminal of the host computer is connected to one output terminal of the third power divider.

[0033] The method also includes a sixth step:

[0034] Step 6: The host computer compares the final output signal with the external signals to obtain the comprehensive error signal. Then, the host computer controls the MCU chip to write the frequency control word and phase control word to the DDS chip based on the comprehensive error signal for adaptive adjustment.

[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0036] 1. In a complementary low-phase-noise frequency synthesizer of the present invention, the synthesizer includes a frequency multiplier module, an adjustment module, and a low-noise PLL module. The low-noise PLL module includes a crystal oscillator, a third mixer, and a PID circuit. The crystal oscillator is signal-connected to a third power divider. One output terminal of the third power divider is sequentially connected to the third mixer, the PID circuit, and the crystal oscillator signal. The other output terminal of the third power divider outputs the final output signal. The third mixer is signal-connected to the second mixer of the adjustment module. The second mixer is sequentially signal-connected to the DDS chip and the first power divider of the frequency multiplier module. The second mixer is signal-connected to the first power divider. The first power divider receives the frequency-multiplied reference signal. In application, the first power divider first outputs a first signal and a second signal. The first signal is input to the DDS chip to output a digitally controlled intermediate frequency (CNC) signal. Then, the CNC signal and the second signal enter... The second mixer performs mixing and outputs a second phase reference signal; the crystal oscillator outputs a third reference signal, and the third power divider outputs a third signal and a fourth signal based on the third reference signal. The third signal and the second phase reference signal then enter the third mixer for mixing, outputting a phase error signal. The PID circuit then drives the crystal oscillator to complete closed-loop locking based on the phase error signal, ensuring that the phase of the third signal tracks the phase of the second phase reference signal. The fourth signal is the final output signal of the synthesizer. Furthermore, based on the requirement for low near-end phase, far-end, or a combination of both phase noise, the loop bandwidth of the PID circuit is adjusted so that the phase of the final output signal inherits the low near-end phase noise characteristic of the second phase reference signal, the low far-end phase noise characteristic of the third reference signal, or a combination of both low near-end and far-end phase noise characteristics. The advantages of this invention also include:

[0037] First point: The final output signal of this invention can be used as a reference signal;

[0038] Secondly, by adjusting the loop bandwidth of the PID circuit, this invention achieves on-demand configuration and optimized complementarity of low noise characteristics at the near end, far end, and the combination of the two (i.e., full offset frequency). It is very suitable for scenarios such as radar and communication base stations that require both low near-end and far-end phase noise of the frequency source.

[0039] Thirdly, the DDS chip's adjustment frequency modulation resolution can reach E-14 or E-15, which is far higher than the E-12 or E-13 adjustment frequency modulation resolution of existing 20-bit DACs, and can meet the required accuracy of E-12 or E-13 in applications; moreover, the quantization noise of the DAC will have a significant impact on the performance of the frequency synthesizer, while the quantization noise of the DDS chip is lower than that of the DAC, so the accuracy of this invention is higher.

[0040] Therefore, the output signal of this invention has low near-end phase noise and low far-end phase noise.

[0041] 2. In the complementary low-phase-noise frequency synthesizer of the present invention, the third power divider is connected to the third comparator, the third buffer, the third bandpass filter amplifier, and the third mixer. The third bandpass filter amplifier includes three bandpass filters and three amplifiers. The center frequency of the bandpass filters is 230MHz, and the cutoff frequency of the third low-pass filter is 10MHz. In application, the third signal (10MHz sine wave) is first converted into a 10MHz square wave signal by the third comparator, then the third buffer enhances the driving capability and normalizes the waveform, and then it is input to the third bandpass filter amplifier. The invention comprises a cascaded combination of three bandpass filters with a center frequency of 230MHz and three amplifiers. This combination performs three progressive filtering and amplification steps on the square wave signal, efficiently extracting and purifying the desired 230MHz sine wave signal from the rich harmonic components while maximally suppressing other harmonics and noise. The sine wave signal is converted into a square wave signal, and the bandpass filters are used to select the appropriate harmonic components for frequency doubling. This method offers advantages such as simple circuitry and low noise. Furthermore, the "three-stage progressive purification" ensures spectral purity, resulting in a pure 230MHz signal that carries the characteristic of low far-end phase noise from the crystal oscillator. Therefore, the far-end phase noise of this invention is low.

[0042] 3. In the complementary low-phase-noise frequency synthesizer of the present invention, the DDS chip is connected to the second low-pass filter, and the second low-pass filter is connected to the second mixer. The cutoff frequency of the second low-pass filter is 50MHz. In application, the DDS chip uses the first signal (250MHz) as a reference and outputs a digitally controlled intermediate frequency (CIF) signal (20MHz) with precisely adjustable frequency and phase under the input configuration. The second low-pass filter then filters the CIF signal (20MHz) to output a clean CIF signal (20MHz). The CIF signal (20MHz) is then sent to the second mixer and... The second signal (250MHz) is mixed and then filtered by a second low-pass filter to generate the required high-phase-purity second phase reference signal (230MHz), which is used for subsequent phase comparison and closed-loop locking. The frequency modulation resolution of the E-14 or E-15 of the DDS chip can be adjusted in extremely fine "micro-steps," meeting the stringent requirements of ultra-high precision fine-tuning in applications such as mercury ion microwave frequency standards. The DDS chip can adjust the frequency and phase of the digitally controlled intermediate frequency signal to achieve the effect of adjusting the second phase reference signal, i.e., without the need for high-resolution synthesis of the second phase reference signal (which is more complex and noisier). Therefore, the adjustment of this invention is convenient.

[0043] 4. In the complementary low-phase-noise frequency synthesizer of the present invention, a first power divider is signal-connected to a first bandpass filter amplifier, a first buffer, a first comparator, and a first low-pass filter. The first low-pass filter receives a reference signal as input. The first bandpass filter amplifier includes three bandpass filters and three amplifiers. The center frequency of the bandpass filters is 250MHz, and the cutoff frequency of the first low-pass filter is 10MHz. In application, the externally input first reference signal (10MHz) is first sent to the first low-pass filter for preliminary filtering to improve signal purity. Then, the first comparator converts the first reference signal (10MHz) into a 10MHz square wave signal. The square wave signal is then enhanced with driving capability and regulated waveform by the first buffer before being input to the first bandpass filter amplifier. A cascaded combination of three bandpass filters with a center frequency of 250MHz and three amplifiers performs three progressive filtering and amplification steps on the square wave signal, thereby efficiently extracting and purifying the required first reference signal (250MHz sine wave signal) from the rich harmonic components, while suppressing other harmonics and noise. This first reference signal is finally input to the first power divider, where it is split into a first signal and a second signal with equal power and consistent phase, for use by the DDS chip and the second mixer. The first low-pass filter lays the foundation for generating a high-purity signal from the source, and the first comparator and the first bandpass filter amplifier implement an efficient and low-noise frequency multiplication method. Combined with the "three-stage progressive purification" to ensure spectral purity, the first and second signals with homogeneity, phase consistency, and high purity are finally generated. Therefore, the front-end signal quality of this invention is good.

[0044] 5. In this invention, a complementary low-phase-noise frequency synthesizer, the power supply module is signal-connected to the frequency multiplier module, the adjustment module, and the low-noise PLL module. The power supply module includes multiple power rails and multiple ground lines. Each power rail is isolated using an LDO / filter and ferrite beads. The multiple ground lines are arranged in analog / RF / digital partitions and shielded. In application, the power supply module provides the required multiple operating voltages to the frequency multiplier module, the adjustment module, and the low-noise PLL module. The LDO (low dropout linear regulator) and filters further filter out ripple and noise from the preceding power supply, providing "clean" DC voltage. Ferrite bead isolation prevents high-frequency noise between different power rails from interfering with each other through the power lines. Physically separating the power supplies and ground lines of circuits with different noise characteristics (analog, RF, digital) significantly reduces the interference of severe ground potential fluctuations (i.e., "ground bounce noise") caused by digital circuit switching on analog RF signals. By addressing the two most fundamental noise coupling channels—"power supply" and "ground line"—this invention provides crucial and fundamental hardware support for achieving the ultimate goal of "low phase noise" in the synthesizer. Therefore, the power supply noise of this invention is low.

[0045] 6. In the complementary low-phase-noise frequency synthesizer of this invention, the DDS chip is connected to the MCU chip and the host computer. The host computer is connected to the third power divider. In application, the host computer performs a high-precision phase or frequency comparison between the final output signal and a higher-level or more stable external signal, generating a synthesis error signal. This error signal reflects the long-term deviation or drift trend between the two signals. The host computer then analyzes and calculates the synthesis error signal to obtain the required frequency correction amount. The MCU chip then writes a new frequency control word and / or phase control word to the DDS chip based on the frequency correction amount to adjust the second phase reference signal (230MHz). Finally, through the closed-loop control of the low-noise PLL module, the final output signal (10MHz) of the crystal oscillator is forced to undergo a corresponding high-precision adjustment, thereby eliminating the deviation from the external signal and achieving stable interlocking with the external signal. Therefore, this invention has an adaptive adjustment function. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of the present invention.

[0047] Figure 2 yes Figure 1 A schematic diagram of the structure of the intermediate frequency multiplier module, the adjustment module, and the low-noise PLL module.

[0048] Figure 3 yes Figure 1 A schematic diagram of the intermediate frequency multiplier module.

[0049] Figure 4 yes Figure 1 A schematic diagram of the structure of the adjustment module.

[0050] Figure 5 yes Figure 1 A schematic diagram of the structure of a low-noise PLL module.

[0051] Figure 6 yes Figure 5 A schematic diagram of the structure of the third bandpass filter amplifier.

[0052] Figure 7 yes Figure 3 A schematic diagram of the structure of the first bandpass filter amplifier.

[0053] Figure 8 This is a schematic diagram of the phase noise of the output signal of the present invention.

[0054] In the diagram: Frequency multiplier module 1, first power divider 11, first bandpass filter amplifier 12, first bandpass filter 121, first amplifier 122, first second bandpass filter 123, first second amplifier 124, first third bandpass filter 125, first third amplifier 126, first buffer 13, first comparator 14, first low-pass filter 15, adjustment module 2, second mixer 21, DDS chip 22, second low-pass filter 23, MCU chip 24, low-noise PLL module 3, crystal oscillator 31, third mixer 32, PID circuit 33, third power divider 34, third comparator 35, third buffer 36, third bandpass filter amplifier 37, third first bandpass filter 371, third first amplifier 372, third second bandpass filter 373, third second amplifier 374, third third bandpass filter 375, third third amplifier 376, third low-pass filter 38, power supply module 4. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] Please see Figure 1 — Figure 8 A complementary low phase noise frequency synthesizer, the synthesizer comprising a frequency multiplication module 1, an adjustment module 2 and a low noise PLL module 3;

[0057] The low-noise PLL module 3 includes a crystal oscillator 31, a third mixer 32, and a PID circuit 33. The output terminal of the crystal oscillator 31 is connected to the input terminal of the third power divider 34. One output terminal of the third power divider 34 is connected to one input terminal of the third mixer 32. The output terminal of the third mixer 32 is connected to the input terminal of the PID circuit 33. The output terminal of the PID circuit 33 is connected to the voltage control terminal of the crystal oscillator 31. The other output terminal of the third power divider 34 outputs the final output signal. The other input terminal of the third mixer 32 is connected to the output terminal of the second mixer 21 of the adjustment module 2.

[0058] One input terminal of the second mixer 21 is connected to the output terminal of the DDS chip 22, and the input terminal of the DDS chip 22 is connected to one output terminal of the first power divider 11 of the frequency multiplier module 1; the other input terminal of the second mixer 21 is connected to the other output terminal of the first power divider 11; the input terminal of the first power divider 11 receives the frequency multiplied signal of the reference signal.

[0059] One output terminal of the third power divider 34 is connected to the input terminal of the third comparator 35. The output terminal of the third comparator 35 is connected to the input terminal of the third buffer 36. The output terminal of the third buffer 36 is connected to the input terminal of the third bandpass filter amplifier 37. The output terminal of the third bandpass filter amplifier 37 is connected to one input terminal of the third mixer 32.

[0060] The other output terminal of the third power divider 34 is connected to the input terminal of the third low-pass filter 38, and the output terminal of the third low-pass filter 38 outputs a signal.

[0061] The third bandpass filter amplifier 37 includes a third first bandpass filter 371, a third first amplifier 372, a third second bandpass filter 373, a third second amplifier 374, a third third bandpass filter 375, and a third third amplifier 376.

[0062] The output terminal of the third bandpass filter 371 is connected to the input terminal of the third amplifier 372. The output terminal of the third amplifier 372 is connected to the input terminal of the third bandpass filter 373. The output terminal of the third bandpass filter 373 is connected to the input terminal of the third amplifier 374. The output terminal of the third amplifier 374 is connected to the input terminal of the third bandpass filter 375. The output terminal of the third bandpass filter 375 is connected to the input terminal of the third amplifier 376.

[0063] The center frequency of the third bandpass filter 371 is 230MHz, the center frequency of the third bandpass filter 373 is 230MHz, and the center frequency of the third bandpass filter 375 is 230MHz.

[0064] The cutoff frequency of the third low-pass filter 38 is 10MHz.

[0065] The output terminal of the DDS chip 22 is connected to the input terminal of the second low-pass filter 23, and the output terminal of the second low-pass filter 23 is connected to one input terminal of the second mixer 21.

[0066] The cutoff frequency of the second low-pass filter 23 is 50MHz.

[0067] The input terminal of the first power divider 11 is connected to the output terminal of the first bandpass filter amplifier 12. The input terminal of the first bandpass filter amplifier 12 is connected to the output terminal of the first buffer 13. The input terminal of the first buffer 13 is connected to the output terminal of the first comparator 14. The input terminal of the first comparator 14 is connected to the output terminal of the first low-pass filter 15. The input terminal of the first low-pass filter 15 receives a reference signal.

[0068] The first bandpass filter amplifier 12 includes a first bandpass filter 121, a first amplifier 122, a first second bandpass filter 123, a first second amplifier 124, a first third bandpass filter 125, and a first third amplifier 126;

[0069] The output terminal of the first bandpass filter 121 is connected to the input terminal of the first amplifier 122. The output terminal of the first amplifier 122 is connected to the input terminal of the first second bandpass filter 123. The output terminal of the first second bandpass filter 123 is connected to the input terminal of the first second amplifier 124. The output terminal of the first second amplifier 124 is connected to the input terminal of the first third bandpass filter 125. The output terminal of the first third bandpass filter 125 is connected to the input terminal of the first third amplifier 126.

[0070] The center frequency of the first bandpass filter 121 is 250MHz, the center frequency of the first second bandpass filter 123 is 250MHz, and the center frequency of the first third bandpass filter 125 is 250MHz.

[0071] The cutoff frequency of the first low-pass filter 15 is 10MHz.

[0072] The frequency multiplier module 1 is connected to the power supply module 4 by signal, the adjustment module 2 is connected to the power supply module 4 by signal, and the low noise PLL module 3 is connected to the power supply module 4 by signal.

[0073] The power module 4 includes multiple power rails and multiple ground lines. Each power rail is connected to its corresponding ground line. The power rails are isolated from each other using LDOs / filters and ferrite beads. The multiple ground lines are partitioned and shielded in an analog / RF / digital manner.

[0074] A method of using a complementary low-phase-noise frequency synthesizer, the method comprising the following steps:

[0075] Step 1: First, input the first reference signal to the first power divider 11, and then output the same first signal and second signal from the first power divider 11;

[0076] Step 2: First, write the frequency control word and phase control word into the DDS chip 22. At the same time, the first signal is input to the DDS chip 22. Then, the DDS chip 22 outputs the digitally controlled intermediate frequency signal according to the frequency control word and phase control word. Then, the digitally controlled intermediate frequency signal and the second signal enter the second mixer 21 for mixing. Then, the second mixer 21 outputs the second phase reference signal with lower near-end phase noise.

[0077] Step 3: First, the crystal oscillator 31 outputs a third reference signal with low phase noise at the far end. Then, the third power divider 34 outputs the third signal and the fourth signal based on the third reference signal. Then, the third signal and the second reference signal enter the third mixer 32 for mixing. Then, the third mixer 32 outputs a phase error signal. Then, the PID circuit 33 generates a control signal based on the phase error signal. Then, the crystal oscillator 31 forms a closed-loop lock based on the control signal so that the phase of the third reference signal tracks the phase of the second phase reference signal.

[0078] Step 4: The fourth signal output by the third power divider 34 is the final output signal of the synthesizer;

[0079] Step 5: When the near-end phase noise of the final output signal is low, narrow the loop bandwidth of the PID circuit 33; when the far-end phase noise of the final output signal is low, widen the loop bandwidth of the PID circuit 33; when the phase noise of the final output signal is low at both the near and far ends, adjust the loop bandwidth of the PID circuit 33 to the offset frequency of the intersection of the phase noise curves of the first reference signal and the third reference signal.

[0080] One input terminal of the DDS chip 22 is connected to the output terminal of the MCU chip 24, and the input terminal of the MCU chip 24 is connected to the output terminal of the host computer; the input terminal of the host computer is connected to one output terminal of the third power divider 34.

[0081] The method also includes a sixth step:

[0082] Step 6: The host computer compares the final output signal with the external signals to obtain the comprehensive error signal. Then, the host computer controls the MCU chip 24 to write the frequency control word and phase control word to the DDS chip 22 based on the comprehensive error signal for adaptive adjustment.

[0083] The following are supplementary descriptions of the present invention:

[0084] The crystal oscillator 31 mentioned in this invention refers to a crystal oscillator that outputs a 10MHz sine wave or a 10MHz square wave, and is generally a temperature-controlled crystal oscillator with voltage control.

[0085] The design basis for the key frequency parameters (10MHz, 20MHz, 50MHz, 230MHz, 250MHz) of this invention is as follows:

[0086] ① The selection criteria for 10MHz: It is the standard frequency used by the frequency synthesizer system, which determines the interface reference of the system; and in this invention, the pure 10MHz reference sine wave is converted into a square wave. Its core purpose is to utilize the rich odd harmonic characteristics inherent in the ideal square wave signal so as to extract the required high-order harmonic components (i.e., 250MHz) from it.

[0087] ② Selection Criteria for 250MHz: The selection of 250MHz (i.e., the 25th harmonic of 10MHz) as the target frequency is mainly based on two engineering considerations: First, anti-interference: 250MHz is far enough from the fundamental frequency of 10MHz to effectively reduce crosstalk between harmonics on the circuit board; Second, meeting the optimal operating conditions of the DDS chip 22: The DDS chip 22 requires a reference clock between 250MHz and 1GHz; if a clock lower than 250MHz is used directly, the DDS chip 22 will be forced to start its internal phase-locked loop for frequency multiplication, which will introduce additional noise and degrade its inherent high frequency resolution; by providing a 250MHz reference directly through an external circuit, the DDS chip 22 can operate in its optimal state and maintain its resolution advantage;

[0088] ③ Selection criteria for 20MHz and 230MHz: These two frequencies are strongly correlated and bundled together, and their sum must equal 250MHz. If 230MHz is changed to 210MHz or 190MHz, the DDS chip 22 will need to use the 250MHz reference to output 40MHz or 60MHz, resulting in a sawtooth pattern in the output sine wave. Although this can be addressed with a filter, it will introduce unnecessary noise. The working principle of the DDS chip 22 is that its internal 48-bit counter counts and samples the required output frequency based on 250MHz. Generally, it is required that the frequency of the DDS output does not exceed 40% of its reference frequency. Therefore, 20MHz and 230MHz are selected. 20MHz (accounting for 8%) fully meets this requirement and can avoid waveform degradation ("sawtooth") caused by excessively high output frequencies (such as 40MHz or 60MHz), thereby reducing the need for subsequent filtering to repair the waveform and the additional noise it introduces.

[0089] ④ Selection criteria for 50MHz: The DDS chip 22 outputs a stepped sine wave based on counting sampling. Using a cutoff frequency that is slightly twice as wide (50MHz) here can just retain the required 20MHz without distortion, while being sufficient to strongly filter out these more harmful high-frequency noise and image components that are far from 20MHz.

[0090] In summary, the frequency planning of this frequency synthesizer is a series of interconnected system engineering projects: the interface frequency (10MHz) is determined based on the application (mercury ion clock); the optimal reference clock (250MHz) and its intermediate frequency synthesis strategy (20MHz) are determined based on the device performance (DDS chip 22); and another local oscillator frequency (230MHz) is determined through frequency calculation relationships (mixing requirements). The entire set of parameters aims to balance performance, purity, and feasibility.

[0091] Example 1:

[0092] Please see Figure 1 — Figure 8 A complementary low-phase-noise frequency synthesizer is disclosed. The synthesizer includes a frequency multiplier module 1, an adjustment module 2, and a low-noise PLL module 3. The low-noise PLL module 3 includes a crystal oscillator 31, a third mixer 32, and a PID circuit 33. The output of the crystal oscillator 31 is connected to the input of a third power divider 34. One output of the third power divider 34 is connected to one input of the third mixer 32. The output of the third mixer 32 is connected to the input of the PID circuit 33. The output of the PID circuit 33 is connected to the voltage-controlled terminal of the crystal oscillator 31. The third power divider 34 outputs the final output signal at another output terminal; the third mixer 32's other input terminal is connected to the output signal of the second mixer 21 of the adjustment module 2; one input terminal of the second mixer 21 is connected to the output signal of the DDS chip 22, and the input terminal of the DDS chip 22 is connected to one output signal of the first power divider 11 of the frequency multiplier module 1; the other input terminal of the second mixer 21 is connected to the other output signal of the first power divider 11; the first power divider 11 inputs the reference signal multiplied signal.

[0093] A method of using a complementary low-phase-noise frequency synthesizer, the method comprising the following steps:

[0094] Step 1: First, input the first reference signal to the first power divider 11, and then output the same first signal and second signal from the first power divider 11;

[0095] Step 2: First, write the frequency control word and phase control word into the DDS chip 22. At the same time, the first signal is input to the DDS chip 22. Then, the DDS chip 22 outputs the digitally controlled intermediate frequency signal according to the frequency control word and phase control word. Then, the digitally controlled intermediate frequency signal and the second signal enter the second mixer 21 for mixing. Then, the second mixer 21 outputs the second phase reference signal with lower near-end phase noise.

[0096] Step 3: First, the crystal oscillator 31 outputs a third reference signal with low phase noise at the far end. Then, the third power divider 34 outputs the third signal and the fourth signal based on the third reference signal. Then, the third signal and the second reference signal enter the third mixer 32 for mixing. Then, the third mixer 32 outputs a phase error signal. Then, the PID circuit 33 generates a control signal based on the phase error signal. Then, the crystal oscillator 31 forms a closed-loop lock based on the control signal so that the phase of the third reference signal tracks the phase of the second phase reference signal.

[0097] Step 4: The fourth signal output by the third power divider 34 is the final output signal of the synthesizer;

[0098] Step 5: Please refer to Figure 8 When the near-end phase noise of the final output signal is low, the loop bandwidth of the PID circuit 33 is narrowed. At this time, the phase of the third reference signal tracks the second phase reference signal with low near-end phase noise, so the fourth signal with low near-end phase noise is output. When the far-end phase noise of the final output signal is low, the loop bandwidth of the PID circuit 33 is widened. At this time, the phase of the third reference signal retains its characteristic of low far-end phase noise, so the fourth signal with low far-end phase noise is output. When the phase noise of the final output signal is low at both the near end and the far end, the loop bandwidth of the PID circuit 33 is adjusted to the offset frequency of the intersection of the phase noise curves of the first reference signal and the third reference signal. At this time, the fourth signal with low near-end phase noise and low far-end phase noise is output.

[0099] Preferably, before the first step, the frequency multiplier module 1, the adjustment module 2 and the low-noise PLL module 3 are powered on and reset and self-tested.

[0100] Preferably, in the fifth step, when adjusting the loop bandwidth of the PID circuit 33, the target bandwidth range can be initially determined based on the intersection of the phase noise curves of the first phase reference signal and the third reference signal, and then the loop bandwidth can be gradually and finely adjusted until the target bandwidth range is reached, so as to achieve the optimal noise complementarity effect.

[0101] Example 2:

[0102] The basic content is the same as in Example 1, except that:

[0103] Please see Figure 1 — Figure 6One output terminal of the third power divider 34 is connected to the input terminal of the third comparator 35. The output terminal of the third comparator 35 is connected to the input terminal of the third buffer 36. The output terminal of the third buffer 36 is connected to the input terminal of the third bandpass filter amplifier 37. The output terminal of the third bandpass filter amplifier 37 is connected to one input terminal of the third mixer 32. The other output terminal of the third power divider 34 is connected to the input terminal of the third low-pass filter 38. The output terminal of the third low-pass filter 38 outputs a signal. The third bandpass filter amplifier 37 includes a third first bandpass filter 371, a third first amplifier 372, a third second bandpass filter 373, a third second amplifier 374, a third third bandpass filter 375, and a third third amplifier 376. The output terminal of the third first bandpass filter 371 is connected to the input terminal of the third first amplifier 372. The output terminal of the third first amplifier 372 is connected to the input terminal of the third second bandpass filter 373. The output terminal of the third second bandpass filter 373 is connected to the input terminal of the third second amplifier 376. The input signal of 74 is connected, the output of the third second amplifier 374 is connected to the input signal of the third third bandpass filter 375, and the output of the third third bandpass filter 375 is connected to the input signal of the third third amplifier 376; the center frequency of the third first bandpass filter 371 is 230MHz, the center frequency of the third second bandpass filter 373 is 230MHz, the center frequency of the third third bandpass filter 375 is 230MHz; the cutoff frequency of the third low-pass filter 38 is 10MHz.

[0104] In application, the third power divider 34 receives the third reference signal (10MHz sine wave) from the crystal oscillator 31 and splits it into a third signal and a fourth signal with equal power. The third signal is sent to a signal processing link consisting of a third comparator 35, a third buffer 36, and a third bandpass filter amplifier 37 connected in sequence. The third signal (10MHz sine wave signal) is first converted into a 10MHz square wave signal of the same frequency by the third comparator 35 to utilize its rich odd harmonic components. Then, the third buffer 36 enhances the driving capability and shapes the waveform. Finally, it is input to the third bandpass filter amplifier 37. Through its internal link consisting of a third bandpass filter 371, a third amplifier 372, a third bandpass filter 373, a third amplifier 374, a third bandpass filter 375, and a third amplifier 376 cascaded in sequence, the input 10MHz square wave signal undergoes three "filter-amplification" processes. The process involves progressive purification. Since the center frequency of all bandpass filters is 230MHz, this link can efficiently and progressively filter, enhance, and extract the required 23rd harmonic (i.e., the 230MHz component) from the numerous harmonics contained in the square wave signal, while suppressing the 10MHz fundamental wave, other harmonics, and circuit noise to the maximum extent. Then, a high-purity, high-intensity third reference signal (230MHz sine wave signal) is obtained. The third reference signal is used to perform a high-precision phase comparison with the second phase reference signal from the adjustment module. At the same time, the fourth signal (10MHz sine wave signal) output by the third power divider 34 is sent to the third low-pass filter 38 with a center frequency of 10MHz for filtering to further filter out any high-frequency noise or spurious signals that may remain in the signal path, thereby outputting a purer 10MHz signal. This signal is the final output signal of the frequency synthesizer after internal closed-loop optimization.

[0105] Example 3:

[0106] The basic content is the same as in Example 1, except that:

[0107] Please see Figure 1 — Figure 4 The output of the DDS chip 22 is connected to the input of the second low-pass filter 23, and the output of the second low-pass filter 23 is connected to one input of the second mixer 21. The cutoff frequency of the second low-pass filter 23 is 50MHz.

[0108] In application, the DDS chip 22 uses the first signal (250MHz) from the first power divider 11 as a reference and outputs a digitally controlled intermediate frequency (20MHz) signal with precisely adjustable frequency and phase according to the frequency control word and phase control word written in it. The digitally controlled intermediate frequency signal is then sent to the second low-pass filter 23 with a cutoff frequency of 50MHz for filtering to remove high-frequency quantization noise, image components and other out-of-band spurious signals generated by the DDS chip 22 during digital synthesis, thereby outputting a spectrum-clean digitally controlled intermediate frequency signal (20MHz). Here, a cutoff frequency of 50MHz is used to match the output characteristics of the DDS chip 22. Then, the clean digitally controlled intermediate frequency signal (20MHz) is sent to the second mixer 21 to perform a mixing operation with the second signal (250MHz) from the first power divider 11 to finally generate the high-purity, adjustable second phase reference signal required by the system.

[0109] Example 4:

[0110] The basic content is the same as in Example 1, except that:

[0111] Please see Figure 1 — Figure 7 The input terminal of the first power divider 11 is connected to the output terminal of the first bandpass filter amplifier 12. The input terminal of the first bandpass filter amplifier 12 is connected to the output terminal of the first buffer 13. The input terminal of the first buffer 13 is connected to the output terminal of the first comparator 14. The input terminal of the first comparator 14 is connected to the output terminal of the first low-pass filter 15. The input terminal of the first low-pass filter 15 receives a reference signal. The first bandpass filter amplifier 12 includes a first bandpass filter 121, a first amplifier 122, a first second bandpass filter 123, a first second amplifier 124, a first third bandpass filter 125, and a first third amplifier 126. The output terminal of the first first bandpass filter 121 is connected to the input terminal of the first first amplifier 122. The output terminal of the first first amplifier 122 is connected to the input terminal of the first second bandpass filter 123. The output terminal of the first second bandpass filter 123 is connected to the input terminal of the first second amplifier 126. The input signal of 24 is connected, the output of the first and second amplifiers 124 is connected to the input signal of the first and third bandpass filters 125, and the output of the first and third bandpass filters 125 is connected to the input signal of the first and third amplifiers 126; the center frequency of the first bandpass filter 121 is 250MHz, the center frequency of the first and second bandpass filters 123 is 250MHz, and the center frequency of the first and third bandpass filters 125 is 250MHz; the cutoff frequency of the first low-pass filter 15 is 10MHz.

[0112] In application, the externally input reference signal (10MHz) is first fed into a first low-pass filter 15 with a center frequency of 10MHz for filtering to suppress any non-10MHz spurious noise and harmonics in the signal, thereby obtaining a pure 10MHz sine wave base signal. Then, the first comparator 14 converts the pure 10MHz sine wave base signal into a 10MHz square wave signal of the same frequency. The purpose of this conversion is to utilize the characteristic of an ideal square wave signal being rich in odd harmonics in the frequency domain, to prepare for the subsequent generation of the required higher harmonics (250MHz). The first buffer 13 enhances the driving capability of the 10MHz square wave signal and smooths its waveform edges. The 10MHz square wave signal then enters the first bandpass filter amplifier 12 for a progressive purification process. Specifically, the 10MHz square wave signal first passes through the first bandpass filter 121 with a center frequency of 250MHz. Its function is to initially filter out the desired 25th harmonic (250MHz frequency component) from the numerous harmonics contained in the input square wave signal, while simultaneously suppressing the 10MHz fundamental wave and other harmonics. After filtering, the amplitude of the 250MHz component will attenuate. Therefore, the first amplifier 122 compensates for the filtering loss and increases the signal power. The amplified signal is then sent to the first and second bandpass filters 123, which also have a center frequency of 250MHz, for a second filtering to further filter out any residual out-of-band components and noise introduced by the amplifier after the first filtering. Then, the first and second amplifiers 124 perform a second amplification to maintain the signal strength. The signal then passes through the first and third bandpass filters 125 for final spectrum purification. Finally, the first and third amplifiers 126 act as the output stage driver amplifier to ensure that the output signal has sufficient power and a good signal-to-noise ratio. After the above three-stage cascaded "filtering-amplification" process, the final output from the first bandpass filter amplifier 12 is a high-purity, high signal-to-noise ratio, and high-intensity 250MHz sine wave signal. If only two stages of "filtering-amplification" are used, the output waveform signal-to-noise ratio will be very poor. If four stages of "filtering-amplification" are used, there will be redundancy, and the more electronic components used in the analog circuit, the more noise will be introduced.

[0113] Example 5:

[0114] The basic content is the same as in Example 1, except that:

[0115] Please see Figure 1 — Figure 5 The frequency multiplier module 1 is signal-connected to the power supply module 4, the adjustment module 2 is signal-connected to the power supply module 4, and the low-noise PLL module 3 is signal-connected to the power supply module 4. The power supply module 4 includes multiple power rails and multiple ground lines. Each power rail is connected to its corresponding ground line. The power rails are isolated from each other using LDOs / filters and ferrite beads. The multiple ground lines are arranged in analog / RF / digital partitions and shielding.

[0116] In application, power module 4 provides the required stable and clean operating voltage to all active devices in frequency multiplier module 1, regulation module 2, and low-noise PLL module 3. Its specific operation and function are as follows: Power module 4 generates multiple power rails of different voltage levels, such as 12V, 5V, 3.3V, 2.5V, and 1.8V, through its internal circuitry, ensuring that each rail's power supply forms a complete circuit through its corresponding ground wire. During power supply, the module implements two core noise management and suppression measures: ① Power purification and rail isolation: LDOs (low dropout linear regulators) and filters are used on each output power rail for secondary voltage regulation and filtering to completely remove ripple and broadband noise from the primary power supply or switching power supply, ensuring optimal power for the final output. The chip provides an "ultra-clean" DC voltage. At the same time, ferrite beads are inserted between critical power paths. Utilizing their high-frequency impedance characteristics, they effectively block high-frequency noise crosstalk that may occur between different power rails through power lines. For example, this prevents noise pollution of analog RF circuit power supplies by digital circuits. ② Ground system optimization and shielding: The ground lines are strictly physically separated into different areas such as analog ground, RF ground, and digital ground. The ground current paths of various types of circuits are controlled to minimize the impact of drastic ground potential fluctuations (i.e., "ground bounce noise") caused by the rapid switching of digital circuits on the reference ground of analog and RF circuits. At the same time, shielding arrangements such as metal shielding are implemented in critical circuit areas to cut off electromagnetic interference coupled through spatial radiation.

[0117] Example 6:

[0118] The basic content is the same as in Example 1, except that:

[0119] Please see Figure 1 — Figure 8 One input terminal of the DDS chip 22 is connected to the output terminal of the MCU chip 24, and the input terminal of the MCU chip 24 is connected to the output terminal of the host computer; the input terminal of the host computer is connected to one output terminal of the third power divider 34.

[0120] The method also includes a sixth step:

[0121] Step 6: The host computer compares the final output signal with the external signals to obtain the comprehensive error signal. Then, the host computer controls the MCU chip 24 to write the frequency control word and phase control word to the DDS chip 22 based on the comprehensive error signal for adaptive adjustment.

[0122] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A complementary low-phase-noise frequency synthesizer, characterized in that: The synthesizer includes a frequency multiplier module (1), an adjustment module (2), and a low-noise PLL module (3). The low-noise PLL module (3) includes a crystal oscillator (31), a third mixer (32), and a PID circuit (33). The output terminal of the crystal oscillator (31) is connected to the input terminal of the third power divider (34). One output terminal of the third power divider (34) is connected to one input terminal of the third mixer (32). The output terminal of the third mixer (32) is connected to the input terminal of the PID circuit (33). The output terminal of the PID circuit (33) is connected to the voltage control terminal of the crystal oscillator (31). The other output terminal of the third power divider (34) outputs the final output signal. The other input terminal of the third mixer (32) is connected to the output terminal of the second mixer (21) of the adjustment module (2). One input terminal of the second mixer (21) is connected to the output terminal of the DDS chip (22), and the input terminal of the DDS chip (22) is connected to one output terminal of the first power divider (11) of the frequency multiplier module (1); the other input terminal of the second mixer (21) is connected to the other output terminal of the first power divider (11); the first power divider (11) receives the frequency multiplied signal of the reference signal at its input terminal. The reference signal, after being frequency multiplied, is a 10MHz signal. This 10MHz signal is then processed by a 250MHz first bandpass filter (12) to extract a 250MHz first reference signal. This 250MHz first reference signal is then divided by a first power divider (11) into two identical 250MHz first and second signals. The 250MHz first signal is input to a DDS chip (22), which outputs a 20MHz digitally controlled intermediate frequency (CIF) signal. This 20MHz CIF signal is then input to a second mixer (21) to mix with the 250MHz second signal. The second mixer (21) then outputs a 230MHz second phase reference signal, which is input to a third mixer (32). Simultaneously, a crystal oscillator (31) outputs a 10MHz third reference signal. The third reference signal is divided into the same 10MHz third signal and 10MHz fourth signal by the third power divider (34). The 10MHz third signal is then extracted into a 230MHz third reference signal by the third bandpass filter amplifier (37) of 230MHz. The 230MHz third reference signal is then input to the third mixer (32) for phase comparison with the 230MHz second phase reference signal. The third mixer (32) outputs a phase error signal. The PID circuit (33) generates a control signal based on the phase error signal. The crystal oscillator (31) forms a closed-loop lock based on the control signal to make the phase of the 230MHz third reference signal track the phase of the 230MHz second phase reference signal. The loop bandwidth of the PID circuit (33) is then adjusted, and the 10MHz fourth signal is the final output signal.

2. The complementary low-phase-noise frequency synthesizer according to claim 1, characterized in that: One output of the third power divider (34) is connected to the input of the third comparator (35), the output of the third comparator (35) is connected to the input of the third buffer (36), the output of the third buffer (36) is connected to the input of the third bandpass filter amplifier (37), and the output of the third bandpass filter amplifier (37) is connected to one input of the third mixer (32). The other output of the third power divider (34) is connected to the input of the third low-pass filter (38), and the output of the third low-pass filter (38) outputs a signal.

3. A complementary low-phase-noise frequency synthesizer according to claim 2, characterized in that: The third bandpass filter amplifier (37) includes a third first bandpass filter (371), a third first amplifier (372), a third second bandpass filter (373), a third second amplifier (374), a third third bandpass filter (375), and a third third amplifier (376). The output of the third bandpass filter (371) is connected to the input of the third amplifier (372), the output of the third amplifier (372) is connected to the input of the third bandpass filter (373), the output of the third bandpass filter (373) is connected to the input of the third amplifier (374), the output of the third amplifier (374) is connected to the input of the third bandpass filter (375), and the output of the third bandpass filter (375) is connected to the input of the third amplifier (376). The center frequency of the third bandpass filter (371) is 230MHz, the center frequency of the third bandpass filter (373) is 230MHz, and the center frequency of the third bandpass filter (375) is 230MHz. The cutoff frequency of the third low-pass filter (38) is 10MHz.

4. A complementary low-phase-noise frequency synthesizer according to claim 1, characterized in that: The output of the DDS chip (22) is connected to the input of the second low-pass filter (23), and the output of the second low-pass filter (23) is connected to one input of the second mixer (21).

5. A complementary low-phase-noise frequency synthesizer according to claim 4, characterized in that: The cutoff frequency of the second low-pass filter (23) is 50MHz.

6. A complementary low-phase-noise frequency synthesizer according to claim 1, characterized in that: The input terminal of the first power divider (11) is connected to the output terminal of the first bandpass filter amplifier (12). The input terminal of the first bandpass filter amplifier (12) is connected to the output terminal of the first buffer (13). The input terminal of the first buffer (13) is connected to the output terminal of the first comparator (14). The input terminal of the first comparator (14) is connected to the output terminal of the first low-pass filter (15). The input terminal of the first low-pass filter (15) receives a reference signal.

7. A complementary low-phase-noise frequency synthesizer according to claim 6, characterized in that: The first bandpass filter amplifier (12) includes a first bandpass filter (121), a first amplifier (122), a first second bandpass filter (123), a first second amplifier (124), a first third bandpass filter (125), and a first third amplifier (126). The output of the first bandpass filter (121) is connected to the input of the first amplifier (122), the output of the first amplifier (122) is connected to the input of the first second bandpass filter (123), the output of the first second bandpass filter (123) is connected to the input of the first second amplifier (124), the output of the first second amplifier (124) is connected to the input of the first third bandpass filter (125), and the output of the first third bandpass filter (125) is connected to the input of the first third amplifier (126). The center frequency of the first bandpass filter (121) is 250MHz, the center frequency of the first second bandpass filter (123) is 250MHz, and the center frequency of the first third bandpass filter (125) is 250MHz. The cutoff frequency of the first low-pass filter (15) is 10MHz.

8. A complementary low-phase-noise frequency synthesizer according to claim 1, characterized in that: The frequency multiplier module (1) is connected to the power supply module (4) by signal, the adjustment module (2) is connected to the power supply module (4) by signal, and the low noise PLL module (3) is connected to the power supply module (4) by signal. The power module (4) includes multiple power rails and multiple ground lines. Each power rail is connected to its corresponding ground line. The power rails are isolated from each other by LDO / filter and ferrite beads. The multiple ground lines are partitioned and shielded in an analog / RF / digital manner.

9. A method of using the complementary low-phase-noise frequency synthesizer of claim 1, characterized in that: The method includes the following steps: Step 1: First, input the first reference signal into the first power divider (11), and then output the same first signal and second signal from the first power divider (11); Step 2: First, write the frequency control word and phase control word into the DDS chip (22). At the same time, the first signal is input to the DDS chip (22). Then, the DDS chip (22) outputs the numerically controlled intermediate frequency signal according to the frequency control word and phase control word. Then, the numerically controlled intermediate frequency signal and the second signal enter the second mixer (21) for mixing. Then, the second mixer (21) outputs the second phase reference signal with lower near-end phase noise. Step 3: First, the crystal oscillator (31) outputs a third reference signal with low phase noise at the far end. Then, the third power divider (34) outputs the third signal and the fourth signal based on the third reference signal. Then, the third signal and the second reference signal enter the third mixer (32) for mixing. Then, the third mixer (32) outputs a phase error signal. Then, the PID circuit (33) generates a control signal based on the phase error signal. Then, the crystal oscillator (31) forms a closed-loop lock based on the control signal so that the phase of the third reference signal tracks the phase of the second phase reference signal. Step 4: The fourth signal output by the third power divider (34) is the final output signal of the synthesizer; Step 5: When the near-end phase noise of the final output signal is low, narrow the loop bandwidth of the PID circuit (33); when the far-end phase noise of the final output signal is low, widen the loop bandwidth of the PID circuit (33); when the phase noise of the final output signal is low at both the near end and the far end, adjust the loop bandwidth of the PID circuit (33) to the offset frequency of the intersection of the phase noise curves of the first reference signal and the third reference signal.

10. The method of using a complementary low-phase-noise frequency synthesizer according to claim 9, characterized in that: One input terminal of the DDS chip (22) is connected to the output terminal of the MCU chip (24), and the input terminal of the MCU chip (24) is connected to the output terminal of the host computer; the input terminal of the host computer is connected to one output terminal of the third power divider (34). The method also includes a sixth step: Step 6: The host computer compares the final output signal with the external signal to obtain the comprehensive error signal. Then, the host computer controls the MCU chip (24) to write the frequency control word and phase control word to the DDS chip (22) based on the comprehensive error signal for adaptive adjustment.

Images